AD8582
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
a
FUNCTIONAL BLOCK DIAGRAM
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
The high speed parallel data interface connects to the fastest
processors without wait states. The double-buffered input struc-
ture allows the user to load the input registers one at a time,
then a single load strobe tied to both LDA + LDB inputs will
update both DAC outputs simultaneously. LDA and LDB can
also be activated independently to immediately update their re-
spective DAC registers. An address input decodes DAC A or
DAC B when the chip select CS input is strobed. An asynchro-
nous reset input sets the output to zero scale. The MSB bit can
be used to establish a preset to midscale when the reset input is
strobed.
The AD8582 is available in the 24-pin plastic DIP and the sur-
face mount SOIC-24. Each part is fully specified for operation
over –40°C to +85°C, and the full +5 V ± 5% power supply
range.
FEATURES
Complete Dual 12-Bit DAC
No External Components
Single +5 Volt Operation
1 mV/Bit with 4.095 V Full Scale
True Voltage Output, ±5 mA Drive
Very Low Power: 5 mW
APPLICATIONS
Digitally Controlled Calibration
Portable Equipment
Servo Controls
Process Control Equipment
PC Peripherals
+5 Volt, Parallel Input
Complete Dual 12-Bit DAC
GENERAL DESCRIPTION
The AD8582 is a complete, parallel input, dual 12-bit, voltage
output DAC designed to operate from a single +5 volt supply.
Built using a CBCMOS process, this monolithic DAC offers the
user low cost, and ease-of-use in +5 volt only systems.
Included on the chip, in addition to the DACs, are a rail-to-rail
amplifier, latch and reference. The reference (V
REF
) is trimmed
to 2.5 volts output, and the on-chip amplifier gains up the DAC
output to 4.095 volts full scale. The user needs only supply a +5
volt supply.
The AD8582 is coded natural binary. The op amp output
swings from 0 volt to +4.095 volts for a one-millivolt-per-bit
resolution, and is capable of driving ±5 mA. Operation down to
4.3 V is possible with output load currents less than 1 mA.
DATA REFERENCE
12-BIT
DAC A
DAC A
REGISTER
INPUT A
REGISTER
12-BIT
DAC B
DAC B
REGISTER
INPUT B
REGISTER
12
12
2
12
VDD
VOUTA
VOUTB
VREF
AGND
DGND MSB
RST
LDA
CS
A/B
LDB
AD8582
OUTPUT LOAD CURRENT – mA
V
DD
MIN – Volts
5.0
4.4
4.0
0.01 0.1 100101.0
4.2
4.6
4.8
∆∆VFS
≤
1 LSB
DATA = FFF
H
T
A
= +25
°
C
PROPER OPERATION
WHEN V
DD
SUPPLY
VOLTAGE ABOVE
CURVE
Figure 1. Minimum Supply Voltage vs. Load
2.0
–2.0 4096
–1.0
–1.5
0
0.0
–0.5
0.5
1.0
1.5
307220481024
DIGITAL INPUT CODE – Decimal
LINEARITY ERROR – LSB
VDD = +5V
TA = –55°C, +25°C, +85°C
= +25°C & +85°C
= –55°C
Figure 2. Linearity Error vs. Digital Code and Temperature
AD8582–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
REV. 0
–2–
(@ VDD = +5.0 V ± 5%, RL = No Load, –40°C ≤ TA ≤ +85°C, unless otherwise noted)
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Resolution N Note 1 12 Bits
Relative Accuracy INL –2 ±3/4 +2 LSB
Differential Nonlinearity DNL Monotonic –1 ±3/4 +1 LSB
Zero-Scale Error V
ZSE
Data = 000
H
+0.2 +3 mV
Full-Scale Voltage V
FS
Data = FFF
H
,
2
4.079 4.095 4.111 V
Full-Scale Tempco TCV
FS
Notes 2 and 3 ±16 ppm/°C
MATCHING PERFORMANCE
Linearity Matching Error ∆V
FS
A/B ±1 LSB
REFERENCE OUTPUT
Output Voltage V
REF
2.484 2.500 2.516 V
Output Source Current I
REF
Note 4 –5 mA
Line Rejection LN
REJ
0.08 %/V
Load Regulation LD
REG
I
REF
= 0 mA to 5 mA 0.1 %/mA
ANALOG OUTPUT
Output Current I
OUT
Data = 800
H
±5mA
Load Regulation at Half Scale LD
REG
R
L
= 402 Ω to ∞, Data = 800
H
1 3 LSB
Capacitive Load C
L
No Oscillation
3
500 pF
DYNAMIC CHARACTERISTICS
3
Crosstalk C
T
>64 dB
Voltage Output Settling Time
5
t
S
To ±1 LSB of Final Value 16 µs
Digital Feedthrough F
T
Signal Measured at DAC Output, While 35 nV s
Changing Data (LDA = LDB = “1”)
LOGIC INPUTS
Logic Input Low Voltage V
IL
0.8 V
Logic Input High Voltage V
IH
2.4 V
Input Leakage Current I
IL
10 µA
Input Capacitance C
IL
Note 3 10 pF
TIMING SPECIFICATIONS
3, 6
Chip Select Pulse Width t
CSW
30 ns
DAC Select Setup t
AS
30 ns
DAC Select Hold t
AH
0ns
Data Setup t
DS
30 ns
Data Hold t
DH
10 ns
Load Setup t
LS
20 ns
Load Hold t
LH
10 ns
Load Pulse Width t
LDW
20 ns
Reset Pulse Width t
RSW
30 ns
SUPPLY CHARACTERISTICS
Positive Supply Current I
DD
V
IH
= 2.4 V, V
IL
= 0.8 V 4 7 mA
V
IL
= 0 V, V
DD
= +5 V 1 2 mA
Power Dissipation
7
P
DISS
V
IH
= 2.4 V, V
IL
= 0.8 V 20 35 mW
V
IL
= 0 V, V
DD
= +5 V 5 10 mW
Power Supply Sensitivity PSS ∆V
DD
= ±5% 0.002 0.004 %/%
NOTES
1
1 LSB = 1 mV for 0 V to +4.095 V output range.
2
Includes internal voltage reference error.
3
These parameters are guaranteed by design and not subject to production testing.
4
Very little sink current is available at the V
REF
pin. Use external buffer if setting up a virtual ground.
5
Settling time is not guaranteed for the first six codes 0 through 5.
6
All input control signals are specified with t
R
= t
F
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
7
Power dissipation is a calculated value I
DD
× 5 V.
Specifications subject to change without notice.
–3–
REV. 0
AD8582
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8582 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
V
DD
to DGND & AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
Logic Inputs to DGND . . . . . . . . . . . . . . .–0.3 V, V
DD
+ 0.3 V
V
OUT
to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, V
DD
+ 0.3 V
V
REF
to AGND . . . . . . . . . . . . . . . . . . . . .–0.3 V, V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
I
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . . .(T
J
max–T
A
)/θ
JA
Thermal Resistance, θ
JA
24-Pin Plastic DIP Package (N-24) . . . . . . . . . . . . . 62°C/W
24-Lead SOIC Package (SOL-24) . . . . . . . . . . . . . . 73°C/W
Maximum Junction Temperature (T
J
max) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN DESCRIPTION
Pin No. Name Description
1, 24 V
OUTA
Voltage outputs from the DACs. Fixed
V
OUTB
output voltage range of 0 V to 4.095 V
with 1 mV/LSB. An internal
temperature stabilized reference
maintains a fixed full-scale voltage
independent of time, temperature and
power supply variations.
2 AGND Analog Ground. Ground reference for
the internal bandgap reference voltage,
the DAC, and the output buffer.
3 DGND Digital ground for input logic.
4, 21 LDA, Load DAC register strobes. Transfers
LDB input register data to the DAC registers.
Active low inputs, Level sensitive latch.
May be connected together to double-
buffer load DAC registers.
5 MSB Digital Input: High presets DAC
registers to half scale (800
H
), Low
clears DAC registers to zero (000
H
)
upon RST assertion.
6RST Active low digital input that clears the
DAC register to zero, setting the DAC
to minimum scale when MSB pin = 0,
or half-scale when MSB pin = 1.
7–18 DB
0–11
Twelve Binary Data Bit Inputs. DB11 is
the MSB and DB0 is the LSB.
19 CS Chip Select. Active low input.
20 A/B Select DAC A = 0 or DAC B = 1.
22 V
DD
Positive Supply. Nominal value +5 V, ±5%.
23 V
REF
Nominal 2.5 V reference output
voltage. This node must be buffered if
required to drive external loads.
PIN CONFIGURATIONS
N-24
24-Pin Plastic DIP SOL-24
24-Pin SOIC
V
OUTA
AGND
V
OUTB
V
REF
MSB
DB0 DB11
DGND V
DD
DB1 DB10
DB2 DB9
DB3 DB8
DB4 DB7
DB5 DB6
14
1
2
24
23
5
6
7
20
19
18
3
4
22
21
817
916
10 15
11
TOP VIEW
(Not to Scale)
12 13
AD8582
LDA
RST
LDB
CS
A/B TOP VIEW
(Not to Scale)
12 13
AD8582
124
LDA, LDB
CS
A/B
D0–D11
RST
tAS tAH
tDS tDH
tLDW
tRSW
tLS tLH
VOUT
tS tS ± 1LSB
ERROR BAND
tCSW
Timing Diagram
ORDERING INFORMATION*
Temperature Package Package
Model Range Description Option
AD8582AN –40°C to +85°C 24-Pin Plastic DIP N-24
AD8582AR –40°C to +85°C 24-Lead SOIC SOL-24
AD8582Chips +25°C Die
*For die specifications contact your local Analog Devices sales office. The
AD8582 contains 1270 transistors.
REV. 0
–4–
AD8582
Table I. Control Logic Truth Table
CS A/B LDA LDB RST MSB Input Register DAC Register
LLHHHX Write to A Latched
LHHHHX Write to B Latched
LLLHH X Write to A A Transparent
L H H L H X Write to B B Transparent
H X L L H X Latched A & B Transparent
H X ^ ^ H X Latched Latched
XXXXLL Reset to Zero Scale Reset to Zero Scale
XXXXLH Reset to Midscale Reset to Midscale
HXXX^ X Latch Reset Value Latch Reset Value
^Denotes positive edge triggered.
OPERATION
The AD8582 is a complete, ready-to-use dual 12-bit digital-to-
analog converter. Only one +5 V power supply is necessary for
operation. It contains two voltage-switched, 12-bit, laser-
trimmed digital-to-analog converters, a curvature-corrected
bandgap reference, rail-to-rail output op amps, input registers,
and DAC registers. The parallel data interface consists of twelve
data bits, DB0–DB11, an address select pin A/B, two load
strobe pins (LDA, LDB) and an active low CS strobe. In addi-
tion an asynchronous RST pin will set all DAC register bits to
zero causing the V
OUT
to become zero volts, or to midscale for
trimming applications when the MSB pin is programmed to
Logic 1. This function is useful for power on reset or system
failure recovery to a known state.
D/A CONVERTER SECTION
The internal DAC is a 12-bit voltage-mode device with an
output that swings from AGND potential to the 2.5 volt in-
ternal bandgap voltage. It uses a laser trimmed R-2R
ladder which is switched by N channel MOSFETs. The out-
put voltage of the DAC has a constant resistance independent
of digital input code. The DAC output (not available to the
user) is internally connected to the rail-to-rail output op amp.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. This low power amplifier contains
a differential PNP pair input stage which provides low offset
voltage and low noise, as well as the ability to amplify the zero-
scale DAC output voltages. The rail-to-rail amplifier is config-
ured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the
4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an
equivalent circuit schematic of the analog section.
The op amp has a 16 µs typical settling time to 0.01%. There
are slight differences in settling time for negative slewing signals
versus positive. See the oscilloscope photos in the Typical Per-
formances section of this data sheet.
Figure 3. Equivalent Schematic of Analog Portion
R1
R2
V
OUT
RAIL-TO-RAIL
OUTPUT
AMPLIFIER
R
BANDGAP
REFERENCE
V
REF
2.5V
2R
R
2R
2R
SPDT
N CH FET
SWITCHES 2R
AV = 4.095/2.5
= 1.638V/V
VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER
BUFFER
2R
OUTPUT SECTION
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 4 shows an equivalent output schematic of
the rail-to-rail amplifier with its N channel pull-down FETs that
will pull an output load directly to GND. The output sourcing
current is provided by a P channel pull-up device that can sup-
ply GND terminated loads, especially important at the –5%
supply tolerance value of 4.75 volts.
Figure 4. Equivalent Analog Output Circuit
V
DD
V
OUT
AGND
N-CH
P-CH
–5–
REV. 0
AD8582
Figures 5 and 6 in the typical performance characteristics sec-
tion provide information on output swing performance near
ground and full-scale as a function of load. In addition to resis-
tive load driving capability, the amplifier has also been carefully
designed and characterized for up to 500 pF capacitive load
driving capability.
REFERENCE SECTION
The internal 2.5 V curvature-corrected bandgap voltage refer-
ence is laser trimmed for both initial accuracy and low tempera-
ture coefficient. The voltage generated by the reference is
available at the V
REF
pin. Since V
REF
is not intended to drive ex-
ternal loads, it must be buffered. The equivalent emitter fol-
lower output circuit of the V
REF
pin is shown in Figure 3.
Bypassing the V
REF
pin will improve noise performance; how-
ever, bypassing is not required for proper operation. Figure 8
shows broadband noise performance.
POWER SUPPLY
The very low power consumption of the AD8582 is a direct re-
sult of a circuit design optimizing use of the CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors good analog accuracy is achieved.
For power-consumption sensitive applications it is important to
note that the internal power consumption of the AD8582 is
strongly dependent on the actual logic-input voltage levels
present on the DB0–DB11, CS, A/B, MSB, LDA, LDB and
RST pins. Since these inputs are standard CMOS logic struc-
tures they contribute static power dissipation dependent on the
actual driving logic V
OH
and V
OL
voltage levels. The graph in
Figure 9 shows the effect on total AD8582 supply current as a
function of the actual value of input logic voltage. Conse-
quently, for optimum dissipation use of CMOS logic versus
TTL provides minimal dissipation in the static state. A V
INL
=
0 V on the DB0–11 pins provides the lowest standby dissipation
of 1 mA typical with a +5 V power supply.
As with any analog system, it is recommended that the AD8582
power supply be bypassed on the same PC card that contains
the chip. Figure 10 shows the power supply rejection versus fre-
quency performance. This should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifiers used in the
AD8582 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current
capability near full scale can be tolerated, operation of the
AD8582 is possible down to +4.3 volts. The minimum operat-
ing supply voltage versus load current plot, in Figure 1, pro-
vides information for operation below V
DD
= +4.75 V.
TIMING AND CONTROL
The input registers are level triggered and acquire data from the
data bus during the time period when CS is low. The input reg-
ister selected is determined by the A/B select pin, see Table I.
for a complete description. When CS goes high, the data is
latched into the register and held until CS returns low. The
minimum time required for the data to be present on the bus
before CS returns high is called the data setup time (t
DS
) as seen
in Timing Diagram. The data hold time (t
DH
) is the amount
of time that the data has to remain on the bus after CS goes
high. The high speed timing offered by the AD8582 provides
for direct interface with no wait states in all but the fastest
microprocessors.
The data from the input registers is transferred to the DAC reg-
isters by the active low LDA and LDB pins. If these inputs are
tied together, a single logic input can perform a double buffer
update of the DAC registers, which in turn simultaneously
changes the analog output voltages to a new value. If the LDA
and LDB pins are wired low, they become transparent. In this
mode the input register data will directly control the output
voltages. Refer to the Control Logic Truth
Table for a com-
plete description.
Unipolar Output Operation
This is the basic mode of operation for the AD8582. The
AD8582 has been designed to drive loads as low as 820Ω in par-
allel with 500 pF. The code table for this operation is shown in
Table II.
Table II. Unipolar Code Table
Hexadecimal
Number in DAC Decimal Number Analog Output
Register in DAC Register Voltage (V)
FFF 4095 + 4.095
801 2049 + 2.049
800 2048 + 2.048
7FF 2047 + 2.047
000 0 0
AD8582–Typical Performance Characteristics
REV. 0
–6–
80
–60
–80 1
–20
–40
0
20
40
60
32
OUTPUT VOLTAGE – Volts
OUTPUT CURRENT – mA
POSITIVE0
CURRENT0
LIMIT0
NEGATIVE
CURRENT
LIMIT
DATA = 800H
RL TIED TO +2V
110 1000100
100
1
0.01
0.1
10
OUTPUT SINK CURRENT – µA
OUTPUT PULL-DOWN VOLTAGE – mV
V
DD
= +5V
DATA = 000
H
T
A
= +85
°
C T
A
= –40
°
C
T
A
= +25
°
C
5
2
010 100 100k10k1k
1
3
4
OUTPUT VOLTAGE – Volts
RL TIED TO AGND
DATA = FFFH
VDD = +5V
TA = +25°C
RL TIED TO +5V
DATA = 000H
LOAD RESISTANCE – Ω
Figure 6. Pull-Down Voltage vs.
Output Sink Current Capability Figure 7. I
OUT
vs. V
OUT
Figure 5. Output Swing vs. Load
5
05
1
0
3
2
4
3241
LOGIC VOLTAGE VALUE – Volts
SUPPLY CURRENT – mA
VDD = +4.75V VDD = +5V
TA = +25°C
100
010 100 100k10k1k
60
80
20
40
POWER SUPPLY REJECTION – dB
FREQUENCY – Hz
VDD = +5V ±200mV AC
TA = +25°C
DATA = FFFH
TIME = 100µs/DIV
OUTPUT NOISE VOLTAGE – 200µV/DIV
T
A
= +25°C
NBW = 630kHz
Figure 9. Supply Current vs. Logic
Input Voltage Figure 10. Power Supply Rejection
vs. Frequency
Figure 8. Broadband Noise
2.028
2.018
2.048
2.038
0
5
TIME – 500ns/DIV
V
OUT
– Volts
LD
2048
10
TO 2047
10
2.008
0
5
V
DD
= +5V
T
A
= +25
°
C
OUTPUT VOLTAGE
1mV/DIV DATA
TIME – 5µs/DIV
15µs
5
0
4
3
2
1
0
TIME = 20µs/DIV
INPUT
OUTPUT
10
90
100 LDB
V
DD
= +5V
T
A
= +25
°
C
1V 20µs
5V
0%
Figure 11. Midscale Transition
Performance Figure 12. Large Signal Settling Time Figure 13. Output Voltage Rise
Time Detail
–7–
REV. 0
AD8582
0
5
V
DD
= +5V
T
A
= +25
°
C
OUTPUT VOLTAGE
1mV/DIV DATA
TIME – 5µs/DIV
15µs
3
–1 125
0
–25–50
1
2
1007550250
TEMPERATURE –
°
C
ZERO-SCALE OUTPUT – Volts
V
DD
= +4.75V
NO LOAD
SS = 298 UNITS
8
0125
2
1
–25–50
4
3
5
6
7
1007550250
TEMPERATURE –
°
C
SUPPLY CURRENT – mA
V
DATA
= +2.4V
NO LOAD
V
DD
= +4.75V
V
DD
= +5.00V
V
DD
= +5.25V
0
10
30
20
40
–8 1–5 0–7 –6
TOTAL UNADJUSTED ERROR – mV
FREQUENCY
–4 –3 –2 –1
5
15
25
35
45 TUE =
Σ
INL+ZS+FS
SS = 297 UNITS
V
DD
= +4.75V
T
A
= +25°C
100
1.0
0.110 100 100k10k1k
10
FREQUENCY – Hz
VDD = +5V
TA = +25°C
DATA = FFFH
OUTPUT NOISE DENSITY – µV/
Hz
4.115
4.075 125
4.085
4.080
–25–50
4.095
4.090
4.100
4.105
4.110
1007550250
TEMPERATURE –
°
C
FULL-SCALE OUTPUT – Volts
V
DD
= +4.75V
NO LOAD
SS = 298 UNITS
AVG
σAVG +1σ
σAVG –1σ
HOURS OF OPERATION AT +150°C
3
–3 600
0
–2
100
–1
0
2
1
500400300200
NOMINAL FULL-SCALE
VOLTAGE CHANGE – mV
V
DD
= +5V
SS = 135 UNITS
DATA = FFF
H
AVG
σ
AVG +2
σ
σ
AVG –2
σ
V
DD
V
REF
0V
0V
TIME – 1µs/DIV
10
90
100
0%
2V
2V 1µs
∞T
A
= +25
°
C
R
L
= ∞
V
DD
= +5V
1
0
DATA
V
OUT
10mV/DIV
TIME – 5µs/DIV
10
90
100
0%
10mV
5V 5µs
CS = HIGH
Figure 16. Full-Scale Voltage vs.
Temperature
Figure 15. Total Unadjusted Error
Histogram
Figure 14. Output Voltage Fall
Time Detail
Figure 17. Zero-Scale Voltage vs.
Temperature Figure 18. Output Voltage Noise
Density vs. Frequency Figure 19. Long-Term Drift
Accelerated by Burn-In
Figure 21. Reference Startup vs.
Time Figure 22. Digital Feedthrough vs.
Time
Figure 20. Supply Current vs.
Temperature
REV. 0
–8–
AD8582
10
–10 125
–4
–8
–25
–6
–50
2
–2
0
4
6
8
10050 75
025
TEMPERATURE –
°
C
REFERENCE ERROR – mV
V
DD
= +4.75V
σAVG +1σAVG
σAVG –1σ
0.000
–0.005 125–25
–0.004
–50
–0.002
–0.003
–0.001
10050 75
025
TEMPERATURE –
°
C
REF LOAD REGULATION – %/mA
σAVG +1σ
AVG
σAVG –1σ
∆V
DD
= +4.75V
∆I
L
= 5mA
PRINTED IN U.S.A. C1869–18–12/93
Figure 23. Reference Error vs.
Temperature Figure 24. Reference Load Regulation
vs. Temperature Figure 25. Reference Line Regulation
vs. Temperature
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
N-24
24-Pin Narrow Body Plastic DIP
SOL-24
24-Lead Wide Body SOIC
0.195 (4.95)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
PIN 1 24
1
13
12
0.280 (7.11)
0.240 (6.10)
0.210
(5.33)
MAX
0.100 (2.54)
BSC SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
0.200 (5.05)
0.125 (3.18)
1.275 (32.30)
1.125 (28.60)
PIN 1
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
13
12
1
24
0.0192 (0.49)
0.0138 (0.35)
0.0500 (1.27)
BSC
0.1043 (2.65)
0.0926 (2.35)
0.6141 (15.60)
0.5985 (15.20)
0.0118 (0.30)
0.0040 (0.10) 0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
0.0291 (0.74)
0.0098 (0.25) x 45
°
8
°
0
°