PRODUCT GUIDE
RISC/CISC ASIC
4594C-9904
Published in April, 1999
32 32
Customer support
Application development
Solution proposals
Documentation
Design kits
Communications, Office equipment
AV equipment,
Home-use information appliances,
Video games, Multimedia platforms,
Set-top boxes, DVD players
COS Solution
Gateway to the COS Age – RISC/CISC ASICs from Toshiba.
Services
ASICs
Packaging
EDA tools
Semiconductor Enablers
Hardware IP: MCUs, Memory, DSP,
USB, IrDA, IEEE 1394
Software IP: Middleware functions,
embedded OSes
Platforms
Applications
User System
Specialized microcontrollers are increasingly used to control devices of all kinds such as automobiles, home
and office appliances, handheld equipment, etc. With this trend getting into high gear, application software is
customized more often than ever before to fit specific needs of target systems.
Toshiba offers a computer-on-silicon (COS) solution to help its customers improve the time-to-market for
their new processor-based systems. The combination of Toshiba’s world-class computer and silicon
technologies provides its customers with a total solution - a partnership with Toshiba brings you not only the
performance of our hardware and software IP, but
also comprehensive services and development tool
support. The COS solution allows our customers to
commit their effor ts to development work.
To meet diverse customer needs, Toshiba provides a broad range of Reduced Instruction Set Computer
(RISC) and Complex Instruction Set Computer (CISC) processors. Our RISC and CISC processors are
available either as ASIC-ready cores or as standard products. Toshiba's ASIC core por tfolio includes a gallery
of 32- and 64-bit TX families of RISC cores as well as Toshiba's proprietary 16-bit CISC processor families
such as TLCS-900/H and TLCS900/L1. Also included among ASIC-ready cores are a variety of hardware and
software IP cores targeted for consumer, computer, and communications applications. All these cores give
you great flexibility in the design of advanced multimedia products.
Compilers
Emulators
Simulators
De velopment Tools
Continuous Evolution of Toshiba’s MPU Cores
ASIC-Ready RISC Cores
TX Sytem RISC
TX39 Family
ASIC-Ready RISC Cores
TX Sytem RISC
TX19 Family
ASIC-Ready CISC Cores
900 Family
RISC ASIC
CISC ASIC
IP Core Lines
Hardware/Software Co-verification Environment
Development Flow
Test Methodologies
Software Development Tools for RISC ASICs
Software Development Tools for CSIC ASICs
Toshiba ASIC Road Map
Packaging
Toshiba Documents
4
5
6
7
8
9
10
11
12
13
14
16
17
18
19
4
The following road map shows a whole suite of Toshiba's ASIC-ready MPU cores. Toshiba offers a
broad and varied range of RISC and CISC options to suit your unique needs, including applications,
power dissipation, and performance requirements. Encompassing Toshiba's MPU core offerings are
the TLCS-900 CISC family and the TX19, TX39, TX49, and the next-generation RISC families.
MIPS
✽: In Development
ASIC-ready cores
1
10
100
1000
TLCS-900 TLCS-900/L
TLCS-900/H
TLCS-900/H2
TLCS-900/L1
TX19
TX39
TX49
TX79
TX39/H
●
64-bit RISC processors
●
Addition of the MIPS-III
instruction set
●
64-bit RISC processors
●
Addition of the MIPS-IV
instruction set
●
Superscaler execution
●
Lower-voltage version
●
75% power savings
●
Low noise
●
Higher-performance
version
●
Lower-voltage version
●
50% power savings
●
✕
2 performance
●
✕
4 performance
●
32-bit RISC processors
●
Addition of the MIPS 16
™
ASE
(reduced code size)
●
Low power dissipation
●
32-bit RISC processors
●
MIPS-I, MIPS-II, and multiply-add
operation instructions
●
High-speed MAC
●
On-chip debug support
✽
✽
✽
TX39/H2
✽
❈ MIPS16 is a trademark of MIPS Technologies, Inc.
●Higher-performance
●Lower-power
●Increased versatility
5
Microprocessor Core
Low Power
Functions for Embedded Applications
Development T ool Support
ASIC Support
Applications
●
R3000A architecture
●
High-performance:
TX39/H:
74 MIPS
(at 70 MHz operation)
TX39/H2
(in development)
:
105 MIPS
(at 100 MHz operation)
based on Dhrystone 2.1 VAX-11/780 benchmarking
●
Built-in cache memory
Separate instruction and data caches
●
Non-blocking load function
●
DSP function
One-cycle Multiply-Accumulate (MAC)
supporting 32-bit
✕
32-bit multiply-add operations
●
C/C++ compiler, assemblers/linkers
●
External real-time debug system support
Provides for real-time debug with caches enabled.
●
Support of various real-time OSes
●
Standard board applicable to evaluation
and user application
●
Proven EDA environment with RTL Verilog models
●
Peripherals add-ons provided as megacells
●
MPU core availability:
■
GR39WAD: TX39/H core (TC220)
■
PTX3904A:
Functionally-equivalent to TMPR3904A (TC220)
■
PTX39WAD: TX39/H2 core (TC240, in development)
●
Multiple power saving modes of operation,
including Reduced-Frequency (RF), Doze,
Halt modes, etc.
●
The PLL oscillation can be halted externally
(standby mode)
●
Improved code density and performance
Branch-likely instructions
Hardware interlock
Set-top boxes
❈ R3000A is a trademark of MIPS Technologies, Inc.
Vehicle navigation systems
Personal information communicators (PIC)
Avoids performance degradation by executing the
next instruction while the data cache is being
refilled.
The TX39 family is a high-performance 32-bit microprocessor for embedded applications developed by
Toshiba based on the MIPS R3000A architecture. The TX39 family can be used as a foundation for
embedded array or cell-based ASIC designs.
■ TX39 Family ASSP Products
Standard MPU
Vehicle navigation systems
Peripherals added to the standard MPU
Peripherals and a PCI controller added to the standard MPU
Personal information communicators (PIC)
Personal information communicators (PIC)
✽: In Development
70 MHz
40 MHz
66 MHz
66 MHz
92 MHz
129/148
✽
MHz
QFP160
QFP208
QFP208
QFP208
LQFP208/FBGA217
LQFP208/FBGA217
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
TMPR3901AF-70
TMPR3903AF
TMPR3904AF-66
✽
TMPR3907F
TMPR3912AU/XB
TMPR3922AU/XB
Product Number Applications
Clock
Frequency
Voltage Package
I/O: 3.3 V
Core: 2.7 V
6
■ Applications
Microprocessor Core
Low Power
ASIC Support
Functions for Embedded Applications
●R3000A architecture
●High-performance:
42 MIPS
(at 40 MHz operation)
based on Dhrystone 2.1 VAX-11/780 benchmarking
●Built-in cache memory and high-speed data RAM
●Non-blocking load function
●DSP function
Fast Multiply-Accumulate (MAC)
supporting 32-bit ✕ 32-bit multiply-add operations
●Compatible with MIPS16™ ASE
●Real-time performance
Minimizes an interrupt response time
(e.g. through one-clock-access RAM)
Instruction/data cache locking function
❈ R3000A and MIPS16 are trademarks of MIPS Technologies, Inc.
●Optimized design implemented
using a low-power cell library
●Power saving modes
Clock gearing function (Reduced-Frequency mode)
Various standby modes
●Implemented with the TC240 technology process
●Requires a very small die area
●Upgrading development tools
Avoids performance degradation by executing the
next instruction while the data cache is being refilled.
The TX19 family is an extremely compact, high-performance 32-bit microprocessor developed by
Toshiba based on the MIPS R3000A architecture. The TX19 family added support for MIPS16™ Application-
Specific Extension (ASE), a highly efficient code compression mechanism, to the TX39 family. Toshiba has
been introducing application-specific standard products (ASSPs) in stages that integrate the TX19
processor core and various peripheral building blocks on the same chip. In addition, the TX19 processor
core can be used in ASIC designs for high-performance embedded systems.
Improved
density
Fast
response
CPU core
CPU Core
Built-in
Provides performance gains.
Object-compatible with TX39.
Supports multiply-add
and coprocessor instructions.
● Handheld devices: Personal information communicators (PIC),
electronic organizers, digital cellulars
● PC peripheral equipment: HDD, DVD-ROM, printers
● Home appliances: DVD players, DVC-based systems,
digital still cameras (DSC)
Provides excellent code density.
Supports PC-relative instructions.
32-bit
instruction
code
Switched
by
an instruction
16-bit
instruction
code
Suitable
for
embedded
applications
Intermixing 16-and 32-bit instructions provides all
the performance benefits of an embedded 32-bit
microprocessor while offering reduced code size
associated with the 16-bit instruction set.
4215/MRP
7
■ Applications ■ Reduction of Power Dissipation
■ Serial Printer Block Diagram ■
Examples of Low-Power Design Techniques
The 900 family is a high-performance 16-bit microcontroller (MCU) with high C code efficiency. The 900
family offers a wide range of features to fit a variety of requirements for different products ranging from
office equipment such as printers and facsimiles to high-end consumer electronic products like digital still
cameras (DSC) and DVC-based systems to portable equipment that mandates low power dissipation. To
significantly reduce the time and expense of controller design, a wide range of powerful and consistent
development tools are available from Toshiba and several third-party development tool vendors.
The 900 family contains two product series: high-performance 900/H and low-power, low-noise 900 /L1.
(Relative to Toshiba's previous microcontrollers)
High-Performance CISC Core
Suitable for high-end office equipment Suitable for applications
with low-power and low-noise requirements
Compact Core
Low Power
(
900/L1
)
●
Minimum instruction execution time:
160 ns (at 25 MHz)
●
32-bit ALU
●
4-bit barrel shifter
Tentative Specifications
●
Operating voltage range: 1.8 to 5.5 V
●
Minimum instruction execution time:
250 ns (at 16 MHz, Vcc ≥ 2.7 V)
400 ns (at 10 MHz, Vcc ≥ 1.8 V)
●
Low power dissipation: 3.0 mA typical
(16 MHz, 3.0V, NORMAL mode)
●
Clock gearing function: (fc, fc/2, fc/4, fc8, fc/16)
●
Dual clock function
●
Three standby modes
●
Low-power design techniques (e.g. gated clocks)
●
Reduced die size due to a very lean set of
instructions selected for embedded applications
GXT-8500
..........
Printers
CD-ROM drives
Digital still cameras
Digital-video-cassette-based
systems
HDD
Electronic musical instruments
Cellular phones
(mobile phones)
5
10
20
15
Icc
(mA)
900/H
0.6 µm
900/L1
0.6 µm
900/L1
0.4 µm
Conditions: 95CW64 equivalent
ROM: 128 Kbytes
RAM: 4 Kbytes
3 V, 16 MHz, 25˚C
19 mA
6 mA
3 mA
Approx.
Approx.
Decoder
Decoder
Before
Decoder
Decoder
Precharge
Signal Precharge
Signal
900/L1
Clock
SIO
H
L
H
L
Timer
INTC
L
The enabling and disabling
of the clock can be controlled
via this signal.
Control
Logic
RAM and ROM Gated-Clock Logic
Head Driver
Paper Sensor
Data BusAddress Bus
Display LED Operation Switches
Memory Gate Array Motor Driver
Carriage
Detection
Head
MCU
900/H Series
Interface
Host Computer
8
■ RISC ASIC Configurations
■ Application Example
The RISC ASIC allows designers to integrate a TX System RISC megacell (or system CPU) with
peripheral IP cores and/or user-defined logic on one chip.
The integral G-bus directly connects system components together, such as a DMA controller acting as a
bus master, a memory controller, a interrupt controller, etc. The specification of G-bus is provided to
users of a TX System RISC megacell.
Low-speed peripherals like a timer and a UART block are connected through IM-Bus via a bridging logic.
Currently, the TX System RISC megacells are
available in two versions: GR39WAD which
integrates a TX39 CPU core with a Address
Protection Unit (APU), Write Buffer Unit (WBU),
and a Debug Support Unit (DSU) and
PTX3904A which is functionally equivalent to
TX3904A. The high-performance megacell,
PTX39WAD, is in development using the
TC240 technology.
The TX39-based ASIC chip requires a pack-
age with at least 160 pins.
RISC ASIC
Memory,
High-Speed
Peripheral
(e.g. DMAC)
Low-Speed
Peripheral
(e.g. Timer)
External
Bus Interface
CPU Core
Instruction Cache
G-Bus Interface
IM-Bus Bridge
G-Bus IM-Bus
Data Cache
DSU
WBU
APU
Debug
(
Support
)
Unit
Write
(
Buffer
)
Unit
Address
(
Protection
)
Unit
MPU ASIC Core
Photo of the TC81220F
Digital BS Receiver
MPEG-2 Decoder IC:
TC81220F
Toshiba's TC81220F integrates a TX39 core, a
MPEG-2 video decoder, a MPEG-1/2 audio
decoder, a programmable transport processor,
standard peripherals, a memory controller, etc.
9
■ CISC ASIC Configurations
■ Application Example
The CISC ASIC offers a megacell, SMC95C001, which integrates a 900/H core with such built-in
functions as a chip-select/wait controller and an interrupt controller. The SMC95C001 is functionally
equivalent to Toshiba's standard product TMP95C001.
The TLCS-900/H Bus, which is the standard bus specification for all 900/H products, connects the 900/H
core with memories (RAMs, ROMs, etc.), peripheral I/O functions, and user-defined logic.
The TLCS-900/H Bus is routed off-chip, so the same emulator can be used to test both the standard
TMP95C001 product and 900/H core-based ASICs.
Communications IC Implemented as a CISC-Processor-Core-Based ASIC
Toshiba used its CISC ASIC solution to integrate
a 900/H core with ROM, RAM, standard
peripherals, and A/D converters to build a
communications IC. This IC is fabricated using
the TC222C technology. While the I/O interfaces
with 3 V, the core operates at 2 V, reducing
power dissipation.
CISC ASIC
Memory Peripheral
CPU Core
Chip Select /
Wait Controller
TLCS-900/H
ASIC Bus
Interrupt Controller
MPU ASIC Core
User-Defined
Logic
10
■ IP Core Availability
(Cores in development are included.)
A broad range of high-density, high-performance IP cores is an essential element for
the success of advanced ASIC designs for all consumer, communications, and data
processing applications.
For true systems-on-a-chip, the supporting ASIC silicon technologies cover a full spectrum of application
requirements with a wide range of power, density, and speed solutions.
IP core offerings meet the requirements of system chips. Hardware IP libraries include cores that
implement RISC and CISC processors as well as multimedia, network, and protocol functions. Software
(or synthesizable) IP libraries include cores that implement middleware functions such as JPEG, speech
processing, and fax modem as well as real-time embedded operating systems and software drivers.
DRAM,
Flash Memory
Toshiba's
Electronic Equipment
Divisions
System Chips
Third-Party
Portable
IP Cores
SoftwareHardware
Image processing MH / MR / MMR, JBIG, JPEG
Audio processing ADPCM, CELP
Human-machine interface
Speech recognition, Speech synthesis,
Handwriting recognition
Communication and PC interface
Software modems, IEEE1394, USB, IrDA,
PCMCIA, TCP/IP, PPP, SNMP, DOS filesystem
µITRON/UDEOS, pSOSystem
®
, Windows
®
CE, Tornado
™
Middleware
RISC Processors
CISC Processors
Peripherals
Analog Cores
Memory
Standard ASIC Cells
Multimedia
Protocols
High-Performance I/O
Networking
Real-time
Embedded OSes
IEEE1394, IEEE1284, PCI controller, TCP/IP,
USB, IrDA (V1.1), PCMCIA, CardBUS, AGP, SSFDC interface, ATAPI
622MHz SCI-LVDS, SSTL-3 (SDRAM interface), 66 MHz PCI,
USB, AGP, Direct RAC (1.6 GBps Rambus
™
ASIC cell)
TX49 (64-bit), TX39 (32-bit), TX19 (32-bit),
TLCS-900 (16-bit), TLCS-Z80 (8-bit)
DRAM controller, ROM controller, Interrupt controller, Timer, DMAC,
Serial interface (UART), Parallel interface, External bus interface
A/D converters, D/A converters, PLL
DRAM, SRAM, FIFO, ROM, E
2
PROM, Flash E
2
PROM
Primitive cells, I/O cells
JPEG core, MPEG-2 decoder, NTSC/PAL video encoder, MPEG-4 core
Ethernet 10/100 MHz MAC, Ethernet 100 MHz PHY, 155 MHz CDR
System Chips
(ASSPs)
Microcomputers,
ASICs
✽ Company names and product names may be trademarks or registered trademarks by their respective companies.
11
■ Seamless Co-verification Flow
TX39
Model
Peripheral
Logic
TX39
Co-verification Using the CAE Plus Tools Co-verification Using the Mentor Graphics Tools
Memory
C/C++
Compiler
Cygnus Solutions
Mentor Graphics Corp. Cadence Design
Systems, Inc.
Mentor Graphics Corp.
Mentor Graphics Corp.
Debugger
XRAY
®
Seamless CVE
Verilog-XL
ModelSim
Software Hardware
C Source RTL Code
TX39 Model Peripheral Logic
Model
C/C++
Compiler
Green Hills Software, Inc.
Green Hills
Software, Inc.
Debugger
MULTI
®
Software
C Source
ASVP Lab
CAE Plus, Inc.
CAE Plus, Inc.
ArchGen
Hardware
Data Flow
The traditional approach to the development of system chips with an embedded CPU core is usually
a series of sequential and independent steps. This means system development is fragmented into
task-oriented specialties like hardware and software designs. Detailed analysis of interactions between
hardware and software is only possible after hardware prototyping. While software errors are relatively
easy to fix, errors in hardware can cause significant delays if design rework is needed. Today's
increasingly complex designs and shortened design cycles make the traditional approach unsuitable.
The hardware/software co-verification environment addresses the problems of the traditional design
cycle by linking software and hardware verification together. Toshiba supports ASVP Lab from CAE
Plus and Seamless CVE from Mentor Graphics by offering the C model of the TX39 core. ASVP Lab
provides all-C model hardware and software debugging by assembling ArchGen C models of user-
defined logic and the TX39 C model into a high-speed virtual prototype. Seamless CVE delivers high-
performance system verification environment by combining embedded software development tools with
behavioral and logic simulation.
✽ Company names and product names may be trademarks or registered trademarks by their respective companies.
System Development
Software Implementation Hardware Implementation
C Source Code RTL Code
int caller (int Pl)
{
int total;
total=Pl;
.
.
.
always@(DATA) begin
F=0;
F[DATA]=l'bl;
end .
.
.
12
■ Development Flow
The following flowchart shows a typical process for developing an ASIC with an integrated TX39 family
RISC processor core, GR39WAD. For support of EDA tools not shown in the flowchart, please contact
your local Toshiba customer support group.
✽ Company names and product names may be trademarks or registered trademarks by their respective companies.
●
System software design
●
Applications software design
●
Prototype board test
■
C/C++ compiler
■
Debugger
■
TX39 standard board
■
Processor probe
■
ROM emulator
■
Real-time operating system
Software Design
●
Hardware design
Verilog RTL coding
●
Test logic insertion
Verilog RTL coding
●
Verification environment modeling
Verilog RTL coding
●
System simulation
✦
●
Test vector development
■
Cadence Verilog-XL
■
Megacell RTL library
■
Megacell test vectors
Tools and libraries used
✦: Recommended hardware platform
Sun UltraSPARC
with LAN interface or equivalent
Main memory: 512 Kbytes
Hard disk: 3 Gbytes
CD-ROM drive
Tape streamer
Wafer Personalization and Testing
Hardware and Software Partitioning
System Specification
System Design
■
VSO megacell models
■
ASIC libraries
■
Verilog-XL Sign-Off (VSO)
System software
Back-annotation files
derived from chip layout
Deliverables
from Toshiba
●
Synthesis parameter tuning
●
Array sizing
✦
/
Critical path extraction
✦
●
Gate-level simulation
✦
■
Synopsys
Design Compiler
and Design Analyzer
■
ASIC libraries
■
VSO megacell models
Logic Synthesis
and Optimization
First Signoff
Resimulation
Second Signoff
Engineering Sample Shipment
■
ASIC documentation set
■
TX39 User's Manual
■
TX39 Programming Guide
■
GR39WAD Megacell
Specification
■
IP core specifications
■
Megacell RTL library
■
Megacell test vector set
13
There are two issues for testing of a chip with embedded blocks such as an MPU core. One is testing
of the block itself. In the case of a large, complex block like an MPU core, it is necessary to test the
block separately from the rest of the chip. The figure below shows a direct access approach where the
MPU core is isolated from the user-defined logic by providing an access collar around it. All inputs and
outputs of the MPU core are made directly accessible and observable for testing by connecting
multiplexers to package pin test points. A test vector set for the stand-alone test of an embedded core is
provided by Toshiba.
Toshiba Users
Testability Design Package
●
Test structure guidebook
●
Test structure examples (Verilog RTL coding)
●
MPU test vector set
●
Netlist / Test vector
●
List of I/O pin assignment for MPU testing
●
Testability design
●
Signoff simulation (First signoff, Second signoff)
■ Testability Design Flow
Test structures need to be designed as part of the user-defined logic.
Test structure examples coded at RTL are provided by Toshiba.
An automated test synthesis system is being planned.
■ Isolating the MPU Core
RISC/CISC ASIC
MUX
User Logic
MPU ASIC Core
Stand-alone Testing of the MPU
Peripheral
CPU Core
MUX
RISC/CISC ASIC
MPU ASIC Core
Testing of the User-Defined Logic
Peripheral
CPU Core
MUX
User Logic
MUX
✽ Company names and product names may be trademarks or registered trademarks by their respective companies.
The MPU core is isolated from the rest of the design during testing. Test vectors for the MPU core are provided
by Toshiba and multiplexed through a set of I/O pins. The flow of data while the MPU core is tested is shown
by the bold paths below.
The user-defined logic is isolated from the MPU core for testing purposes. Test vectors for the user-defined
logic are created by the designer, and internal signals are routed as necessary to ASIC I/O pins to improve
testability. The flow of data while the user-defined logic is tested is shown by bold paths below.
14
Hewlett-Packard Company
E5900A, E5901A
E5902A, E5903A
Lightwell Co., Ltd.
MDX700
DENSAN Systems, Inc.
DVE-R3900
DVE-R3904/20
Emulators Monitors / Evaluation Boards
Integrated Systems, Inc.
(Green Hills Software + MULTI
[1.8.7C]
)
pRISM+
■ Software Development Environment
Exactly the same suite of tools are supported for the software development of RISC
ASICs as for standard TX family products. To significantly reduce the time and expense of processor-
based design, a wide range of powerful and consistent development tools, including compilers,
debuggers, real-time operating systems, and processor probes, are available from Toshiba and several
third-party development tool vendors.
✽ Company names and product names may be trademarks or registered trademarks by their respective companies.
Ethernet
PC
(IBM-PC)
EWS
(Sun, HP)
✽
1
✽
2
■
Emulation Solution
or ROM Emulator
Processor Probe / ROM Emulator Connection
✽1 Only PCs are supported as a host of the ROM emulator.
✽2 The ROM emulator can operate
over a dedicated RS232C parallel interface.
✽3
TX39
/
H2
(in development): 10 pins for debugging
■
Real-time OS
●
µITRON
●
C Executive
●
Tornado
●
pSOSystem
8
X Windows System
Windows® 9 5/NT
TX39 ASIC
Memory
Target Board
TX39 Core
User-Defined
Logic
Debug Support
Unit (DSU)
4 kgates (DSU) + 8 dedicated pins
✽
3
Real-time Debug Support System
The DSU is built into the TX39 core, and permits monitoring of the internal
TX39 core state provided its eight debug pins are routed to ASIC I/O. This
results in debug break exceptions or triggers, enabling the use of general-
purpose real-time debuggers for TX39-core-based ASIC development.
■
GHS Language Tools
■
Cygnus Solutions
GNU Language Tools
Debuggers
Cygnus Solutions
GNU Debugger
Third-Party Development Tools for TX39
Cygnus Solutions
GNU C/C++gcc
Language Tools
Wind River Systems, Inc.
Tornado
™
Real-time OS
Green Hills Software, Inc.
MULTI
®
Green Hills Software, Inc.
C/C++ Compiler
Integrated Systems, Inc.
pSOSystem
®
15
■ Third-Party Development Tools
Language Tool
Debugger
TX39
C/C++ CROSS MIPS COMPILER
MULTI
®
Green Hills Software, Inc.
Real-time OS pSOSystem
®
Integrated Systems, Inc.
Real-time OS Tornado
™
Wind River Systems, Inc.
Evaluation Board DVE-R3904/20
DVE-R3900/20A
DVE-R3900/20
DENSAN Systems, Inc.
Language Tool
Debugger GNU Pro
™
Tool kit
GDB
Cygnus Solutions
Processor Probe HPE3492B
Hewlett-Packard Company
Vendor Tool Product Name
Vendor Tool Product Name
Language Tool
Debugger
TX19
(Under Development)
C/C++ CROSS MIPS COMPILER
MULTI
®
Green Hills Software, Inc.
Real-time OS pSOSystem
®
Integrated Systems, Inc.
Language Tool
Debugger GNU Pro
™
Tool kit
GDB
Cygnus Solutions
Processor Probe HP Distributed Emulation System
Hewlett-Packard Company
In-circuit Emulator IDB Analyzer
Yokogawa Digital Computer
✽ Company names and product names may be trademarks or registered trademarks by their respective companies.
16
■ Software Development Environment
■ Toshiba's Software Development System
Same configuration as for standard CISC products (provided by Toshiba)
PC or EWS MCU Emulator
QFP Probe
Emulation Pod
Adaptor Board
Target Board
CISC ASIC
Method 1: Using an Adaptor Board
Method 2: Using an ASIC on the Board
PC or EWS
C Compiler OS
MCU Emulator
Connector
Emulation Pod
Target Board
(Breadboard)
CISC ASIC
C Compiler OS
Real-time OS Assembler, C Compiler Debugger model 25 model 15
TLCS-900/H
■ Third-Party Software Development Tools
TMP95C001F
Note: For details, please consult the
Microcomputer DEVEOPMENT SYSTEM GUIDE
brochure.
Supported MCU
Product
Real-time Emulator
Embedded
Software Controller Test ToolLanguage Tool
Assembler
C Compiler
Simulator Debugger
Emulator Debugger
TLCS-900/H
Development kit
C-SPY/S 900
C Compiler
ICE Debugger XASS-V Series
GAIO TECHNOLOGY Co., Ltd.
ADViCEIn-circuit Emulator
Yokogawa Digital Computer
IAR Systems AB
Vendor Tool Product Name
✽ Company names and product names may be trademarks or registered trademarks by their respective companies.
17
In keeping with our overriding commitment to meeting customers' present and future needs, Toshiba
continuously pursues new goals in the exploration of both silicon technologies and design techniques.
For true system-scale integrations, ASIC silicon technologies must cover a full spectrum of application
requirements with a broad range of power, density and speed solutions, complete with support of core
functions and high-performance I/O.
■ Toshiba ASIC Trend
■ Embedded Array Product Lines
■ TC240 Family Product Summary
■ Cell-Based IC Product Lines
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
40 M 80 M
5V
5V
5V
3.3V
3.3V
3.3V 2.5V
2V
100 M 120 M 140 M 160 M
Performance (Hz)
Relative Power Dissipation
(vs. TC160G/E at 5.0 V)
High-Performance and Low-Power ASIC Solutions
60 M
TC220G/C/E
TC200G/C/E
TC240C/E
TC222C
TC160G/E
TC170G/C
TC190G/C
TC180G/C/E
: Supports embedded RISC/CISC cores.
0.3 µm
0.06 ns
0.14 ns
2.1 M
512
768
0.41 µW
0.24 µW
40
TC220C
0.4 µm
0.10 ns
0.17 ns
729 k
512
768
0.91 µW
0.48 µW
39
TC200C
0.3 µm
0.06 ns
0.14 ns
2.1 M
504
768
0.41 µW
0.24 µW
40
TC223C
0.4 µm
0.10 ns
0.17 ns
718 k
504
768
0.91 µW
0.48 µW
38
TC203C
Product Family
Process
Delay
Time★
Power
Dissi-
pation★★
★: High-drive 2-input NAND gate
★★:
µW/gate/MHz (2, 3.3, or 5 V), ND2: 2-input NAND, NR2R: Low-power 2-input NAND
Fanout = 2
+ typical interconnect
Fanout = 1
ND2 (Fanout = 1)
ND2R (Fanout = 1)
I/O
Pads TAB
Wirebond
Usable Random Gates
Masterslices
I/O: 3.3 V
Core: 3.3 V I/O: Mixed 3.3/5 V
Core: 3.3 V
0.3 µm
0.07 ns
0.15 ns
1.9 M
512
768
0.65 µW
38
TC220E
0.4 µm
0.11 ns
0.19 ns
704 k
512
776
1.14 µW
39
TC200E
0.3 µm
0.07 ns
0.15 ns
193 k
504
768
0.65 µW
40
TC223E
0.4 µm
0.11 ns
0.19 ns
694 k
504
768
1.14 µW
38
TC203E
Product Family
Process
Delay
Time★
★: High-drive 2-input NAND gate
★★: µW/gate/MHz (3.3 or 5 V), 2-input NAND, fanout = 1
Note: The above tables give only the product families supporting embedded RISC and CISC cores.
Fanout = 2
+ typical interconnect
Fanout = 1
I/O
Pads TAB
Wirebond
Usable Random Gates
Power Dissipation★★
Masterslices
I/O: 3.3 V
Core: 3.3 V I/O: Mixed 3.3/5 V
Core: 3.3 V
GND2X1
77
141
0.156
GND2X2
68
101
0.270
GND2X4
61
79
0.487
CND2XL
87
218
0.107
CND2X1
70
118
0.170
CND2X2
55
83
0.296
CND2X4
54
68
0.563
Process Technology
Series
Cell Name★★
Delay Time (ps)
Power Dissipation (µW/MHz, Fanout = 1)
Operating Voltage
★: Depends on design configurations.
★★: ❑ND2X1: 2-input NAND gate, ✕1 drive ❑ND2X2: 2-input NAND gate, ✕2 drive ❑ND2X4: 2-input NAND gate, ✕4 drive ❑ND2XL: 2-input NAND gate, ✕1/2 drive
Fanout = 1 + typical interconnect
Fanout = 1
Maximum Usable Gates★ (with four metals)
0.25 µm
HC2MOS Si-gate five layer metal
Embedded Arrays Cell-Based IC
8.8 Mgates 10.2 Mgates
Core: 2.5 V
I/O: 2.5 V/3.3 V
18
PQFP
44 – 304 pins
4.45 mm
LQFP
48 – 208 pins 1.6 mm
TQFP
64 – 128 (176) pins 1.2 mm
TBGA
256 – 576 (840) pins 1.4 mm
Packages with lead counts shown in parentheses are under development.
BGAs provide the highest I/O-to-body-size ratio, with solder
balls formed on the bottom in an area array format and a ball
pitch of 1.27 or 0.8 mm. In spite of increased ball pitches,
BGAs result in smaller footprints than PQFPs. The photo at right
shows an FBGA and a TBGA, in contrast to PQFPs with the
same lead counts. Formally known as chip scale packages
(CSPs), the fine-pitch BGA (FBGA) is generally defined as
having a package body size no larger than 1.2 times the die
size. Tape BGA (TBGA) packages support ultra-high pin count
applications. TBGAs combine the fine die pad pitch
interconnect advantages of TAB with the assembly ease of
BGAs. The center balls of the TBGA is
depopulated to allow room for the face-
down TAB bonded and encapsulated die.
LQFP and TQFP packages provide a thin,
lightweight surface mount solution to
system miniaturization. The package
height is 1.4 mm (seating height = 1.6
mm) for the LQFP lines and 1.0 mm
(seating height = 1.2 mm) for the ultra-thin TQFP lines. Also, TBGAs support both the low-profile and ultra-high-pin-count requirements. With
their excellent heat dissipation, low profile, and low cost, TBGAs can handle a wide variety of applications.
■ High-Density Packages
■ Thin and Light Packages
■ Lead Count Chart
144 Pins
FBGA
0.8 mm-pitch PQFP
0.5 mm-pitch TBGA
1.27 mm-pitch PQFP
0.5 mm-pitch
304 Pins
100 200 300 400 500 600 700 800 900
1.0 mm
0.8 mm
0.65 mm
0.5 mm
0.65 –
0.5 mm
0.5 mm
0.4 mm
0.5 mm
0.4 mm
0.65 mm
0.5 mm
0.4 mm
0.8 mm
2.54 mm
1.5 –
1.27 mm
0.5 –
0.4 mm
1 .27 mm
1 .0 mm
0.8 mm
0.8 mm
0.5 mm
PQFP
LQFP
TQFP
LQFP
[Cu]
TQFP
[Cu]
PQFP
[Cu]
PQFP
[TAB/Cu]
HQFP
CPGA
2.54 mm
CPGA
[CD]1 .27 mm
PBGA
TBGA
PFBGA
(CSP)
CQFP 0.65 mm
0.5 mm
0.65 mm
0.5 mm
CQFP
[A N]
0.5 mm
0.4 mm
0.5 mm
0.4 mm
304 420 480 576256 352
336 400 480 560 648 768
432 620520 720 840
225 256
R100
100 120 128
144 160
176
184
100 144 176 208 240 304
101 121 145 181 225
160 184
169
48 64 80 100 144
12064 100 144
64
R64
80 100
85 14197 205201 241109
177 209 241 305 337273
145 181177 217 301
160
44 60 R80100 120
120
64 69
184
208 240
296
100
144
176
208
208 240 304
155 223 299
160
208 240 304
160
208 240 304
85
144 176
176128 144 208
144
176 216 256
256
391
Package
Family Lead Pitch
# I/O
: Available
Not all die sizes are available with all packaging options. When your need for an ASIC arises,
please contact the nearest ASIC service group.
: In Development : Planned
19
■ Brochures
■ TX39
■ TX19
■ TX49
■ TLCS-900/H and TLCS-900/L1
■ Design Handbooks
●
CMOS ASICs Product Guide
●
ASIC Packaging
●
32-Bit TX System RISC TX19 Family
●
32-Bit TX System RISC TX39 Family
●
64-Bit TX System RISC TX49 Family
●
Microcomputers Product Guide
●
Microcomputer Development System Guide
●
32-Bit RISC Microprocessor TLCS-R3900 Family (Architecture TMPR3901F)
●
32-Bit TX System RISC TX39 Family User's Manual (Hardware)
●
32-Bit TX System RISC TX39 ASIC Design Guide
●
32-Bit TX System RISC TX19 User's Manual (Architecture)
●
64-Bit RISC Microprocessor TX49 User's Manual
●
16-Bit Microcontroller TLCS-900/H Series User's Manual (1)
●
Development System Manual (ASSEMBLER)
●
Development System Manual (C COMPILER)
●
Microcomputer Development System Real-time OS (User's Manual)
●
16-Bit Microcontroller TLCS-900/H, TLCS-900/L APPLICATION NOTE
●
User's manuals for various EDA tools
●
CMOS ASIC Design Manual
●
Design-for-Test Handbook
●
ASIC Packaging
©1999 TOSHIBA CORPORATION
Printed in Japan
Electronic Devices Sales & Marketing Group
1-1, Shibaura 1-chome, Minato-ku, Tokyo, 105-8001, Japan
Tel: (03)3457-3405 Fax: (03)5444-9431
OVERSEAS SUBSIDIARIES AND AFFILIATES
Toshiba America
Electronic Components, Inc.
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3100 Arapahoe Avenue, Ste. 500,
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Tel: (303)442-3801 Fax: (303)442-7216
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Tel: (561)374-6193 Fax: (561)374-6194
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One Pkwy., North, Suite 500, Deerfield,
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Tel: (847)945-1500 Fax: (847)945-1044
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3700 Crestwood Parkway, Ste. 460,
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Tel: (770)931-3363 Fax: (770)931-7602
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Tel: (949)453-0224 Fax: (949)453-0125
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Tel: (972)480-0470 Fax: (972)235-4114
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Tel: (02)750-5510 Fax: (02)750-5511
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Hong Kong Head Office
Level 11, Top Glory Insurance Building, Grand Century
Place, No.193, Prince Edward Road West,
Mong Kok, Kowloon, Hong Kong
Tel: 2375-6111 Fax: 2375-0969
Beijing Office
Rm 714, Beijing Fortune Building,
No.5 Dong San Huan Bei-Lu, Chao Yang District,
Beijing, 100004, China
Tel: (010)6590-8795 Fax: (010)6590-8791
Chengdu Office
Unit F, 18th Floor, New Times Plaza, 42 Wenwu Road,
Xinhua Avenue, Chengdu, 610017, China
Tel: (028)675-1773 Fax: (028)675-1065
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Rm 3010-3012, Office Tower Shun Hing Square,
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Tel: (0755)246-1582 Fax: (0755)246-1581
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Co., Ltd.
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Corporation
Taipei Head Office
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Tel: (02)514-9988 Fax: (02)514-7892
Kaohsiung Office
16F-A, Chung-Cheng Bldg., Chung-Cheng 3Rd.,
80027, Kaohsiung, Taiwan R.O.C.
Tel: (07)222-0826 Fax: (07)223-0046
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products.
No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others.
TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices
in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility
of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction
or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs,
please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products
specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability
Handbook.
990426(B)
The products described in this document may include products subject to the foreign exchange and foreign trade laws.
