1
¡ Semiconductor MSC2343257A-xxBS8/DS8
101
¡ Semiconductor
MSC2343257A-xxBS8/DS8
4,194,304-Word ¥ 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The Oki MSC2343257A-xxBS8/DS8 is a fully decoded 4,194,304-word ¥ 32-bit CMOS dynamic
random access memory composed of eight 16-Mb DRAMs (4M ¥ 4) in SOJ. The mounting of eight
DRAMs together with decoupling capacitors on a 72-pin glass epoxy SIMM Package supports
any application where high density and large capacity of storage memory are required.
FEATURES
• 4,194,304-word ¥ 32-bit organization
• 72-pin SIMM
MSC2343257A-xxBS8 : Gold tab
MSC2343257A-xxDS8 : Solder tab
• Single 5 V supply ±10% tolerance
• Input : TTL compatible
• Output : TTL compatible, 3-state, nonlatch
• Refresh : 2048 cycles/32 ms
•CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Fast Page Mode with EDO capability
PRODUCT FAMILY
Family Access Time (Max.) Cycle Time
(Min.)
Power Dissipation
Operating (Max.)
Standby (Max.)
tRAC
MSC2343257A-70BS8/DS8 4840 mW 44 mW
tAA tCAC
70 ns 35 ns 20 ns 130 ns
MSC2343257A-60BS8/DS8 5280 mW
60 ns 30 ns 15 ns 110 ns
MSC2343257A-xxBS8/DS8 ¡ Semiconductor
102
PIN CONFIGURATION
MSC2343257A-xxBS8/DS8
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1V
SS 16 A4 31 A8
Pin No.
Pin Name
46 NC
Pin No. Pin Name
67 PD1
Pin No.
Pin Name
61 DQ13
2 DQ0 17 A5 32 A9 47 WE 62 DQ30
3 DQ16 18 A6 33 NC 48 NC 63 DQ14
4 DQ1 19 A10 34 RAS2 49 DQ8 64 DQ31
5 DQ17 20 DQ4 35 NC 50 DQ24 65 DQ15
6 DQ2 21 DQ20 36 NC 51 DQ9 66 NC
7 DQ18 22 DQ5 37 NC 52 DQ25 67 PD1
8 DQ3 23 DQ21 38 NC 53 DQ10 68 PD2
9 DQ19 24 DQ6 39 VSS 54 DQ26 69 PD3
10 VCC 25 DQ22 40 CAS0 55 DQ11 70 PD4
11 NC 26 DQ7 41 CAS2 56 DQ27 71 NC
12 A0 27 DQ23 42 CAS3 57 DQ12 72 VSS
13 A1 28 A7 43 CAS1 58 DQ28
14 A2 29 NC 44 RAS0 59 VCC
15 A3 30 Vcc 45 NC 60 DQ29
68 PD2
69 PD3
70 PD4
-70BS8/DS8
VSS
NC
VSS
NC
-60BS8/DS8
VSS
NC
NC
NC
MSC2343257AMSC2343257A
Presence Detect Pins
Typ.
10.16 Typ.
6.35
101.19 Typ.3.38 ±0.2
107.95 ±0.2
6.35 Typ. 1.04 Typ.
95.25
2.03 Typ.
3.7 Min.
1.27 +0.1
–0.08
5.28 Max.
3.18φ
1.27 ±0.1
72
1
* 1
6.35
*1 The common size difference of the board width 12.5 mm of its height is
specified as ±0.2. The value above 12.5 mm is specified as ±0.5.
25.4 ±0.2
R1.57
(Unit : mm)
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¡ Semiconductor MSC2343257A-xxBS8/DS8
103
BLOCK DIAGRAM
DQ
VCC
A0 - A10
DQ
RAS DQ
CAS
OE
WE DQ
VSS
DQ
VCC
A0 - A10
DQ
RAS DQ
CAS
OE
WE DQ
VSS
DQ
VCC
A0 - A10
DQ
RAS DQ
CAS
OE
WE DQ
VSS
A0 - A10
RAS0
CAS0
WE
VCC
VSS
C1 C8
DQ0
DQ1
DQ2
DQ3
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
VCC
A0 - A10
DQ
RAS DQ
CAS
OE
WE DQ
VSS
DQ
VCC
A0 - A10
DQ
RAS DQ
CAS
OE
WE DQ
VSS
DQ
VCC
A0 - A10
DQ
RAS DQ
CAS
OE
WE DQ
VSS
DQ16
DQ17
DQ18
DQ19
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
VCC
A0 - A10
DQ
RAS DQ
CAS
OE
WE DQ
VSS
DQ4
DQ5
DQ6
DQ7
DQ
VCC
A0 - A10
DQ
RAS DQ
CAS
OE
WE DQ
VSS
DQ20
DQ21
DQ22
DQ23
CAS1
RAS2
CAS2
CAS3
MSC2343257A-xxBS8/DS8 ¡ Semiconductor
104
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Unit
Power Supply Voltage VCC
Input High Voltage
Typ.
Min. Max.
4.5 5.0 5.5 V
(Ta = 0°C to 70°C)
VSS 000V
V
IH 2.4 — 6.5 V
VIL –1.0 — 0.8 V
Input Low Voltage
Capacitance
Parameter Symbol Unit
CIN1 pFInput Capacitance (A0 - A10)
Typ. Max.
—57
(Ta = 25°C, f = 1 MHz)
CIN2 pFInput Capacitance (WE)—65
C
IN3 pFInput Capacitance (RAS0, RAS2)—35
C
IN4 pFInput Capacitance (CAS0 - CAS3)—20
C
DQ pFI/O Capacitance (DQ0 - DQ31) — 16
Note : Capacitance measured with Boonton Meter.
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to VSS VIN, VOUT –1.0 to 7.0 V
Voltage VCC Supply Relative to VSS VCC –1.0 to 7.0 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD8W
Operating Temperature Topr 0 to 70 °C
Storage Temperature Tstg –40 to 125 °C
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¡ Semiconductor MSC2343257A-xxBS8/DS8
105
DC Characteristics
All other pins not
Parameter
MSC2343257A
Unit
Condition
Input Leakage Current
Note
ILI µA
1, 2
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
Symbol
0 V £ VI £ 6.5 V;
under test = 0 V
DOUT disable
0 V £ VO £ 5.5 V
IOH = –5.0 mA
IOL = 4.2 mA
RAS, CAS cycling,
tRC = Min.
RAS, CAS = VIH
RAS, CAS
≥ VCC –0.2 V
RAS cycling,
CAS = VIH,
tRC = Min.
RAS cycling,
CAS before RAS,
tRC = Min.
RAS = VIL,
CAS cycling,
tHPC = Min.
Output Leakage Current
Output High Voltage
Output Low Voltage
Average Power
Supply Current
(Operating)
Power Supply
Current (Standby)
Supply Current
(RAS-only Refresh)
Average Power
Supply Current
(CAS before RAS Refresh)
Average Power
Supply Current
(Fast Page Mode)
Average Power
ILO
VOH
VOL
ICC1
ICC2
ICC3
ICC6
ICC7
µA
V
V
mA
mA
mA
mA
mA
mA
Min.
–80
–10
2.4
0
—
—
—
—
—
—
Max.
80
10
VCC
0.4
880
16
8
880
880
1040
1
1
1, 2
1, 2
1, 3
-70BS8/DS8
Min.
–80
–10
2.4
0
—
—
—
—
—
—
Max.
80
10
VCC
0.4
960
16
8
960
960
1120
MSC2343257A
-60BS8/DS8
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. Address can be changed once or less while RAS=VIL.
3. Address can be changed once or less while CAS=VIH.
MSC2343257A-xxBS8/DS8 ¡ Semiconductor
106
AC Characteristics (1/2)
Parameter
Symbol
Unit
Random Read or Write Cycle Time
Note
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3,10,11
tRC ns
MSC2343257A
Fast Page Mode Cycle Time tHPC ns
Access Time from RAS tRAC ns
Access Time from CAS tCAC ns
Access Time from Column Address tAA ns
Access Time from CAS Precharge tCPA ns
Output Low Impedance Time from CAS tCLZ ns
CAS to Data Output Buffer Turn-off Delay Time
tCEZ ns
Transition Time tTns
Refresh Period tREF ms
RAS Precharge Time tRP ns
RAS Pulse Width tRAS ns
RAS Pulse Width (Fast Page Mode) tRASP ns
RAS Hold Time tRSH ns
CAS Precharge Time tCP ns
CAS Pulse Width tCAS ns
RAS Low to CAS High Delay Time tCSH ns
CAS High to RAS Low Delay Time tCRP ns
RAS to CAS Delay Time tRCD ns
RAS to Column Address Delay Time tRAD ns
Row Address Set-up Time tASR ns
Row Address Hold Time tRAH ns
Column Address Set-up Time tASC ns
Column Address Hold Time tCAH ns
Column Address Hold Time from RAS tAR ns
Column Address to RAS Lead Time tRAL ns
4, 5, 6
4, 5
4, 6
4
7, 8
3
5
6
-70BS8/DS8
MSC2343257A
-60BS8/DS8
4
RAS Hold Time from CAS Precharge tRHCP ns
Min.
130
30
—
—
—
—
0
0
2
—
50
70
70
20
10
10
45
10
20
15
0
10
0
15
45
35
40
Max.
—
—
70
20
35
40
—
20
50
32
—
10k
100k
—
—
10k
—
—
50
35
—
—
—
—
—
—
—
Min.
110
25
—
—
—
—
0
0
2
—
40
60
60
15
10
10
40
10
20
15
0
10
0
10
40
30
35
Max.
—
—
60
15
30
35
—
15
50
32
—
10k
100k
—
—
10k
—
—
45
30
—
—
—
—
—
—
—
Output Hold Time from CAS Low tDOH ns5—5—
RAS to Data Output Buffer Turn-off Delay Time
tREZ ns 7, 8020015
WE to Data Output Buffer Turn-off Delay Time
tWEZ ns 7020015
RAS to Second CAS Delay Time tRSCD ns70 —60 —
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¡ Semiconductor MSC2343257A-xxBS8/DS8
107
AC Characteristics (2/2)
Parameter
Symbol
Unit
Read Command Hold Time
Note
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3,10,11
tRRH
ns
Read Command Hold Time referenced to RAS
tWCS
ns
Write Command Set-up Time
tWCH
ns
Write Command Hold Time
tWCR
ns
Write Command Hold Time from RAS
tWP
ns
Write Command Pulse Width
tRWL
ns
Write Command to RAS Lead Time
tCWL
ns
Write Command to CAS Lead Time
tDS
ns
Data-in Set-up Time
tDH
ns
Data-in Hold Time
tDHR
ns
Data-in Hold Time from RAS
tRPC
ns
CAS Active Delay Time from RAS Precharge
tCSR
ns
RAS to CAS Set-up Time (CAS before RAS)
tCHR
ns
RAS to CAS Hold Time (CAS before RAS)ns
Read Command Set-up Time
tRCH
ns
Min.
0
0
0
15
50
10
20
20
0
15
45
10
10
20
0
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—tRCS
9
9
Min.
0
0
0
10
45
10
15
15
0
15
40
10
10
20
0
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tWPE
Write Command Pulse Width (Output Disable)
ns10 —5—
MSC2343257A
-70BS8/DS8
MSC2343257A
-60BS8/DS8
tWRP
WE to RAS Precharge Time (CAS before RAS)
ns10 —10 —
tWRH
WE Hold Time from RAS (CAS before RAS)
ns10 —10 —
tWTS
RAS to WE Set-up Time (Test Mode)
ns10 —10 —
tWTH
RAS to WE Hold Time (Test Mode)
ns20 —20 —
MSC2343257A-xxBS8/DS8 ¡ Semiconductor
108
See ADDENDUM I for AC Timing Waveforms
Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, access time is controlled by tAA.
7. tCEZ (Max.), tREZ (Max.) and tWEZ (Max.) define the time at which the output achieves
the open circuit condition and are not referenced to output voltage levels.
8. tCEZ and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is an 8-bit parallel test function. CA0, CA1
and CA10 are not used. In a read cycle, if all internal bits are equal, the DQ pin will
indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low
level. The test mode is cleared and the memory device returned to its normal
operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh
cycle.
The 4M ¥ 32 module can be tested as an 1M ¥ 32 module in this test mode.
11. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test
mode parameters are obtained by adding 5 ns to the normal read cycle values.
