SDLS029C − DECEMBER 1983 − REVISED JANUAR Y 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DDependable Texas Instruments Quality and
Reliability
description/ordering information
These devices contain six independent inverters.
Copyright 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
SN5404 . . . J PACKAGE
SN54LS04, SN54S04 . . . J OR W PACKAGE
SN7404, SN74S04 . . . D, N, OR NS PACKAGE
SN74LS04 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
2Y
2A
VCC
3A
3Y
4A
1Y
6A
6Y
GND
5Y
5A
4Y
SN5404 . . . W PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
6Y
NC
5A
NC
5Y
2A
NC
2Y
NC
3A
SN54LS04, SN54S04 . . . FK PACKAGE
(TOP VIEW)
1Y
1A
NC
4Y
4A 6A
3Y
GND
NC
NC − No internal connection
VCC
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
#&! #% -./.010 %% #"" " ""&
!%" ("*" "&' %% (" #&! #&!
#", &" ""%+ %!&" ", %% #""'
SDLS029C − DECEMBER 1983 − REVISED JANUAR Y 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
Tube SN7404N SN7404N
PDIP − N Tube SN74LS04N SN74LS04N
PDIP − N
Tube SN74S04N SN74S04N
Tube SN7404D
7404
Tape and reel SN7404DR 7404
SOIC − D
Tube SN74LS04D
LS04
0°C to 70°CSOIC − D Tape and reel SN74LS04DR LS04
0C to 70 C
Tube SN74S04D
S04
Tape and reel SN74S04DR S04
Tape and reel SN7404NSR SN7404
SOP − NS Tape and reel SN74LS04NSR 74LS04
SOP − NS
Tape and reel SN74S04NSR 74S04
SSOP − DB Tape and reel SN74LS04DBR LS04
Tube SN5404J SN5404J
Tube SNJ5404J SNJ5404J
CDIP − J
Tube SN54LS04J SN54LS04J
CDIP − J Tube SN54S04J SN54S04J
Tube SNJ54LS04J SNJ54LS04J
−55°C to 125°CTube SNJ54S04J SNJ54S04J
−55 C to 125 C
Tube SNJ5404W SNJ5404W
CFP − W Tube SNJ54LS04W SNJ54LS04W
CFP − W
Tube SNJ54S04W SNJ54S04W
LCCC − FK
Tube SNJ54LS04FK SNJ54LS04FK
LCCC − FK Tube SNJ54S04FK SNJ54S04FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT
AOUTPUT
Y
H L
L H
SDLS029C − DECEMBER 1983 − REVISED JANUAR Y 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
Y = A
SDLS029C − DECEMBER 1983 − REVISED JANUAR Y 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics (each gate)
Input A
VCC
Output Y
GND
130 Ω
1 kΩ
1.6 kΩ
’04
4 kΩ
Input
A
VCC
Output
Y
GND
20 kΩ120 Ω
’LS04
8 kΩ
12 kΩ
1.5 kΩ
3 kΩ
4 kΩ
Input
A
VCC
Outpu
t
Y
GND
2.8 kΩ900 Ω
’S04
50 Ω
3.5 kΩ
250 Ω
500 Ω
Resistor values shown are nominal.
SDLS029C − DECEMBER 1983 − REVISED JANUAR Y 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI: ’04, ’S04 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
’LS04 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN5404
SN7404
SN5404
SN7404
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current −0.4 −0.4 mA
IOL Low-level output current 16 16 mA
TAOperating free-air temperature −55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS‡
SN5404 SN7404
UNIT
PARAMETER
TEST CONDITIONS
‡
MIN TYP§MAX MIN TYP§MAX
UNIT
VIK VCC = MIN, II = −12 mA −1.5 −1.5 V
VOH VCC = MIN, VIL = 0.8 V, IOH = −0.4 mA 2.4 3.4 2.4 3.4 V
VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V
IIVCC = MAX, VI = 5.5 V 1 1 mA
IIH VCC = MAX, VI = 2.4 V 40 40 µA
IIL VCC = MAX, VI = 0.4 V −1.6 −1.6 mA
IOS¶VCC = MAX −20 −55 −18 −55 mA
ICCH VCC = MAX, VI = 0 V 6 12 6 12 mA
ICCL VCC = MAX, VI = 4.5 V 18 33 18 33 mA
‡For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§All typical values are at VCC = 5 V, TA = 25°C.
¶Not more than one output should be shorted at a time.
SDLS029C − DECEMBER 1983 − REVISED JANUAR Y 2004
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN5404
SN7404
UNIT
PARAMETER
(INPUT)
(OUTPUT)
TEST CONDITIONS
MIN TYP MAX
UNIT
tPLH
A
Y
RL = 400 Ω,
CL = 15 pF
12 22
ns
tPHL
A
Y
R
L
= 400
Ω
,
C
L
= 15 pF
8 15
ns
recommended operating conditions (see Note 3)
SN54LS04
SN74LS04
SN54LS04
SN74LS04
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current −0.4 −0.4 mA
IOL Low-level output current 4 8 mA
TAOperating free-air temperature −55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54LS04 SN74LS04
UNIT
PARAMETER
TEST CONDITIONS
†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VIK VCC = MIN, II = −18 mA −1.5 −1.5 V
VOH VCC = MIN, VIL = MAX, IOH = −0.4 mA 2.5 3.4 2.7 3.4 V
VOL
VCC = MIN,
VIH = 2 V
IOL = 4 mA 0.25 0.4 0.4
V
V
OL
V
CC
= MIN,
V
IH
= 2 V
IOL = 8 mA 0.25 0.5
V
IIVCC = MAX, VI = 7 V 0.1 0.1 mA
IIH VCC = MAX, VI = 2.7 V 20 20 µA
IIL VCC = MAX, VI = 0.4 V −0.4 −0.4 mA
IOS§VCC = MAX −20 −100 −20 −100 mA
ICCH VCC = MAX, VI = 0 V 1.2 2.4 1.2 2.4 mA
ICCL VCC = MAX, VI = 4.5 V 3.6 6.6 3.6 6.6 mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN54LS04
SN74LS04
UNIT
PARAMETER
(INPUT)
(OUTPUT)
TEST CONDITIONS
MIN TYP MAX
UNIT
tPLH
A
Y
RL = 2 kΩ,
CL = 15 pF
9 15
ns
tPHL
A
Y
R
L
= 2 k
Ω
,
C
L
= 15 pF
10 15
ns
SDLS029C − DECEMBER 1983 − REVISED JANUAR Y 2004
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54S04
SN74S04
SN54S04
SN74S04
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current −1 −1 mA
IOL Low-level output current 20 20 mA
TAOperating free-air temperature −55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54S04 SN74S04
UNIT
PARAMETER
TEST CONDITIONS
†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VIK VCC = MIN, II = −18 mA −1.2 −1.2 V
VOH VCC = MIN, VIL = 0.8 V, IOH = −1 mA 2.5 3.4 2.7 3.4 V
VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V
IIVCC = MAX, VI = 5.5 V 1 1 mA
IIH VCC = MAX, VI = 2.7 V 50 50 µA
IIL VCC = MAX, VI = 0.5 V −2 −2 mA
IOS§VCC = MAX −40 −100 −40 −100 mA
ICCH VCC = MAX, VI = 0 V 15 24 15 24 mA
ICCL VCC = MAX, VI = 4.5 V 30 54 30 54 mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN54S04
SN74S04
UNIT
PARAMETER
(INPUT)
(OUTPUT)
TEST CONDITIONS
MIN TYP MAX
UNIT
tPLH
A
Y
RL = 280 Ω,
CL = 15 pF
3 4.5
ns
tPHL
A
Y
R
L
= 280
Ω
,
C
L
= 15 pF
3 5
ns
tPLH
A
Y
RL = 280 Ω,
CL = 50 pF
4.5
ns
tPHL
A
Y
R
L
= 280
Ω
,
C
L
= 50 pF
5
ns
SDLS029C − DECEMBER 1983 − REVISED JANUAR Y 2004
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 AND 54S/74S DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B
)
V
CC RL
From Output
Under Test
CL
(see Note A)
Test
Point
1 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL
.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Serie
s
54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time, with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D) ≈1.5 V
VOH − 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
tw
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
VOH
VOL
Figure 1. Load Circuits and Voltage Waveforms
SDLS029C − DECEMBER 1983 − REVISED JANUAR Y 2004
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
tPHL tPLH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B
)
V
CC RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 kΩ
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL
.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns
.
G. The outputs are measured one at a time, with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D) ≈1.5 V
VOH − 0.5 V
VOL + 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
tw
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
VOL
VOH
Figure 2. Load Circuits and Voltage Waveforms
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
JM38510/00105BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00105BCA
JM38510/00105BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00105BDA
JM38510/07003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
07003BCA
JM38510/07003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
07003BDA
JM38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
30003B2A
JM38510/30003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003BCA
JM38510/30003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003BDA
JM38510/30003SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003SCA
M38510/00105BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00105BCA
M38510/00105BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
00105BDA
M38510/07003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
07003BCA
M38510/07003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
07003BDA
M38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
30003B2A
M38510/30003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003BCA
M38510/30003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003BDA
M38510/30003SCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
30003SCA
SN5404J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN5404J
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN54LS04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS04J
SN54S04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54S04J
SN7404D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404
SN7404DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7404
SN7404N ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN7404N
SN7404NE4 ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN7404N
SN74LS04D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04DBR ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LS04
SN74LS04DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS04
SN74LS04N ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N
SN74LS04NE4 ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N
SN74LS04NSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS04
SN74S04D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04
SN74S04DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 S04
SN74S04N ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN74S04N
SN74S04NE4 ACTIVE PDIP N 14 25 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN74S04N
PACKAGE OPTION ADDENDUM
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Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74S04NSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74S04
SNJ5404J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5404J
SNJ5404W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5404W
SNJ54LS04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54LS
04FK
SNJ54LS04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS04J
SNJ54LS04W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54LS04W
SNJ54S04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54S
04FK
SNJ54S04J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S04J
SNJ54S04W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54S04W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 4
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN5404, SN54LS04, SN54LS04-SP, SN54S04, SN7404, SN74LS04, SN74S04 :
•Catalog: SN7404, SN74LS04, SN54LS04, SN74S04
•Military: SN5404, SN54LS04, SN54S04
•Space: SN54LS04-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN7404DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LS04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74S04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74S04NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN7404DR SOIC D 14 2500 367.0 367.0 38.0
SN74LS04DR SOIC D 14 2500 367.0 367.0 38.0
SN74S04DR SOIC D 14 2500 367.0 367.0 38.0
SN74S04NSR SO NS 14 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2018
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X .008-.014
[0.2-0.36]
TYP
-15
0
AT GAGE PLANE
-.314.308 -7.977.83[ ]
14X -.026.014 -0.660.36[ ]
14X -.065.045 -1.651.15[ ]
.2 MAX TYP
[5.08] .13 MIN TYP
[3.3]
TYP-.060.015 -1.520.38[ ]
4X .005 MIN
[0.13]
12X .100
[2.54]
.015 GAGE PLANE
[0.38]
A
-.785.754 -19.9419.15[ ]
B -.283.245 -7.196.22[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
78
14
1
PIN 1 ID
(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND
[0.05] MAX.002
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
METAL
(.063)
[1.6]
(R.002 ) TYP
[0.05]
14X ( .039)
[1]
( .063)
[1.6]
12X (.100 )
[2.54]
(.300 ) TYP
[7.62]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
78
14
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
DETAIL B
13X, SCALE: 15X
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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