AIN1
AIN8
MUX T/H
ADC78H90 SCLK
AVDD
AGND
DGND
DVDD
CS
DIN
DOUT
CONTROL
LOGIC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
.
.
.
AGND
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
CS SCLK
AV DD DOUT
AGND DIN
AIN1 DVDD
AIN2 DGND
AIN3 AIN8
AIN4 AIN7
AIN5 AIN6
ADC78H90
ADC78H90
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SNAS227D –NOVEMBER 2003–REVISED MARCH 2013
ADC78H90 8-Channel, 500 kSPS, 12-Bit A/D Converter
Check for Samples: ADC78H90
The ADC78H90 is packaged in a 16-lead TSSOP
1FEATURES package. Operation over the industrial temperature
2• Eight input channels range of −40°C to +85°C is ensured.
• Variable power management Connection Diagram
• Independent analog and digital supplies
• SPI™/QSPI™/MICROWIRE™/DSP compatible
• Packaged in 16-lead TSSOP
APPLICATIONS
• Automotive Navigation
• Portable Systems
• Medical Instruments
• Mobile Communications
• Instrumentation and Control Systems
KEY SPECIFICATIONS Figure 1. 16-Lead TSSOP
• Conversion Rate: 500kSPS See PW Package
• DNL: ± 1LSB (max)
• INL: ± 1LSB (max) Block Diagram
• Power Consumption
– 3V Supply: 1.5 mW (typ)
– 5V Supply: 8.3 mW (typ)
DESCRIPTION
The ADC78H90 is a low-power, eight-channel CMOS
12-bit analog-to-digital converter with a conversion
throughput of 500 kSPS. The converter is based on a
successive-approximation register architecture with
an internal track-and-hold circuit. It can be configured
to accept up to eight input signals at inputs AIN1
through AIN8.
The output serial data is straight binary, and is
compatible with several standards, such as SPI™,
QSPI™, MICROWIRE™, and many common DSP PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
serial interfaces. Pin Equivalent Description
Symbol
The ADC78H90 may be operated with independent No. Circuit
analog and digital supplies. The analog supply (AVDD)ANALOG I/O
can range from +2.7V to +5.25V, and the digital 4 - AIN1 to Analog inputs. These signals
supply (DVDD) can range from +2.7V to AVDD. Normal 11 AIN8 can range from 0V to AVDD.
power consumption using a +3V or +5V supply is 1.5 DIGITAL I/O
mW and 8.3 mW, respectively. The power-down
feature reduces the power consumption to just 0.3
µW using a +3V supply, or 0.5 µW using a +5V
supply.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADC78H90
SNAS227D –NOVEMBER 2003–REVISED MARCH 2013
www.ti.com
PIN DESCRIPTIONS AND EQUIVALENT PIN DESCRIPTIONS AND EQUIVALENT
CIRCUITS (continued) CIRCUITS (continued)
Pin Equivalent Description Pin Equivalent Description
Symbol Symbol
No. Circuit No. Circuit
Digital clock input. The range of Positive analog supply pin. This
frequencies for this input is 50 pin should be connected to a
kHz to 8 MHz, with ensured quiet +2.7V to +5.25V source
16 SCLK performance at 8 MHz. This and bypassed to GND with a 1
2 AVDD
clock directly controls the µF tantalum capacitor and a 0.1
conversion and readout µF ceramic monolithic capacitor
processes. located within 1 cm of the
power pin.
Digital data output. The output
samples are clocked out of this Positive digital supply pin. This
15 DOUT pin on falling edges of the pin should be connected to a
SCLK pin. +2.7V to AVDD supply, and
13 DVDD bypassed to GND with a 0.1 µF
Digital data input. The ceramic monolithic capacitor
ADC78H90's Control Register
14 DIN located within 1 cm of the
is loaded through this pin on power pin.
rising edges of the SCLK pin. The ground return for the
Chip select. On the falling edge 3 AGND analog supply and signals.
of CS, a conversion process
1 CS begins. Conversions continue The ground return for the digital
12 DGND
as long as CS is held low. supply and signals.
POWER SUPPLY
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
Analog Supply Voltage AVDD −0.3V to 6.5V
Digital Supply Voltage DVDD −0.3V to AVDD + 0.3V, max 6.5V
Voltage on Any Pin to GND −0.3V to AVDD +0.3V
Input Current at Any Pin (3) ±10 mA
Package Input Current(3) ±20 mA
Power Dissipation at TA= 25°C See (4)
ESD Susceptibility (5)
Human Body Model 2500V
Machine Model 250V
Soldering Temperature, Infrared,
10 seconds (6) 260°C
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN >VAor VD), the current at that pin should be
limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 10 mA to two.
(4) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax −TA)/θJA. In the 16-pinTSSOP, θJA is 96°C/W, so PDMAX = 1,200mW at 25°C and 625 mW at the maximum
operating ambient temperature of85°C. Note that the power consumption of this device under normal operation is a maximum of 12 mW.
The values for maximum power dissipation listed above will be reached only when the ADC78H90 is operated in a severe fault condition
(e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such
conditions should always be avoided.
(5) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through ZERO ohms
(6) See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any
post 1986 Texas Instruments Linear Data Book, for other methods of soldering surface mount devices.
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Operating Ratings (1)(2)
Operating Temperature Range −40°C ≤TA≤+85°C
AVDD Supply Voltage +2.7V to +5.25V
DVDD Supply Voltage +2.7V to AVDD
Digital Input Pins Voltage Range -0.3V to AVDD
Clock Frequency 50 kHz to 8 MHz
Analog Input Voltage 0V to AVDD
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
Package Thermal Resistance
Package θJA
16-lead TSSOP on 4-layer, 2 oz. PCB 96°C / W
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ADC78H90 Converter Electrical Characteristics (1)
The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 8 MHz, fSAMPLE = 500
KSPS, unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.
Limits
Symbol Parameter Conditions Typical Units
(2)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits
INL Integral Non-Linearity AVDD = +5.0V, DVDD = +3.0V ±1 LSB (max)
DNL Differential Non-Linearity AVDD = +5.0V, DVDD = +3.0V ±1 LSB (max)
VOFF Offset Error AVDD = +5.0V, DVDD = +3.0V ±2 LSB (max)
OEM Offset Error Match AVDD = +5.0V, DVDD = +3.0V ±2 LSB (max)
GE Gain Error AVDD = +5.0V, DVDD = +3.0V ±3 LSB (max)
GEM Gain Error Match AVDD = +5.0V, DVDD = +3.0V ±3 LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
AVDD = +5.0V, DVDD = +3.0V,
SINAD Signal-to-Noise Plus Distortion Ratio 73 70 dB (min)
fIN = 40.2 kHz, −0.02 dBFS
AVDD = +5.0V, DVDD = +3.0V,
SNR Signal-to-Noise Ratio 73 70.8 dB (min)
fIN = 40.2 kHz, −0.02 dBFS
AVDD = +5.0V, DVDD = +3.0V,
THD Total Harmonic Distortion −86 −74 dB (max)
fIN = 40.2 kHz, −0.02 dBFS
AVDD = +5.0V, DVDD = +3.0V,
SFDR Spurious-Free Dynamic Range 88 75.6 dB (min)
fIN = 40.2 kHz, −0.02 dBFS
ENOB Effective Number of Bits AVDD = +5.0V, DVDD = +3.0V, 11.8 11.3 Bits (min)
AVDD = +5.0V, DVDD = +3.0V,
Channel-to-Channel Crosstalk -82 dB
fIN = 40.2 kHz
Intermodulation Distortion, Second AVDD = +5.0V, DVDD = +3.0V, -93 dB
Order Terms fa= 40.161 kHz, fb= 41.015 kHz
IMD Intermodulation Distortion, Third Order AVDD = +5.0V, DVDD = +3.0V, -90 dB
Terms fa= 40.161 kHz, fb= 41.015 kHz
AVDD = +5V 11 MHz
FPBW -3 dB Full Power Bandwidth AVDD = +3V 8 MHz
ANALOG INPUT CHARACTERISTICS
VIN Input Range 0 to AVDD V
IDCL DC Leakage Current ±1 µA (max)
Track Mode 33 pF
CINA Input Capacitance Hold Mode 3 pF
DIGITAL INPUT CHARACTERISTICS
DVDD = +4.75Vto +5.25V 2.4 V (min)
VIH Input High Voltage DVDD = +2.7V to +3.6V 2.1 V (min)
VIL Input Low Voltage DVDD = +2.7V to +5.25V 0.8 V (max)
IIN Input Current VIN = 0V or DVDD ±0.01 ±1 µA (max)
CIND Digital Input Capacitance 2 4pF (max)
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA, DVDD = +2.7V to
VOH Output High Voltage DVDD −0.5 V (min)
+5.25V
VOL Output Low Voltage ISINK = 200 µA 0.4 V (max)
IOZH, IOZL TRI-STATE® Leakage Current ±1 µA (max)
COUT TRI-STATE® Output Capacitance 2 4pF (max)
Output Coding Straight (Natural) Binary
(1) Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
(2) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
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ADC78H90 Converter Electrical Characteristics (1) (continued)
The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 8 MHz, fSAMPLE = 500
KSPS, unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.
Limits
Symbol Parameter Conditions Typical Units
(2)
POWER SUPPLY CHARACTERISTICS (CL= 10 pF)
2.7 V (min)
AVDD,Analog and Digital Supply Voltages AVDD ≥DVDD
DVDD 5.25 V (max)
AVDD = DVDD = +4.75V to +5.25V, 1.65 2.3 mA (max)
fSAMPLE = 500 kSPS, fIN = 40 kHz
Total Supply Current, Normal Mode
(Operational, CS low) AVDD = DVDD = +2.7V to +3.6V, 0.5 2.3 mA (max)
fSAMPLE = 500 kSPS, fIN = 40 kHz
IA+ IDAVDD = DVDD = +4.75V to +5.25V, 200 nA
fSAMPLE = 0 kSPS
Total Supply Current, Shutdown (CS
high) AVDD = DVDD = +2.7V to +3.6V, 200 nA
fSAMPLE = 0 kSPS
\AVDD = DVDD = +4.75V to +5.25V 8.3 12 mW (max)
Power Consumption, Normal Mode
(Operational, CS low) AVDD = DVDD = +2.7V to +3.6V 1.5 8.3 mW (max)
PDAVDD = DVDD = +4.75V to +5.25V 0.5 µW
Power Consumption, Shutdown (CS
high) AVDD = DVDD = +2.7V to +3.6V 0.3 µW
AC ELECTRICAL CHARACTERISTICS
fSCLK Maximum Clock Frequency 8MHz (min)
fSMIN Minimum Clock Frequency 50 kHz
fSMaximum Sample Rate 500 KSPS (min)
tCONV Conversion Time 13 SCLK cycles
40 % (min)
DC SCLK Duty Cycle 50 60 % (max)
tACQ Track/Hold Acquisition Time Full-Scale Step Input 3SCLK cycles
Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles
fRATE Throughput Rate 500 kSPS (min)
tAD Aperture Delay 4 ns
ADC78H90 Timing Specifications
The following specifications apply for AVDD = DVDD = +2.7V to 5.25V, AGND = DGND = 0V, fSCLK = 8 MHz, fSAMPLE = 500
KSPS, CL= 50 pF, Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C. Limits
Symbol Parameter Conditions Typical Units
(1)
Setup Time SCLK High to CS Falling
t1a (2) 10 ns (min)
Edge
Hold time SCLK Low to CS Falling
t1b (2) 10 ns (min)
Edge
t2Delay from CS Until DOUT active 30 ns (max)
Data Access Time after SCLK Falling
t330 ns (max)
Edge
Data Setup Time Prior to SCLK Rising
t410 ns (min)
Edge
t5Data Valid SCLK Hold Time 10 ns (min)
t6SCLK High Pulse Width 0.4 x tSCLK ns (min)
t7SCLK Low Pulse Width 0.4 x tSCLK ns (min)
CS Rising Edge to DOUT High-
t820 ns (max)
Impedance
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by t1a and t1b.
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tCONVERT
tACQ
t6
t7t3
t2
t5
t4
Z3 Z2 Z1 Z0 DB10
DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC
DB11 DB9 DB8 DB1
1687654321
DB0
DIN
DOUT
SCLK
CS
t8
ADC78H90
SNAS227D –NOVEMBER 2003–REVISED MARCH 2013
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Timing Diagrams
Figure 2. Timing Test Circuit
Figure 3. ADC78H90 Operational Timing Diagram
Figure 4. ADC78H90 Serial Timing Diagram
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Figure 5. SCLK and CS Timing Parameters
Specification Definitions
ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold
capacitor to charge up to the input voltage.
APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the
input signal is acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy
from one analog input that appears at the measured analog input.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last
code transition). The deviation of any given code from this straight line is measured from the center of that
code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the
power in the second and third order intermodulation products to the sum of the power in both of the
original frequencies. IMD is usually expressed in dB.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC78H90 is ensured
not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of
the input signal to the rms value of all of the other spectral components below half the clock frequency,
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2
f1
2
f6
2
f2
10
‡A
A++A
logTHD = 20
ADC78H90
SNAS227D –NOVEMBER 2003–REVISED MARCH 2013
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including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal where a spurious signal is any signal present in the output
spectrum that is not present at the input, excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five
harmonic components at the output to the rms level of the input signal frequency as seen at the output.
THD is calculated as
where
• Af1 is the RMS power of the input frequency at the output
• Af2 through Af6 are the RMS power in the first 5 harmonic frequencies (1)
THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the
acquisition time plus the conversion time. In the case of the ADC78H90, this is 16 SCLK periods.
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Typical Performance Characteristics
TA= +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.
DNL DNL
Figure 6. Figure 7.
INL INL
Figure 8. Figure 9.
DNL vs. Supply INL vs. Supply
Figure 10. Figure 11.
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Typical Performance Characteristics (continued)
TA= +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.
SNR vs. Supply THD vs. Supply
Figure 12. Figure 13.
ENOB vs. Supply SNR vs. Input Frequency
Figure 14. Figure 15.
THD vs. Input Frequency ENOB vs. Input Frequency
Figure 16. Figure 17.
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Typical Performance Characteristics (continued)
TA= +25°C, fSAMPLE = 500 kSPS, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.
Spectral Response Spectral Response
Figure 18. Figure 19.
Power Consumption vs. Throughput
Figure 20.
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AIN1
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
AIN8
AVDD/2
AIN1
MUX
AGND
SAMPLING
CAPACITOR
SW1
-
+CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
AVDD/2
SW2
AIN8
ADC78H90
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APPLICATIONS INFORMATION
ADC78H90 OPERATION
The ADC78H90 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter. Simplified schematics of the ADC78H90 in both track and hold
operation are shown in Figure 21 and Figure 22, respectively. In Figure 21, the ADC78H90 is in track mode:
switch SW1 connects the sampling capacitor to one of eight analog input channels through the multiplexer, and
SW2 balances the comparator inputs. The ADC78H90 is in this state for the first three SCLK cycles after CS is
brought low.
There is no power-up delay or dummy conversions with the ADC78H90. The ADC is able to sample and convert
an input to full resolution in the first conversion immediately following power up. The first conversion result after
power up will be that of the first channel.
Figure 22 shows the ADC78H90 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC78H90 is in this state for the last thirteen SCLK cycles after
CS is brought low.
Figure 21. ADC78H90 in Track Mode
Figure 22. ADC78H90 in Hold Mode
The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of
16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is
clocked into the DIN pin to indicate the multiplexer address for the next conversion.
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USING THE ADC78H90
Figure 3 and Figure 4 for the ADC78H90 are shown in Timing Diagrams. CS, chip select, initiates conversions
and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of
serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB
first. Data to be written to the ADC78H90's Control Register is placed on DIN, the serial data input pin. New data
is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when
CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a
power down state when CS is high.
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out, MSB first. If there is more than one
conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising
edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK, where "N" must be an
integer.
When CS is brought high, SCLK is internally gated off. If SCLK is in a low state when CS goes high, the
subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track
mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is in a high state when CS goes high,
the ADC enters the track mode on the first falling edge of SCLK after the falling edge of CS.
During each conversion, data is clocked into the DIN pin on the first 8 rising edges of SCLK after the fall of CS.
For each conversion, it is necessary to clock in the data indicating the input that is selected for the conversion
after the current one. See Table 1,Table 2, and Table 3.
If CS and SCLK go low simultaneously, it is the following rising edge of SCLK that is considered the first rising
edge for clocking data into DIN.
Table 1. Control Register Bits
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC
Table 2. Control Register Bit Descriptions
Bit #: Symbol: Description
7, 6, 2, 1, 0 DONTC Don't care. The value of these bit do not affect the device.
5 ADD2 These three bits determine which input channel will be sampled and converted on the next falling
edge of CS. The mapping between codes and channels is shown in Table 3.
4 ADD1
3 ADD0
Table 3. Input Channel Selection
ADD2 ADD1 ADD0 Input Channel
0 0 0 AIN1 (Default)
0 0 1 AIN2
0 1 0 AIN3
0 1 1 AIN4
1 0 0 AIN5
1 0 1 AIN6
1 1 0 AIN7
1 1 1 AIN8
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AIN1
AIN8
.
.
.MICROPROCESSOR
DSP
SCLK
CS
DIN
DOUT
AGND
AVDD
DVDD
ADC78H90
LP2950 5V
100:
0.1 PF680 nF 1 PF
TANT 0.1 PF 0.1 PF1 PF
DGND
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ADC78H90 TRANSFER FUNCTION
The output format of the ADC89H90 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC78H90 is AVDD / 4096. The ideal transfer characteristic is shown
in Figure 23. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB,
or a voltage of AVDD / 8192. Other code transitions occur at steps of one LSB.
Figure 23. Ideal Transfer Characteristic
TYPICAL APPLICATION CIRCUIT
A typical application of the ADC78H90 is shown in Figure 24. The split analog and digital supplies are both
provided in this example by the TI LP2950 low-dropout voltage regulator, available in a variety of fixed and
adjustable output voltages. The analog supply is bypassed with a capacitor network located close to the
ADC78H90. The digital supply is separated from the analog supply by an isolation resistor and conditioned with
additional bypass capacitors. The ADC78H90 uses the analog supply (AVDD) as its reference voltage, so it is
very important that AVDD be kept as clean as possible. Because of the ADC78H90's low power requirements, it is
also possible to use a precision reference as a power supply to maximize performance. The four-wire interface is
also shown connected to a microprocessor or DSP.
Figure 24. Typical Application Circuit
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SNAS227D –NOVEMBER 2003–REVISED MARCH 2013
ANALOG INPUTS
An equivalent circuit for one of the ADC78H90's input channels is shown in Figure 25. Diodes D1 and D2 provide
ESD protection for the analog inputs. At no time should an analog input go beyond (AVDD + 300 mV) or (GND -
300 mV), as these ESD diodes will begin conducting, which could result in erratic operation.
The capacitor C1 in Figure 25 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor
R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the
ADC78H90 sampling capacitor, and is typically 30 pF. The ADC78H90 will deliver best performance when driven
by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is
especially important when using the ADC78H90 to sample AC signals. Also important when sampling dynamic
signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic performance.
Figure 25. Equivalent Input Circuit
DIGITAL INPUTS AND OUTPUTS
The ADC78H90's digital inputs (SCLK, CS, and DIN) are limited by and cannot exceed the analog supply voltage
AVDD. The digital input pins are not prone to latch-up; SCLK, CS, and DIN may be asserted before DVDD without
any risk.
POWER SUPPLY CONSIDERATIONS
The ADC78H90 has two supplies, although they could both have the same potential. There are two major power
supply concerns with this product. They are relative power supply levels, including power on sequencing, and the
effect of digital supply noise on the analog supply.
Power Management
The ADC78H90 is a dual-supply device. These two supplies share ESD resources, and thus care must be
exercised to ensure that the power supplies are applied in the correct sequence. To avoid turning on the ESD
diodes, the digital supply (DVDD) cannot exceed the analog supply (AVDD) by more than 300 mV. The
ADC78H90's analog power supply must, therefore, be applied before (or concurrently with) the digital power
supply.
The ADC78H90 is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with one
exception: the ADC78H90 automatically enters power-down mode between the 16th falling edge of a conversion
and the 1st falling edge of the subsequent conversion (see Figure 3).
The ADC78H90 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles. The
ADC78H90 will perform conversions continuously as long as CS is held low.
The user may trade off throughput for power consumption by simply performing fewer conversions per unit time.
Figure 20 in Typical Performance Characteristics shows the typical power consumption of the ADC78H90 versus
throughput. To calculate the power consumption, simply multiply the fraction of time spent in the normal mode by
the normal mode power consumption (8.3 mW with AVDD = DVDD = +3.6V, for example), and add the fraction of
time spent in shutdown mode multiplied by the shutdown mode power dissipation (0.3 mW with AVDD = DVDD =
+3.6V).
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
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SNAS227D –NOVEMBER 2003–REVISED MARCH 2013
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Power Supply Noise Considerations
The charging of any output load capacitance requires current from the digital supply, DVDD. The current pulses
required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If
these variations are large enough, they could cause degrade SNR and SINAD performance of the ADC.
Furthermore, if the analog and digital supplies are tied directly together, the noise on the digital supply will be
coupled directly into the analog supply, causing greater performance degradation than noise on the digital
supply. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic
low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground
bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger is
the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into
the analog channel, degrading noise performance.
The first solution is to decouple the analog and digital supplies from each other, or use separate supplies for
them, to keep digital noise out of the analog supply. To keep noise out of the digital supply, keep the output load
capacitance as small as practical. If the load capacitance is greater than 25 pF, use a 100 Ωseries resistor at
the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge
current of the output capacitance and improve noise performance.
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SNAS227D –NOVEMBER 2003–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADC78H90CIMT/NOPB ACTIVE TSSOP PW 16 92 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 78H90
CIMT
ADC78H90CIMTX/NOPB ACTIVE TSSOP PW 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 78H90
CIMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADC78H90CIMTX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADC78H90CIMTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
BNOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
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