DMN2004DWK
Document number: DS30935 Rev. 8 - 2
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October 2020
© Diodes Incorporated
DMN2004DWK
DUAL N-CHANNEL ENHANCEMENT MODE MOSFET
Product Summa r y
BVDSS RDS(ON) max
I
D
TA = +25°C
20V
0.55Ω @ VGS = 4.5V
540mA
Description and Applications
This MOSFET is designed to minimize the on-s tate resistance
(RDS(ON)) and yet maintain superior switching performance, making
it ideal for high-effici ency power managem ent applic at i ons.
• Load Switch
Features
• Dual N-Channel MOSFET
• Low On-Resistance
• Low Gate Threshold Voltage
• Low Input Capacitance
• Fast Switching Speed
• Low Input/Output Leakage
• Ultra-Sm al l Surfac e Mount Package
• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
• Halogen and Antimony Free. “Green” Device (Note 3)
• Qualified to AEC-Q101 Standards for High-Reliability
• An Automotive-Comp li ant Part is Available Under
Separate Datasheet (DMN2004DWKQ)
Mechanical Data
• Case: SOT363
• Case Material: Molded Plast ic, “Green” Molding Com pound.
UL Flammabilit y Classification Rating 94V-0
• Moisture Sensitivi t y: Level 1 per J-STD-020
• Terminal Connecti ons: See Diagram
• Terminals: Finish - Matte Tin Annealed over Alloy 42 Lead-
Frame. Solderable per MIL-STD-202, Method 208
• Weight: 0.006 grams (Approximate)
Ordering Information (Note 4)
Case
Packaging
SOT363
3,000/Tape & Reel
Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.
2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
4. For packaging details, go to our website at https://www.diodes.com/design/support/packaging/diodes-packaging/.
Marking Information
Date Code Key
Year
2006
2007
….
2020
2021
2022
2023
2024
2025
2026
2027
2028
Code
T
U
….
H
I
J
K
L
M
N
O
P
Month
Jan
Feb
Mar
Apr
May
Jun
Jul
Aug
Sep
Oct
Nov
Dec
Code
1
2
3
4
5
6
7
8
9
O
N
D
SOT363
Top View
Top View
Internal Schematic
S
1
D
1
D
2
S
2
G
1
G
2
ESD PROTECTED TO 2kV
NAB YM
NAB YM
e3
NAB = Product Type Marking Code
YM = Date Code Marking
Y
or Y = Year (ex: H = 2020)
M = Month (ex: 9 = September)
DMN2004DWK
Document number: DS30935 Rev. 8 - 2
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October 2020
© Diodes Incorporated
DMN2004DWK
Maximum Ratings (@ TA = +25°C, unless otherwise speci fied.)
Characteristic
Symbol
Value
Unit
Drain-Source Voltage
VDSS
20
V
Gate-Source Voltage
VGSS
±8
V
Drain Current (Note 5) Steady
State TA = +25°C
TA = +85°C
ID 540
390 mA
Pulsed Drain Current (Note 6)
IDM
1.5
A
Thermal Characteristics (@ TA = +25°C, unless otherwise specified. )
Characteristic
Symbol
Value
Unit
Total Power Dissipation (Note 5)
PD
200 mW
Thermal Resistance, Junction to Ambient
RθJA
625 °C/W
Operating and Storage Tem perature Range
TJ, TSTG
-55 to +150
°C
Electrical Characteristics (@ TA = +25°C, unless otherwise specified.)
Characteristic
Symbol
Min
Typ
Max
Unit
Test Condition
OFF CH ARACTERISTICS (Note 7)
Drain-Source Breakdown Voltage
BVDSS
20
—
—
V
VGS = 0V , ID = 10µA
Zero Gate Voltage Drain Current I
DSS
— — 1 µA V
DS
= 16V, V
GS
= 0V
Gate-Source Leakage I
GSS
— — ±1 µA V
GS
= ±4.5V, V
DS
= 0V
ON CHARACTERIS TICS (Note 7)
Gate Threshold Voltage
V
GS(TH)
0.5
—
1.0
V
V
DS
= V
GS
, I
D
= 250µA
Static Drain-Source On-Resistance RDS(ON) — 0.4
0.5
0.7
0.55
0.70
0.9 Ω
VGS = 4.5V, ID = 540mA
VGS = 2.5 V, ID = 500mA
VGS = 1.8 V, ID = 350mA
Forward Transfer Admittance
|Yfs|
200 — — mS
VDS =10V, ID = 0 .2A
Diode Forward Voltage (Note 7)
VSD
0.5
—
1.4
V
VGS = 0V , IS = 115mA
DYNAMIC CH ARACTERISTICS (Note 7)
Input Capacitance
Ciss
—
36
150
pF
VDS = 16V, VGS = 0V
f = 1.0MHz
Output Capacitance
Coss
—
5.7
25
pF
Reverse Transfer Capaci t ance
Crss
—
4.2
20
pF
Total Gate Charge (V
GS
= 4.5V) Q
g
— 0.53 —
nC VDS = 10V, ID = 250mA
Total Gate Charge (V
GS
= 8.0V) Q
g
— 0.95 —
Gate-Source Charge
Q
gs
—
0.08
—
Gate-Drain Charge
Qgd
—
0.07
—
Turn-On Delay Time
tD(ON)
— 4.1 — ns
VDD = 10V, RL = 47Ω,
VGEN = 4.5V, RGEN = 10Ω
Turn-On Rise Time
tR
— 7.3 — ns
Turn-Off Delay Time
tD(OFF)
— 13.8 — ns
Turn-Off Fall Time
tF
—
10.5
—
ns
Notes: 5. Dev ice mounted on FR-4 PCB.
6. Pulse wi dth ≤10µs, Duty Cycle ≤1%.
7. Short duration pulse test used to minimize self-heatin g effe c t.
DMN2004DWK
Document number: DS30935 Rev. 8 - 2
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October 2020
© Diodes Incorporated
DMN2004DWK
0
01 2 3 4 5
V , DRAIN-SOURCE VOLTAGE (V)
Fig. 1 Typical Output Charact eristics
DS
I , DRAIN CURRENT (A)
D
V , GATE-SOURCE VOLTAGE (V)
Fig. 2
GS
Reverse Drain Current vs. Source-Drain Voltage
T , CHANNEL TEMPERATURE (°C)
Fig. 3 Gate Threshold Voltage vs. Channel Temperature
ch
0.1
I DRAIN CURRENT(A)
Fig. 4 Stati c Drain-Source On-Resistance Vs. Drain Curre nt
D,
1
R , STATIC DRAIN-SOURCE
ON-RESISTANCE ( )
DS(on)
Ω
I , DRAIN CURRENT (A)
Fig. 5 Static Drain-Source On-Resistance vs. Drain Current
D
R , STATIC DRAIN-SOURCE
ON-RESISTANCE ( )
DS(on)
Ω
6
V
GS
, GATE -SOURCE VOLTAGE (V)
Fig. 2 Typical Transfer Characteristic
(°C)
DMN2004DWK
Document number: DS30935 Rev. 8 - 2
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October 2020
© Diodes Incorporated
DMN2004DWK
I , DRAIN CURRENT (A)
Fig. 7
D
On-Resist ance vs . Drain Current and Gate Volt age
0.6
0.8
1
1.2
1.4
1.6
-50 -25 025 50 75 100 125 150
RDS(ON), DRAIN-SOURCE ON-RESISTANCE
(NORMALIZED)
TJ, JUNCTION TEMPERATURE (
℃
)
Fig. 8 On-Resistance Variation with Temperature
VGS = 4.5V, ID = 1.0A
VGS = 2.5V, ID = 500mA
I , DRAIN-SOURCE LEAKAGE CURRENT (nA)
DSS
I , REVERSE DRAIN CURRENT (A)
DR
1000
I , DRAIN CURRENT (mA)
D
Fi g. 11 Forw a r d Tr a ns fe r Ad m ittanc e vs . D rain C urr e nt
|Y |, FORWARD TRANSFER ADMITTANCE (S)
fs
0
10
20
30
40
50
60
0 5 10 15 20
f=1MHz
C , JUNCTION CAPACITANCE (pF)
T
V, DRAIN-SOURCE VOLT AGE (V)
DS
Figure 12 T ypical Junction Capacitance
C
iss
C
oss
C
rss
ZERO GATE VOLTAGE DRAIN CURRENT (nA)
V
SD
, SOURCE-DRAIN VOLTAGE ( V)
Fig. 10 Reverse Drain Current vs. Source-Drain Voltage
DMN2004DWK
Document number: DS30935 Rev. 8 - 2
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October 2020
© Diodes Incorporated
DMN2004DWK
0
2
4
6
8
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
V GATE THRESHOLD VOLTAGE (V)
GS
Q, TOTAL GATE CHARGE (nC)
g
Figure 13 Gate Charge
V = 10V
DS
I = 250m A
D
0.001
0.01
0.1
1
10
0.1 110 100
I , DRAIN CURRENT (A)
D
V, DRAIN-SOURCE VOLTAGE (V)
DS
Figure 14 SOA, Safe Operation Area
T = 150°C
J(max)
T = 25°C
A
V = 4.5V
GS
Single Pulse
DUT on 1 * MRP Board
DC
P = 10s
W
P = 1s
W
P = 100m s
W
P = 10m s
W
P = 1m s
W
P = 100µs
W
R
DS(on)
Limited
V
GS
, GATE-SOURCE VOLTAGE (V)
DMN2004DWK
Document number: DS30935 Rev. 8 - 2
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October 2020
© Diodes Incorporated
DMN2004DWK
Package Ou t lin e Dim en sio ns
Please see http://www.diodes.com/package-outlines.html for the latest version.
Suggested Pad Layout
Please see http://www.diodes.com/package-outlines.html for the latest version.
e
D
L
E1
b
E
F
A2
A1
ca
Y1 G
Y
X
C
SOT363
Dim
Min
Max
Typ
A1
0.00
0.10
0.05
A2
0.90
1.00
1.00
b
0.10
0.30
0.25
c
0.10
0.22
0.11
D
1.80
2.20
2.15
E
2.00
2.20
2.10
E1
1.15
1.35
1.30
e
0.650 BSC
F
0.40
0.45
0.425
L
0.25
0.40
0.30
a
0°
8°
--
All Dimensions in mm
Dimensions
Value
(in mm)
C
0.650
G
1.300
X
0.420
Y
0.600
Y1
2.500
DMN2004DWK
Document number: DS30935 Rev. 8 - 2
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October 2020
© Diodes Incorporated
DMN2004DWK
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