Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 LM25117/Q1 Wide Input Range Synchronous Buck Controller With Analog Current Monitor 1 Features 3 Description * The LM25117 is a synchronous buck controller intended for step-down regulator applications from a high voltage or widely varying input supply. The control method is based upon current mode control utilizing an emulated current ramp. Current mode control provides inherent line feed-forward, cycle-bycycle current limiting and ease of loop compensation. The use of an emulated control ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable control of very small duty cycles necessary in high input voltage applications. 1 * * * * * * * * * * * * * * * * LM25117-Q1 is Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 1: -40C to 125C Ambient Operating Temperature Range Emulated Peak Current Mode Control Wide Operating Range from 4.5 V to 42 V Robust 3.3 A Peak Gate Drives Adaptive Dead-time Output Driver Control Free-run or Synchronizable Clock up to 750 kHz Optional Diode Emulation Mode Programmable Output from 0.8 V Precision 1.5% Voltage Reference Analog Current Monitor Programmable Current Limit Hiccup Mode Over Current Protection Programmable Soft-start and Tracking Programmable Line Undervoltage Lockout Programmable Switch-over to External Bias Supply Thermal Shutdown The operating frequency is programmable from 50 kHz to 750 kHz. The LM25117 drives external highside and low-side NMOS power switches with adaptive dead-time control. A user-selectable diode emulation mode enables discontinuous mode operation for improved efficiency at light load conditions. A high voltage bias regulator that allows external bias supply further improves efficiency. The LM25117's unique analog telemetry feature provides average output current information. Additional features include thermal shutdown, frequency synchronization, hiccup mode current limit and adjustable line undervoltage lockout. Device Information(1) PART NUMBER 2 Applications * * * * Automotive Infotainment Industrial DC-DC Motor Drivers Automotive USB Power Telecom Server PACKAGE BODY SIZE (NOM) LM25117 HTSSOP (20) PWP 6.50 mm x 4.40 mm LM25117-Q1 WQFN (24) RTW 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application VIN SW UVLO VIN DEMB VCC HB RAMP LM25117 HO VOUT VOUT VCCDIS SW COMP FB CM RT LO CS CSG RES SS AGND PGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 5 5 5 6 6 7 8 9 Absolute Maximum Ratings ...................................... ESD Ratings (LM25117) ........................................... ESD Ratings (LM25117-Q1) ..................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 13 7.4 Device Functional Modes........................................ 21 8 Application and Implementation ........................ 22 8.1 8.2 8.3 8.4 Application Information............................................ Typical Applications ............................................... Detailed Design Procedure ..................................... Application Curves .................................................. 22 22 22 32 9 Power Supply Recommendations...................... 35 10 Layout................................................................... 35 10.1 Layout Guideline ................................................... 35 11 Device and Documentation Support ................. 36 11.1 11.2 11.3 11.4 11.5 Community Resources.......................................... Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 36 36 36 36 36 12 Mechanical, Packaging, and Orderable Information ........................................................... 36 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (March 2013) to Revision F Page * Added Device Information and Pin Configuration and Functions sections, ESD Rating table, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support , and Mechanical, Packaging, and Orderable Information sections ................................................ 1 * Changed H to F ................................................................................................................................................................ 29 Changes from Revision D (March 2013) to Revision E * 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 34 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 5 Pin Configuration and Functions PWP Package 20-Pin HTSSOP Top View UVLO 1 20 VIN DEMB 2 19 HB RES 3 18 HO SS 4 17 SW RT 5 16 VCC 15 LO EP AGND 6 VCCDIS 7 14 PGND FB 8 13 CSG COMP 9 12 CS CM 10 11 RAMP UVLO NC VIN NC HB HO RTW Package 24-Pin WQFN Top View 24 23 22 21 20 19 DEMB 1 18 SW RES 2 17 NC SS 3 16 VCC EP 14 PGND NC 6 13 CSG 7 8 9 10 11 12 CS 5 RAMP AGND CM LO COMP 15 FB 4 VCCDIS RT Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 3 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Pin Functions PIN WQFN NO. NAME TYPE (1) DESCRIPTION 1 24 UVLO I Undervoltage lockout programming pin. If the UVLO pin voltage is below 0.4V, the regulator is in the shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4V and less than 1.25V, the regulator is in standby mode with the VCC regulator operational, the SS pin grounded, and no switching at the HO and LO outputs. If the UVLO pin voltage is above 1.25 V, the SS pin is allowed to ramp and pulse width modulated gate drive signals are delivered to the HO and LO pins. A 20A current source is enabled when UVLO exceeds 1.25V and flows through the external UVLO resistors to provide hysteresis. 2 1 DEMB I Optional logic input that enables diode emulation when in the low state. In diode emulation mode, the low-side NMOS is latched off for the remainder of the PWM cycle after detecting reverse current flow (current flow from output to ground through the low-side NMOS). When DEMB is high, diode emulation is disabled allowing current to flow in either direction through the low-side NMOS. A 50k pull-down resistor internal to the LM25117 holds DEMB pin low and enables diode emulation if the pin is left floating. 3 2 RES O The restart timer pin that configures the hiccup mode current limiting. A capacitor on the RES pin determines the time the controller remains off before automatically restarting. The hiccup mode commences when the controller experiences 256 consecutive PWM cycles of cycle-bycycle current limiting. After this occurs, an 10A current source charges the RES pin capacitor to the 1.25V threshold and restarts LM25117. 4 3 SS I An external capacitor and an internal 10A current source set the ramp rate of the error amplifier reference during soft-start. The SS pin is held low when VCC< 4V, UVLO < 1.25V or during thermal shutdown. 5 4 RT I The internal oscillator is programmed with a single resistor between RT and the AGND. The recommended maximum oscillator frequency is 750kHz. The internal oscillator can be synchronized to an external clock by coupling a positive pulse into the RT pin through a small coupling capacitor. 6 5 AGND G Analog ground. Return for the internal 0.8V voltage reference and analog circuits. 7 7 VCCDIS I Optional input that disables the internal VCC regulator. If VCCDIS>1.25V, the internal VCC regulator is disabled. VCCDIS has an internal 500k pull-down resistor to enable the VCC regulator when the pin is left floating. The internal 500k pull-down resistor can be overridden by pulling VCCDIS above 1.25V with a resistor divider connected to an external bias supply. 8 8 FB I Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is 0.8V. 9 9 COMP O Output of the internal error amplifier. The loop compensation network should be connected between this pin and the FB pin. 10 10 CM O Current monitor output. Average of the sensed inductor current is provided. Monitor directly between CM and AGND. CM should be left floating when the pin is not used. 11 11 RAMP I PWM ramp signal. An external resistor and capacitor connected between the SW pin, the RAMP pin and the AGND pin sets the PWM ramp slope. Proper selection of component values produces a RAMP signal that emulates the AC component of the inductor with a slope proportional to input supply voltage. 12 12 CS I Current sense amplifier input. Connect to the high-side of the current sense resistor. 13 13 CSG I Kelvin ground connection to the current sense resistor. Connect directly to the low-side of the current sense resistor. 14 14 PGND G Power ground return pin for low-side NMOS gate driver. Connect directly to the low-side of the current sense resistor. 15 15 LO O Low-side NMOS gate drive output. Connect to the gate of the low-side synchronous NMOS transistor through a short, low inductance path. 16 16 VCC P/O/I Bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to controller as possible. 17 18 SW I/O Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side NMOS transistor and the drain terminal of the low-side NMOS through a short, low inductance path. 18 19 HO O High-side NMOS gate drive output. Connect to the gate of the high-side NMOS transistor through a short, low inductance path. 19 20 HB P High-side driver supply for the bootstrap gate drive. Connect to the cathode of the external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side NMOS gate and should be placed as close to controller as possible. HTSSO P NO. (1) 4 I = Input, O = Output, G = Ground, P = Power Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 Pin Functions (continued) PIN WQFN NO. NAME TYPE (1) 20 22 VIN P/I EP EP EP - Exposed pad of the package. Electrically isolated. Should be soldered to the ground plane to reduce thermal resistance. HTSSO P NO. DESCRIPTION Supply voltage input source for the VCC regulator. 6 NC - No electrical contact. 17 NC - No electrical contact. 21 NC - No electrical contact. 23 NC - No electrical contact. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VIN to AGND -0.3 45 V SW to AGND -3.0 45 V HB to SW -0.3 15 V VCC to AGND (2) -0.3 15 V HO to SW -0.3 HB+0.3 V LO to AGND -0.3 VCC+0.3 V FB, DEMB, RES, VCCDIS, UVLO to AGND -0.3 15 V CM, COMP to AGND (3) -0.3 7 V SS, RAMP, RT to AGND -0.3 7 V CS, CSG, PGND, to AGND -0.3 0.3 V Storage temperature, Tstg -55 150 C Junction Temperature -40 150 C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. See Application and Implementation when input supply voltage is less than the VCC voltage. These pins are output pins. As such they are not specified to have an external voltage applied. 6.2 ESD Ratings (LM25117) V(ESD) (1) (2) Electrostatic discharge VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 V Charged-device model (CDM), per JEDEC specification JESD22- V C101 (2) 750 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings (LM25117-Q1) V(ESD) (1) Human-body model (HBM), per AEC Q100-002 Electrostatic discharge (1) Charged-device model (CDM), per AEC Q100-011 VALUE UNIT 2000 V 750 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 5 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIN (1) (2) MIN MAX UNIT 4.5 42 V VCC 4.5 14 V HB to SW 4.5 14 V Junction Temperature -40 125 C (1) (2) Recommended Operating Conditions are conditions under which operation of the device is intended to be functional, but does not ensure specific performance limits. For specifications and test conditions see .Electrical Characteristics Minimum VIN operating voltage is defined with VCC supplied by the internal HV startup regulator and no external load on VCC. When VCC is supplied by an external source, minimum VIN operating voltage is 4.5 V. 6.5 Thermal Information LM25117, LM25117-Q1 THERMAL METRIC (1) PWP (HTSSOP) RTW (WQFN) 20 PINS 24 PINS UNIT RJA Junction-to-ambient thermal resistance 40 40 C/W RJC(top) Junction-to-case (top) thermal resistance 4 6 C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 6.6 Electrical Characteristics Typical limits are for TJ = 25C only; typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Minimum and maximum limits apply over the junction temperature range of -40C to +125C. Unless otherwise specified, the following conditions apply: VVIN = 24 V, VVCCDIS = 0 V, RT = 25 k, no load on LO & HO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN SUPPLY IBIAS VIN Operating Current ISHUTDOWN VIN Shutdown Current (1) VSS = 0V 4.8 6.2 mA VSS = 0V, VVCCDIS = 2V 0.4 0.55 mA VSS = 0V, VUVLO = 0V 16 40 A VCC Regulator VCC(REG) VCC Regulation No Load 7.6 8.2 V VCC Dropout (VIN to VCC) VVIN = 4.5V, No external load 0.05 0.14 V VVIN = 5.0V, ICC = 20mA 0.4 0.5 VCC Sourcing Current Limit IVCC VCC Operating Current VVCC = 0V (1) VCC Under-voltage Threshold 6.85 30 42 V mA VSS = 0V, VVCCDIS = 2V 4.0 5.0 mA VSS = 0V, VVCCDIS = 2V, VVCC = 14V 5.8 7.3 mA 4.0 4.15 V VCC Rising 3.75 VCC Under-voltage Hysteresis 0.2 V VCC Disable VCCDIS Threshold VCCDIS Rising 1.22 VCCDIS Hysteresis VCCDIS Input Current VVCCDIS = 0V VCCDIS Pull-down Resistance 1.25 1.29 V 0.06 V -20 nA 500 k UVLO UVLO Threshold UVLO Rising 1.22 1.25 1.29 V UVLO Hysteresis Current VUVLO = 1.4V 15 20 25 A UVLO Shutdown Threshold UVLO Falling 0.23 0.3 V 0.1 V UVLO Shutdown Hysteresis Soft Start ISS SS Current Source VSS = 0V 7 SS Pull-down Resistance 10 12 A 13 24 800 812 mV Error Amplifier VREF FB Reference Voltage Measured at FB, FB = COMP FB Input Bias Current VFB = 0.8V 788 VOH COMP Output High Voltage ISOURCE = 3mA VOL COMP Output Low Voltage ISINK = 3mA AOL DC Gain 80 dB fBW Unity Gain Bandwidth 3 MHz 1 nA 2.8 V 0.26 V PWM Comparator tHO(OFF) Forced HO Off-time tON(MIN) Minimum HO On-time 260 VVIN = 42V COMP to PWM comparator offset 320 440 ns 100 ns 1.2 V Oscillator fSW1 Frequency 1 RT = 25k 180 fSW2 Frequency 2 RT = 10k 430 RT Output Voltage (1) 200 220 kHz 480 530 kHz 1.25 RT Sync Positive Threshold 2.6 Sync Pulse Width 100 3.2 V 3.95 V ns Operating current does not include the current into the RT resistor. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 7 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Electrical Characteristics (continued) Typical limits are for TJ = 25C only; typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Minimum and maximum limits apply over the junction temperature range of -40C to +125C. Unless otherwise specified, the following conditions apply: VVIN = 24 V, VVCCDIS = 0 V, RT = 25 k, no load on LO & HO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Current Limit VCS(TH) Cycle-by-cycle Sense Voltage Threshold VRAMP = 0, CSG to CS 106 120 135 mV CS Input Bias Current VCS = 0V -100 -66 A CSG Input Bias Current VCSG = 0V -100 -66 A Current Sense Amplifier Gain 10 V/V Hiccup Mode Fault Timer 256 Cycles IRES RES Current Source 10 A VRES RES Threshold RES RES Rising 1.22 1.25 1.285 V 2.0 1.65 V Diode Emulation VIL DEMB Input Low Threshold VIH DEMB Input High Threshold 2.5 V SW Zero Cross Threshold 2.95 -5 mV DEMB Input Pull-down Resistance 50 k Current Monitor Current Monitor Amplifier Gain CS to CM Current Monitor Amplifier Gain Drift over Temperature 17.5 20.5 23.5 -2 0 +2 % 25 120 mV Zero Input Offset V/V HO Gate Driver VOHH HO High-state Voltage Drop IHO = -100mA, VOHH = VHB - VHO 0.17 0.3 V VOLH HO Low-state Voltage Drop IHO = 100mA, VOLH = VHO - VSW 0.1 0.2 V HO Rise Time C-load = 1000pF (2) HO Fall Time C-load = 1000pF (2) IOHH Peak HO Source Current VHO = 0V, SW = 0V, HB = 7.6V IOLH Peak HO Sink Current VHO = VHB = 7.6V ns 5 ns 2.2 A 3.3 HB to SW Under-voltage HB DC Bias Current 6 2.56 HB - SW = 7.6V A 2.9 3.32 V 65 100 A V LO Gate Driver VOHL LO High-state Voltage Drop ILO = -100mA, VOHL = VCC-VLO 0.17 0.27 VOLL LO Low-state Voltage Drop ILO = 100mA, VOLL = VLO 0.1 0.2 LO Rise Time C-load = 1000pF (2) LO Fall Time C-load = 1000pF (2) IOHL Peak LO Source Current VLO = 0V IOLL Peak LO Sink Current VLO = 7.6V 3.3 A Thermal Shutdown Temperature Rising 165 C 25 C V 6 ns 5 ns 2.5 A Thermal TSD Thermal Shutdown Hysteresis (2) High and low reference are 80% and 20% of the pulse amplitude respectively. 6.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TDLH LO fall to HO rise delay TDHL HO fall to LO rise delay 8 Submit Documentation Feedback TEST CONDITIONS MIN No load TYP MAX UNIT 72 ns 71 ns Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 6.8 Typical Characteristics Figure 1. HO Peak Driver Current Vsoutput Voltage Figure 2. LO Peak Driver Current vs Output Voltage Figure 3. Driver Dead Time vs VVCC Figure 4. Driver Dead Time vs Temperature Figure 5. Forced Ho Off-Time vs Temperature Figure 6. Switching Frequency vs RT Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 9 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Typical Characteristics (continued) Figure 7. VVCC vs IVCC Figure 8. VVCC vs VVIN Figure 9. VCS(TH) vs Temperature Figure 10. VREF vs Temperature Figure 12. Error Amp Gain And Phase vs Frequency Figure 11. VVCC vs Temperature 10 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 Typical Characteristics (continued) Figure 13. VCM vs IOUT Figure 14. VCM vs VCSG-CS 7 Detailed Description 7.1 Overview The LM25117 high voltage switching controller features all of the functions necessary to implement an efficient high voltage buck regulator that operates over a very wide input voltage range. This easy to use controller integrates high-side and low-side NMOS drivers. The regulator control method is based upon peak current mode control utilizing an emulated current ramp. Peak current mode control provides inherent line feed-forward, cycleby-cycle current limiting and ease of loop compensation. The use of an emulated control ramp reduces noise sensitivity of the PWM circuit, allowing reliable processing of the very small duty cycles necessary in high input voltage applications. The switching frequency is user programmable up to 750 kHz. The RT pin allows the switching frequency to be programmed by a single resistor or synchronized to an external clock. Fault protection features include cycle-bycycle and hiccup mode current limiting, thermal shutdown and remote shutdown capability by pulling down UVLO pin. The UVLO input enables the regulator when the input voltage reaches a user selected threshold and provides a very low quiescent shutdown current when pulled low. A unique analog telemetry feature provides averaged output current information, allowing various applications that need either a current monitor or current control. The functional block diagram and typical application circuit of the LM25117 are shown in Functional Block Diagram The device is available in HTSSOP-20 and WQFN-24 (4mmx4mm) package featuring an exposed pad to aid in thermal dissipation. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 11 12 Submit Documentation Feedback SYNC CSYNC CSS Product Folder Links: LM25117 LM25117-Q1 CRES CHF RT RUV1 RUV2 RCOMP CCOMP CFT CIN REF RES RES Current COMP FB SS RT + + ERR + AMP - + + - RESTART TIMER - 1.2V + STANDBY REF STANDBY SS Current OSCILLATOR/ SYNC DETECTOR UVLO Shutdown Threshold UVLO UVLO Threshold UVLO Hysteresis Current LM25117 + AGND CLK Q Q R S STANDBY VCC OFF HO_ENABLE + PGND HICCUP MODE FAULT TIMER 256 CYCLES C/L Comparator RES RESET HICCUP 10uVCS(TH) + 500 k: VCCDIS Threshold THERMAL SHUTDOWN PWM Comparator DE_ENABLE CLK STANDBY VCC OFF RES RESET STANDBY VCCDIS + 50 k: DE_ENABLE DIODE EMULATION CONTROL HB UVLO -5 mV CONDITIONER VCC CSG A=2 RAMP 40 k: CM CCM RCM RCS2 CCS RCS1 CS RGH RGL CHB DHB RS CVCC LO SW HO HB DEMB VCC UVLO VCC Current Monitor Amplifier Current Sense Amplifier A=10 LO Driver + - HO Driver DISABLE STANDBY ZCD Comparator 2.0/2.5V VCC Regulator CVIN LEVEL SHIFT/ ADAPTIVE TIMER VCC OFF LO_ENABLE HO_ENABLE DE_ENABLE VCC OFF VIN RVIN + - VIN QL QH CSNB RSNB CRAMP RRAMP COUT1 LO RFB1 RFB2 COUT2 VOUT LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com 7.2 Functional Block Diagram Copyright (c) 2011-2015, Texas Instruments Incorporated LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 7.3 Feature Description 7.3.1 High Voltage Startup Regulator and VCC Disable The LM25117 contains an internal high voltage bias regulator that provides the VCC bias supply for the PWM controller and NMOS gate drivers. The VIN pin can be connected to an input voltage source as high as 42V. The output of the VCC regulator is set to 7.6V. When the input voltage is below the VCC set-point level, the VCC output tracks the VIN with a small dropout voltage. The output of the VCC regulator is current limited at 30mA minimum. Upon power-up, the regulator sources current into the capacitor connected to the VCC pin. The recommended capacitance range for the pin VCC is 0.47F to 10F. When the VCC pin voltage exceeds the VCC UV threshold and the UVLO pin is greater than UVLO threshold, the HO and LO drivers are enabled and a soft-start sequence begins. The HO and LO drivers remain enabled until either the VCC pin voltage falls below VCC UV threshold, the UVLO pin voltage falls below UVLO threshold, hiccup mode is activated or the die temperature exceeds the thermal shutdown threshold. Enabling/Disabling the IC by controlling UVLO is recommended in most of cases. An output voltage derived bias supply can be applied to the VCC pin to reduce the controller power dissipation at higher input voltage. The VCCDIS input can be used to disable the internal VCC regulator when external biasing is supplied. The externally supplied bias should be coupled to the VCC pin through a diode, preferably a Schottky diode. If the VCCDIS pin voltage exceeds the VCCDIS threshold, the internal VCC regulator is disabled. VCCDIS has a 500k internal pull-down resistor to ground for normal operation with no external bias. The VCC regulator series pass transistor includes a diode between VCC (Anode) and VIN (Cathode) that should not be forward biased in normal operation. If the voltage of the external bias supply is greater than the VIN pin voltage, an external blocking diode is required from the input power supply to the VIN pin to prevent the external bias supply from passing current to the input supply through VCC. VIN VIN LM25117 External VCC Supply VCC Figure 15. VIN Configuration For VVIN<VVCC For VOUT between 5V and 14.5V, the output can be connected directly to VCC through a diode. VOUT VCC LM25117 VCCDIS resistor divider is required when external VCC supplying voltage is smaller than 8.5V VCCDIS Figure 16. External VCC Supply For 5 V< VOUT<14.5 V For VOUT < 5V, a bias winding on the output inductor can be added to generate the external VCC supply voltage. VCC LM25117 VCCDIS VOUT SW VCCDIS resistor divider is required when external VCC supplying voltage is smaller than 8.5V Figure 17. External VCC Supply For VOUT <5 V Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 13 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Feature Description (continued) For 14.5 V <VOUT, the external supply voltage can be regulated by using a series Zener diode from the output to VCC. VOUT R1 VCC Zener 30 k: R1 is required to limit maximum reverse zener current 30 k: minimum resistive loss at VCC guarantees minimum reverse zener current LM25117 Figure 18. External VCC Supply For 14.5 V <VOUT In high input voltage applications, extra care should be taken to ensure the VIN pin does not exceed the absolute maximum voltage rating of 45V. During line or load transients, voltage ringing on the VIN that exceeds the Absolute Maximum Rating can damage the IC. Both careful PC board layout and the use of quality bypass capacitors located close to the VIN and AGND pin are essential. Adding an R-C filter (RVIN, CVIN) on VIN is optional and helps to prevent faulty operation caused by poor PC board layout and high frequency switching noise injection. The recommended capacitance and resistance range are 0.1F to 10F and 1 to 10. 7.3.2 UVLO The LM25117 contains a dual level UVLO (under-voltage lockout) circuit. When the UVLO is less than 0.4 V, the LM25117 is in shutdown mode. The shutdown comparator provides 100mV of hysteresis to avoid chatter during transitions. When the UVLO pin voltage is greater than 0.4 V but less than 1.25 V, the controller is in standby mode. In the standby mode, the VCC bias regulator is active but the HO and LO drivers are disabled and the SS pin is held low. This feature allows the UVLO pin to be used as a remote shutdown function by pulling the UVLO pin down below 0.4V with an external open collector or open drain device. When the VCC pin exceeds its undervoltage lockout threshold and the UVLO pin voltage is greater than 1.25V, the HO and LO drivers are enabled and normal operation begins. UVLO Hysteresis Current VIN UVLO Threshold RUV2 UVLO CFT RUV1 LM25117 UVLO Shutdown Threshold + + STANDBY SHUTDOWN Figure 19. UVLO Configuration The UVLO pin should not be left floating. An external UVLO set-point voltage divider from the VIN to AGND is used to set the minimum input operating voltage of the regulator. The divider must be designed such that the voltage at the UVLO pin is greater than 1.25V and never exceeds 15V when the input voltage is in the desired operating range. If necessary, the UVLO pin can be clamped with a Zener diode. UVLO hysteresis is accomplished with an internal 20A current source that is switched on or off into the impedance of the UVLO set-point divider. When the UVLO pin voltage exceeds the 1.25 V threshold, the current source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25 V threshold, the current source is disabled causing the voltage at the UVLO pin to quickly fall. The use of a CFT capacitor in parallel with RUV1 helps to minimize switching noise injection into UVLO pin, but it may slow down the falling speed of the UVLO pin when the 20A current source is disabled. The recommended range for CFT is 10pF to 220pF. 14 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 Feature Description (continued) The values of RUV1 and RUV2 can be determined from the following equations: VHYS [5] RUV2 = 20 A RUV1 = (1) 1.25V x RUV2 [5] VIN(STARTUP) - 1.25V (2) Where VHYS is the desired UVLO hysteresis and VIN(STARTUP) is the desired startup voltage of the regulator during turn-on. 7.3.3 Oscillator And Sync Capability The LM25117 switching frequency is programmed by a single external resistor connected between the RT pin and the AGND pin. The resistor should be located very close to the device and connected directly to the RT and AGND pins. To set a desired switching frequency (fSW), the resistor value can be calculated from the following equation: 9 RT = 5.2 x 10 - 948 [5] fSW (3) The RT pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be synchronized by AC coupling a positive edge into the RT pin. The voltage at the RT pin is nominally 1.25 V and the voltage at the RT pin must exceed the RT Sync Positive Threshold to trip the internal synchronization pulse detector. A 5 V amplitude pulse signal coupled through 100pF capacitor is a good starting point. The frequency of the external synchronization pulse is recommended to be within +/-10% of the frequency programmed by the RT resistor but will operate to +100/-40% of the programmed frequency. Care should be taken to make sure that the RT pin voltage does not go below -0.3V at the falling edge of the external pulse. This may limit the duty cycle of external synchronization pulse. The RT resistor is always required, whether the oscillator is free running or externally synchronized. 7.3.4 Ramp Generator and Emulated Current Sense The ramp signal used in the pulse width modulator for traditional current mode control is typically derived directly from the high-side switch current. This switch current corresponds to the positive slope portion of the inductor current. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feed-forward compensation. The disadvantage of using the high-side switch current signal for PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Minimum achievable pulse width is limited by the filtering, blanking time and propagation delay with a high-side current sensing scheme. In the applications where the input voltage may be relatively large in comparison to the output voltage, controlling small pulse widths and duty cycles are necessary for regulation. The LM25117 utilizes a unique ramp generator which does not actually measure the high-side switch current but rather reconstructs the signal. Representing or emulating the inductor current provides a ramp signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays, while maintaining the advantages of traditional peak current mode control. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 15 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Feature Description (continued) The current reconstruction is comprised of two elements: a sample-and-hold DC level and the emulated inductor current ramp as shown in Figure 20. The sample-and-hold DC level is derived from a measurement of the recirculating current flowing through the current sense resistor. The voltage across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the high-side switch. The current sense amplifier with a gain of 10 and sample-and-hold circuit provide the DC level of the reconstructed current signal as shown in Figure 21. Additional Slope RAMPPK = VIN x tON RRAMP x CRAMP ILO x RS x 10 Sample and Hold DC Level tON Figure 20. Composition of Emulated Current Sense Signal CS 10 x VCS(TH) Current Sense Amplifier + - AS=10 + Current Limit Comparator RS IL CSG HO_ENABLE LM25117 RAMP SW RRAMP CRAMP Figure 21. Ramp Generator and Current Limit Circuit The positive slope inductor current ramp is emulated by CRAMP connected between RAMP and AGND and RRAMP connected between SW and RAMP. RRAMP should not be connected to VIN directly because the RAMP pin absolute maximum voltage rating could be exceeded under high input voltage conditions. CRAMP is discharged by an internal switch during the off-time and must be fully discharged during the minimum off-time. This limits the ramp capacitor to be less than 2nF. A good quality, thermally stable ceramic capacitor is recommended for CRAMP. The selection of RRAMP and CRAMP can be simplified by adopting a K factor, which is defined as: LO K= RRAMP x CRAMP x RS x AS (4) Where AS is the current sense amplifier gain which is normally 10. By choosing 1 as the K factor, the regulator removes any error after one switching cycle and the design procedure is simplified. See Application Information for detailed information. 16 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 Feature Description (continued) 7.3.5 Error Amplifier and PWM Comparator The internal high-gain error amplifier generates an error signal proportional to the difference between the FB pin voltage and the internal precision 0.8V reference. The output of error amplifier is connected to the COMP pin allowing the user to provide Type 2 loop compensation components, RCOMP, CCOMP and optional CHF. VOUT LM25117 PWM Comparator REF RFB2 FB + + - Error Amplifier RCOMP CCOMP + - COMP RAMP Generator Output RFB1 CHF (optional) Type 2 Compensation Components Figure 22. Feedback Configuration and PWM Comparator RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to achieve a stable voltage loop gain. This network creates a pole at DC (FP1), a mid-band zero (FZ) for phase boost, and a high frequency pole (FP2). The recommended range of RCOMP is 2k to 40k. See Application Information for detailed information. FP1 = 0 [Hz] (5) FZ = 1 2S x RCOMP x CCOMP [Hz] (6) 1 [Hz] FP2 = CCOMP x CHF* 2S x RCOMP x (c)CCOMP + CHF (7) The PWM comparator compares the emulated current sense signal from Ramp Generator to the voltage at the COMP pin through a 1.2 V internal voltage drop and terminates the present cycle when the emulated current sense signal is greater than VCOMP - 1.2 V. 7.3.6 Soft-Start The soft-start feature allows the regulator to gradually reach the steady state operating point, thus reducing startup stresses and surges. The LM25117 regulates the FB pin to the SS pin voltage or the internal 0.8V reference, whichever is lower. The internal 10A soft-start current source gradually increases the voltage on an external soft-start capacitor connected to the SS pin. This results in a gradual rise of the output voltage. Soft-start time (tss) can be calculated from the following equation: tSS = CSS x 0.8V 10 A [sec] (8) The LM25117 can track the output of a master power supply during soft-start by connecting a voltage divider from the output of master power supply to the SS pin. At the beginning of the soft-start sequence, VSS should be allowed to go below 25mV by the internal SS pull-down switch. During soft-start period, when SS pin voltage is less than 0.8V, the LM25117 forces diode emulation for startup into a pre-biased load. If the tracking feature is desired, connect the DEMB pin to GND or leave the pin floating. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 17 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Feature Description (continued) 7.3.7 Cycle-By-Cycle Current Limit The LM25117 contains a current limit monitoring scheme to protect the regulator from possible over-current conditions as shown in Figure 21. If the emulated ramp signal exceeds 1.2 V, the present cycle is terminated. For the case where the switch current overshoots when the inductor is saturated or the output is shorted to ground, the sample-and-hold circuit detects the excess recirculating current before the high-side NMOS driver is turned on again. The high-side NMOS driver is disabled and will skip pulses until the current has decayed below the current limit threshold. This approach prevents current runaway conditions since the inductor current is forced to decay to a controlled level following any current overshoot. Maximum peak inductor current can be calculated as: VCS(TH) VOUT [A] IL(MAX)_PK = + IPP RS fSW x AS x RS x RRAMP x CRAMP (9) IL(MAX)_AVE = IL(MAX)_PK - IPP [A] 2 (10) Where IPP represents inductor peak to peak ripple current in Figure 23, and is defined as: IPP = VOUT LO x fSW (c) x 1 - VOUT VIN * [A] (11) IPP IOUT T= 1 fSW 0 Figure 23. Inductor Current During an output short condition, the worst case peak inductor current is limited to: VIN(MAX) x tON(MIN) VCS(TH) ILIM_PK = RS + [A] LO (12) Where tON(MIN) is the minimum HO on-time. In most of cases, especially if the output voltage is relatively high, it is recommended that a soft-saturating inductor such as a powder core device is used. If a sharp-saturating inductor is used, the inductor saturation level must be above ILIM_PK. The temperatures of the NMOS devices, RS and inductor should be checked under this output short condition. 7.3.8 Hiccup Mode Current Limiting To further protect the regulator during prolonged current limit conditions, LM25117 provides a hiccup mode current limit. An internal hiccup mode fault timer counts the PWM clock cycles during which cycle-by-cycle current limiting occurs. When the hiccup mode fault timer detects 256 consecutive cycles of current limiting, an internal restart timer forces the controller to enter a low power dissipation standby mode and starts sourcing 10A current into the RES pin capacitor CRES. In this standby mode, HO and LO outputs are disabled and the soft-start capacitor CSS is discharged. 18 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 Feature Description (continued) CRES is connected from RES pin to AGND and determines the time (tRES) in which the LM25117 remains in the standby before automatically restarting. When the RES pin voltage exceeds the 1.25 V RES threshold, RES capacitor is discharged and a soft-start sequence begins. tRES can be calculated from the following equation: CRES x 1.25V [sec] tRES = 10 PA (13) Current Limit Detected 1.25V RES Threshold IRES = 10 A 0V RES ISS = 10 A SS 0.8V REF HO LO Current Limit persists during 256 consecutive cycles tRES tSS Figure 24. Hiccup Mode Current Limit Timing Diagram LM25117 STANDBY RES Current RESTART TIMER RES CRES HICCUP HICCUP MODE FAULT TIMER 256 CYCLES Current Limit Comparator + Figure 25. Hiccup Mode Current Limit Circuit The RES pin can also be configured for latch-off mode current limiting or non-hiccup mode cycle-by-cycle current limiting. If the RES pin is tied to VCC or a voltage greater than the RES threshold at initial power-on, the restart timer is disabled and the regulator operates with non-hiccup mode cycle-by-cycle current limit. If the RES pin is tied to GND, the regulator enters into the standby mode after 256 consecutive cycles of current limiting and then never restarts until UVLO shutdown is cycled. The restart timer is configured during initial power-on when UVLO is above the UVLO threshold and VCC is above the VCC UV threshold. RES RES CRES LM25117 RES LM25117 LM25117 VCC VCC (a) Hiccup Mode Current Limit (b) Latch-off Mode Current Limit (c) Cycle-by-cycle Current Limit Figure 26. Res Configurations Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 19 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Feature Description (continued) 7.3.9 HO and LO Drivers The LM25117 contains high current NMOS drivers and an associated high-side level shifter to drive the external high-side NMOS device. This high-side gate driver works in conjunction with an external diode DHB, and bootstrap capacitor CHB. A 0.1F or larger ceramic capacitor, connected with short traces between the HB and SW pin, is recommended. During the off-time of the high-side NMOS driver, the SW pin voltage is approximately 0V and the CHB is charged from VCC through the DHB. When operating with a high PWM duty cycle, the highside NMOS device is forced off each cycle for 320ns to ensure that CHB is recharged. The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs are never enabled at the same time. When the controller commands HO to be enabled, the adaptive dead-time logic first disables LO and waits for the LO voltage to drop. HO is then enabled after a small delay (LO Fall to HO Rise Delay). Similarly, the LO turn-on is delayed until the HO voltage has discharged. LO is then enabled after a small delay (HO Fall to LO Rise Delay). This technique insures adequate dead-time for any size NMOS device, especially when VCC is supplied by a higher external voltage source. The adaptive dead-time circuitry monitors the voltages of HO and LO outputs and insures the dead-time between the HO and LO outputs. Adding a gate resister, RGH or RGL, may decrease the effective dead-time. Care should be exercised in selecting an output NMOS device with the appropriate threshold voltage, especially if VCC is supplied by an external bias supply voltage below the VCC regulation level. During startup at low input voltages, the low-side NMOS device gate plateau voltage should be lower than the VCC under-voltage lockout threshold. Otherwise, there may be insufficient VCC voltage to completely enhance the NMOS device as the VCC under-voltage lockout is released during startup. If the high-side NMOS drive voltage is lower than the highside NMOS device gate plateau voltage during startup, the regulator may not start or it may hang up momentarily in a high power dissipation state. This condition can be addressed by selecting an NMOS device with a lower threshold voltage. This situation can be avoided if the minimum input voltage programmed by the UVLO resistor is above the VCC regulation level. 7.3.10 Current Monitor The LM25117 provides average output current information, enabling various applications requiring monitoring or control of the output current. Current Sense Amplifier Output LM25117 Current Monitor Amplifier CM CONDITIONER RCM AM = 2 40 k: CCM Figure 27. Current Monitor The average of CM output can be calculated by: VCM _ AVE = (IPEAK + IVALLEY ) RS A S [V ] (14) The current monitor output is only valid in continuous conduction operation. The current monitor has a limited bandwidth of approximately one tenth of fSW. Adding an R-C filter, RCM and CCM, on the output of current monitor with the cut off frequency below one tenth of fSW is recommended to attenuate sampling noise. 20 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 Feature Description (continued) 7.3.11 Maximum Duty Cycle When operating with a high PWM duty cycle, the high-side NMOS device is forced off each cycle for 320ns to ensure that CHB is recharged and to allow time to sample and hold the current in the low-side NMOS FET. This forced off-time limits the maximum duty cycle of the controller. When designing a regulator with high switching frequency and high duty cycle requirements, a check should be made of the required maximum duty cycle against the graph shown in Figure 28. The actual maximum duty cycle varies with the switching frequency as follows: Figure 28. Maximum Duty Cycle vs Switching Frequency 7.3.12 Thermal Protection Internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction temperature is exceeded. When activated, typically at 165C, the controller is forced into a low power shutdown mode, disabling the output drivers and the VCC regulator. This feature is designed to prevent overheating and destroying the device. 7.4 Device Functional Modes 7.4.1 Diode Emulation A fully synchronous buck regulator implemented with a freewheeling NMOS rather than a diode has the capability to sink current from the output in certain conditions such as light load, over-voltage or pre-bias startup. The LM25117 provides a diode emulation feature that can be enabled to prevent reverse current flow in the lowside NMOS device. When configured for diode emulation, the low-side NMOS driver is disabled when SW pin voltage is greater than -5mV during the off-time of the high-side NMOS driver, preventing reverse current flow. A benefit of the diode emulation is lower power loss at no load or light load conditions. The negative effect of diode emulation is degraded light load transient response. The diode emulation feature is configured with the DEMB pin. To enable diode emulation, connect the DEMB pin to GND or leave the pin floating. If continuous conduction operation is desired, the DEMB pin should be tied to a voltage greater than 3V and may be connected to VCC. The LM25117 forces the regulator to operate in diode emulation mode when SS pin voltage is less than the internal 0.8 V reference, allowing for startup into a prebiased load with the continuous conduction configuration. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 21 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM25117 is a step-down dc-dc controller. The device is typically used to convert a higher dc voltage to a lower dc voltage. Use the following design procedure to select component values. Alternately, use the WEBENCH(R) software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. 8.2 Typical Applications Figure 29. 3.3 V, 9 A Typical Application Schematic 8.3 Detailed Design Procedure 8.3.1 Feedback Compensation Open loop response of the regulator is defined as the product of modulator transfer function and feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain. The modulator transfer function includes a power stage transfer function with an embedded current loop and can be simplified as one pole and one zero system as shown in the following equations. s 1+ ^ ZZ_ESR VOUT = AM x ^ V 1+ s * COMP (c) ZP_LF (15) Where AM (Modulator DC gain) = 22 Submit Documentation Feedback RLOAD , R S x AS (16) Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 Detailed Design Procedure (continued) ZZ_ESR (ESR zero) = ZP_LF (Load pole) = 1 , RESR x COUT (17) 1 RLOAD x COUT (18) If the ESR of COUT (RESR) is very small, the modulator transfer function can be further simplified to a one pole system and the voltage loop can be closed with only two loop compensation components, RCOMP and CCOMP, leaving a single pole response at the crossover frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin. The feedback transfer function includes the feedback resistor divider and loop compensation of the error amplifier. RCOMP, CCOMP and optional CHF configure the error amplifier gain and phase characteristics and create a pole at origin, a low frequency zero and a high frequency pole. This is shown mathematically in the following equations. s 1+ ^ ZZ_EA VCOMP = AFB x s ^ s x (1+ V OUT Z ) P_EA (19) Where AFB (Feedback DC gain) = 1 RFB2 x (CCOMP + CHF) wZ_EA (Low frequency zero) = 1 , RCOMP x CCOMP wP_EA (High frequency pole) = 1 RCOMP x CHF , (20) The pole at the origin minimizes output steady state error. The low frequency zero should be placed to cancel the load pole of the modulator. The high frequency pole can be used to cancel the zero created by the output capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at the crossover frequency. The high frequency pole should be placed well beyond the crossover frequency since the addition of CHF adds a pole in the feedback transfer function. The crossover frequency (loop bandwidth) is usually selected between one twentieth and one fifth of the fSW. In a simplified formula, the crossover frequency can be defined as: fCROSS = RCOMP [Hz] 2 x ' x RS x RFB2 x AS x COUT (21) For higher crossover frequency, RCOMP can be increased, while proportionally decreasing CCOMP. Conversely, decreasing RCOMP while proportionally increasing CCOMP, results in lower bandwidth while keeping the same zero frequency in the feedback transfer function. The sampled gain inductor pole is inversely proportional to the K factor, which is defined as: fSW Zp_HF = K - 0.5 (22) The maximum achievable loop bandwidth, in fact, is limited by this sampled gain inductor pole. In traditional current mode control, the maximum achievable loop bandwidth varies with input voltage. With the LM25117's unique slope compensation scheme, the sampled gain inductor pole is independent of changes to the input voltage. This frees the user from additional concerns in wide varying input range applications and is an advantage of the LM25117. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 23 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Detailed Design Procedure (continued) If the sampled gain inductor pole or the ESR zero is close to the crossover frequency, it is recommended that the comprehensive formulas in Table 1 be used and the stability should be checked by a network analyzer. The modulator transfer function can be measured and the feedback transfer function can be configured for the desired open loop transfer function. If a network analyzer is not available, step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot/undershoot with a damped response. 8.3.2 Sub-Harmonic Oscillation Peak current mode regulators can exhibit unstable behavior when operating above 50% duty cycle. This behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin. Sub-harmonic oscillation can be prevented by adding an additional voltage ramp (slope compensation) on top of the sensed inductor current shown in Figure 20. By choosing K1, the regulator will not be subject to sub-harmonic oscillation caused by a varying input voltage. In time-domain analysis, the steady-state inductor current starts and ends at the same value during one clock cycle. If the magnitude of the end-of-cycle current error, dI1, caused by an initial perturbation, dI0, is less than the magnitude of dI0 or dI1/dI0 > -1, the perturbation naturally disappears after a few cycles. When dI1/dI0 < -1, the initial perturbation does not disappear, resulting in sub-harmonic oscillation in steady-state operation. Steady-State Inductor Current dI0 tON dI1 Inductor Current with Initial Perturbation Figure 30. Effect of Initial Perturbation when dl1/dl0 < -1 dI1/dI0 can be calculated by: dl1 1 =1dl0 K (23) The relationship between dI1/dI0 and K factor is illustrated graphically in Figure 31. Figure 31. dl1/dl0 vs K Factor The minimum value of K is 0.5. When K<0.5, the amplitude of dI1 is greater than the amplitude of dI0 and any initial perturbation results in sub-harmonic oscillation. If K=1, any initial perturbation will be removed in one switching cycle. This is known as one-cycle damping. When -1<dl1/dl0<0, any initial perturbation will be underdamped. Any perturbation will be over-damped when 0<dl1/dl0<1. 24 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 Detailed Design Procedure (continued) In the frequency-domain, Q, the quality factor of the sampling gain term in the modulator transfer function, is used to predict the tendency for sub-harmonic oscillation, which is defined as: Q= 1 S(K-0.5) (24) The relationship between Q and K factor is illustrated graphically in Figure 32. Figure 32. Sampling Gain Q vs K Factor The minimum value of K is 0.5 again. This is the same as time domain analysis result. When K<0.5, the regulator is unstable. High gain peaking at 0.5 results in sub-harmonic oscillation at FSW/2. When K=1, one-cycle damping is realized. Q is equal to 0.673 at this point. A higher K factor may introduce additional phase shift by moving the sampled gain inductor pole closer to the crossover frequency, but will help reduce noise sensitivity in the current loop. The maximum allowable value of K factor can be calculated by the Maximum Crossover Frequency equation in Table 1. 8.3.3 Design Requirements DESIGN PARAMETER EXAMPLE VALUE Output Voltage VOUT 3.3 V Full Load Current IOUT 9A Minimum Input Voltage VIN(MIN) 6V Maximum Input Voltage VIN(MAX) 36 V Switching Frequency fSW 230 kHz Diode Emulation Yes External VCC Supply No 8.3.4 Timing Resistor RT Generally, higher frequency applications are smaller but have higher losses. Operation at 230 kHz was selected for this example as a reasonable compromise between small size and high efficiency. The value of RT for 230 kHz switching frequency can be calculated from Equation 3. 9 RT = 5.2 x 10 - 948 = 21.7 k: 230 x 103 (25) A standard value of 22.1k was chosen for RT. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 25 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com 8.3.5 Output Inductor LO The maximum inductor ripple current occurs at the maximum input voltage. Typically, 20% to 40% of the full load current is a good compromise between core loss and copper loss of the inductor. Higher ripple current allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. For this example, a ripple current of 20% of 9A was chosen. Knowing the switching frequency, maximum ripple current, maximum input voltage and the nominal output voltage, the inductor value can be calculated as follows: ae VOUT VOUT o / [H] c1 LO = IPP(MAX) fSW c VIN(MAX ) / e o (26) LO = 3.3V* = 7.2 PH 3.3V x 1 36V 9A x 0.2 x 230 kHz (c) (27) The closest standard value of 6.8H was chosen for LO. Using the value of 6.8H for LO, calculate IPP again. This step is necessary if the chosen value of LO differs significantly from the calculated value. From Equation 11, IPP(MAX) = 3.3V* = 1.9A 3.3V x 16.8 PH x 230 kHz 36V (c) (28) At the minimum input voltage, this value is 0.95A. 8.3.6 Diode Emulation Function The DEMB pin is left floating since this example uses diode emulation to reduce the power loss under no load or light load conditions. 8.3.7 Current Sense Resistor RS The performance of the converter will vary depending on the K value. For this example, K=1 was chosen to control sub-harmonic oscillation and achieve one-cycle damping. The maximum output current capability (IOUT(MAX)) should be 20~50% higher than the required output current, to account for tolerances and ripple current. For this example, 150% of 9A was chosen. The current sense resistor value can be calculated from Equation 9 and Equation 10 as follows: VCS(TH) RS = VOUT x K _ IPP IOUT(MAX) + 2 fSW x LO >:@ (29) 0.12V = 7.9 m: RS = 3.3 x 1 _ 0.95A 9A x 1.5 + 230 kHz x 6.8 H 2 (30) A value of 8m was chosen for RS. A larger value resistor can be placed in parallel with RS to adjust the maximum output current capability. The sense resistor must be rated to handle the power dissipation at maximum input voltage when current flows through the low-side NMOS for the majority of the PWM cycle. The maximum power dissipation of RS can be calculated as: (c) VIN(MAX) (c) 3.3V* 2 x 9A x 8 m: = 0.59W 36V PRS = 1 - PRS = 1 - 26 VOUT * x I 2x R OUT S [W] (31) Submit Documentation Feedback (32) Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 The worst case peak inductor current under the output short condition can be calculated from Equation 12 as follows: 0.12V 36V x 100 ns + = 15.5A ILIM_PK = 8 m: 6.8 PH (33) Where tON(MIN) is normally 100ns. 8.3.8 Current Sense Filter RCS and CCS The LM25117 itself is not affected by the large leading edge spike because it samples valley current just prior to the onset of the high-side switch. A current sense filter is used to minimize a noise injection from any external noise sources. In general, a current sense filter is not necessary. In this example, a current sense filter is not used Adding RCS resistor changes the current sense amplifier gain which is defined as AS=10k / (1k+RCS). A small value of RCS resistor below 100 is recommended to minimize the gain change which is caused by the temperature coefficient difference between internal and external resistors. 8.3.9 Ramp Resistor RRAMP and Ramp Capacitor CRAMP The positive slope of the inductor current ramp signal is emulated by RRAMP and CRAMP. For this example, the value of CRAMP was set at the standard capacitor value of 820pF. With the inductor, sense resistor and the K factor selected, the value of RRAMP can be calculated from Equation 4 as follows: LO [:@ RRAMP = K x CRAMP x RS x AS (34) RRAMP = 6.8 PH = 104 k: 1 x 820 pF x 8 m: x 10 (35) The standard value of 105 k was selected for RRAMP. 8.3.10 UVLO Divider RUV2, RUV1 and CFT The desired startup voltage and the hysteresis are set by the voltage divider RUV1 and RUV2. Capacitor CFT provides filtering for the divider. For this design, the startup voltage was set to 5.7V, 0.3V below VIN(MIN). VHYS was set to 1V. The value of RUV1, RUV2 can be calculated from Equation 1 and Equation 2 as follows: 1V = 50 k: RUV2 = 20 A (36) RUV1 = 1.25V x 50 k: = 14.0 k: 5.7V - 1.25V (37) The standard value of 50k was selected for RUV2. RUV1 was selected to be 14k. A value of 100pF was chosen for CFT. 8.3.11 VCC Disable and External VCC Supply In this example, VCCDIS is left floating to enable the internal VCC regulator. 8.3.12 Power Switches QH and QL Selection of the power NMOS devices is governed by the same trade-offs as switching frequency. Breaking down the losses in the high-side and low-side NMOS devices is one way to compare the relative efficiencies of different devices. Losses in the power NMOS devices can be broken down into conduction loss, gate charging loss, and switching loss. Conduction loss PDC is approximately: PDC (High-Side) = D x (IOUT2 x RDS(ON) x 1.3) PDC (Low-Side) = (1 D) x (IOUT2 [W] x RDS(ON) x 1.3) (38) [W] Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 (39) Submit Documentation Feedback 27 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Where D is the duty cycle and the factor of 1.3 accounts for the increase in the NMOS device on-resistance due to heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the NMOS device can be estimated using the RDS(ON) vs Temperature curves in the MOSFET datasheet. Gate charging loss (PGC) results from the current driving the gate capacitance of the power NMOS devices and is approximated as: PGC = n x VVCC x Qg x fSW [W] (40) Qg refers to the total gate charge of an individual NMOS device, and `n' is the number of NMOS devices. Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the controller IC. Switching loss (PSW) occurs during the brief transition period as the high-side NMOS device turns on and off. During the transition period both current and voltage are present in the channel of the NMOS device. The switching loss can be approximated as: PSW = 0.5 x VIN x IOUT x (tR + tF) x fSW [W] (41) tR and tF are the rise and fall times of the high-side NMOS device. The rise and fall times are usually mentioned in the MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for the high-side NMOS device only. Switching loss in the low-side NMOS device is negligible because the body diode of the low-side NMOS device turns on before and after the low-side NMOS device switches. For this example, the maximum drain-to-source voltage applied to either NMOS device is 36V. The selected NMOS devices must be able to withstand 36V plus any ringing from drain to source and must be able to handle at least the VCC voltage plus any ringing from gate to source. 8.3.13 Snubber Components RSNB and CSNB A resistor-capacitor snubber network across the low-side NMOS device reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to the output voltage. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and 50. Increasing the value of the snubber capacitor results in more damping, but higher snubber losses. Select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the switch waveform at heavy load. A snubber may not be necessary with an optimized layout. 8.3.14 Bootstrap Capacitor CHB and Bootstrap Diode DHB The bootstrap capacitor between the HB and SW pin supplies the gate current to charge the high-side NMOS device gate during each cycle's turn-on and also supplies recovery charge for the bootstrap diode. These current peaks can be several amperes. The recommended value of the bootstrap capacitor is at least 0.1F. CHB should be a good quality, low ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging voltage transients caused by trace inductance. The absolute minimum value for the bootstrap capacitor is calculated as: Qg CHB t [F] 'VHB (42) Where Qg is the high-side NMOS gate charge and VHB is the tolerable voltage droop on CHB, which is typically less than 5% of VCC or 0.15V conservatively. A value of 0.47F was selected for this design. 28 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 8.3.15 VCC Capacitor CVCC The primary purpose of the VCC capacitor (CVCC) is to supply the peak transient currents of the LO driver and bootstrap diode as well as provide stability for the VCC regulator. These peak currents can be several amperes. The recommended value of CVCC should be no smaller than 0.47F, and should be a good quality, low ESR, ceramic capacitor. CVCC should be placed at the pins of the IC to minimize potentially damaging voltage transients caused by trace inductance. A value of 1F was selected for this design. 8.3.16 Output Capacitor CO The output capacitors smooth the output voltage ripple caused by inductor ripple current and provide a source of charge during transient loading conditions. For this design example, a 680F electrolytic capacitor with maximum 10m ESR was selected as the main output capacitor. The fundamental component of the output ripple voltage with maximum ESR is approximated as: 'VOUT = IPP x RESR 2 + (c)8 x 1 * fSW x COUT 2 [V] (43) 2 'VOUT = 1.9 x 1 * 2 = 19 mV 0.01: + 8 x 230 kHz x 680 PF (c) (44) Additional low ERS / ESL ceramic capacitors can be placed in parallel with the main output capacitor to further reduce the output voltage ripple and spikes. In this example, two 22F capacitors were added. 8.3.17 Input Capacitor CIN The regulator input supply voltage typically has high source impedance at the switching frequency. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. When the high-side NMOS device turns on, the current into the device steps to the valley of the inductor current waveform, ramps up to the peak value, and then drops to the zero at turnoff. The input capacitor should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating necessary is IRMS > IOUT / 2. In this example, seven 2.2F ceramic capacitors were used. With ceramic capacitors, the input ripple voltage will be triangular. The input ripple voltage can be approximated as: 'VIN = IOUT 4 x fSW x CIN [V] (45) 9A = 0.63 V 'VIN = 4 x 230 kHz x 2.2 PF x 7 (46) Capacitors connected in parallel should be evaluated for RMS current rating. The current will split between the input capacitors based on the relative impedance of the capacitors at the switching frequency. 8.3.18 VIN Filter RVIN, CVIN An R-C filter (RVIN, CVIN) on VIN is optional. The filter helps to prevent faults caused by high frequency switching noise injection into the VIN pin. 0.47F ceramic capacitor is used for CVIN in the example. 8.3.19 Soft-Start Capacitor CSS The capacitor at the SS pin (CSS) determines the soft-start time (tSS), which is the time for the output voltage to reach the final regulated value. The tSS for a given CSS can be calculated from Equation 8 as follows: 0.047 F x 0.8V = 3.8 ms tSS = 10 A (47) For this example, a value of 0.047F was chosen for a soft-start time of 3.8ms. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 29 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com 8.3.20 Restart Capacitor CRES The capacitor at the RES pin (CRES) determines tRES, which is the time the LM25117 remains off before a restart attempt is made in hiccup mode current limiting. tRES for a given CRES can be calculated from Equation 13 as follows: 0.47 F x 1.25V = 59 ms tRES = 10 A (48) For this example, a value of 0.47F was chosen for a restart time of 59ms. 8.3.21 Output Voltage Divider RFB2 and RFB1 RFB1 and RFB2 set the output voltage level. The ratio of these resistors is calculated as: RFB2 VOUT -1 = RFB1 0.8V (49) The ratio between RCOMP and RFB2 determines the mid-band gain, AFB_MID. A larger value for RFB2 may require a corresponding larger value for RCOMP. RFB2 should be large enough to keep the total divider power dissipation small. 3.24k was chosen for RFB2 in this example, which results in a RFB1 value of 1.05k for 3.3V output. 8.3.22 Loop Compensation Components CCOMP, RCOMP and CHF RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to produce a stable voltage loop. For a quick start, follow the 4 steps listed below. STEP1: Select fCROSS By selecting one tenth of the switching frequency, fCROSS is calculated as follows: fSW = 23 kHz fCROSS = 10 (50) STEP2: Determine required RCOMP Knowing fCROSS, RCOMP is calculated as follows: RCOMP = 2S x RS x AS x COUT x RFB2 x fCROSS [:@ (51) RCOMP = 2S x 8 m: x 10 x 724 F x 3.24 k: x 23 kHz = 27.1 k: (52) The standard value of 27.4k was selected for RCOMP STEP3: Determine CCOMP to cancel load pole Knowing RCOMP, CCOMP is calculated as follows: RLOAD x COUT [F] CCOMP = RCOMP CCOMP = 3.3V 9A (53) x 724 F 27.4 k: = 10 nF (54) The standard value of 10nF was selected for CCOMP STEP4: Determine CHF to cancel ESR zero Knowing RCOMP and CCOMP, CHF is calculated as follows: RESR x COUT x CCOMP CHF = [F] RCOMP x CCOMP - RESR x COUT CHF = (55) 5 m: x 724 F x 10 nF = 134 pF 27.4 k: x 10 nF - 5 m: x 724 F (56) Half of the maximum ESR is assumed as a typical ESR. The standard value of 150pF was selected for CHF. 30 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 Table 1. LM25117 Frequency Analysis Formulas COMPREHENSIVE FORMULA (1) SIMPLE FORMULA s 1+ ^ ZZ_ESR VOUT = AM x ^ VCOMP (1 + s ) Modulator Transfer Function ZP_LF Modulator DC Gain RLOAD R S x AS AM = ZZ_ESR = ESR Zero ESR Pole Dominant Load Pole ZP_LF = R 1 RESR x COUT Not considered Quality Factor Not considered Sub-harmonic Double Pole Not considered - ^ VCOMP ^ V OUT High Frequency Pole (1) 1+ = AFB x LOAD AFB_MID = ZSW Zn = s ZZ_EA 2 s ZP_EA - ) ^ V OUT 1 x (COUT1 // COUT2 ) or ZP_HF = Q x Zn 1 S(K - 0.5) = S x fSW or fn = 1+ = AFB x fSW 2 s ZZ_EA s x (1+ s ZP_EA ) 1 RFB2 x (CCOMP + CHF) AFB = RCOMP RFB2 1 RCOMP x CHF 1 x COUT1 LO RRAMP x CRAMP x RS x AS ^ VCOMP AFB_MID = 1 = fSW 0.5 Q= RCOMP RFB2 1 ZZ_EA = RCOMP x CCOMP ZP_EA K K= s x (1+ ESR1 ESR1 1 1 + + RESR1) x (COUT1 + COUT2) LO x (COUT1 + COUT2) x ZP_HF ZP_HF = 1 RFB2 x (CCOMP + CHF) AFB = Mid-band Gain Low Frequency Zero ZP_LF = (R K=1 K Factor Feedback DC Gain ZP_ESR = R LOAD x COUT 1 RLOAD ZP_HF x LO RLOAD x R S x AS 1 + ZZ_ESR = R 1 Sampled Gain Inductor Pole Feedback Transfer Function ZZ_ESR s s s s2 x ZP_LF) (1 + ZP_ESR ) x (1 + ZP_HF + Zn2 ) AM = Not considered s 1+ ^ VOUT = AM x ^ VCOMP (1 + ZZ_EA = RCOMP x CCOMP ZP_EA = 1 RCOMP x (CHF // CCOMP) Comprehensive Equation includes an inductor pole and a gain peaking at fSW/2, which caused by sampling effect of the current mode control. Also it assumes that a ceramic capacitor COUT2 (No ESR) is connected in parallel with COUT1. RESR1 represents ESR of COUT1 . Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 31 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Table 1. LM25117 Frequency Analysis Formulas (continued) SIMPLE FORMULA s s 1+ 1+ ZZ_ESR ZZ_EA T(s) = AM x AFB x x (1 + s ) s x (1 + s 1+ T(s) = AM x AFB x ZP_EA) ZP_LF Open-Loop Response COMPREHENSIVE FORMULA (1) (1 + AM x AFB x T(s) = s AM x AFB T(s) = s when ZZ_EA = ZP_LF & ZP_EA = ZZ_ESR Crossover Frequency (Open Loop Bandwidth) when & Maximum Crossover Frequency fSW fCROSS_MAX = 5 s ZZ_ESR 2 s s (1 + Z ) x (1 + Z ) x (1 + Z s + s 2 ) P_EA P_ESR P_HF Zn fCROSS = when ZZ_EA = ZP_LF & ZP_EA = ZZ_ESR s 1+ when RCOMP fCROSS = 2 x ' x RS x RFB2 x AS x COUT s 1+ ZZ_ESR ZZ_EA x 2 s s s s s x x ( 1 + s x ZP_EA) ZP_LF) (1 + ZP_ESR ) (1 + ZP_HF + Zn2 ) ZZ_EA = ZP_LF RCOMP 2 x ' x RS x RFB2 x AS x (COUT1 + COUT2) ZZ_EA = ZP_LF ZP_HF fCROSS < 2 x S x 10 fCROSS_MAX = ZP_EA = ZZ_ESR & & fCROSS < ZP_ESR 2 x S x 10 fSW x ( 1 + 4 x Q2 -1) 4xQ The frequency at which 45 phase shift occurs in modulator phase characteristics. 8.4 Application Curves Figure 33. Start-Up with Resistive Load 32 Submit Documentation Feedback Figure 34. Typical Efficiency vs Load Current Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 Application Curves (continued) 8.4.1 Constant Current Regulator The LM25117 can be configured as a constant current regulator by using the current monitor feature (CM) as the feedback input. A voltage divider at the VCCDIS pin from VOUT to AGND can be used to protect against output over-voltage. When the VCCDIS pin voltage is greater than the VCCDIS threshold, the controller disables the VCC regulator and the VCC pin voltage decays. When the VCC pin voltage is less than the VCC UV threshold, both HO and LO outputs stop switching. Due to the time delay required for VCC to decay below the VCC UV threshold, the over-voltage protection operates in hiccup mode. See Figure 35. VIN 100k: CIN UVLO VIN SW RES DEMB VCC 15 k: LM25117 Hiccup Mode OVP 100 k: Triggered at 13.4V HB RAMP VOUT CVCC DHB CHB 1500 pF HO 3.24 k: QH 68 H CC Mode: 2A SW VCCDIS LO 332: VOUT QL 80 F CS 47 m: 0.022 F 3.24 k: CSG CM COMP FB RT SS AGND PGND 2.37 k: 22.1 k: 0.47 F Current Control (CC) Figure 35. Constant Current Regulator with Hiccup Mode Output OVP 8.4.2 Constant Voltage and Constant Current Regulator The LM25117 also can be configured as a constant voltage and constant current regulator, known as CV+CC regulator. In this configuration, there is much less variation in the current limiting as compared to peak cycle-bycycle current limiting of the inductor current. The LMV431 and the PNP transistor create a voltage-to-current amplifier in the current loop. This amplifier circuitry does not affect the normal operation when the output current is less than the current limit set-point. When the output current is greater than the set-point, the PNP transistor sources a current into CRAMP and increases the positive slope of emulated inductor current ramp until the output current is less than or equal to the current limit set-point. See Figure 36 and Figure 37. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 33 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com Application Curves (continued) VIN Current Control (CC) 100 k: VCC SW 10 k: 100: CIN UVLO VIN 15 k: RES DEMB VCC LM25117 100 k: PNP CVCC DHB HB RAMP CHB 1 nF 1500 pF QH HO 100 k: CM 68 PH VOUT CV Mode : 5V CC Mode: 2A SW LMV431 200 k: QL LO VCCDIS 80 PF CS 47 m: VOUT 3.24 k: CSG 34.8 k: 0.1 PF COMP FB RT SS AGND PGND 619: 22.1 k: 0.33 PF x2 Voltage Control (CV) Figure 36. Constant Voltage Regulator with Accurate Current Limit Figure 37. Current Limit Comparison 34 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 LM25117, LM25117-Q1 www.ti.com SNVS714F - APRIL 2011 - REVISED AUGUST 2015 9 Power Supply Recommendations LM25117 is a power management device. The power supply for the device is any DC voltage source within the specified input range. 10 Layout 10.1 Layout Guideline Controller QL Place controller as close to the switches Inductor QH RSENSE VIN CIN COUT CIN COUT GND GND VOUT Figure 38. Layout Example 10.1.1 PC Board Layout Recommendations In a buck regulator the primary switching loop consists of the input capacitor, NMOS power switches and current sense resistor. Minimizing the area of this loop reduces the stray inductance and minimizes noise and possible erratic operation. High quality input capacitors should be placed as close as possible to the NMOS power switches, with the VIN side of the capacitor connected directly to the high-side NMOS drain and the ground side of the capacitor connected as close as possible to the current sense resistor ground connection. Connect all of the low power ground connections (RUV1, RT, RFB1, CSS, CRES, CCM, CVIN, CRAMP) directly to the regulator AGND pin. Connect CVCC directly to the regulator PGND pin. Note that CVIN and CVCC must be as physically close as possible to the IC. AGND and PGND must be directly connected together through a top-side copper pattern connected to the exposed pad. Ensure no high current flows beneath the underside exposed pad. The LM25117 has an exposed thermal pad to aid power dissipation. Adding several vias under the exposed pad helps conduct heat away from the IC. The junction to ambient thermal resistance varies with application. The most significant variables are the area of copper in the PC board, the number of vias under the exposed pad and the amount of forced air cooling. The integrity of the solder connection from the IC exposed pad to the PC board is critical. Excessive voids greatly decrease the thermal dissipation capacity. The highest power dissipating components are the two power switches. Selecting NMOS switches with exposed pads aids the power dissipation of these devices. Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 Submit Documentation Feedback 35 LM25117, LM25117-Q1 SNVS714F - APRIL 2011 - REVISED AUGUST 2015 www.ti.com 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LM25117 Click here Click here Click here Click here Click here LM25117-Q1 Click here Click here Click here Click here Click here 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 36 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM25117 LM25117-Q1 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM25117PMH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM25117 PMH LM25117PMHE/NOPB ACTIVE HTSSOP PWP 20 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM25117 PMH LM25117PMHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM25117 PMH LM25117PSQ/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25117P LM25117PSQE/NOPB ACTIVE WQFN RTW 24 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25117P LM25117PSQX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25117P LM25117QPMH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM25117 QPMH LM25117QPMHE/NOPB ACTIVE HTSSOP PWP 20 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM25117 QPMH LM25117QPMHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM25117 QPMH LM25117QPSQ/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25117Q LM25117QPSQE/NOPB ACTIVE WQFN RTW 24 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25117Q LM25117QPSQX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25117Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2018 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM25117, LM25117-Q1 : * Catalog: LM25117 * Automotive: LM25117-Q1 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LM25117PMHE/NOPB HTSSOP PWP 20 250 178.0 16.4 LM25117PMHX/NOPB HTSSOP PWP 20 2500 330.0 LM25117PSQ/NOPB WQFN RTW 24 1000 178.0 LM25117PSQE/NOPB WQFN RTW 24 250 LM25117PSQX/NOPB WQFN RTW 24 LM25117QPMHE/NOPB HTSSOP PWP LM25117QPMHX/NOPB HTSSOP PWP W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 16.4 6.95 7.1 1.6 8.0 16.0 Q1 12.4 4.3 4.3 1.3 8.0 12.0 Q1 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25117QPSQ/NOPB WQFN RTW 24 LM25117QPSQE/NOPB WQFN RTW 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25117QPSQX/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Sep-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM25117PMHE/NOPB HTSSOP PWP LM25117PMHX/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0 20 2500 367.0 367.0 38.0 LM25117PSQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0 LM25117PSQE/NOPB WQFN RTW 24 250 210.0 185.0 35.0 LM25117PSQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0 LM25117QPMHE/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0 LM25117QPMHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 38.0 LM25117QPSQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0 LM25117QPSQE/NOPB WQFN RTW 24 250 210.0 185.0 35.0 LM25117QPSQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE RTW0024A WQFN - 0.8 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD 4.1 3.9 A B PIN 1 INDEX AREA 4.1 3.9 C 0.8 MAX SEATING PLANE 0.05 0.00 0.08 C 2X 2.5 7 20X 0.5 6 13 2X 2.5 25 2.6 0.1 1 PIN 1 ID (OPTIONAL) (0.1) TYP EXPOSED THERMAL PAD 12 18 24 19 0.5 24X 0.3 24X 0.3 0.2 0.1 0.05 C A B C 4222815/A 03/2016 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT RTW0024A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 2.6) SYMM 24 19 24X (0.6) 1 18 24X (0.25) (1.05) 25 SYMM (3.8) 20X (0.5) (R0.05) TYP 13 6 ( 0.2) TYP VIA 7 12 (1.05) (3.8) LAND PATTERN EXAMPLE SCALE:15X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4222815/A 03/2016 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com EXAMPLE STENCIL DESIGN RTW0024A WQFN - 0.8 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X ( 1.15) (0.675) TYP (R0.05) TYP 24 19 24X (0.6) 1 18 24X (0.25) (0.675) TYP 25 20X (0.5) SYMM (3.8) 13 6 METAL TYP 7 SYMM 12 (3.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 25: 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4222815/A 03/2016 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com MECHANICAL DATA PWP0020A MXA20A (Rev C) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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