DataSheeT - enpirion(R) power solutions EN6360QI 8A PowerSoC Step-Down DC-DC Switching Converter with Integrated Inductor DESCRIPTION The EN6360QI is an Intel(R) Enpirion(R) Power System on a Chip (PowerSoC) DC-DC converter. It integrates the inductor, MOSFET switches, small-signal circuits and compensation in an advanced 8mm x 11mm x 3mm 68-pin QFN package. FEATURES * High Efficiency (Up to 96%) * Excellent Ripple and EMI Performance * Up to 8A Continuous Operating Current * Input Voltage Range (2.5V to 6.6V) The EN6360QI is specifically designed to meet the precise voltage and fast transient requirements of present and future high-performance, low-power processor, DSP, FPGA, memory boards and system level applications in distributed power architectures. The device's advanced circuit techniques, high switching frequency, and proprietary integrated inductor technology deliver high-quality, ultra compact, non-isolated DC-DC conversion. * Frequency Synchronization (Clock or Primary) Intel Enpirion Power Solutions significantly help in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. In addition, a reduction in the number of components required for the complete power solution helps to enable an overall system cost saving. * RoHS Compliant, MSL Level 3, 260C Reflow All Enpirion products are RoHS compliant and leadfree manufacturing environment compatible. * 1.5% VOUT Accuracy (Over Load and Temperature) * Optimized Total Solution Size (190mm2) * Precision Enable Threshold for Sequencing * Programmable Soft-Start * Master/Slave Configuration for Parallel Operation * Thermal Shutdown, Over-Current, Short Circuit, and Under-Voltage Protection APPLICATIONS * Point of Load Regulation for Low-Power, ASICs Multi-Core and Communication Processors, DSPs, FPGAs and Distributed Power Architectures * Blade Servers, RAID Storage and LAN/SAN Adapter Cards, Industrial Automation, Test and Measurement, Embedded Computing, and Printers * Beat Frequency/Noise Sensitive Applicati PVIN ENABLE EN6360QI 2x 22F 1206 90 VOUT AVIN 2x 47F 1206 RA VFB SS 15nF CA R1 80 EFFICIENCY (%) VIN PGND PGND AGND FQADJ Efficiency vs. Output Current 100 VOUT 70 Actual Solution Size 190mm2 60 50 CONDITIONS VIN = 5.0V 40 30 VOUT = 3.3V 20 RB VOUT = 1.2V 10 0 RFQADJ Figure 1: Simplified Applications Circuit 0 1 2 3 4 5 OUTPUT CURRENT (A) 6 7 8 Figure 2: Highest Efficiency in Smallest Solution Size Page 1 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI ORDERING INFORMATION Part Number Package Markings TJ Rating Package Description EN6360QI EN6360QI -40C to +125C 68-pin (8mm x 11mm x 3mm) QFN T&R EVB-EN6360QI EN6360QI QFN Evaluation Board Packing and Marking Information: https://www.intel.com/support/quality-and-reliability/packing.html VFB M/S AGND AVIN ENABLE POK S_OUT 54 53 52 51 50 49 FQADJ 60 55 EN_PB 61 EAOUT NC(SW) 62 56 NC(SW) 63 SS NC 64 57 NC 65 VSENSE NC 66 58 NC 67 59 NC 68 PIN FUNCTIONS 48 S_IN 2 47 BGND NC 3 46 VDDB NC 4 45 NC NC 5 44 NC NC 6 43 PVIN NC 7 42 PVIN NC 8 41 PVIN NC 9 40 PVIN NC 10 39 PVIN NC 11 38 PVIN NC 12 37 PVIN NC 13 36 PVIN NC 14 35 PVIN 69 PGND 25 26 27 28 29 30 31 32 33 34 NC NC(SW) NC(SW) PGND PGND PGND PGND PGND PGND PGND KEEP OUT 24 VOUT 23 VOUT 20 VOUT 22 19 VOUT VOUT 18 VOUT 21 17 VOUT VOUT 16 KEEP OUT VOUT NC KEEP OUT 15 1 NC NC Figure 3: Pin Diagram (Top View) NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NOTE B: White `dot' on top left is pin 1 indicator on top of the device package. NOTE C: Keep-Out are No Connect pads that should not to be electrically connected to each other or to any external signal, ground or voltage. They do not need to be soldered to the PCB. Page 2 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI PIN DESCRIPTIONS PIN 1-15, 25, 4445, 59, 64-68 16-24 26, 27, 62, 63 NAME NC VOUT NC(SW) TYPE FUNCTION - No Connect. These pins must be soldered to PCB but not electrically connected to each other or to any external signal, voltage, or ground. These pins may be connected internally. Failure to follow this guideline may result in device damage. Power Regulated converter output. Connect to the load and place output filter capacitor(s) between these pins and PGND pins. Refer to the Layout Recommendation section. - No Connect. These pins are internally connected to the common switching node of the internal MOSFETs. They must be soldered to PCB but not be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may result in device damage. 28-34 PGND Ground Input/Output power ground. Connect to the ground electrode of the input and output filter capacitors. See VOUT and PVIN pin descriptions for more details. 35-43 PVIN Power Input power supply. Connect to input power supply. Decouple with input capacitor to PGND pin. Refer to the Layout Recommendation section. 46 VDDB Power Internal regulated voltage used for the internal control circuitry. Decouple with an optional 0.1F capacitor to BGND for improved efficiency. This pin may be left floating if board space is limited. 47 BGND Power Ground for VDDB. Refer to pin 46 description. Analog Digital input. A high level on the M/S pin will make this EN6360QI a Slave and the S_IN will accept the S_OUT signal from another EN6360QI for parallel operation. A low level on the M/S pin will make this device a Master and the switching frequency will be phase locked to an external clock. Leave this pin floating if it is not used. Analog Digital output. A low level on the M/S pin will make this EN6360QI a Master and the internal switching PWM signal is output on this pin. This output signal is connected to the S_IN pin of another EN6360QI device for parallel operation. Leave this pin floating if it is not used. Digital POK is a logic level high when VOUT is within -10% to +20% of the programmed output voltage (0.9VOUT_NOM VOUT 1.2VOUT_NOM). This pin has an internal pull-up resistor to AVIN with a nominal value of 94k. Analog Device enable pin. A high level or floating this pin enables the device while a low level disables the device. A voltage ramp from another power converter may be applied for precision enable. Refer to Power Up Sequencing Power Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN) at a quiet point. Can also be connected to an auxiliary supply within a voltage range that is sequencing. 48 49 50 51 52 S_IN S_OUT POK ENABLE AVIN Page 3 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI PIN NAME TYPE FUNCTION 53 AGND Power The quiet ground for the control circuits. Connect to the ground plane with a via right next to the pin. Analog Ternary (three states) input pin. Floating this pin disables parallel operation. A low level configures the device as Master and a high level configures the device as a Slave. A REXT resistor is recommended to pulling M/S high. Refer to Ternary Pin description in the Functional Description section for REXT values. Also refer to S_IN and S_OUT pin descriptions. 54 M/S 55 VFB Analog This is the external feedback input pin. A resistor divider connects from the output to AGND. The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor (CA) and resistor (R1) are required parallel to the upper feedback resistor (RA). The output voltage regulation is based on the VFB node voltage equal to 0.600V. For Slave devices, leave VFB floating. 56 EAOUT Analog Error amplifier output. Allows for customization of the control loop. May be left floating. 57 SS Analog A soft-start capacitor is connected between this pin and AGND. The value of the capacitor controls the soft-start interval. Refer to Soft-Start Operation in the Functional Description section for more details. 58 VSENSE Analog This pin senses output voltage when the device is in pre-bias (or backfeed) mode. Connect VSENSE to VOUT when EN_PB is high or floating. Leave floating when EN_PB is low. 60 FQADJ Analog Frequency adjust pin. This pin must have a resistor to AGND which sets the free running frequency of the internal oscillator. Analog Enable pre-bias input. When this pin is pulled high, the device will support monotonic start-up under a pre-biased load. VSENSE must be tied to VOUT for EN_PB to function. This pin is pulled high internally. Enable pre-bias feature is not available for parallel operations. Ground Power ground thermal pad. Not a perimeter pin. Connect thermal pad to the system GND plane for heat-sinking purposes. Refer to the Layout Recommendation section. 61 69 EN_PB PGND Page 4 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI ABSOLUTE MAXIMUM RATINGS CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Absolute Maximum Pin Ratings PARAMETER SYMBOL MIN MAX UNITS PVIN, AVIN, VOUT -0.3 7.0 V ENABLE, POK, M/S -0.3 VIN+0.3 V VFB, EXTREF, EAOUT, SS, S_IN, S_OUT, FQADJ -0.3 2.5 V MIN MAX UNITS +150 C +150 C +260 C MAX UNITS Absolute Maximum Thermal Ratings PARAMETER CONDITION Maximum Operating Junction Temperature Storage Temperature Range Reflow Peak Body Temperature -65 (10 Sec) MSL3 JEDEC J-STD-020A Absolute Maximum ESD Ratings PARAMETER CONDITION MIN HBM (Human Body Model) 2000 V CDM (Charged Device Model) 500 V RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX UNITS VIN 2.7 6.6 V Output Voltage Range VOUT 0.6 VIN - VDO (1) V Output Current Range IOUT 8 A Operating Ambient Temperature Range TA -40 +85 C Operating Junction Temperature TJ -40 +125 C Input Voltage Range Page 5 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI THERMAL CHARACTERISTICS PARAMETER SYMBOL TYPICAL UNITS TSD 150 C TSDHYS 20 C Thermal Resistance: Junction to Ambient (0 LFM) (2) JA 15 C/W Thermal Resistance: Junction to Case (0 LFM) JC 1.0 C/W Thermal Shutdown Thermal Shutdown Hysteresis (1) VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table. (2) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high thermal conductivity boards. Page 6 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI ELECTRICAL CHARACTERISTICS NOTE: VIN = 6.6V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted. Typical values are at TA = 25C. PARAMETER SYMBOL Operating Input Voltage VIN Feedback Pin Voltage VFB TEST CONDITIONS MIN TYP 2.5 Internal Voltage Reference at: VIN = 5V, ILOAD = 0, TA = 25C MAX UNITS 6.6 V 0.594 0.600 0.606 V 0.591 0.600 0.609 V 0.588 0.600 0.612 V 10 nA 0A ILOAD 8A Feedback Pin Voltage (Load, Temp.) VFB VFB Pin Voltage (Line, Load and Temperature) VVFB Starting Date Code: X501 or greater 2.5V VIN 6.6V 0A ILOAD 8A Feedback pin Input Leakage Current (3) IFB VFB pin input leakage current Shut-Down Supply Current IS Power Supply Current with ENABLE=0 1.5 mA -10 Under Voltage LockOut - VIN Rising VUVLOR Voltage above which UVLO is not asserted 2.2 V Under Voltage LockOut - VIN Falling VUVLOF Voltage below which UVLO is asserted 2.1 V Drop-Out Voltage VDO VINMIN - VOUT at full load 400 800 mV Drop-Out Resistance RDO Input to output resistance 50 100 m 8 A Continuous Output Current IOUT_SRC 0 Over Current Trip Level IOCP Sourcing Current Switching Frequency FSW RFADJ = 4.42 k, VIN = 5V 16 0.9 1.2 0.9*Fsw Fsw A 1.5 1.1*Fs MHz External SYNC Clock Frequency Lock Range FPLL_LOCK SYNC Clock Input Frequency Range S_IN Clock Amplitude - Low VS_IN_LO SYNC Clock Logic Low 0 0.8 V S_IN Clock Amplitude - High VS_IN_HI SYNC Clock Logic High 1.8 2.5 V w MHz Page 7 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI PARAMETER SYMBOL TEST CONDITIONS S_IN Clock Duty Cycle (PLL) DCS_INPLL M/S Pin Float or Low S_IN Clock Duty Cycle (PWM) DCS_INPWM Pre-Bias Level Non-Monotonicity MAX UNITS 20 80 % M/S Pin High 10 90 % VPB Allowable Pre-bias as a Fraction of Programmed Output Voltage for Monotonic start up. Minimum Pre-bias Voltage = 300mV. 20 75 % VPB_NM Allowable Non-monotonicity Under Pre-bias Startup VOUT Range for POK = High(4) Range of Output Voltage as a Fraction of Programmed Value When POK is Asserted. POK Deglitch Delay Falling Edge Deglitch Delay After Output Crossing 90% level. FSW=1.2 MHz VPOK Logic Low level With 4mA Current Sink into POK Pin MIN TYP 100 90 mV 120 213 % s 0.4 V VPOK Logic high level VIN V POK Internal pull-up resistor 94 k +/-10 % Current Balance IOUT VOUT Rise Time Accuracy(3) TRISE ENABLE Logic High VENABLE_HIGH ENABLE Logic Low VENABLE_LOW ENABLE Pin Current M/S Ternary Pin Logic Low IEN VT-LOW With 2 to 4 Converters in Parallel, the Difference Between Nominal and Actual Current Levels. VIN<50mV; RTRACE< 10 m, Iload= # Converter * IMAX tRISE [ms] = CSS [nF] x 0.065; 10nF CSS 30nF(5) (6) 2.5V VIN 6.6V -25 +25 % 1.2 VIN V 0 0.8 V 50 VIN = 6.6V Tie M/S Pin to GND 0 A 0.7 V Page 8 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI PARAMETER SYMBOL TEST CONDITIONS MIN M/S Ternary Pin Logic Float VT-FLOAT M/S Pin is Open 1.1 M/S Ternary Pin Logic High(7) VT-HIGH Pull Up to VIN through an external resistor REXT . Refer to Figure 7. 1.8 Ternary Pin Input Current ITERN 2.5V VIN 4V, REXT = 15k V V 0.8 V Binary Pin Logic High Threshold VB-HIGH ENABLE, S_IN VS_OUT_HIGH 1.4 A ENABLE, S_IN S_OUT High Level UNITS 4V < VIN 6.6V, REXT = 51k VB-LOW VS_OUT_LOW MAX 117 88 Binary Pin Logic Low Threshold S_OUT Low Level TYP 1.8 V 0.4 2.0 V V (3) Parameter not production tested but is guaranteed by design. (4) POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing the 90% level, there is a 256 clock cycle (~213s at 1.2 MHz) delay before POK is de-asserted. The 90% and 92% levels are nominal values. Expect these thresholds to vary by 3%. (5) Rise time calculation begins when AVIN > VUVLO and ENABLE = HIGH. (6) VOUT Rise Time Accuracy does not include soft-start capacitor tolerance. (7) M/S pin is ternary. Ternary pins have three logic levels: high, float, and low. This pin is meant to be strapped to VIN through an external resistor, strapped to GND, or left floating. The state cannot be changed while the device is on. Page 9 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI TYPICAL PERFORMANCE CURVES Efficiency vs. Output Current Efficiency vs. Output Current 100 90 70 60 EFFICIENCY (%) EFFICIENCY (%) 80 VOUT = 2.5V 50 40 VOUT = 1.8V 30 VOUT = 1.2V 20 CONDITIONS VIN = 3.3V VOUT = 1.0V 10 0 0 1 2 3 4 5 6 7 100 90 80 70 60 50 40 30 20 10 0 VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.2V 0 8 1 2 OUTPUT CURRENT (A) 4 5 6 7 8 Output Voltage vs. Output Current 1.820 1.020 1.815 VOUT = 1.8V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 3 OUTPUT CURRENT (A) Output Voltage vs. Output Current 1.810 1.805 1.800 1.795 1.790 CONDITIONS VIN = 3.3V 1.785 1.780 1.015 VOUT = 1.0V 1.010 1.005 1.000 0.995 0.990 CONDITIONS VIN = 3.3V 0.985 0.980 0 1 2 3 4 5 6 7 8 0 1 2 OUTPUT CURRENT (A) 3 4 5 6 7 8 OUTPUT CURRENT (A) Output Voltage vs. Output Current Output Voltage vs. Output Current 3.320 1.820 3.315 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) CONDITIONS VIN = 5.0V VOUT = 1.0V VOUT = 3.3V 3.310 3.305 3.300 3.295 3.290 CONDITIONS VIN = 5.0V 3.285 1.815 VOUT = 1.8V 1.810 1.805 1.800 1.795 1.790 CONDITIONS VIN = 5.0V 1.785 1.780 3.280 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Page 10 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI TYPICAL PERFORMANCE CURVES (CONTINUED) Output Voltage vs. Output Current Output Voltage vs. Input Voltage 1.820 1.015 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.020 VOUT = 1.0V 1.010 1.005 1.000 0.995 0.990 CONDITIONS VIN = 5.0V 0.985 1.815 1.810 1.805 1.800 1.795 1.790 CONDITIONS Load = 0A 1.785 1.780 0.980 0 1 2 3 4 5 6 7 2.4 8 3 1.820 1.815 1.815 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.820 1.810 1.805 1.800 1.795 CONDITIONS Load = 4A 5.4 6 6.6 1.810 1.805 1.800 1.795 1.790 CONDITIONS Load = 8A 1.785 1.780 1.780 2.4 3 3.6 4.2 4.8 5.4 6 6.6 2.4 INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) LOAD = 4A LOAD = 6A 1.799 LOAD = 8A 1.798 1.797 1.796 CONDITIONS VIN = 6.6V VOUT_NOM = 1.8V 1.795 1.794 -40 -15 5.4 6 6.6 LOAD = 0A LOAD = 2A 1.800 LOAD = 4A LOAD = 6A 1.799 LOAD = 8A 1.798 1.797 1.796 CONDITIONS VIN = 5V VOUT_NOM = 1.8V 1.794 35 4.8 1.801 1.795 10 4.2 Output Voltage vs. Temperature LOAD = 2A 1.800 3.6 1.802 LOAD = 0A 1.801 3 INPUT VOLTAGE (V) Output Voltage vs. Temperature 1.802 OUTPUT VOLTAGE (V) 4.8 Output Voltage vs. Input Voltage Output Voltage vs. Input Voltage 1.785 4.2 INPUT VOLTAGE (V) OUTPUT CURRENT (A) 1.790 3.6 60 85 AMBIENT TEMPERATURE (C) -40 -15 10 35 60 AMBIENT TEMPERATURE ( C) 85 Page 11 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI TYPICAL PERFORMANCE CURVES (CONTINUED) Output Voltage vs. Temperature Output Voltage vs. Temperature 1.802 LOAD = 0A 1.801 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.802 LOAD = 2A LOAD = 4A 1.800 LOAD = 6A 1.799 LOAD = 8A 1.798 1.797 1.796 CONDITIONS VIN = 3.6V VOUT_NOM = 1.8V 1.795 1.794 -40 -15 LOAD = 0A LOAD = 2A LOAD = 4A LOAD = 6A LOAD = 8A 1.801 1.800 1.799 1.798 1.797 1.796 CONDITIONS VIN = 2.5V VOUT_NOM = 1.8V 1.795 1.794 10 35 60 -40 85 -15 9 8 7 6 5 4 3 Conditions CONDITIONS = 5.0V VINVIN = 5.0V VOUT = 3.3V VOUT = 3.3V 1 0 -40 -15 10 35 60 85 GUARANTEED OUTPUT CURRENT (A) GUARANTEED OUTPUT CURRENT (A) No Thermal Derating 10 2 35 60 85 No Thermal Derating 10 9 8 7 6 5 4 3 Conditions CONDITIONS = 5.0V VINVIN = 5.0V V = 3.3V OUT VOUT = 1.0V 2 1 0 -40 -15 10 35 60 85 AMBIENT TEMPERATURE(C) AMBIENT TEMPERATURE(C) EMI Performance (Horizontal Scan) EMI Performance (Vertical Scan) 100.0 100.0 CONDITIONS VIN = 5.0V VOUT_NOM = 1.5V LOAD = 0.2 80.0 70.0 80.0 60.0 50.0 CISPR 22 Class B 3m 40.0 CONDITIONS VIN = 5.0V VOUT_NOM = 1.5V LOAD = 0.2 90.0 LEVEL (dBV/m) 90.0 LEVEL (dBV/m) 10 AMBIENT TEMPERATURE (C) AMBIENT TEMPERATURE (C) 70.0 60.0 50.0 30.0 30.0 20.0 20.0 10.0 CISPR 22 Class B 3m 40.0 10.0 10 100 1000 FREQUENCY (MHz) 10 100 1000 FREQUENCY (MHz) Page 12 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI TYPICAL PARALLEL PERFORMACE CHARACTERISTICS Parallel Efficiency vs. Output Current 100 90 80 70 60 50 40 30 20 10 0 EFFICIENCY (%) EFFICIENCY (%) Parallel Efficiency vs. Output Current VOUT = 2.5V VOUT = 1.8V VOUT = 1.2V VOUT = 1.0V 0 2 CONDITIONS VIN = 3.3V 2x EN6360QI 4 6 8 10 12 OUTPUT CURRENT (A) 14 100 90 80 70 60 50 40 30 20 10 0 VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.2V VOUT = 1.0V 0 16 Parallel Current Share Mis-Match 2 1 0 -1 CONDITIONS EN6360QI VIN = 5V VOUT = 3.3V -3 -4 -5 2 4 6 8 10 12 OUTPUT CURRENT (A) 14 16 INDIVIDUAL OUTPUT CURRENT (A) CURRENT MIS-MATCH (%) Mis-match (%) = (I_Master - I_Slave ) / I_Average x 100 3 -2 4 6 8 10 12 OUTPUT CURRENT (A) 14 16 PARALLEL OUTPUT VOLTAGE (V) PARALLEL OUTPUT VOLTAGE (V) CONDITIONS VIN = 5.0V 2x EN6360QI 2 16 9 8 Master Device 7 Slave Device 6 5 4 CONDITIONS EN6360QI VIN = 5V VOUT = 3.3V 3 2 1 0 2 4 6 8 10 12 14 TOTAL OUTPUT CURRENT (A) 16 Parallel Output Voltage vs. Output Current VOUT = 3.3V 0 14 10 Parallel Output Voltage vs. Output Current 3.4 3.38 3.36 3.34 3.32 3.3 3.28 3.26 3.24 3.22 3.2 4 6 8 10 12 OUTPUT CURRENT (A) Parallel Current Share Breakdown 5 4 2 CONDITIONS VIN = 5.0V 2x EN6360QI 1.1 1.08 1.06 1.04 1.02 1 0.98 0.96 0.94 0.92 0.9 VOUT = 1.0V CONDITIONS VIN = 3.3V 2x EN6360QI 0 2 4 6 8 10 12 OUTPUT CURRENT (A) 14 16 Page 13 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI TYPICAL PERFORMANCE CHARACTERISTICS Output Ripple at 500MHz Bandwidth Output Ripple at 20MHz Bandwidth VOUT (AC Coupled) CONDITIONS VIN = 5V VOUT = 1V IOUT = 8A CIN = 2 x 22F (1206) COUT = 2 x 47 F (1206) Output Ripple at 20MHz Bandwidth VOUT (AC Coupled) VOUT (AC Coupled) Output Ripple at 500MHz Bandwidth CONDITIONS VIN = 5V VOUT = 2.4V IOUT = 8A CIN = 2 x 22F (1206) COUT = 2 x 47 F (1206) VOUT (AC Coupled) VOUT CONDITIONS VIN = 5V VOUT = 2.4V IOUT = 8A CIN = 2 x 22F (1206) COUT = 2 x 47 F (1206) Enable Power Up/Down Enable Power Up/Down ENABLE CONDITIONS VIN = 5V VOUT = 1V IOUT = 8A CIN = 2 x 22F (1206) COUT = 2 x 47 F (1206) ENABLE CONDITIONS VIN = 5V VOUT = 1.0V IOUT = 8A Css = 15nF CIN = 2 x 22F (1206) COUT = 2 x 47 F (1206) VOUT CONDITIONS VIN = 5V VOUT = 2.4V IOUT = 8A Css = 15nF CIN = 2 x 22F (1206) COUT = 2 x 47 F (1206) Page 14 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) Load Transient from 0 to 8A Enable/Disable with POK CONDITIONS VIN = 6.2V VOUT = 1.5V CIN = 2 x 22F (1206) COUT = 2 x 47F (1206) ENABLE VOUT VOUT (AC Coupled) POK LOAD CONDITIONS VIN = 5V, VOUT = 1.0V LOAD = 5A, Css = 15nF LOAD Parallel Operation Current Sharing Parallel Operation SW Waveforms MASTER VSW TOTAL LOAD = 18A SLAVE 2 VSW MASTER LOAD = 6A SLAVE 1 VSW SLAVE 2 LOAD = 6A COMBINED LOAD(18A) CONDITIONS VIN = 5V VOUT = 1.8V LOAD = 18A SLAVE 1 LOAD = 6A CONDITIONS VIN = 5V VOUT = 1.8V LOAD = 18A Page 15 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI FUNCTIONAL BLOCK DIAGRAM S_IN S_OUT PVIN Digital I/O M/S To PLL VDDB Eff UVLO BGND Thermal Limit P-Drive Current Limit NC(SW) VOUT N-Drive (-) PWM Comp (+) PGND 24k AVIN Compensation Network PLL/Sawtooth Generator FQADJ EAOUT (-) Error Amp (+) ENABLE SS Reference Voltage Selector Soft Start MUX VFB Power Good Logic POK AVIN 94k MUX Bandgap Reference AVIN VSENSE AVIN 24k EN_PB EAOUT AGND Figure 4: Functional Block Diagram FUNCTIONAL DESCRIPTION Synchronous DC-DC Step-Down PowerSoC The EN6360QI is a synchronous, programmable buck power supply with integrated power MOSFET switches and integrated inductor. The switching supply uses voltage mode control and a low noise PWM topology. This provides superior impedance matching to ICs processed in sub 90nm process technologies. The nominal input voltage range is 2.5 - 6.6 volts. The output voltage is programmed using an external resistor divider network. The feedback control loop incorporates a type IV voltage mode control design. Type IV voltage mode control maximizes control loop bandwidth and maintains excellent phase margin to improve transient performance. The EN6360QI is designed to support up to 8A continuous output current operation. The operating switching frequency is between 0.9MHz and 1.5MHz and enables the use of small-size input and output capacitors. Page 16 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI The power supply has the following features: * Precision Enable Threshold * Soft-Start * Pre-bias Start-Up * Resistor Programmable Switching Frequency * Phase-Lock Frequency Synchronization * Parallel Operation * Power OK * Over-Current/Short Circuit Protection * Thermal Shutdown with Hysteresis * Under-Voltage Lockout Precision Enable Operation The ENABLE threshold is a precision analog voltage rather than a digital logic threshold. A precision voltage reference and a comparator circuit are kept powered up even when ENABLE is de-asserted. The narrow voltage gap between ENABLE Logic Low and ENABLE Logic High allows the device to turn on at a precise enable voltage level. With the enable threshold pinpointed, a proper choice of soft-start capacitor helps to accurately sequence multiple power supplies in a system as desired. There is an ENABLE lockout time of 2ms that prevents the device from re-enabling immediately after it is disabled. See the Electrical Characteristics Table for technical specifications for the ENABLE pin. Soft-Start Operation The SS pin in conjunction with a small external capacitor between this pin and AGND provides a soft-start function to limit in-rush current during device power-up. When the part is initially powered up, the output voltage is gradually ramped to its final value. The gradual output ramp is achieved by increasing the reference voltage to the error amplifier. A constant current flowing into the soft-start capacitor provides the reference voltage ramp. When the voltage on the soft-start capacitor reaches 0.60V, the output has reached its programmed voltage. Once the output voltage has reached nominal voltage the soft-start capacitor will continue to charge to 1.5V (Typical). The output rise time can be controlled by the choice of soft-start capacitor value. The rise time is defined as the time from when the ENABLE signal crosses the threshold and the input voltage crosses the upper UVLO threshold to the time when the output voltage reaches 95% of the programmed value. The rise time (tRISE) is given by the following equation: tRISE [ms] = Css [nF] x 0.065 The rise time (tRISE) is in milliseconds and the soft-start capacitor (CSS) is in nano-Farads. The soft-start capacitor should be between 10nF and 100nF. Pre-Bias Start-up The EN6360QI supports startup into a pre-biased load. A proprietary circuit ensures the output voltage rises up from the pre-bias value to the programmed output voltage. Start-up is guaranteed to be monotonic for pre-bias voltages in the range of 20% to 75% of the programmed output voltage with a minimum pre-bias voltage of 300mV. Outside of the 20% to 75% range, the output voltage rise will not be monotonic. The PrePage 17 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI Bias feature is automatically engaged with an internal pull-up resistor. For this feature to work properly, VIN must be ramped up prior to ENABLE turning on the device. Tie VSENSE to VOUT if Pre-Bias is used. Tie EN_PB to ground and leave VSENSE floating to disable the Pre-Bias feature. Pre-Bias is supported for external clock synchronization, but not supported for parallel operations. Resistor Programmable Frequency The operation of the EN6360QI can be optimized by a proper choice of the RFQADJ resistor. The frequency can be tuned to optimize dynamic performance and efficiency. Refer to Table 1 for recommended RFQADJ values. Table 1: Recommended RFQADJ (k) VOUT 0.8V 1.2V 1.5V 1.8V 2.5V 3.3V 3.3V 10% 3.57 3.57 4.99 5.49 5.49 NA 5.0V 10% 3.57 3.57 4.99 5.49 5.49 4.99 6.0V 10% 3.57 3.57 4.99 5.49 5.49 5.49 VIN Phase-Lock Operation The EN6360QI can be phase-locked to an external clock signal to synchronize its switching frequency. The M/S pin can be left floating or pulled to ground to allow the device to synchronize with an external clock signal using the S_IN pin. When a clock signal is present at S_IN, an activity detector recognizes the presence of the clock signal and the internal oscillator phase locks to the external clock. The external clock could be the system clock or the output of another EN6360QI. The phase locked clock is then output at S_OUT. Refer to Table 2 for recommended clock frequencies. Table 2: Recommended Clock fsw (MHz)10% VOUT 0.8V 1.2V 1.5V 1.8V 2.5V 3.3V 3.3V 10% 1.15 1.15 1.30 1.35 1.35 NA 5.0V 10% 1.15 1.15 1.30 1.35 1.35 1.30 6.0V 10% 1.15 1.15 1.30 1.35 1.35 1.35 VIN Master / Slave (Parallel) Operation and Frequency Synchronization Multiple EN6360QI devices may be connected in a Master/Slave configuration to handle larger load currents. The device is placed in Master mode by pulling the M/S pin low or in Slave mode by pulling M/S pin high. When the M/S pin is in float state, parallel operation is not possible. In Master mode, a version of the internal switching PWM signal is output on the S_OUT pin. This PWM signal from the Master is fed to the Slave device at its S_IN pin. The Slave device acts like an extension of the power FETs in the Master and inherits the PWM frequency and duty cycle. The inductor in the Slave prevents crow-bar currents from Master to Slave due to timing delays. The Master device's switching clock may be phase-locked to an external clock source or another EN6360QI to move the entire parallel operation frequency away from sensitive frequencies. The feedback network for the Slave device may be left open. Additional Slave devices may be paralleled together with the Page 18 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI Master by connecting the S_OUT of the Master to the S_IN of all other Slave devices. Refer to Figure 5 for details. Careful attention is needed in the layout for parallel operation. The VIN, VOUT and GND of the paralleled devices should have low impedance connections between each other. Maximize the amount of copper used to connect these pins and use as many vias as possible when using multiple layers. Place the Master device between all other Slaves and closest to the point of load. GND EN6360QI SLAVE3 S_IN VOUT M/S VIN REXT VFB OPEN GND EN6360QI SLAVE2 S_IN VOUT M/S VIN REXT VFB OPEN GND S_OUT EN6360QI MASTER VOUT VOUT VIN M/S VIN VFB Feedback & Compensation GND S_IN EN6360QI SLAVE1 VOUT VIN M/S VFB REXT Figure 5: Master/Slave Parallel Operation Diagram POK Operation Page 19 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI POK Operation The POK signals that the output voltage is within the specified range. The POK signal is asserted high when the rising output voltage crosses 92% (nominal) of the programmed output voltage. If the output voltage falls outside the range of 90% to 120%, POK remains asserted for the de-glitch time (213s at 1.2MHz). After the de-glitch time, POK is de-asserted. POK is also de-asserted if the output voltage exceeds 120% of the programmed output voltage. Over-Current Protection (OCP) The current limit function is achieved by sensing the current flowing through a sense P-FET. When the sensed current exceeds the current limit, both power FETs are turned off for the rest of the switching cycle. If the over-current condition is removed, the over-current protection circuit will reenable PWM operation. If the over-current condition persists, the circuit will continue to protect the load. The OCP trip point is nominally set as specified in the Electrical Characteristics table. In the event the OCP circuit trips consistently in normal operation, the device enters a hiccup mode. The device is disabled for 27ms and restarted with a normal soft-start. This cycle can continue indefinitely as long as the over current condition persists. Thermal Protection Temperature sensing circuits in the controller will disable operation when the junction temperature exceeds approximately 150C. Once the junction temperature drops by approx 20C, the converter will re-start with a normal soft-start. Input Under-Voltage Lock-Out (UVLO) When the input voltage is below a required voltage level (V UVHI) for normal operation, the converter switching is inhibited. The lock-out threshold has hysteresis to prevent chatter. Thus when the device is operating normally, the input voltage has to fall below the lower threshold (VUVLO) for the device to stop switching. Page 20 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI APPLICATION INFORMATION Output Voltage Programming and loop Compensation The EN6360QI output voltage is programmed using a simple resistor divider network. A phase lead capacitor plus a resistor are required for stabilizing the loop. Figure 6 shows the required components and the equations to calculate their values. The EN6360QI output voltage is determined by the voltage presented at the VFB pin. This voltage is set by way of a resistor divider between VOUT and AGND with the midpoint going to VFB. The EN6360QI uses a type IV compensation network. Most of this network is integrated. However, a phase lead capacitor and a resistor are required in parallel with upper resistor of the external feedback network (Refer to Figure 6). Total compensation is optimized for use with two 47F output capacitance and will result in a wide loop bandwidth and excellent load transient performance for most applications. Additional capacitance may be placed beyond the voltage sensing point outside the control loop. Voltage mode operation provides high noise immunity at light load. Furthermore, voltage mode control provides superior impedance matching to ICs processed in sub 90nm technologies. In some cases modifications to the compensation or output capacitance may be required to optimize device performance such as transient response, ripple, or hold-up time. The EN6360QI provides the capability to modify the control loop response to allow for customization for such applications. For more information, contact Power Applications support. VOUT RA CA R1 VFB RB Figure 6: External Feedback/Compensation Network The feedback and compensation network values depend on the input voltage and output voltage. Calculate the external feedback and compensation network values with the equations below. RA [] = 48,400 x VIN [V] RB[] = (VFB x RA) / (VOUT - VFB) [V] VFB = 0.6V nominal *Round RA & RB to closest standard value CA [F] = 3.83 x 10-6 / RA [] *Round CA down to closest standard value R1 = 15k Page 21 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI The feedback resistor network should be sensed at the last output capacitor close to the device. Keep the trace to VFB pin as short as possible. Whenever possible, connect RB directly to the AGND pin instead of going through the GND plane. Input Capacitor Selection The EN6360QI has been optimized for use with two 1206 22F input capacitors. Low ESR ceramic capacitors are required with X5R or X7R dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. In some applications, lower value ceramic capacitors may be needed in parallel with the larger capacitors in order to provide high frequency decoupling. The capacitors shown in the table below are typical input capacitors. Other capacitors with similar characteristics may also be used. Table 3: Recommended Input Capacitors Description MFG P/N 22F, 10V, 20%, X5R, 1206 Murata GRM31CR61A226ME19L (2 capacitors needed) Taiyo Yuden LMK316BJ226ML-T Output Capacitor Selection The EN6360QI has been optimized for use with two 1206 47F output capacitors. Low ESR, X5R or X7R ceramic capacitors are recommended as the primary choice. Y5V or equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. The capacitors shown in the Recommended Output Capacitors table are typical output capacitors. Other capacitors with similar characteristics may also be used. Additional bulk capacitance from 100F to 1000F may be placed beyond the voltage sensing point outside the control loop. This additional capacitance should have a minimum ESR of 6m to ensure stable operation. Most tantalum capacitors will have more than 6m of ESR and may be used without special care. Adding distance in layout may help increase the ESR between the feedback sense point and the bulk capacitors. Table 4: Recommended Output Capacitors Description MFG P/N Taiyo Yuden LMK316BJ476ML-T 47F, 6.3V, 20%, X5R, 1206 Murata GRM31CR60J476ME19L (2 capacitors needed) Taiyo Yuden JMK316BJ476ML-T Murata GRM21BR70J106KE76L Taiyo Yuden JMK212B7106KG-T 47F, 10V, 20%, X5R, 1206 (2 capacitors needed) 10F, 6.3V, 10%, X7R, 0805 (Optional 1 capacitor in parallel with 2x47F) Page 22 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI Output ripple voltage is primarily determined by the aggregate output capacitor impedance. Placing multiple capacitors in parallel reduces the impedance and hence will result in lower ripple voltage. 1 Z Total = 1 1 1 + + ... + Z1 Z 2 Zn Table 5: Typical Ripple Voltages Output Capacitor Configuration Typical Output Ripple (mVp-p) 2 x 47 F <10mV 20 MHz bandwidth limit measured on Evaluation Board M/S - Ternary Pin M/S is a ternary pin. This pin can assume 3 states - A low state (0V to 0.7V), a high state (1.8V to VIN) and a float state (1.1V to 1.4V). Device operation is controlled by the state of the pin. The pins may be pulled to ground or left floating without any special care. When pulling high to VIN, a series resistor is recommended. The resistor value may be optimized to reduce the current drawn by the pin. The resistance should not be too high as in that case the pin may not recognize the high state. The recommend resistance (REXT) value is given in the following table. Table 6: Recommended REXT Resistor VIN (V) IMAX (A) REXT (k) 2.5 - 4.0 117 15 4.0 - 6.6 88 51 2.5V R3 319 To VIN M/S R1 134k To Gates REXT Vf D1 2V R2 134k AGND Inside EN6360QI Figure 7: Selection of REXT to Connect M/S pin to VIN Page 23 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI Table 7: M/S (Master/Slave) Pin States M/S Pin Low (0V to 0.7V) Float (1.1V to 1.4V) High (>1.8V) Function M/S pin is pulled to ground directly. This is the Master mode. Switching PWM phase will lock onto S_IN external clock if a signal is available. S_OUT outputs a version of the internal switching PWM signal. M/S pin is left floating. Parallel operation is not feasible. Switching PWM phase will lock onto S_IN external clock if a signal is available. S_OUT outputs a version of the internal switching PWM signal. M/S pin is pulled to VIN with REXT. This is the Slave mode. The S_IN signal of the Slave should connect to the S_OUT of the Master device. This signal synchronizes the switching frequency and duty cycle of the Master to the Slave device. Power-Up Sequencing During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN. Tying all three pins together meets these requirements. Page 24 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI THERMAL CONSIDERATIONS Thermal considerations are important power supply design facts that cannot be avoided in the real world. Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. The Intel Enpirion PowerSoC helps alleviate some of those concerns. The Intel Enpirion EN6360QI DC-DC converter is packaged in an 8x11x3mm 68-pin QFN package. The QFN package is constructed with copper lead frames that have exposed thermal pads. The exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to act as a heat sink. The recommended maximum junction temperature for continuous operation is 125C. Continuous operation above 125C may reduce long-term reliability. The device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 150C. The EN6360QI is guaranteed to support the full 8A output current up to 85C ambient temperature. The following example and calculations illustrate the thermal performance of the EN6360QI. Example: VIN = 5V VOUT = 3.3V IOUT = 8A First calculate the output power. POUT = 3.3V x 8A = 26.4W Next, determine the input power based on the efficiency () shown in Figure 8. EFFICIENCY (%) Efficiency vs. Output Current 100 90 80 70 60 50 40 30 20 10 0 CONDITIONS VIN = 5.0V VOUT = 3.3V 0 1 2 3 4 5 6 7 8 OUTPUT CURRENT (A) Figure 6: Efficiency vs. Output Current Page 25 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI For VIN = 5V, VOUT = 3.3V at 8A, 94% = POUT / PIN = 94% = 0.94 PIN = POUT / PIN 26.4W / 0.94 28.085W The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output power from the input power. PD = PIN - POUT 28.085W - 26.4W 1.685W With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA value (JA). The JA parameter estimates how much the temperature will rise in the device for every watt of power dissipation. The EN6360QI has a JA value of 15 C/W without airflow. Determine the change in temperature (T) based on PD and JA. T = PD x JA T 1.685W x 15C/W = 25.28C 25.3C The junction temperature (TJ) of the device is approximately the ambient temperature (T A) plus the change in temperature. We assume the initial ambient temperature to be 25C. TJ = TA + T TJ 25C + 25.3C 50.3C With 1.685W dissipated into the device, the TJ will be 50.3C. The maximum operating junction temperature (TJMAX) of the device is 125C, so the device can operate at a higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated. TAMAX = TJMAX - PD x JA 125C - 25.3C 99.7C The ambient temperature can actually rise by another 74.7C, bringing it to 99.7C before the device will reach TJMAX. This indicates that the EN6360QI can support the full 8A output current range up to approximately 99.7C ambient temperature given the input and output voltage conditions. This allows the EN6360QI to guarantee full 8A output current capability at 85C with room for margin. Note that the efficiency will be slightly lower at higher temperatures and this estimate will be slightly lower. Page 26 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI ENGINEERING SCHEMATIC Figure 9: Engineering Schematic with Engineering Notes Page 27 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI LAYOUT RECOMMENDATIONS Figure 10: Top Layout with Critical Components Only (Top View) This layout only shows the critical components and top layer traces for minimum footprint in single-supply mode with ENABLE tied to AVIN. Alternate circuit configurations & other low-power pins need to be connected and routed according to customer application. Please see the Gerber files at http://www.intel.com/enpirion for details on all layers. Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EN6360QI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EN6360QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: The PGND connections for the input and output capacitors on layer 1 need to have a slit between them in order to provide some separation between input and output current loops. Recommendation 3: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Recommendation 4: The thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the path for heat dissipation from the converter. Recommendation 5: Multiple small vias (the same size as the thermal vias discussed in recommendation 4) should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. It is preferred to put these vias along the edge of the GND copper closest to the +V copper. These vias Page 28 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops. Recommendation 6: AVIN is the power supply for the small-signal control circuits. It should be connected to the input voltage at a quiet point. In Figure 10 this connection is made at the input capacitor. Recommendation 7: The layer 1 metal under the device must not be more than shown in Figure 10. Refer to the section regarding Exposed Metal on Bottom of Package. As with any switch-mode DC/DC converter, try not to run sensitive signal or control lines underneath the converter package on other layers. Recommendation 8: The VOUT sense point should be just after the last output filter capacitor. Keep the sense trace short in order to avoid noise coupling into the node. Recommendation 9: Keep RA, CA, RB, and R1 close to the VFB pin (Refer to Figure 10). The VFB pin is a highimpedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect R B directly to the AGND pin instead of going through the GND plane. Recommendation 10: Follow all the layout recommendations as close as possible to optimize performance. Not following layout recommendations can complicate designs and create anomalies different than the expected operation of the product. Page 29 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES Exposed Metal on Bottom of Package Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. However, they do require some special considerations. In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package, as shown in Figure 11. Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board. The PCB top layer under the EN6360QI should be clear of any metal (copper pours, traces, or vias) except for the thermal pad. The "shaded-out" area in Figure 11 represents the area that should be clear of any metal on the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted connections even if it is covered by soldermask. The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from causing bridging between adjacent pins or other exposed metal under the package. Please consult EN6360QI Application Notes - Soldering Guidelines for more details and recommendations. Figure 11: Lead-Frame exposed metal (Bottom View) Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB. Page 30 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI Figure 12: EN6360QI PCB Footprint (Top View) The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing specifications. Page 31 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI PACKAGE DIMENSIONS Figure 13: EN6360QI Package Dimensions Packing and Marking Information: https://www.intel.com/support/quality-and-reliability/packing.html Page 32 06489 October 16, 2019 Rev J Datasheet | Intel(R) Enpirion(R) Power Solutions: EN6360QI REVISION HISTORY Rev Date Change(s) H May, 2018 Changed datasheet into Intel format. Updated EMI Horizontal and Vertical graphs. I Dec, 2018 Updated EN6360QI Package J Oct, 2019 Corrected Package Top Marking WHERE TO GET MORE INFORMATION For more information about Intel(R) and Enpirion(R) PowerSoCs, visit: www.intel.com/enpirion (c) 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. * Other marks and brands may be claimed as the property of others. Page 33 06489 October 16, 2019 Rev J