General Description
The MAX6892/MAX6893/MAX6894 pin-selectable, mul-
tivoltage supply sequencers/supervisors monitor sever-
al voltage-detector inputs and one watchdog input,
asserting the respective voltage detector or watchdog
output when the inputs drop below the configured volt-
age thresholds or the watchdog timer expires. The
MAX6892 features eight voltage detector inputs and 10
outputs. The MAX6893 features six voltage-detector
inputs and eight outputs, while the MAX6894 features
four voltage detector inputs and six outputs. A RESET
output ensures all monitored inputs are above the set
thresholds. The voltage detector outputs are configured
as open drain. Manual reset and margin disable inputs
offer additional flexibility.
The thresholds of the MAX6892/MAX6893/MAX6894 are
selected through five logic inputs (TH0–TH4). The logic on
these five inputs selects the supply voltage tolerance (5%
or 10%) and one of 32 factory-set thresholds settings.
Watchdog and reset timeout periods can use factory
default settings or are independently adjustable by con-
necting external capacitors.
When any of the monitored voltages falls below its
threshold, the respective output asserts and remains
asserted for 6.25ms (typ) after the monitored voltage
exceeds the threshold. The outputs can be connected
to the shutdown or enable inputs of DC-DC regulators
to provide turn-on power sequencing to ensure proper
system initialization.
The MAX6892 is available in a 5mm x 5mm x 0.8mm,
32-pin, Thin QFN package, while the MAX6893/
MAX6894 are available in a 5mm x 5mm x 0.8mm, 28-
pin, Thin QFN package. The MAX6892/MAX6893/
MAX6894 are specified to operate over the extended
temperature range (-40°C to +85°C).
Applications
Telecommunication/Central Office Systems
Networking Systems
Servers/Workstations
Base Stations
Storage Equipment
Multimicroprocessor/Voltage Systems
Features
oPin-Selectable or User-Adjustable Voltage
Detector Thresholds
oDedicated RESET and WDO Outputs
oCapacitor-Adjustable Reset and Watchdog
Timeout Periods
oFactory-Default Reset and Watchdog Timeout
Periods
oUp to Eight Independent, Open-Drain Power-Good
Outputs
oEnable Margining Disable and Manual Reset
Controls
o-40°C to +85°C Operating Temperature Range
oSmall 5mm x 5mm Thin QFN Package
oFew External Components
o±1% Threshold Accuracy
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
________________________________________________________________
Maxim Integrated Products
1
PART TEMP RANGE PIN-PACKAGE
MAX6892ETJ -40°C to +85°C 32 Thin QFN-EP*
MAX6893ETI -40°C to +85°C 28 Thin QFN-EP*
MAX6894ETI -40°C to +85°C 28 Thin QFN-EP*
Ordering Information
19-3596; Rev 2; 9/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Typical Operating Circuit appears at end of data sheet.
Pin Configurations
32 31 30 29 28 27 26
9 101112131415
18
19
20
21
+
22
23
24
7
6
5
4
3
2
1
MAX6892
THIN QFN
TOP VIEW
PG3
PG2
PG4
GND
PG5
PG6
PG7
8
*EP
*EXPOSED PAD INTERNALLY CONNECTED TO GND.
PG8
PG1
WDI
IN1
IN2
IN3
IN4
IN5
25
IN6
IN7
IN8
DBP
VCC
ENABLE
SRT
SWT
17 TH4
TH2
TH1
16
TH3
TH0
MR
MARGIN
WDO
RESET
Pin Configurations continued at end of data sheet.
Note: Devices are also available in a lead(Pb)-free/RoHS-compli-
ant package. Specify lead-free by adding a plus (+) to the part
number when ordering.
*
EP = Exposed pad.
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN1 = VIN6–VIN8 = VGND, VIN2–VIN5 = 2.7V to 5.5V, WDI = ENABLE = GND, TH0–TH4 = MARGIN = MR = DBP, TA= -40°C to
+85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
PG_, RESET, WDO .................................................-0.3V to +14V
IN1–IN8, TH0–TH4, ENABLE, WDI, MR, MARGIN,
SRT, SWT, VCC .....................................................-0.3V to +6V
DBP ..........................................................................-0.3V to +3V
Input/Output Current (all pins)..........................................±20mA
Continuous Power Dissipation (TA= +70°C)
28-Pin Thin QFN (derate 21.3mW/°C
above +70°C).............................................................1702mW
32-Pin Thin QFN (derate 21.3mW/°C
above +70°C)............................................................1702mW
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
Lead(Pb)-Free..............................................................+260°C
Containing Lead (Pb)...................................................+240°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage Range
(Note 3)
Voltage on either one of IN2–IN5 or VCC that
guarantees the part is fully operational 2.7 5.5 V
Undervoltage Lockout VUVLO
For 1V < (VIN2–VIN5 or VCC ) < VUVLO,
PG_ are pulled down to GND with a 10µA
current
2.5 V
Digital Bypass Voltage VDBP No load
2.48 2.55 2.67
V
Supply Current ICC VIN2 = 5.5V, VIN1, VIN3–VIN8 = VGND, no
load 0.9 1.1 mA
TA = +25°C to +85°C -1 +1
Threshold Accuracy (Table 2) VTH IN1–IN8,
IN_ falling TA = -40°C to +85°C -2 +2
% VTH
Threshold Hysteresis
VTH-HYS
0.3
% VTH
Threshold Tempco
ΔVTH/°C
10
ppm/°C
IN1, IN6–IN8
Input Leakage Current IIN IN2–IN5 set as adjustable thresholds
-50
+50
nA
IN2–IN5 Input Impedance
RIN2–IN5
For IN_ voltages < the highest IN_ supply or
< VCC and thresholds are not set as
adjustable
290 400 555
kΩ
Power-Up Delay tD-PO VCC ≥ VUVLO 3ms
IN_ to PG_ Delay tD-R IN_ falling/rising, 100mV overdrive 25 µs
PG_ Timeout Period tPG
5.625 6.25 6.875
ms
RESET Default Timeout Period tRP VSRT = VCC
180 200 220
ms
RESET Adjustable Timeout Period
tRP-ADJ CSRT = 47nF
135 207 280
ms
SRT Adjustable Timeout Current ISRT VSRT = VGND
180 230 280
nA
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN6–VIN8 = VGND, VIN2–VIN5 = 2.7V to 5.5V, WDI = ENABLE = GND, TH0–TH4 = MARGIN = MR = DBP, TA= -40°C to
+85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
SRT Default Timeout Threshold
VSRT-DEF
VSRT ≥ VSRT-DEF, selects reset default
timeout 1.1
1.25
1.5 V
SRT Adjustable Timeout
Threshold
VSRT-ADJ
(Note 4)
0.95
1.0
1.05
V
SRT Adjustable Timeout
Discharge Threshold
VSRT-DIS
(Note 5)
100
mV
SRT Adjustable Timeout Output
Low Discharge Current
ISRT-DIS
VSRT = 0.3V 0.7 mA
PG_, RESET, WDO Output Low VOL ISINK = 4mA, output asserted 0.4 V
PG_, RESET, WDO Output Initial
Pulldown Current IUV VCC
<
VUVLO, VPG_, V RESET, V WDO = 0.8V 10 40 µA
PG_, RESET, WDO Output Open-
Drain Leakage Current ILKG Output high impedance -1 +1 µA
VIL 0.6
MR, MARGIN, ENABLE,
TH0–TH4, WDI Input Voltage VIH 1.4 V
MR Input Pulse Width T MR 1µs
MR Glitch Rejection
100
ns
MR to RESET Delay tD-MR 2µs
MR to DBP Pullup Current I MR V MR = 1.4V 5 10 15 µA
MARGIN to DBP Pullup Current
I MARGIN
V MARGIN = 1.4V 5 10 15 µA
ENABLE to PG_ Delay
tD-ENPG 200
ns
ENABLE Pulldown Current V ENABLE = 0.6V 5 10 15 µA
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN6–VIN8 = VGND, VIN2–VIN5 = 2.7V to 5.5V, WDI = ENABLE = GND, TH0–TH4 = MARGIN = MR = DBP, TA= -40°C to
+85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
TH0–TH4 Input Current -1 +1 µA
WDI Pulldown Current IWDI VWDI = 0.6V 5 10 15 µA
WDI Input Pulse Width 50 ns
Initial mode
92.16 102.4 112.64
Watchdog Default Timeout Period
tWD VSWT = VCC Normal mode
1.44
1.6
1.76
s
Initial mode
53.7 82.5 111.9
Watchdog Adjustable Timeout
Period
tWD-ADJ
CSWT = 0.33µF Normal mode
0.93 1.43 1.94
s
SWT Adjustable Timeout Current
ISWT VSWT = VGND
180 230 280
nA
SWT Default Timeout Threshold
VSWT-DEF
VSWT ≥ VSWT-DEF, selects watchdog default
timeout period 1.1
1.25
1.5 V
SWT Adjustable Timeout
Threshold
VSWT-ADJ
(Note 4)
0.95
1.0
1.05
V
SWT Adjustable Timeout
Discharge Threshold
VSWT-DIS
(Note 5)
100
mV
SWT Adjustable Timeout Output
Low Discharge Current
ISWT-DIS
VSWT = 0.3V 0.7 mA
Note 1: 100% production tested at TA= +25°C and TA= +85°C. Specifications at TA= -40°C are guaranteed by design.
Note 2: Device may be supplied from any one of IN2–IN5, or VCC.
Note 3: The internal supply voltage, measured at VCC, equals the maximum of IN2–IN5.
Note 4: External capacitor is charged by IS_T when VS_T-DIS < VS_T < VS_T-ADJ.
Note 5: External capacitor is discharged by IS_T-DIS down to VS_T-DIS after VS_T reaches VS_T-ADJ.
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
_______________________________________________________________________________________
5
Typical Operating Characteristics
(VIN1 = VIN6–VIN8 = VGND, VIN2–VIN5 = 2.7V to 5.5V, VWDI = VGND, VTH0–VTH4 = VMARGIN = VMR = VDBP. Typical values are at TA= +25°C.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE (IN2–IN5)
MAX6892 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
5.04.54.03.53.0
0.6
0.7
0.8
0.9
1.0
1.1
0.5
2.5 5.5
TA = +85°C
TA = -40°CTA = +25°C
5.04.54.03.53.02.5 5.5
SUPPLY CURRENT
vs. SUPPLY VOLTAGE (VCC)
MAX6892 toc02
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
0.6
0.7
0.8
0.9
1.0
1.1
0.5
TA = +85°C
TA = -40°C
TA = +25°C
NORMALIZED PG_ TIMEOUT PERIOD
vs. TEMPERATURE
MAX6892 toc03
TEMPERATURE (°C)
NORMALIZED PG_ TIMEOUT PERIOD
603510-15
0.8
0.9
1.0
1.1
1.2
1.3
0.7
-40 85
IN_TO PG_ PROPAGATION DELAY (μs)
12
14
16
18
20
22
24
26
28
30
10
IN_ TO PG_ PROPAGATION DELAY
vs. TEMPERATURE
MAX6892 toc04
TEMPERATURE (°C)
603510-15-40 85
100mV OVERDRIVE
NORMALIZED RESET TIMEOUT PERIOD
0.985
0.990
0.995
1.000
1.010
1.005
1.015
1.020
0.980
NORMALIZED DEFAULT RESET
TIMEOUT PERIOD vs. TEMPERATURE
MAX6892 toc05
TEMPERATURE (°C)
603510-15-40 85
tRP = 200ms
VSRT = VCC
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
0.90
NORMALIZED RESET TIMEOUT PERIOD
NORMALIZED ADJUSTABLE RESET
TIMEOUT PERIOD vs. TEMPERATURE
MAX6892 toc06
TEMPERATURE (°C)
603510-15-40 85
tRP = 200ms
CSRT = 47nF
NORMALIZED WATCHDOG TIMEOUT PERIOD
0.97
0.98
0.99
1.00
1.02
1.01
1.03
1.04
0.96
NORMALIZED DEFAULT WATCHDOG
TIMEOUT PERIOD vs. TEMPERATURE
MAX6892 toc07
TEMPERATURE (°C)
603510-15-40 85
tRP = 1.6s
VSWT = VCC
NORMALIZED WATCHDOG TIMEOUT PERIOD
0.85
0.90
0.95
1.00
1.10
1.05
1.15
1.20
0.80
NORMALIZED ADJUSTABLE WATCHDOG
TIMEOUT PERIOD vs. TEMPERATURE
MAX6892 toc08
TEMPERATURE (°C)
603510-15-40 85
tRP = 1.6s
CSWT = 0.33μF
0.996
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
0.995
NORMALIZED IN_ THRESHOLD
NORMALIZED IN_ THRESHOLD
vs. TEMPERATURE
MAX6892 toc09
TEMPERATURE (°C)
603510-15-40 85
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
6 _______________________________________________________________________________________
100101 1000
MAXIMUM IN_ TRANSIENT
vs. IN_ THRESHOLD OVERDRIVE
MAX6892 toc10
IN_ THRESHOLD OVERDRIVE (mV)
MAXIMUM TRANSIENT DURATION (μs)
25
50
75
100
125
150
175
200
0
PG_ ASSERTION OCCURS
OUTPUT VOLTAGE LOW
vs. SINK CURRENT
MAX6892 toc11
ISINK (mA)
VOL (mV)
13 141210 11345678912
50
100
150
200
250
300
350
400
450
500
0
015
MR TO RESET PROPAGATION DELAY (ns)
1.85
1.90
1.95
2.00
2.10
2.05
2.15
2.20
1.80
MR TO RESET PROPAGATION DELAY
vs. TEMPERATURE
MAX6892 toc12
TEMPERATURE (°C)
603510-15-40 85
RESET TIMEOUT PERIOD vs. CSRT
MAX6892 toc13
CSRT (nF)
TIMEOUT PERIOD (ms)
100101
1
10
100
1000
10,000
0.1
0.1 1000
WATCHDOG TIMEOUT PERIOD vs. CSWT
MAX6892 toc14
CSWT (nF)
TIMEOUT PERIOD (ms)
100101
1
10
100
1000
10,000
0.1
0.1 1000
Typical Operating Characteristics (continued)
(VIN1 = VIN6–VIN8 = VGND, VIN2–VIN5 = 2.7V to 5.5V, VWDI = VGND, VTH0–VTH4 = VMARGIN = VMR = VDBP. Typical values are at TA= +25°C.)
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
_______________________________________________________________________________________ 7
PIN
MAX6892 MAX6893 MAX6894 NAME FUNCTION
1 1 1 PG2
Open-Drain, Power-Good Output 2. PG2 asserts low when the voltage input at
IN2 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG2 deasserts with a factory preset timeout period of 6.25ms.
2 2 2 PG3
Open-Drain, Power-Good Output 3. PG3 asserts low when the voltage input at
IN3 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG3 deasserts with a factory preset timeout period of 6.25ms.
3 3 3 PG4
Open-Drain, Power-Good Output 4. PG4 asserts low when the voltage input at
IN4 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG4 deasserts with a factory preset timeout period of 6.25ms.
4 4 4 GND Ground
5 5 — PG5
Open-Drain, Power-Good Output 5. PG5 asserts low when the voltage input at
IN5 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG5 deasserts with a factory preset timeout period of 6.25ms.
6 6 — PG6
Open-Drain, Power-Good Output 6. PG6 asserts low when the voltage input at
IN6 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG6 deasserts with a factory preset timeout period of 6.25ms.
7 — — PG7
Open-Drain, Power-Good Output 7. PG7 asserts low when the voltage input at
IN7 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG7 deasserts with a factory preset timeout period of 6.25ms.
8 — — PG8
Open-Drain, Power-Good Output 8. PG8 asserts low when the voltage input at
IN8 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG8 deasserts with a factory preset timeout period of 6.25ms.
97 7RESET
Open-Drain, Active-Low Reset Output Stage. RESET asserts low when any
monitored input (IN_) is below the selected threshold or manual reset (MR) is
pulled low. RESET remains low for the reset timeout period after all reset-
causing conditions are cleared, and then deasserts.
10 8 8 WDO
Open-Drain, Active-Low Watchdog Output Stage. If WDI remains high or low for
longer than the watchdog timeout period, the internal watchdog timer runs out
and the WDO output asserts low. The internal watchdog timer clears whenever
RESET is asserted or WDI sees a rising or falling edge. Connect WDO to MR to
automatically assert the RESET output after each watchdog timeout fault.
11 9 9 MARGIN
Margin Input. MARGIN holds PG_, RESET, and WDO in their existing states
when driven low. Leave MARGIN unconnected or connect to DBP if unused.
MARGIN overrides MR if both assert at the same time. MARGIN is internally
pulled up to DBP through a 10µA current source.
12 10 10 MR
Active-Low Manual Reset Input. Pull MR low to assert RESET. RESET remains
asserted for its preset/adjustable reset timeout period when MR is driven/pulled
high. MR is internally pulled up to DBP through a 10µA current source.
13 11 11 TH0
Threshold Selection Input 0. Logic input to select desired thresholds. Connect
TH0 to GND or DBP. See Table 2 for available thresholds. Input has no internal
pullup or pulldown.
Pin Description
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
8 _______________________________________________________________________________________
Pin Description (continued)
PIN
MAX6892
MAX6893 MAX6894
NAME FUNCTION
14 12 12 TH1
Threshold Selection Input 1. Logic input to select desired thresholds. Connect
TH1 to GND or DBP. See Table 2 for available thresholds. Input has no internal
pullup or pulldown.
15 13 13 TH2
Threshold Selection Input 2. Logic input to select desired thresholds. Connect
TH2 to GND or DBP. See Table 2 for available thresholds. Input has no internal
pullup or pulldown.
16 14 14 TH3
Threshold Selection Input 3. Logic input to select desired thresholds. Connect
TH3 to GND or DBP. See Table 2 for available thresholds. Input has no internal
pullup or pulldown.
17 15 15 TH4
Threshold Selection Input 4. Logic input to select desired thresholds. Connect
TH4 to GND or DBP. See Table 2 for available thresholds. Input has no internal
pullup or pulldown.
18 16 16 SWT
Watchdog Timeout Adjust Input. Connect SWT to VCC to select the default
watchdog timeout period. Connect an external capacitor between SWT and
GND to adjust the watchdog timeout period. The adjustable timeout period is
calculated by tWP = 4.348E6 x CSWT (tWP in seconds and CSWT in Farads).
Disable the watchdog timer by connecting SWT to GND.
19 17 17 SRT
Reset Timeout Adjust Input. Connect SRT to VCC to select the default reset
timeout period. Connect an external capacitor between SRT and GND to adjust
the reset timeout period. The adjustable timeout period is calculated by tRP =
4.348E6 x CSWT (tRP in seconds and CSRT in Farads).
20 18 18
ENABLE
Active-Low, PG_ Enable Input. Pull ENABLE high to force all PG_ outputs low.
PG_ outputs remain asserted for their timeout period when ENABLE is
driven/pulled low. ENABLE is internally pulled down to GND through a 10µA
current sink.
21 19 19 VCC
Internal Supply Voltage. Bypass VCC to GND with a 1µF capacitor as close to
the device as possible. VCC supplies power to the internal circuitry. VCC is
internally powered from the highest of the monitored IN2–IN5 voltages. Do not
use VCC to supply power to external circuitry. To externally supply VCC, see the
Powering the MAX6892/MAX6893/MAX6894 section.
22 20 20 DBP
Digital Bypass Voltage. DBP supplies power to the output stages. Bypass DBP
to GND with a 1µF capacitor as close to the device as possible. Do not use
DBP to supply power to external circuitry.
23 — — IN8
Input Voltage 8. Select undervoltage threshold using TH0–TH4. See Table 2.
For improved noise immunity, bypass IN8 to GND with a 0.1µF capacitor as
close to the device as possible.
24 — — IN7
Input Voltage 7. Select undervoltage threshold using TH0–TH4. See Table 2.
For improved noise immunity, bypass IN7 to GND with a 0.1µF capacitor as
close to the device as possible.
MAX6892/MAX6893/MAX6894
Pin Description (continued)
PIN
MAX6892 MAX6893 MAX6894 NAME FUNCTION
25 21 — IN6
Input Voltage 6. Select undervoltage threshold using TH0–TH4. See Table 2.
For improved noise immunity, bypass IN6 to GND with a 0.1µF capacitor as
close to the device as possible.
26 22 — IN5
Input Voltage 5. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or VCC (see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN5 to GND with a 0.1µF capacitor as close to the device as possible.
27 23 23 IN4
Input Voltage 4. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or VCC (see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN4 to GND with a 0.1µF capacitor as close to the device as possible.
28 24 24 IN3
Input Voltage 3. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or VCC (see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN3 to GND with a 0.1µF capacitor as close to the device as possible.
29 25 25 IN2
Input Voltage 2. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or VCC (see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN2 to GND with a 0.1µF capacitor as close to the device as possible.
30 26 26 IN1
Input Voltage 1. Select undervoltage threshold using TH0–TH4. See Table 2.
For improved noise immunity, bypass IN1 to GND with a 0.1µF capacitor as
close to the device as possible.
31 27 27 WDI
Watchdog Timer Input. Logic input for the watchdog timer function. If WDI is
not strobed with a valid low-to-high or high-to-low transition within the watchdog
timeout period, the watchdog output asserts low. The watchdog timeout period
is externally adjustable with capacitor CSWT or selectable for a fixed internal
timeout period. The watchdog has a long timeout period (92.16s minimum fixed
or 64x the adjusted short timeout period) after each reset event and a short
timeout period (1.44s minimum or an adjusted timeout period) after the first
valid WDI transition.
32 28 28 PG1
Open-Drain, Power-Good Output 1. PG1 asserts low when the voltage input at
IN1 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG1 deasserts with a factory preset timeout period of 6.25ms.
— — 5, 6, 21, 22 N.C. No Connection. Not internally connected.
——— EP
Exposed Pad. Internally connected to GND. Connect EP to GND or leave
unconnected.
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
_______________________________________________________________________________________ 9
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
10 ______________________________________________________________________________________
Functional Diagram
LOGIC ARRAY
WOI
ENABLE
MARGIN
MR
VREF
IN2 DETECTOR
IN3 DETECTOR
IN4 DETECTOR
IN5 DETECTOR
IN6 DETECTOR
IN1
IN3
IN4
IN5*
IN6*
IN2 IN_
DETECTOR
PG2 OUTPUT
PG3 OUTPUT
PG4 OUTPUT
PG5 OUTPUT
PG6 OUTPUT
PG7 OUTPUT
PG8 OUTPUT
PG2
SWT
DBP
DBP
SRT
PG3
PG4
PG5*
PG6*
PG7**
PG8
PG1
10μA POWER-UP
PULLDOWN
1μF
1μF
THRESHOLD
SELECTION
LOGIC
TH1
TH0
TH2
TH3
TH4
GND
*FOR MAX6892/MAX6893 ONLY.
**FOR MAX6892 ONLY.
IN7 DETECTORIN7**
IN8 DETECTORIN8**
WDO OUTPUT
RESET OUTPUT
WDO
RESET
OPEN-DRAIN
ACTIVE-LOW
PG_ OUTPUT
2.55V
LDO
DBP
(VIRTUAL
DIODES)
VCC
MAX6892
MAX6893
MAX6894
MAX6892/MAX6893/MAX6894
Detailed Description
The MAX6892/MAX6893/MAX6894 pin-selectable, mul-
tivoltage supply sequencers/supervisors monitor sever-
al voltage detector inputs and one watchdog input,
asserting the outputs when the respective input thresh-
olds have been reached or a timeout occurs. All ver-
sions have an enable manual reset and margin input
disable. The MAX6892/MAX6893/MAX6894 voltage
thresholds are selected by logic inputs and/or an exter-
nal voltage-divider. A RESET output ensures all moni-
tored inputs are above the pin-selected/adjustable
thresholds. Watchdog and reset timeout periods can
use factory default settings or are independently
adjustable by connecting external capacitors. In addi-
tion, all devices can be powered through the voltage
detector inputs alone, or externally supplied from a
constant supply on the VCC pin (see the
Powering the
MAX6892/MAX6893/MAX6894
section). The outputs
are factory configured as open drain.
Powering the
MAX6892/MAX6893/MAX6894
The MAX6892/MAX6893/MAX6894 derive power from
the voltage detector inputs: IN2–IN5 (MAX6892/
MAX6893), IN2–IN4 (MAX6894), or through an external-
ly supplied VCC. A virtual diode-ORing scheme selects
the positive input that supplies power to the device
(see the
Functional Diagram
). The highest input voltage
on IN2–IN5 (MAX6892/MAX6893)/IN2–IN4 (MAX6894)
supplies power to the device. One of IN2–IN5
(MAX6889/MAX6890)/IN2–IN4 (MAX6891) or VCC must
be at least 2.7V to ensure proper operation.
Internal hysteresis ensures that the supply input that
initially powered the device continues to power the
device when multiple input voltages are within 50mV of
each other.
VCC powers the analog circuitry and is the bypass con-
nection for the MAX6892/MAX6893/MAX6894 internal
supply. Bypass VCC to GND with a 1µF ceramic capac-
itor installed as close to the device as possible. The
internal supply voltage, measured at VCC, equals the
maximum of IN2–IN5. If VCC is externally supplied, VCC
must be at least 200mV higher than any voltage
applied to IN2–IN5 and VCC must be brought up first.
VCC always powers the device when all IN_ are factory
set as “ADJ.” Do not use the internally generated VCC
to provide power to external circuitry.
The MAX6892/MAX6893/MAX6894 also generate a dig-
ital supply voltage (DBP) for the internal logic circuitry
and the output stages. Bypass DBP to GND with a 1µF
ceramic capacitor installed as close to the device as
possible. The nominal DBP output voltage is 2.55V. Do
not use DBP to provide power to external circuitry.
Inputs
The MAX6892/MAX6893/MAX6894 contain multiple
logic and voltage detector inputs. Each voltage detec-
tor input is monitored for undervoltage thresholds.
Voltage Detector Inputs (IN_)
The MAX6892/MAX6893/MAX6894 offer several moni-
tor options with both pin-selectable and adjustable
reset thresholds. The threshold voltage at each
adjustable IN_ input is typically 0.6V. To monitor a volt-
age > 0.6V, connect a resistor-divider network to the
circuit as shown in Figure 1:
VIN_TH = VTH (R1+ R2)/R2 (Equation 1)
where VIN_TH is the desired reset threshold voltage for
the respective IN_ and VTH is the input threshold
(0.6V).
Resistors R1and R2can have high values to minimize
current consumption due to low-leakage currents. Set
R2to some conveniently high value (10kΩ, for exam-
ple) and calculate R1based on the desired reset
threshold voltage, using the following formula:
R1= R2x (VIN_TH/VTH - 1)
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
______________________________________________________________________________________ 11
IN_
GND
VCC
VCC
VIN_TH
VIN_TH = 0.6 x (R1 + R2)/R2
R1
R2
MAX6892
MAX6893
MAX6894
Figure 1. Adjusting the Monitored Threshold
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
12 ______________________________________________________________________________________
Threshold Logic Inputs (TH0–TH4)
The TH0–TH4 logic inputs select the undervoltage thresh-
olds and tolerance of the IN1–IN8 inputs (MAX6892),
IN1–IN6 inputs (MAX6893), and IN1–IN4 inputs
(MAX6894). TH0–TH4 define 32 unique options for the
supervisor functionality. Connect the respective TH_ to
GND for a logic 0 or to DBP for a logic 1. Tables 1 and 2
show the 32 unique threshold options available. TH4 sets
the threshold tolerance of the undervoltage threshold. A
logic 1 selects a 5% supply tolerance and a logic 0
selects 10% supply tolerance. The MAX6892/MAX6893/
MAX6894 logic determines which thresholds should be
used for the IN inputs only at power-up. Use the voltage-
divider circuit of Figure 1 and Equation 1 to set the
threshold for the user-adjustable inputs as described in
the
Voltage Detector Inputs (IN_)
section.
Table 1. Nominal Monitored Supply Voltages
MONITORED SUPPLY VOLTAGES (V)
SELECTION TH4–TH0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8
SUPPLY
TOLERANCE (%)
1 11111 ADJ 5 3.3 2.5 1.8 ADJ ADJ ADJ 5
2 11110 ADJ 5 3 2.5 1.8 ADJ ADJ ADJ 5
3 11101 ADJ 5 3.3 2.5 ADJ ADJ ADJ ADJ 5
4 11100 ADJ 5 3 2.5 ADJ ADJ ADJ ADJ 5
5 11011 ADJ 5 3.3 1.8 ADJ ADJ ADJ ADJ 5
6 11010 ADJ 5 3 1.8 ADJ ADJ ADJ ADJ 5
7 11001 ADJ 5 3.3 ADJ ADJ ADJ ADJ ADJ 5
8 11000 ADJ 5 3 ADJ ADJ ADJ ADJ ADJ 5
9 10111 ADJ 3.3 2.5 1.8 ADJ ADJ ADJ ADJ 5
10 10110 ADJ 3 2.5 1.8 ADJ ADJ ADJ ADJ 5
11 10101 ADJ 3.3 2.5 ADJ ADJ ADJ ADJ ADJ 5
12 10100 ADJ 3 2.5 ADJ ADJ ADJ ADJ ADJ 5
13 10011 ADJ 3.3 1.8 ADJ ADJ ADJ ADJ ADJ 5
14 10010 ADJ 3 1.8 ADJ ADJ ADJ ADJ ADJ 5
15 10001 ADJ 3.3 2.5 1.8 1.5 ADJ ADJ ADJ 5
16 10000 ADJ 3 2.5 1.8 1.5 ADJ ADJ ADJ 5
17 01111 ADJ 5 3.3 2.5 1.8 ADJ ADJ ADJ 10
18 01110 ADJ 5 3 2.5 1.8 ADJ ADJ ADJ 10
19 01101 ADJ 5 3.3 2.5 ADJ ADJ ADJ ADJ 10
20 01100 ADJ 5 3 2.5 ADJ ADJ ADJ ADJ 10
21 01011 ADJ 5 3.3 1.8 ADJ ADJ ADJ ADJ 10
22 01010 ADJ 5 3 1.8 ADJ ADJ ADJ ADJ 10
23 01001 ADJ 5 3.3 ADJ ADJ ADJ ADJ ADJ 10
24 01000 ADJ 5 3 ADJ ADJ ADJ ADJ ADJ 10
25 00111 ADJ 3.3 2.5 1.8 ADJ ADJ ADJ ADJ 10
26 00110 ADJ 3 2.5 1.8 ADJ ADJ ADJ ADJ 10
27 00101 ADJ 3.3 2.5 ADJ ADJ ADJ ADJ ADJ 10
28 00100 ADJ 3 2.5 ADJ ADJ ADJ ADJ ADJ 10
29 00011 ADJ 3.3 1.8 ADJ ADJ ADJ ADJ ADJ 10
30 00010 ADJ 3 1.8 ADJ ADJ ADJ ADJ ADJ 10
31 00001 ADJ 3.3 2.5 1.8 1.5 ADJ ADJ ADJ 10
32 00000 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ —
MAX6892/MAX6893/MAX6894
Table 2. Threshold Options
THRESHOLD VOLTAGES (V)
SELECTION TH4–TH0* IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8
1 11111 0.60 4.62 3.06 2.31 1.67 0.60 0.60 0.60
2 11110 0.60 4.62 2.78 2.31 1.67 0.60 0.60 0.60
3 11101 0.60 4.62 3.06 2.31 0.60 0.60 0.60 0.60
4 11100 0.60 4.62 2.78 2.31 0.60 0.60 0.60 0.60
5 11011 0.60 4.62 3.06 1.67 0.60 0.60 0.60 0.60
6 11010 0.60 4.62 2.78 1.67 0.60 0.60 0.60 0.60
7 11001 0.60 4.62 3.06 0.60 0.60 0.60 0.60 0.60
8 11000 0.60 4.62 2.78 0.60 0.60 0.60 0.60 0.60
9 10111 0.60 3.06 2.31 1.8 0.60 0.60 0.60 0.60
10 10110 0.60 2.78 2.31 1.8 0.60 0.60 0.60 0.60
11 10101 0.60 3.06 2.31 0.60 0.60 0.60 0.60 0.60
12 10100 0.60 2.78 2.31 0.60 0.60 0.60 0.60 0.60
13 10011 0.60 3.06 1.67 0.60 0.60 0.60 0.60 0.60
14 10010 0.60 2.78 1.67 0.60 0.60 0.60 0.60 0.60
15 10001 0.60 3.06 2.31 1.67 1.39 0.60 0.60 0.60
16 10000 0.60 2.78 2.31 1.67 1.39 0.60 0.60 0.60
17 01111 0.60 4.38 2.88 2.19 1.58 0.60 0.60 0.60
18 01110 0.60 4.38 2.62 2.19 1.58 0.60 0.60 0.60
19 01101 0.60 4.38 2.88 2.19 0.60 0.60 0.60 0.60
20 01100 0.60 4.38 2.62 2.19 0.60 0.60 0.60 0.60
21 01011 0.60 4.38 2.88 1.58 0.60 0.60 0.60 0.60
22 01010 0.60 4.38 2.62 1.58 0.60 0.60 0.60 0.60
23 01001 0.60 4.38 2.88 0.60 0.60 0.60 0.60 0.60
24 01000 0.60 4.38 2.62 0.60 0.60 0.60 0.60 0.60
25 00111 0.60 2.88 2.19 1.8 0.60 0.60 0.60 0.60
26 00110 0.60 2.62 2.19 1.8 0.60 0.60 0.60 0.60
27 00101 0.60 2.88 2.19 0.60 0.60 0.60 0.60 0.60
28 00100 0.60 2.62 2.19 0.60 0.60 0.60 0.60 0.60
29 00011 0.60 2.88 1.58 0.60 0.60 0.60 0.60 0.60
30 00010 0.60 2.62 1.58 0.60 0.60 0.60 0.60 0.60
31 00001 0.60 2.88 2.19 1.58 1.31 0.60 0.60 0.60
32 00000 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60
*
TH4 = ‘1’ selects 7.5% threshold tolerance, TH4 = ‘0’ selects 12.5% threshold tolerance.
Contact factory for alternative thresholds.
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
______________________________________________________________________________________ 13
WDI
tRP *tWDI *tWDI
tWD
tD-PO
tRP tRP
*tWDI *tWDI
tWD
tD-PO
WDO NOT CONNECTED TO MR
WDO CONNECTED TO MR.
VCC OR IN2–IN5
2.5V
WDI
VCC OR IN2–IN5
2.5V
*tWDI IS THE INITIAL WATCHDOG TIMEOUT PERIOD.
RESET
WDO
WDO
RESET
Figure 2. Watchdog, Reset, and Power-Up Timing Diagram
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
14 ______________________________________________________________________________________
Watchdog Timer
The MAX6892/MAX6893/MAX6894s’ watchdog circuit
monitors the microprocessor’s (µP’s) activity. If the µP
does not toggle the watchdog input (WDI) within the
watchdog timeout period, the watchdog output (WDO)
asserts. The internal watchdog timer is cleared by
RESET, or by a transition at WDI (which can detect
pulses as short as 50ns). The watchdog timer remains
cleared while reset is asserted. The timer starts count-
ing as soon as WDO is released (see Figure 2).
The MAX6892/MAX6893/MAX6894 feature two modes
of watchdog timer operation: normal mode and initial
mode. At power-up, after a reset event, or after the
watchdog timer expires, the initial watchdog timeout is
active. After the first transition on WDI, the normal
watchdog timeout is active. The initial and normal
watchdog timeouts are determined by the value of the
capacitor connected between SWT and ground or by
connecting SWT to VCC (see the
Selecting the Reset and
Watchdog Timeout Capacitor
section). The initial watch-
dog timeout is approximately 64 times the normal watch-
dog timeout. For example, in initial mode a 1µF capacitor
gives a watchdog timeout period of about 5min.
If WDO is connected to MR, the WDO asserts for a
short duration (~5µs), long enough to assert the RESET
output. Asserting RESET clears the watchdog timer and
WDO goes high. The reset output remains asserted for
its timeout period after a watchdog fault. The watchdog
timer stays cleared as long as RESET is low.
The watchdog timeout period is determined by the
value of the capacitor connected between SWT and
ground (see the
Selecting the Reset/Watchdog Timeout
Capacitor
section). Connect SWT to DBP to select fac-
tory-programmed watchdog timeout. To disable the
watchdog timer connect SWT to GND.
MAX6892/MAX6893/MAX6894
Manual Reset (MR)
Many µP-based products require manual reset capabil-
ity to allow an operator or external logic circuitry to initi-
ate a reset. The manual reset input (MR) can connect
directly to a switch without an external pullup resistor or
debouncing network. MR is internally pulled up to DBP
through a 10µA current source and, therefore, can be
left unconnected if unused.
MR is designed to reject fast falling transients (typically
100ns pulses) and it must be held low for a minimum of
1µs to assert RESET. After MR transitions from low to
high, RESET remains asserted for the duration of the
reset timeout period.
Margin Output Disable (MARGIN)
MARGIN allows system-level testing while power sup-
plies exceed the normal ranges. Driving MARGIN low
forces PG_, RESET, and WDO to hold the last state
while system-level testing occurs. Leave MARGIN
unconnected or connect to DBP if unused. An internal
10µA current source pulls MARGIN to DBP. The state of
each programmable output, RESET, and WDO does
not change while MARGIN = GND.
Enable Input
ENABLE is an active-low, logic input. Driving ENABLE
high pulls all PG_ low. Drive ENABLE low or leave
unconnected for normal operation. ENABLE is internally
pulled down to GND through a 10µA current sink.
Power-Good Outputs
The MAX6892 features eight power-good outputs, the
MAX6893 features six power-good outputs, and the
MAX6894 features four power-good outputs. Each out-
put (PG_) responds to its respective input (IN_). Each
PG_ is open drain. During power-up, the outputs pull
down to GND with an internal 10µA current sink for 1V
< VCC < VUVLO.
RREESSEETT
Output
The reset output is typically connected to the reset
input of a µP. A µP’s reset input starts or restarts the µP
in a known state. The MAX6892/MAX6893/MAX6894
supervisory circuits provide the reset logic to prevent
code-execution errors during power-up, power-down,
and brownout conditions.
RESET changes from high to low whenever one or more
input voltage (IN1–IN8) monitors drop below their
respective reset threshold voltage or when MR is pulled
low for a minimum of 1µs. Once the affected input volt-
age monitor(s) exceeds its respective reset threshold
voltage(s), RESET remains low for the reset timeout
period, then deaaserts.
Applications Information
Selecting the Reset/Watchdog
Timeout Capacitor
The reset timeout period can be adjusted to accommo-
date a variety of µP applications. Adjust the reset time-
out period (tRP) by connecting a capacitor (CSRT)
between SRT and ground. Calculate the reset timeout
capacitor as follows:
CSRT = tRP/(4.348 x 106)
with tRP in seconds and CSRT in Farads. Connect SRT
to VCC for a factory-programmed reset timeout of
200ms (typ).
The watchdog timeout period can be adjusted to
accommodate a variety of µP applications. With this
feature, the watchdog timeout can be optimized for
software execution. The programmer can determine
how often the watchdog timer should be serviced.
Adjust the watchdog timeout period (tWD) by connect-
ing a specific value capacitor (CSWT) between SWT
and GND. For normal mode operation, calculate the
watchdog timeout capacitor as follows:
CSWT = tWD/(4.348 x 106)
with tWD in seconds and CSWT in Farads. Connect SWT
to VCC for a factory-programmed watchdog timeout of
1.6s (normal mode) and 102.4s (initial mode).
CSRT and CSWT must be a low-leakage (< 10nA) type
capacitor. Ceramic capacitors are recommended.
Layout and Bypassing
For better noise immunity, bypass each of the voltage
detector inputs to GND with 0.1µF capacitors installed
as close to the device as possible. Bypass VCC and
DBP to GND with 1µF capacitors installed as close to
the device as possible.
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
______________________________________________________________________________________ 15
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
16 ______________________________________________________________________________________
Pin Configuration (continued)
28 27 26 25 24 23 22
8 9 10 11 12 13
16
17
18
19
20
21
7
6
5
4
3
2
1
MAX6893
THIN QFN
TOP VIEW
PG3
PG2
PG4
GND
PG5
PG6
RESET
*EXPOSED PAD INTERNALLY CONNECTED TO GND.
PG1
WDI
IN1
IN2
IN3
IN4
IN5
IN6
DBP
VCC
ENABLE
SRT
SWT
15 TH4
TH2
TH1
14
TH3
TH0
MR
MARGIN
WDO
28 27 26 25 24 23 22
8 9 10 11 12 13
16
17
18
19
20
21
7
6
5
4
3
2
1
MAX6894
THIN QFN
TOP VIEW
PG3
PG2
PG4
GND
N.C.
N.C.
RESET
*EXPOSED PAD INTERNALLY CONNECTED TO GND.
PG1
WDI
IN1
IN2
IN3
IN4
N.C.
N.C.
DBP
VCC
ENABLE
SRT
SWT
15 TH4
TH2
TH1
14
TH3
TH0
MR
MARGIN
WDO
*EP *EP
++
MAX6892/MAX6893/MAX6894
MAX6893
5V SUPPLY
PG2
PG3
PG4
5V BUS INPUT
tPG2
tPG3
tPG4
tPG5
ENABLE 3.3V DC-DC CONVERTER
3.3V SUPPLY 3.3V OUTPUT
ENABLE 1.8V DC-DC CONVERTER
1.8V SUPPLY 1.8V OUTPUT
ENABLE 2.5V DC-DC CONVERTER
2.5V SUPPLY
PG5
RESET
2.5V OUTPUT
ENABLE 1.5V DC-DC CONVERTER
1.5V SUPPLY 1.5V OUTPUT
tRESET
DC-DC
1
DBP
TH0
TH1
TH2
TH3
TH4
PG2IN2IN1
DC-DC
2
IN3 PG3
DC-DC
3
IN4 PG4 PG5
GND
IN5 IN6
1.5V
1.8V
2.5V
5V
3.3V
5V
WDI
WDO
RESETRESET
MR
MARGIN
LOGIC OUTPUT
LOGIC INPUT
PG1 PG6SRT SWT
VCC
CSRT CSWT
ENABLE
SYSTEM RESET
DC-DC
4
μP
Typical Operating Circuit
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
______________________________________________________________________________________ 17
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
18 ______________________________________________________________________________________
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
28 Thin QFN T2855+8 21-0140 90-0028
32 Thin QFN T3255+4 21-0140 90-0012
MAX6892/MAX6893/MAX6894
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
19
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 2/05 Initial release —
1 9/10 Add lead-free package, add exposed pad info, update Absolute Maximum Ratings,
style edits
1–6, 8–11, 13,
15, 16, 18, 19
