PS020823-0208
DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
Document Disclaimer
©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this
document has been verified according to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered
trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.
Warning:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Revision History
iii
Revision History
Each instance in the Revision History table reflects a change to this document from its
previous revision. For more details, refer to the corresponding pages or appropriate link in
the table.
Date
Revision
Level Description
Page
Number
February
2008
23 Updated Ordering Information section. 87
January
2008
22 Updated Ordering Information section. 87
July 2007 21 Updated Disclaimer section and implemented style
guide.
All
February
2007
20 Updated Low-Voltage Detection.58
May
2006
19 Updated Figure 33 with pin P22 in SMR block input. 52
December
2005
18 Updated Clock and Input/Output Ports sections. 15 and 51
Crimzon® ZLP32300
Product Specification
PS020823-0208 Table of Contents
iv
Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Development Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Watchdog Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . . . 60
Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . . . . 65
Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Crimzon® ZLP32300
Product Specification
PS020823-0208 Architectural Overview
1
Architectural Overview
Zilog’s Crimzon® ZLP32300 is an OTP-based member of the MCU family of infrared
microcontrollers. With 237 B of general-purpose RAM and 8 KB to 32 KB of OTP,
Zilog’s CMOS microcontrollers offer fast-executing, efficient use of memory,
sophisticated interrupts, input/output bit manipulation capabilities, automated pulse
generation/reception, and internal key-scan pull-up transistors.
The Crimzon ZLP32300 architecture (see Figure 1 on page 3) is based on Zilog’s 8-bit
microcontroller core with an Expanded Register File allowing access to register-mapped
peripherals, input/output (I/O) circuits, and powerful counter/timer circuitry. The Z8®
CPU offers a flexible I/O scheme, an efficient register and address space structure, and a
number of ancillary features that are useful in many consumer, automotive, computer
peripheral, and battery-operated hand-held applications.
There are three basic address spaces available to support a wide range of configurations:
1. Program Memory
2. Register File
3. Expanded Register File
The register file is composed of 256 Bytes of RAM. It includes four I/O port registers, 16
control and status registers, and 236 general-purpose registers. The Expanded Register
File consists of two additional register groups (F and D).
To unburden the program from coping with such real-time problems as generating
complex waveforms or receiving and demodulating complex waveform/pulses, the
Crimzon ZLP32300 offers a new intelligent counter/timer architecture with 8-bit and
16-bit counter/timers (see Figure 2 on page 4). Also included are a large number of user-
selectable modes and two on-board comparators to process analog signals with separate
reference voltages.
All signals with an overline, “ ”, are active Low. For example, B/W, in which WORD is
active Low, and B/W, in which BYTE is active Low.
Power connections use the conventional descriptions listed in Table 1.
Table 1. Power Connections
Connection Circuit Device
Power VCC VDD
Ground GND VSS
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Architectural Overview
2
Development Features
Table 2 lists the features of Crimzon ZLP32300 family.
The additional features include:
•
Low power consumption–11 mW (typical)
•
Three standby modes:
–STOP—1.7 µA (typical)
–HALT—0.6 mA (typical)
–Low-voltage reset
•
Special architecture to automate both generation and reception of complex pulses or
signals:
–One programmable 8-bit counter/timer with two capture registers and two load
registers
–One programmable 16-bit counter/timer with one 16-bit capture register pair and
one 16-bit load register pair
–Programmable input glitch filter for pulse reception
•
Six priority interrupts
–Three external
–Two assigned to counter/timers
–One Low-Voltage Detection interrupt
•
Low-Voltage Detection and high voltage detection Flags
•
Programmable Watchdog Timer/Power-On Reset (WDT/POR) circuits
•
Two independent comparators with programmable interrupt polarity
•
Programmable EPROM options
–Port 0: 0–3 pull-up transistors
–Port 0: 4–7 pull-up transistors
–Port 1: 0–3 pull-up transistors
–Port 1: 4–7 pull-up transistors
Table 2. Crimzon ZLP32300 MCU Features
Device OTP(KB) RAM* (Bytes) I/O Lines Voltage Range
Crimzon ZLP32300 8, 16, 32 237 32, 24 or 16 2.0–3.6 V
*General purpose
Crimzon® ZLP32300
Product Specification
PS020823-0208 Architectural Overview
3
–Port 2: 0–7 pull-up transistors
–EPROM Protection
–WDT enabled at POR
Functional Block Diagram
Figure 1 displays the Crimzon ZLP32300 MCU functional block diagram.
Figure 1. Crimzon ZLP32300 MCU Functional Block Diagram
Z8® Core
Port 2
Port 0
P21
P22
P23
P24
P25
P26
P27
P20
I/O Bit
Programmable
P04
P05
P06
P07
P00
P01
P02
P03
I/O Nibble
Programmable
Register File
256 x 8-Bit
Register Bus
Internal
Address Bus
Internal
Data Bus
Expanded
Register
File
Expanded
Register Bus
Z8
®
Core
Counter/Timer 8
8-Bit
Counter/Timer 16
16-Bit
V
DD
V
SS
XTAL
RESET
Pref1/P30
P31
P32
P33
P34
P35
P36
P37
Port 3
Machine
Timing and
Instruction
Control
Power
4
4
OTP
Up to 32 K x 8
Port 1
P14
P15
P16
P17
P10
P11
P12
P13
I/O Byte
Programmable
8
Watchdog
Timer
Low-Voltage
Detection
High-Voltage
Detection
Power-On
reset
Note: Refer to the specific package for available pins.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Architectural Overview
4
Figure 2. Counter/Timers Diagram
HI16 LO16
16-Bit
T16
TC16H TC16L
HI8 LO8
And/Or
Logic
Clock
Divider
Glitch
Filter
Edge
Detect
Circuit 8-Bit
T8
TC8H TC8L
88
16
8
Input
SCLK
1248
Timer 16
Timer 8/16
Timer 8
88
88
8
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
5
Pin Description
The pin configuration for the 20-pin PDIP/SOIC/SSOP is displayed in Figure 3 and
described in Table 3. The pin configuration for the 28-pin PDIP/SOIC/SSOP are depicted
in Figure 4 and described in Table 4. The pin configurations for the 40-pin PDIP and 48-
pin SSOP versions are displayed in Figure 5, Figure 6, and described in Table 5.
Figure 3. 20-Pin PDIP/SOIC/SSOP Pin Configuration
Table 3. 20-Pin PDIP/SOIC/SSOP Pin Identification
Pin No Symbol Function Direction
1–3 P25–P27 Port 2, Bits 5,6,7 Input/Output
4 P07 Port 0, Bit 7 Input/Output
5V
DD Power Supply
6 XTAL2 Crystal Oscillator Clock Output
7 XTAL1 Crystal Oscillator Clock Input
8–10 P31–P33 Port 3, Bits 1,2,3 Input
11,12 P34, P36 Port 3, Bits 4,6 Output
13 P00/Pref1/P30 Port 0, Bit 0/Analog reference input
Port 3 Bit 0
Input/Output for P00
Input for Pref1/P30
14 P01 Port 0, Bit 1 Input/Output
15 VSS Ground
16–20 P20–P24 Port 2, Bits 0,1,2,3,4 Input/Output
P25
P26
P27
P07
VDD
XTAL2
XTAL1
P31
P32
P33
P24
P23
P22
P21
P20
VSS
P01
P00/Pref1/P30
P36
P34
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
20-Pin
PDIP
SOIC
SSOP
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
6
Figure 4. 28-Pin PDIP/SOIC/SSOP Pin Configuration
Table 4. 28-Pin PDIP/SOIC/SSOP Pin Identification
Pin No Symbol Direction Description
1-3 P25-P27 Input/Output Port 2, Bits 5, 6, 7
4-7 P04-P07 Input/Output Port 0, Bits 4, 5, 6, 7
8V
DD Power supply
9 XTAL2 Output Crystal, oscillator clock
10 XTAL1 Input Crystal, oscillator clock
11-13 P31-P33 Input Port 3, Bits 1, 2, 3
14 P34 Output Port 3, Bit 4
15 P35 Output Port 3, Bit 5
16 P37 Output Port 3, Bit 7
17 P36 Output Port 3, Bit 6
18 Pref1/P30
Port 3 Bit 0
Input Analog ref input; connect to
VCC if not used
Input for Pref1/P30
19-21 P00-P02 Input/Output Port 0, Bits 0, 1, 2
22 VSS Ground
23 P03 Input/Output Port 0, Bit 3
24-28 P20-P24 Input/Output Port 2, Bits 0–4
P24
P23
P22
P21
P20
P03
VSS
P02
P01
P00
Pref1/P30
P36
P37
P35
P25
P26
P27
P04
P05
P06
P07
VDD
XTAL2
XTAL1
P31
P32
P33
P34
1
28-Pin
PDIP
SOIC
SSOP
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
7
Figure 5. 40-Pin PDIP Pin Configuration
NC
P25
P26
P27
P04
P05
P06
P14
P15
P07
VDD
P16
P17
XTAL2
XTAL1
P31
P32
P33
P34
NC
NC
P24
P23
P22
P21
P20
P03
P13
P12
VSS
P02
P11
P10
P01
P00
Pref1/P30
P36
P37
P35
RESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40-Pin
PDIP
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
8
Figure 6. 48-Pin SSOP Pin Configuration
Table 5. 40- and 48-Pin Configuration
40-Pin PDIP No 48-Pin SSOP No Symbol
26 31 P00
27 32 P01
30 35 P02
34 41 P03
55 P04
67 P05
78 P06
10 11 P07
28 33 P10
29 34 P11
NC
P25
P26
P27
P04
N/C
P05
P06
P14
P15
P07
VDD
VDD
N/C
P16
P17
XTAL2
XTAL1
P31
P32
P33
P34
NC
VSS
NC
NC
P24
P23
P22
P21
P20
P03
P13
P12
VSS
VSS
N/C
P02
P11
P10
P01
P00
N/C
PREF1/P30
P36
P37
P35
RESET
48-Pin
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
9
32 39 P12
33 40 P13
89 P14
910 P15
12 15 P16
13 16 P17
35 42 P20
36 43 P21
37 44 P22
38 45 P23
39 46 P24
22 P25
33 P26
44 P27
16 19 P31
17 20 P32
18 21 P33
19 22 P34
22 26 P35
24 28 P36
23 27 P37
20 23 NC
40 47 NC
11 NC
21 25 RESET
15 18 XTAL1
14 17 XTAL2
11 12, 13 VDD
31 24, 37, 38 VSS
25 29 Pref1/P30
48 NC
6NC
Table 5. 40- and 48-Pin Configuration (Continued)
40-Pin PDIP No 48-Pin SSOP No Symbol
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
10
Pin Functions
XTAL1 Crystal 1 (Time-Based Input)
This pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator
input. Additionally, an optional external single-phase clock can be coded to the on-chip
oscillator input.
XTAL2 Crystal 2 (Time-Based Output)
This pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator
output.
Input/Output Ports
The CMOS input buffer for each Port 0, 1, or 2 pin is always connected to the pin, even
when the pin is configured as an output. If the pin is configured as an open-drain output
and no external signal is applied, a High output state can cause the CMOS input buffer
to float. This might lead to excessive leakage current of more than 100 µA. To prevent
this leakage, connect the pin to an external signal with a defined logic level or ensure
its output state is Low, especially during STOP mode.
Internal pull-ups are disabled on any given pin or group of port pins when programmed
into output mode.
Port 0, 1, and 2 have both input and output capability. The input logic is always present
no matter whether the port is configured as input or output. When doing a READ in-
struction, the MCU reads the actual value at the input logic but not from the output buff-
er. In addition, the instructions of OR, AND, and XOR have the Read-Modify-Write
sequence. The MCU first reads the port, and then modifies the value and load back to
the port.
Precaution must be taken if the port is configured as open-drain output or if the port is
driving any circuit that makes the voltage different from the desired output logic. For
example, pins P00–P07 are not connected to anything else. If it is configured as
14 NC
30 NC
36 NC
Table 5. 40- and 48-Pin Configuration (Continued)
40-Pin PDIP No 48-Pin SSOP No Symbol
Caution:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
11
open-drain output with output logic as ONE, it is a floating port and reads back as
ZERO. The following instruction sets P00-P07 all Low.
AND P0,#%F0
Port 0 (P00–P07)
Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are config-
ured under software control as a nibble I/O port. The output drivers are push-pull or open-
drain controlled by bit D2 in the PCON register.
If one or both nibbles are needed for I/O operation, they must be configured by writing to
the Port 01 mode register (P01M). After a hardware reset or Stop Mode Recovery, Port 0
is configured as an input port.
An optional pull-up transistor is available as a OTP option bit on all Port 0 bits with nibble
select.
The Port 0 direction is reset to be input following an SMR.
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
12
Figure 7. Port 0 Configuration
Port 1 (P17–P10)
Port 1 can be configured for standard port input or output mode (see Figure 8). After POR
or Stop Mode Recovery, Port 1 is configured as an input port. The output drivers are either
push-pull or open-drain and are controlled by bit D1 in the PCON register.
1. The Port 1 direction is reset to be input following an SMR.
2. In 20- and 28-pin packages, Port 1 is reserved. A write to this register will
have no effect and will always read FF.
OTP Programming
Option
4
4
ZLP32300
OTP
Port 0 (I/O)
Pad
In
Out
I/O
Open-Drain
Resistive
Transistor
Pull-up
VCC
Notes:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
13
Figure 8. Port 1 Configuration
Port 2 (P27–P20)
Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 9). These eight I/O
lines can be independently configured under software control as inputs or outputs. Port 2
is always available for I/O operation. A EPROM option bit is available to connect eight
pull-up transistors on this port. Bits programmed as outputs are globally programmed as
either push-pull or open-drain. The POR resets with the eight bits of Port 2 configured as
inputs.
Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up the part.
P20 can be programmed to access the edge-detection circuitry in DEMODULATION
mode.
OTP Programming
Option
8
ZLP32300
OTP Port 1 (I/O)
Pad
In
Out
OEN
Open-Drain
Resistive
Transistor
Pull-up
VCC
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
14
Figure 9. Port 2 Configuration
Port 3 (P37–P30)
Port 3 is a 8-bit, CMOS-compatible fixed I/O port (see Figure 10). Port 3 consists of four
fixed input (P33–P30) and four fixed output (P37–P34), which can be configured under
software control for interrupt and as output from the counter/timers. P30, P31, P32, and
P33 are standard CMOS inputs; P34, P35, P36, and P37 are push-pull outputs.
OTP Programming
Option
ZLP32300
OTP
Port 2 (I/O)
Pad
In
Out
I/O
Open-Drain Resistive
Transistor
Pull-up
VCC
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
15
Figure 10. Port 3 Configuration
Two on-board comparators process analog signals on P31 and P32, with reference to the
voltage on Pref1 and P33. The Analog function is enabled by programming the Port 3
Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge trig-
gered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference
voltage inputs. Access to the Counter Timer edge-detection circuit is through P31 or P20
-
ZLP32300
OTP
Port 3 (I/O)
P32 (AN2)
P31 (AN1)
Pref1
From Stop Mode Recovery Source of SMR
P33 (REF2)
IRQ2, P31 Data Latch
Pref1/P30
P31
P32
P33
P34
P35
P36
P37
D1 1 = Analog
0 = Digital
R247 = P3M
+
-
+IRQ0, P32 Data Latch
IRQ1, P33 Data Latch
Comp1
Comp2
Dig.
An.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
16
(see T8 and T16 Common Functions—CTR1(0D)01h on page 28). Other edge detect and
IRQ modes are described in Table 6.
Comparators are powered down by entering STOP mode. For P31–P33 to be used in a
Stop Mode Recovery source, these inputs must be placed into DIGITAL mode.
2
Port 3 also provides output for each of the counter/timers and the AND/OR Logic (see
Figure 11). Control is performed by programming bits D5–D4 of CTR1, bit 0 of CTR0,
and bit 0 of CTR2.
Table 6. Port 3 Pin Function Summary
Pin I/O Counter/Timers Comparator Interrupt
Pref1/P30 IN RF1
P31 IN IN AN1 IRQ2
P32 IN AN2 IRQ0
P33 IN RF2 IRQ1
P34 OUT T8 AO1
P35 OUT T16
P36 OUT T8/16
P37 OUT AO2
P20 I/O IN
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
17
Figure 11. Port 3 Counter/Timer Output Configuration
Pad
P34
Comp1
VDD
MUX
PCON, D0
MUX
CTR0, D0
P31
P30 (Pref1)
P34 data
T8_Out
+
Pad
P35
VDD
MUX
CTR2, D0
Out 35
T16_Out
Pad
P36
VDD
MUX
CTR1, D6
Out 36
T8/T16_Out
Pad
P37
VDD
MUX
PCON, D0
P37 data
-
P31
P3M D1
Comp2
P32
P33
+
-
P32
P3M D1
Crimzon® ZLP32300
Product Specification
PS020823-0208 Pin Description
18
Comparator Inputs
In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference
is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its correspond-
ing IRQ1 are diverted to the SMR sources (excluding P31, P32, and P33) as displayed in
Figure 10 on page 15. In DIGITAL mode, P33 is used as D3 of the Port 3 input register,
which then generates IRQ1.
Comparators are powered down by entering STOP mode. For P31–P33 to be used in a
Stop Mode Recovery source, these inputs must be placed into DIGITAL mode.
Comparator Outputs
These channels can be programmed to be output on P34 and P37 through the PCON regis-
ter.
RESET (Input, Active Low)
Reset initializes the MCU and is accomplished either through Power-On, Watchdog
Timer, Stop Mode Recovery, Low-Voltage detection, or external reset. During Power-On
Reset and Watchdog Timer Reset, the internally generated reset drives the reset pin Low
for the POR time. Any devices driving the external reset line must be open-drain to avoid
damage from a possible conflict during reset conditions. Pull-up is provided internally.
When the ZLP32300 asserts (Low) the RESET pin, the internal pull-up is disabled. The
ZLP32300 does not assert the RESET pin when under VBO.
The external Reset does not initiate an exit from STOP mode.
Note:
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
19
Functional Description
This device incorporates special functions to enhance the Z8 functionality in consumer
and battery-operated applications.
Program Memory
This device addresses 32 KB of OTP memory. The first 12 bytes are reserved for interrupt
vectors. These locations contain the six 16-bit vectors that correspond to the six available
interrupts. See Figure 12.
RAM
This device features 256 B of RAM.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
20
Figure 12. Program Memory Map (32 K OTP)
Expanded Register File
The register file has been expanded to allow for additional system control registers and for
mapping of additional peripheral devices into the register address area. The Z8 register
address space (R0 through R15) has been implemented as 16 banks, with 16 registers per
bank. These register groups are known as the ERF (Expanded Register File). Bits 7–4 of
On-Chip
ROM
Reset Start Address
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
12
11
10
9
8
7
6
5
4
3
2
1
0
32768
Location of
first Byte of
instruction
executed
after RESET
Interrupt Vector
(Lower Byte)
Interrupt Vector
(Upper Byte)
Not Accessible
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
22
Figure 13. Expanded Register File Architecture
UUUUUUU0
00000000
00000000
00000000
00
0F
7F
F0
FF
FF SPL
00000000
UUUUUUUU
00000000
UUUUUUUU
UUUUUUUU
UUUUUUUU
11111111
00000000
11001111
UUUUUUUU
UUUUUUUU
UUUUUUUU
UUUUUUUU
UUUUUUUU
FE SPH
FD RP
FC FLAGS
FB IMR
FA IRQ
F9 IPR
F8 P01M
F7 P3M
F6 P2M
F5 Reserved
F4 Reserved
F3 Reserved
F2 Reserved
F1 Reserved
F0 Reserved
D7 D6 D5 D4 D3 D2 D1 D0
UU001101
U01000U0
11111110
(F) 0F WDTMR
(F) 0E Reserved
(F) 0D SMR2
(F) 0C Reserved
(F) 0B SMR
(F) 0A Reserved
(F) 09 Reserved
(F) 08 Reserved
(F) 07 Reserved
(F) 06 Reserved
(F) 05 Reserved
(F) 04 Reserved
(F) 03 Reserved
(F) 02 Reserved
(F) 01 Reserved
(F) 00 PCON
76543210
Expanded Register
Bank Pointer
Working Register
UUUUUUUU
UUUUUUUU
00000000
(D) 0C LVD
(D) 0B HI8
(D) 0A LO8
(D) 09 HI16
(D) 08 LO16
(D) 07 TC16H
(D) 06 TC16L
(D) 05 TC8H
(D) 04 TC8L
(D) 03 CTR3
(D) 02 CTR2
(D) 01 CTR1
(D) 00 CTR0
Group Pointer
Register File (Bank 0)**
00011111
*
*
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
U = Unknown
* Not reset with a Stop Mode Recovery. P1 reserved in 20 or 28-pin package.
** All addresses are in hexadecimal
↑
Is not reset with a Stop Mode Recovery, except Bit 0
↑↑
Bit 5 Is not reset with a Stop Mode Recovery
↑↑↑
Bits 5,4,3,2 not reset with a Stop Mode Recovery
↑↑↑↑
Bits 5 and 4 not reset with a Stop Mode Recovery
↑↑↑↑↑
Bits 5,4,3,2,1 not reset with a Stop Mode Recovery
Expanded Reg. Bank 0/Group (0)
*
(0) 03 P3
(0) 02 P2
(0) 01 P1
(0) 00 P0
0U
U
U
U
↑↑↑↑↑
↑↑↑↑
↑↑↑
↑↑
*
*
*
*
*
*
*
*
*
*
*
Expanded Reg. Bank F/Group 0**
Expanded Reg. Bank 0/Group 15**
Register Pointer
Z8 Standard Control Registers
Expanded Reg. Bank D/Group 0
↑
Reset
Condition
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
23
The upper nibble of the register pointer (see Figure 14) selects which working register
group, of 16 bytes in the register file, is accessed out of the possible 256. The lower nibble
selects the expanded register file bank and, in the case of the Crimzon ZLP32300 family,
banks 0, F, and D are implemented. A 0h in the lower nibble allows the normal register
file (bank 0) to be addressed. Any other value from 1h to Fh exchanges the lower 16
registers to an expanded register bank.
Figure 14. Register Pointer
Example: Crimzon ZLP32300 (see Figure 13 on page 22)
R253 RP = 00h
R0 = Port 0
R1 = Port 1
R2 = Port 2
R3 = Port 3
But if:
R253 RP = 0Dh
R0 = CTR0
R1 = CTR1
R2 = CTR2
R3 = CTR3
The counter/timers are mapped into ERF group D. Access is easily performed using the
following:
LD RP, #0Dh ; Select ERF D
for access to bank D ; (working
register group 0)
LD R0,#xx ; load CTR0
LD 1, #xx ; load CTR1
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register
File Pointer
Working Register
Pointer
Default Setting After Reset = 0000 0000
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
24
LD R1, 2 ; CTR2→CTR1
LD RP, #0Dh ; Select ERF D
for access to bank D ; (working
register group 0)
LD RP, #7Dh ; Select
expanded register bank D and working ; register
group 7 of bank 0 for access.
LD 71h, 2
; CTRL2→register 71h
LD R1, 2
; CTRL2→register 71h
Register File
The register file (bank 0) consists of 4 I/O port registers, 237 general-purpose registers, 16
control and status registers (R0–R3, R4–R239, and R240–R255, respectively), and two
expanded registers groups in Banks D (see Table 7 on page 27) and F. Instructions can
access registers directly or indirectly through an 8-bit address field, thereby allowing a
short, 4-bit register address to use the Register Pointer (see Figure 15). In the 4-bit mode,
the register file is divided into 16 working register groups, each occupying 16 continuous
locations. The Register Pointer addresses the starting location of the active working regis-
ter group.
Working register group E0–EF can only be accessed through working registers and indi-
rect addressing modes.
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
25
Figure 15. Register Pointer—Detail
Stack
The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is used
for the internal stack that resides in the general-purpose registers (R4–R239). SPH (R254)
can be used as a general-purpose register.
Timers
T8_Capture_HI—HI8(D)0Bh
This register holds the captured data from the output of the 8-bit Counter/Timer0. Typi-
cally, this register holds the number of counts when the input signal is 1.
Field Bit Position Description
T8_Capture_HI [7:0] R/W Captured Data—No Effect
R7R6R5R4R3R2R1R
The upper nibble of the register file address
provided by the register pointer specifies the
active working-register group.
Specified Working
Register Group
Register Group 1
Register Group 0
I/O Ports
R253
The lower nibble of the
register file address provided
by the instruction points to
the specified register.
* RP = 00: Selects Register Bank 0, Working Register Group 0
R15 to R0
R15 to R4 *
R3 to R0 *
FF
F0
EF
E0
DF
D0
40
3F
30
2F
20
1F
10
0F
00
Register Group 2
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
26
T8_Capture_LO—L08(D)0Ah
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register holds the number of counts when the input signal is 0.
T16_Capture_HI—HI16(D)09h
This register holds the captured data from the output of the 16-bit Counter/Timer16. This
register holds the MS-Byte of the data.
T16_Capture_LO—L016(D)08h
This register holds the captured data from the output of the 16-bit Counter/Timer16. This
register holds the LS-Byte of the data.
Counter/Timer2 MS-Byte Hold Register—TC16H(D)07h
Counter/Timer2 LS-Byte Hold Register—TC16L(D)06h
Field Bit Position Description
T8_Capture_L0 [7:0] R/W Captured Data—No Effect
Field Bit Position Description
T16_Capture_HI [7:0] R/W Captured Data—No Effect
Field Bit Position Description
T16_Capture_LO [7:0] R/W Captured Data—No Effect
Field Bit Position Description
T16_Data_HI [7:0] R/W Data
Field Bit Position Description
T16_Data_LO [7:0] R/W Data
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
27
Counter/Timer8 High Hold Register—TC8H(D)05h
Counter/Timer8 Low Hold Register—TC8L(D)04h
CTR0 Counter/Timer8 Control Register—CTR0(D)00h
Table 7 lists and briefly describes the fields for this register.
Field Bit Position Description
T8_Level_HI [7:0] R/W Data
Field Bit Position Description
T8_Level_LO [7:0] R/W Data
Table 7. CTR0(D)00h Counter/Timer8 Control Register
Field Bit Position Value Description
T8_Enable 7------- R/W 0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Single/Modulo-N -6------- R/W 0*
1
Modulo-N
Single Pass
Time_Out --5------ R/W 0**
1
0
1
No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0
T8 _Clock ---43--- R/W 0 0**
0 1
1 0
1 1
SCLK
SCLK/2
SCLK/4
SCLK/8
Capture_INT_Mask -----2-- R/W 0**
1
Disable Data Capture Interrupt
Enable Data Capture Interrupt
Counter_INT_Mask ------1- R/W 0**
1
Disable Time-Out Interrupt
Enable Time-Out Interrupt
P34_Out -------0 R/W 0*
1
P34 as Port Output
T8 Output on P34
*Indicates the value upon Power-On Reset.
**Indicates the value upon Power-On Reset. Not reset with a Stop Mode Recovery.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
28
T8 Enable
This field enables T8 when set (written) to 1.
Single/Modulo-N
When set to 0 (Modulo-N), the counter reloads the initial value when the terminal count is
reached. When set to 1 (single-pass), the counter stops when the terminal count is reached.
Timeout
This bit is set when T8 times out (terminal count reached). To reset this bit, write a 1 to its
location.
Writing a 1 is the only way to reset the Terminal Count status condition. Reset this bit
before using/enabling the counter/timers. The first clock of T8 might not have complete
clock width and can occur any time when enabled.
Ensure to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (DEMODULATION mode)
when using the OR or AND commands. These instructions use a Read-Modify-Write
sequence in which the current status from the CTR0 and CTR1 registers is ORed or
ANDed with the designated value and then written back into the registers.
T8 Clock
These bits define the frequency of the input signal to T8.
Capture_INT_Mask
Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon a posi-
tive or negative edge detection in DEMODULATION mode.
Counter_INT_Mask
Set this bit to allow an interrupt when T8 has a timeout.
P34_Out
This bit defines whether P34 is used as a normal output pin or the T8 output.
T8 and T16 Common Functions—CTR1(0D)01h
This register controls the functions in common with the T8 and T16.
Table 8 lists and briefly describes the fields for this register.
Caution:
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
29
Table 8. CTR1(0D)01h T8 and T16 Common Functions
Field Bit Position Value Description
Mode 7------- R/W 0*
1
TRANSMIT Mode
DEMODULATION Mode
P36_Out/
Demodulator_Input
-6------ R/W
0*
1
0*
1
TRANSMIT Mode
Port Output
T8/T16 Output
DEMODULATION Mode
P31
P20
T8/T16_Logic/
Edge _Detect
--54---- R/W
00**
01
10
11
00**
01
10
11
TRANSMIT Mode
AND
OR
NOR
NAND
DEMODULATION Mode
Falling Edge
Rising Edge
Both Edges
Reserved
Transmit_Submode/
Glitch_Filter
----32-- R/W
00*
01
10
11
00*
01
10
11
TRANSMIT Mode
Normal Operation
PING-PONG Mode
T16_Out = 0
T16_Out = 1
DEMODULATION Mode
No Filter
4 SCLK Cycle
8 SCLK Cycle
Reserved
Initial_T8_Out/
Rising Edge
------1-
R/W
R
W
0*
1
0*
1
0
1
TRANSMIT Mode
T8_OUT is 0 Initially
T8_OUT is 1 Initially
DEMODULATION Mode
No Rising Edge
Rising Edge Detected
No Effect
Reset Flag to 0
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
30
Mode
If the result is 0, the counter/timers are in TRANSMIT mode; otherwise, they are in
DEMODULATION mode.
P36_Out/Demodulator_Input
In TRANSMIT mode, this bit defines whether P36 is used as a normal output pin or the
combined output of T8 and T16.
In DEMODULATION mode, this bit defines whether the input signal to the Counter/Tim-
ers is from P20 or P31.
If the input signal is from Port 31, a capture event may also generate an IRQ2 interrupt. To
prevent generating an IRQ2, either disable the IRQ2 interrupt by clearing its IMR bit D2
or use P20 as the input.
T8/T16_Logic/Edge _Detect
In TRANSMIT mode, this field defines how the outputs of T8 and T16 are combined
(AND, OR, NOR, NAND).
In DEMODULATION mode, this field defines which edge should be detected by the edge
detector.
Transmit_Submode/Glitch Filter
In TRANSMIT mode, this field defines whether T8 and T16 are in the PING-PONG mode
or in independent normal operation mode. Setting this field to normal operation mode ter-
minates the ‘PING-PONG Mode’ operation. When set to 10, T16 is immediately forced to
a 0; a setting of 11 forces T16 to output a 1.
In DEMODULATION mode, this field defines the width of the glitch that must be filtered
out.
Initial_T16_Out/
Falling_Edge
-------0
R/W
R
W
0*
1
0*
1
0
1
TRANSMIT Mode
T16_OUT is 0 Initially
T16_OUT is 1 Initially
DEMODULATION Mode
No Falling Edge
Falling Edge Detected
No Effect
Reset Flag to 0
*Default at Power-On Reset
**Default at Power-On Reset. Not reset with a Stop Mode Recovery.
Table 8. CTR1(0D)01h T8 and T16 Common Functions (Continued)
Field Bit Position Value Description
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
31
Initial_T8_Out/Rising_Edge
In TRANSMIT mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the out-
put of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is
set to 1 or 0, T8_OUT is set to the opposite state of this bit. This ensures that when the
clock is enabled, a transition occurs to the initial state set by CTR1, D1.
In DEMODULATION mode, this bit is set to 1 when a rising edge is detected in the input
signal. In order to reset the mode, a 1 should be written to this location.
Initial_T16 Out/Falling _Edge
In TRANSMIT mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is
1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal
or PING-PONG mode (CTR1, D3; D2). When the counter is not enabled and this bit is set,
T16_OUT is set to the opposite state of this bit. This ensures that when the clock is
enabled, a transition occurs to the initial state set by CTR1, D0.
In DEMODULATION mode, this bit is set to 1 when a falling edge is detected in the input
signal. In order to reset it, a 1 should be written to this location.
Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output
from T8/16_OUT.
CTR2 Counter/Timer 16 Control Register—CTR2(D)02h
Table 9 lists and briefly describes the fields for this register.
Table 9. CTR2(D)02h: Counter/Timer16 Control Register
Field Bit Position Value Description
T16_Enable 7------- R
W
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Single/Modulo-N -6------ R/W
0*
1
0
1
TRANSMIT Mode
Modulo-N
Single Pass
DEMODULATION Mode
T16 Recognizes Edge
T16 Does Not Recognize
Edge
Time_Out --5----- R
W
0*
1
0
1
No Counter Timeout
Counter Timeout
Occurred
No Effect
Reset Flag to 0
Note
:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
32
T16_Enable
This field enables T16 when set to 1.
Single/Modulo-N
In TRANSMIT mode, when set to 0, the counter reloads the initial value when it reaches
the terminal count. When set to 1, the counter stops when the terminal count is reached.
In DEMODULATION mode, when set to 0, T16 captures and reloads on detection of all
the edges. When set to 1, T16 captures and detects on the first edge but ignores the subse-
quent edges. For details, see T16 DEMODULATION Mode on page 41.
Time_Out
This bit is set when T16 times out (terminal count reached). To reset the bit, write a 1 to
this location.
T16_Clock
This bit defines the frequency of the input signal to Counter/Timer16.
Capture_INT_Mask
This bit is set to allow an interrupt when data is captured into LO16 and HI16.
Counter_INT_Mask
Set this bit to allow an interrupt when T16 times out.
T16 _Clock ---43--- R/W 00**
01
10
11
SCLK
SCLK/2
SCLK/4
SCLK/8
Capture_INT_Mask -----2-- R/W 0**
1
Disable Data Capture Int.
Enable Data Capture Int.
Counter_INT_Mask ------1- R/W 0
1
Disable Timeout Int.
Enable Timeout Int.
P35_Out -------0 R/W 0*
1
P35 as Port Output
T16 Output on P35
*Indicates the value upon Power-On Reset.
**Indicates the value upon Power-On Reset. Not reset with a Stop Mode Recovery.
Table 9. CTR2(D)02h: Counter/Timer16 Control Register (Continued)
Field Bit Position Value Description
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
33
P35_Out
This bit defines whether P35 is used as a normal output pin or T16 output.
CTR3 T8/T16 Control Register—CTR3(D)03h
Table 10 lists and briefly describes the fields for this register. This register allows the T8
and T16 counters to be synchronized.
Counter/Timer Functional Blocks
Input Circuit
The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5–D4, a
pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in
the input signal that have a width less than specified (CTR1 D3, D2) are filtered out (see
Figure 16).
Table 10.CTR3 (D)03h: T8/T16 Control Register
Field Bit Position Value Description
T16 Enable 7------- R
R
W
W
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
T8 Enable -6------ R
R
W
W
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Sync Mode --5----- R/W 0**
1
Disable Sync Mode
Enable Sync Mode
Reserved ---43210 R
W
1
x
Always reads 11111
No Effect
*Indicates the value upon Power-On Reset.
**Indicates the value upon Power-On Reset. Not reset with a Stop Mode Recovery.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
34
Figure 16. Glitch Filter Circuitry
T8 TRANSMIT Mode
Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is 1; if it
is 1, T8_OUT is 0. See Figure 17.
MUX Glitch
Filter
Edge
Detector
P31
P20
Pos
Edge
Neg
Edge
CTR1
D5,D4
CTR1
D6
CTR1
D3, D2
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
35
Figure 17. TRANSMIT Mode Flowchart
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
T8 (8-Bit)
TRANSMIT Mode
No T8_Enable Bit Set
CTR0, D7
Yes
CTR1, D1
Value
Reset T8_Enable Bit
01
Load TC8L
Reset T8_OUT
Load TC8H
Set T8_OUT
Enable T8
No T8_Timeout
Yes
Single Pass Single
Modulo-N
T8_OUT Value 0
Enable T8
No T8_Timeout
Yes
Pass?
Load TC8H
Set T8_OUT
Load TC8L
Reset T8_OUT
1
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
36
When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). If the
initial value (CTR1, D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter.
In SINGLE-PASS mode (CTR0, D6), T8 counts down to 0 and stops, T8_OUT toggles,
the time-out status bit (CTR0, D5) is set, and a time-out interrupt can be generated if it is
enabled (CTR0, D1). In MODULO-N mode, upon reaching terminal count, T8_OUT is
toggled, but no interrupt is generated. From that point, T8 loads a new count (if the
T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0,
toggles T8_OUT, and sets the time-out status bit (CTR0, D5), thereby generating an inter-
rupt if enabled (CTR0, D1). One cycle is thus completed. T8 then loads from TC8H or
TC8L according to the T8_OUT level and repeats the cycle, see Figure 18.
Figure 18. 8-Bit Counter/Timer Circuits
You can modify the values in TC8H or TC8L at any time. The new values take effect
when they are loaded.
To ensure known operation do not write these registers at the time the values are to be
loaded into the counter/timer. An initial count of 1 is not allowed (a non-function oc-
curs). An initial count of 0 causes TC8 to count from 0 to FFh to FEh.
The letter h denotes hexadecimal values.
Transition from 0 to FFh is not a timeout condition.
CTR0 D1
Negative Edge
Positive Edge
Z8 Data Bus
IRQ4
CTR0 D2
SCLK
Z8 Data Bus
CTR0 D4, D3
Clock
T8_OUT
LO8
TC8H TC8L
Clock
Select
8-Bit
Counter T8
HI8
Caution:
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
37
Using the same instructions for stopping the counter/timers and setting the status bits is
not recommended.
Two successive commands are necessary. First, the counter/timers must be stopped. Sec-
ond, the status bits must be reset. These commands are required because it takes one
counter/timer clock interval for the initiated event to actually occur, see Figure 19 and
Figure 20.
Figure 19. T8_OUT in SINGLE-PASS Mode
Figure 20. T8_OUT in MODULO-N Mode
T8 DEMODULATION Mode
You must program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (ris-
ing, falling, or both depending on CTR1, D5; D4) is detected, it starts to count down.
When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected
during counting, the current value of T8 is complemented and put into one of the capture
registers. If it is a positive edge, data is put into LO8; if it is a negative edge, data is put
into HI8. From that point, one of the edge detect status bits (CTR1, D1; D0) is set, and an
interrupt can be generated if enabled (CTR0, D2). Meanwhile, T8 is loaded with FFh and
starts counting again. If T8 reaches 0, the time-out status bit (CTR0, D5) is set, and an
Caution:
TC8H
Counts
Counter Enable Command;
T8_OUT Switches to Its
Initial Value (CTR1 D1)
T8_OUT Toggles;
Timeout Interrupt
Counter Enable Command;
T8_OUT Switches to Its
Initial Value (CTR1 D1)
Timeout
Interrupt
Timeout
Interrupt
T8_OUT
T8_OUT Toggles
TC8L TC8H TC8H TC8LTC8L
...
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
38
interrupt can be generated if enabled (CTR0, D1). T8 then continues counting from FFh
(see Figure 21 and Figure 22).
Figure 21. DEMODULATION Mode Count Capture Flowchart
T8 (8-Bit)
Count Capture
T8 Enable
(Set by User)
No
Yes
Edge Present
What Kind
of Edge
T8 HI8
No
Yes
Negative
FFh T8
Positive
T8 LO8
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
39
Figure 22. DEMODULATION Mode Flowchart
T8 (8-Bit)
DEMODULATION Mode
T8 Enable
CTR0, D7
No
Yes
FFh→ TC8
First
Edge Present
Enable TC8
T8_Enable
Bit Set
Edge Present
T8 Timeout
Set Edge Present Status
Bit and Trigger Data
Capture Int. If Enabled
Set Timeout Status
Bit and Trigger
Timeout Int. If Enabled
Continue Counting
Disable TC8
No
Yes
No
Yes
Yes
Yes
No
No
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
40
T16 TRANSMIT Mode
In NORMAL or PING-PONG mode, the output of T16 when not enabled, is dependent on
CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can force the output
of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 D3; D2 to a 10
or 11.
When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its
initial value (CTR1, D0). When T16 counts down to 0, T16_OUT is toggled (in NOR-
MAL or PING-PONG mode), an interrupt (CTR2, D1) is generated (if enabled), and a sta-
tus bit (CTR2, D5) is set, see Figure 23.
Figure 23. 16-Bit Counter/Timer Circuits
Global interrupts override this function as described in Interrupts on page 43.
If T16 is in SINGLE-PASS mode, it is stopped at this point (see Figure 24). If it is in
MODULO-N mode, it is loaded with TC16H * 256 + TC16L, and the counting continues
(see Figure 25).
You can modify the values in TC16H and TC16L at any time. The new values take effect
when they are loaded.
CTR2 D1
Negative Edge
Positive Edge
Z8 Data Bus
IRQ3
CTR2 D2
SCLK
Z8 Data Bus
CTR2 D4, D3
Clock
T16_OUT
LO16
TC16H TC16L
Clock
Select
16-Bit
Counter T16
HI16
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
41
Do not load these registers at the time the values are to be loaded into the counter/timer
to ensure known operation. An initial count of 1 is not allowed. An initial count of 0
causes T16 to count from 0 to FFFFh to FFFEh. Transition from 0 to FFFFh is not a tim-
eout condition.
Figure 24. T16_OUT in SINGLE-PASS Mode
Figure 25. T16_OUT in MODULO-N Mode
T16 DEMODULATION Mode
You must program TC16L and TC16H to FFh. After T16 is enabled, and the first edge
(rising, falling, or both depending on CTR1 D5; D4) is detected, T16 captures HI16 and
LO16, reloads, and begins counting.
If D6 of CTR2 Is 0
When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected
during counting, the current count in T16 is complemented and put into HI16 and LO16.
When data is captured, one of the edge detect status bits (CTR1, D1; D0) is set, and an
interrupt is generated if enabled (CTR2, D2). T16 is loaded with FFFFh and starts again.
Caution:
TC16H*256+TC16L Counts
“Counter Enable” Command
T16_OUT Switches to Its
Initial Value (CTR1 D0)
T16_OUT Toggles,
Timeout Interrupt
TC16H*256+TC16L
TC16H*256+TC16L
TC16H*256+TC16L
T16_OUT Toggles,
Timeout Interrupt
T16_OUT Toggles,
Timeout Interrupt
“Counter Enable” Command,
T16_OUT Switches to Its
Initial Value (CTR1 D0)
TC16_OUT
...
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
42
This T16 mode is generally used to measure space time, the length of time between bursts
of carrier signal (marks).
If D6 of CTR2 Is 1
T16 ignores the subsequent edges in the input signal and continues counting down. A tim-
eout of T8 causes T16 to capture its current value and generate an interrupt if enabled
(CTR2, D2). In this case, T16 does not reload and continues counting. If the D6 bit of
CTR2 is toggled (by writing a 0 then a 1 to it), T16 captures and reloads on the next edge
(rising, falling, or both depending on CTR1, D5; D4), continuing to ignore subsequent
edges.
This T16 mode generally measures mark time, the length of an active carrier signal burst.
If T16 reaches 0, T16 continues counting from FFFFh. Meanwhile, a status bit (CTR2 D5)
is set, and an interrupt timeout can be generated if enabled (CTR2 D1).
PING-PONG Mode
This operation mode is only valid in TRANSMIT mode. T8 and T16 must be programmed
in SINGLE-PASS mode (CTR0, D6; CTR2, D6), and PING-PONG mode must be pro-
grammed in CTR1, D3; D2. You can begin the operation by enabling either T8 or T16
(CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial
value (CTR1, D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After
the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT then switches
to its initial value (CTR1, D0), data from TC16H and TC16L is loaded, and T16 starts to
count. After T16 reaches the terminal count, it stops, T8 is enabled again, repeating the
entire cycle. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0,
D1; CTR2, D1). To stop the Ping-Pong operation, write 00 to bits D3 and D2 of CTR1, see
Figure 26.
Enabling Ping-Pong operation while the counter/timers are running might cause intermit-
tent counter/timer function. Disable the counter/timers and reset the status Flags before
instituting this operation.
Figure 26. PING-PONG Mode Diagram
Note:
TC8
Enable
Timeout
TC16
Ping-Pong
CTR1
Timeout
Enable
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
43
Initiating PING-PONG Mode
First, make sure both counter/timers are not running. Set T8 into SINGLE-PASS mode
(CTR0, D6), set T16 into SINGLE-PASS mode (CTR2, D6), and set the PING-PONG
mode (CTR1, D2; D3). These instructions can be in random order. Finally, start PING-
PONG mode by enabling either T8 (CTR0, D7) or T16 (CTR2, D7), see Figure 26.
Figure 27. Output Circuit
The initial value of T8 or T16 must not be 1. If you stop the timer and restart the timer,
reload the initial value to avoid an unknown previous value.
During PING-PONG Mode
The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by
hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers
reach the terminal count.
Timer Output
The output logic for the timers is displayed in Figure 27. P34 is used to output T8-OUT
when D0 of CTR0 is set. P35 is used to output the value of TI6-OUT when D0 of CTR2 is
set. When D6 of CTR1 is set, P36 outputs the logic combination of T8-OUT and T16-
OUT determined by D5 and D4 of CTR1.
Interrupts
The Crimzon ZLP32300 features six different interrupts (see Table 11 on page 45). The
interrupts are maskable and prioritized (see Figure 28). The six sources are divided as fol-
lows: three sources are claimed by Port 3 lines P33–P31, two by the
T16_OUT
MUX
CTR1 D3
T8_OUT
P34
AND/OR/NOR/NAND
Logic
MUX
MUX
MUX
P35
P36
P34_Internal
CTR1 D5, D4
P36_Internal
P35_Internal
CTR1, D2
CTR0 D0
CTR1 D6
CTR2 D0
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
44
counter/timers (see Table 11 on page 45) and one for low-voltage detection. The Interrupt
Mask Register (globally or individually) enables or disables the six interrupt requests.
The source for IRQ is determined by bit 1 of the Port 3 mode register (P3M). When in
DIGITAL mode, Pin P33 is the source. When in ANALOG mode, the output of the Stop
Mode Recovery source logic is used as the source for the interrupt, see Figure 33 on
page 52.
Figure 28. Interrupt Block Diagram
Low-Voltage
Detection
Timer 8
Timer 16
Interrupt Edge
Select
IMR
IPR
Priority
Logic
IRQ
5
IRQ2 IRQ0 IRQ1 IRQ3 IRQ4 IRQ5
P31 P32
IRQ Register
D6, D7
Global
Interrupt
Enable
Interrupt
Request
Vector Select
D1 of P3M Register
P33
01
Stop Mode Recovery Source
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
45
When more than one interrupt is pending, priorities are resolved by a programmable
priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle
activates when an interrupt request is granted. As a result, all subsequent interrupts are
disabled, and the Program Counter and Status Flags are saved. The cycle then branches to
the program memory vector location reserved for that interrupt. All Crimzon ZLP32300
interrupts are vectored through locations in the program memory. This memory location
and the next byte contain the 16-bit address of the interrupt service routine for that
particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are
masked, and the Interrupt Request register is polled to determine which of the interrupt
requests require service.
An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is
mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge
triggered. These interrupts are programmable. The software can poll to identify the state of
the pin.
Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250),
bits D7 and D6. The configuration is indicated in Table 12.
Table 11. Interrupt Types, Sources, and Vectors
Name Source Vector Location Comments
IRQ0 P32 0,1 External (P32), Rising, Falling Edge Triggered
IRQ1 P33 2,3 External (P33), Falling Edge Triggered
IRQ2 P31, TIN 4,5 External (P31), Rising, Falling Edge Triggered
IRQ3 T16 6,7 Internal
IRQ4 T8 8,9 Internal
IRQ5 LVD 10,11 Internal
Table 12. IRQ Register
IRQ Interrupt Edge
D7 D6 IRQ2 (P31) IRQ0 (P32)
00F F
01F R
10R F
11R/F R/F
Note: F = Falling Edge; R = Rising Edge
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
46
Clock
The device’s on-chip oscillator has a high-gain, parallel-resonant amplifier, for connection
to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = Input,
XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series
resistance (RS) less than or equal to 100 Ω. The on-chip oscillator can be driven with a
suitable external clock source.
The crystal must be connected across XTAL1 and XTAL2 using the recommended capac-
itors from each pin to ground. The typical capacitor value is 10 pF for 8 MHz. Also check
with the crystal supplier for the optimum capacitance.
Figure 29. Oscillator Configuration
Zilog’s IR MCU supports crystal, resonator, and oscillator. Most resonators have a
frequency tolerance of less than ±0.5%, which is enough for remote control application.
Resonator has a very fast startup time, which is around few hundred microseconds. Most
crystals have a frequency tolerance of less than 50 ppm (±0.005%). However, crystal
needs longer startup time than the resonator. The large loading capacitance slows down the
oscillation startup time. Zilog® suggests not to use more than 10 pF loading capacitor for
the crystal. If the stray capacitance of the PCB or the crystal is high, the loading
capacitance C1 and C2 must be reduced further to ensure stable oscillation before the
TPOR (Power-On Reset time is typically 5-6 ms, see Table 20 on page 79).
For Stop Mode Recovery operation, bit 5 of SMR register allows you to select the Stop
Mode Recovery delay, which is the TPOR. If Stop Mode Recovery delay is not selected, the
MCU executes instruction immediately after it wakes up from the STOP mode. If
resonator or crystal is used as a clock source then Stop Mode Recovery delay needs to be
selected (bit 5 of SMR = 1).
C1
C2
XTAL1
XTAL2
XTAL1
XTAL2
Crystal
C1, C2 = 10 pF *
f=8MHz
External Clock
*Note: preliminary value.
XTAL1
XTAL2
Ceramic Resonator f = 8 MHz
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
47
For both resonator and crystal oscillator, the oscillation ground must go directly to the
ground pin of the microcontroller. The oscillation ground must use the shortest distance
from the microcontroller ground pin and it must be isolated from other connections.
Power Management
Power-On Reset
A timer circuit clocked by a dedicated on-board RC-oscillator is used for the Power-On
Reset timer function. The POR time allows VDD and the oscillator circuit to stabilize
before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
•
Power Fail to Power OK status, including Waking up from VBO Standby
•
Stop Mode Recovery (if D5 of SMR = 1)
•
WDT Timeout
The POR timer is 2.5 ms minimum. Bit 5 of the Stop Mode Register determines whether
the POR timer is bypassed after Stop Mode Recovery (typical for external clock).
HALT Mode
This instruction turns off the internal CPU clock, but not the XTAL oscillation. The
counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain
active. The devices are recovered by interrupts, either externally or internally generated.
An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt
service routine, the program continues from the instruction after HALT Mode.
STOP Mode
This instruction turns OFF the internal clock and external crystal oscillation, reducing the
standby current to 10 µA or less. STOP mode is terminated only by a reset, such as WDT
time-out, POR or SMR. This condition causes the processor to restart the application pro-
gram at address 000Ch. To enter STOP (or HALT) mode, first flush the instruction pipe-
line to avoid suspending execution in mid-instruction. Execute a NOP (Opcode = FFh)
immediately before the appropriate sleep instruction, as follows:
FF NOP ; clear the pipeline
6F STOP ; enter Stop Mode
or
FF NOP ; clear the pipeline
7F HALT ; enter HALT Mode
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
48
Port Configuration
Port Configuration Register
The Port Configuration (PCON) register (see Figure 30) configures the comparator output
on Port 3. It is located in the expanded register 2 at Bank F, location 00.
PCON(FH)00h
Figure 30. Port Configuration Register (PCON) (Write Only)
Comparator Output Port 3 (D0)
Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator
outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration.
Port 1 Output Mode (D1)
Bit 1 controls the output mode of Port 1. A 1 in this location sets the output to push-pull,
and a 0 sets the output to open-drain.
Port 0 Output Mode (D2)
Bit 2 controls the output mode of Port 0. A 1 in this location sets the output to push-pull,
and a 0 sets the output to open-drain.
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Port 1
0: Open-Drain
1: Push-Pull*
Port 0
0: Open-Drain
1: Push-Pull*
Reserved (Must be 1)
* Default setting after reset
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
49
Stop Mode Recovery
Stop Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop Mode Recov-
ery (see Figure 31). All bits are write only except bit 7, which is read only. Bit 7 is a Flag
bit that is hardware set on the condition of Stop recovery and reset by a power-on cycle.
Bit 6 controls whether a low level or a high level at the XOR-gate input (see Figure 33 on
page 52) is required from the recovery source. Bit 5 controls the reset delay after recovery.
Bits D2, D3, and D4 of the SMR register specify the source of the Stop Mode Recovery
signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not. The SMR is located
in Bank F of the Expanded Register Group at address 0Bh.
SMR(0F)0Bh
Figure 31. Stop Mode Recovery Register
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
Reserved (Must be 0)
Stop Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery * *
*Default after Power-On Reset or Watchdog Reset
* *Default setting after Reset and Stop Mode Recovery.
* * *At the XOR gate input
* * * *Default setting after reset. Must be 1 if using a crystal or resonator clock source.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
50
SCLK/TCLK Divide-by-16 Select (D0)
D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (see Figure 32). This
control selectively reduces device power consumption during normal processor execution
(SCLK control) and/or HALT mode (where TCLK sources interrupt logic). After Stop
Mode Recovery, this bit is set to a 0.
Figure 32. SCLK Circuit
Stop Mode Recovery Source (D2, D3, and D4)
These three bits of the SMR specify the wake-up source of the Stop recovery (see
Figure 33 and Table 14).
Stop Mode Recovery Register 2—SMR2(F)0Dh
Table 13 lists and briefly describes the fields for this register.
Table 13. SMR2(F)0Dh:Stop Mode Recovery Register 2*
Field Bit Position Value Description
Reserved 7------- 0 Reserved (Must be 0)
Recovery
Level
-6------ W0
†
1
Low
High
Reserved --5----- 0 Reserved (Must be 0)
SCLK
TCLKSMR, D0
2÷
OSC
16÷
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
51
Source ---432-- W 000†
001
010
011
100
101
110
111
A. POR Only
B. NAND of P23–P20
C. NAND of P27–P20
D. NOR of P33–P31
E. NAND of P33–P31
F. NOR of P33–P31, P00, P07
G. NAND of P33–P31, P00, P07
H. NAND of P33–P31, P22–P20
Reserved ------10 00 Reserved (Must be 0)
*Port pins configured as outputs are ignored as an SMR recovery source.
†Indicates the value upon Power-On Reset.
Table 13. SMR2(F)0Dh:Stop Mode Recovery Register 2* (Continued)
Field Bit Position Value Description
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
52
Figure 33. Stop Mode Recovery Source
SMR2 D4 D3 D2
100
SMR2 D4 D3 D2
111
SMR D4D3D2
010
SMR D4D3D2
111
SMR D4D3D2
101
SMR D4D3D2
100
SMR D4D3D2
011
SMR D4D3D2
000
SMR D4D3D2
110
VCC
P31
P32
P33
P27
P20
P23
P20
P27
SMR2 D4 D3 D2
001
SMR2 D4 D3 D2
000
SMR2 D4 D3 D2
010
SMR2 D4 D3 D2
011
SMR2 D4 D3 D2
101
SMR2 D4 D3 D2
110
VCC
P20
P23
P20
P27
P31
P32
P33
P31
P32
P33
P31
P32
P33
P00
P07
P31
P32
P33
P00
P07
P31
P32
P33
P20
P21
P22
SMR D6
SMR2 D6
To RESET and WDT
Circuitry (Active Low)
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
53
Any Port 2 bit defined as an output drives the corresponding input to the default state. For
example, if the NOR of P23-P20 is selected as the recovery source and P20 is configured
as an output, the remaining SMR pins (P23-P21) form the NOR equation. This condition
allows the remaining inputs to control the AND/OR function, refer to SMR2 register on
page 54 for other recover sources.
Stop Mode Recovery Delay Select (D5)
This bit, if low, disables the TPOR delay after Stop Mode Recovery. The default configura-
tion of this bit is 1. If the ‘fast’ wake up is selected, the Stop Mode Recovery source must
be kept active for at least 10 TpC.
This bit must be set to 1 if a crystal or resonator clock source is used. The TPOR delay
allows the clock source to stabilize before executing instructions.
Stop Mode Recovery Edge Select (D6)
A 1 in this bit position indicates that a High level on any one of the recovery sources
wakes the Crimzon ZLP32300 from STOP mode. A 0 indicates Low level recovery. The
default is 0 on POR.
Cold or Warm Start (D7)
This bit is read only. It is set to 1 when the device is recovered from STOP mode. The bit
is set to 0 when the device reset is other than Stop Mode Recovery.
Table 14. Stop Mode Recovery Source
SMR:432 Operation
D4 D3 D2 Description of Action
0 0 0 POR and/or external reset recovery
001Reserved
010P31 transition
011P32 transition
100P33 transition
101P27 transition
1 1 0 Logical NOR of P20 through P23
1 1 1 Logical NOR of P20 through P27
Note:
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
54
Stop Mode Recovery Register 2 (SMR2)
This register determines the mode of Stop Mode Recovery for SMR2 (see Figure 34).
SMR2(0F)Dh
Figure 34. Stop Mode Recovery Register 2 ((0F)DH:D2–D4, D6 Write Only)
If SMR2 is used in conjunction with SMR, either of the specified events causes a Stop
Mode Recovery.
Port pins configured as outputs are ignored as an SMR or SMR2 recovery source. For
example, if the NAND or P23–P20 is selected as the recovery source and P20 is config-
ured as an output, the remaining SMR pins (P23–P21) form the NAND equation.
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0Low *
1 High
Reserved (Must be 0)
If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery.
*Default setting after reset.
* *At the XOR gate input.
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
55
Watchdog Timer Mode
Watchdog Timer Mode Register (WDTMR)
The Watchdog Timer is a retriggerable one-shot timer that resets the Z8® if it reaches its
terminal count. The WDT must initially be enabled by executing the WDT instruction. On
subsequent executions of the WDT instruction, the WDT is refreshed. The WDT circuit is
driven by an on-board RC-oscillator. The WDT instruction affects the Zero (Z), Sign (S),
and Overflow (V) Flags.
The POR clock source the internal RC-oscillator. Bits 0 and 1 of the WDT register control
a tap circuit that determines the minimum time-out period. Bit 2 determines whether the
WDT is active during HALT, and Bit 3 determines WDT activity during Stop. Bits 4
through 7 are reserved (see Figure 35). This register is accessible only during the first 60
processor cycles (120 XTAL clocks) from the execution of the first instruction after
Power-on reset, Watchdog Reset, or a Stop Mode Recovery (see Figure 34). After this
point, the register cannot be modified by any means (intentional or otherwise). The
WDTMR cannot be read. The register is located in Bank F of the Expanded Register
Group at address location 0Fh. It is organized as shown in Figure 35.
WDTMR(0F)0Fh
Figure 35. Watchdog Timer Mode Register (Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC
00 5 ms min.
01* 10 ms min.
10 20 ms min.
11 80 ms min.
WDT During HALT
0OFF
1ON *
WDT During Stop
0OFF
1ON *
Reserved (Must be 0)
*Default setting after reset
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
56
WDT Time Select (D0, D1)
This bit selects the WDT time period. It is configured as indicated in Table 15.
WDTMR During Halt (D2)
This bit determines whether or not the WDT is active during HALT mode. A 1 indicates
active during HALT. The default is 1, see Figure 36.
Table 15. Watchdog Timer Time Select
D1 D0 Timeout of Internal RC-Oscillator
005 ms min
0110 ms min
1020 ms min
1180 ms min
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
57
Figure 36. Resets and WDT
WDTMR During STOP (D3)
This bit determines whether or not the WDT is active during STOP mode. A 1 indicates
active during Stop. The default is 1.
EPROM Selectable Options
There are seven EPROM Selectable Options to choose from based on ROM code require-
ments. These are listed in Table 16.
-
* CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers res
p
ectivel
y
u
p
on a Low-to-Hi
g
h
+
From Stop
Mode
Recovery
Source
Stop Delay
Select (SMR)
5 Clock Filter *CLR2 18 Clock RESET
CLK Generator RESET
WDT TAP SELECT
POR 5 ms 10 ms 20 ms 80 ms
CLK
*CLR1 WDT/POR Counter Chain
Internal
RC
Oscillator.
WDT
VDD
Low Operating
Voltage Det.
VBO
VDD
Interna
RESE
T
Active
High
12-ns Glitch Filter
XTAL
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
58
Voltage Brownout/Standby
An on-chip Voltage Comparator checks that the VDD is at the required level for correct
operation of the device. Reset is globally driven when VDD falls below VBO. A small drop
in VDD causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. If
the VDD is allowed to stay above VRAM, the RAM content is preserved. When the power
level is returned to above VBO, the device performs a POR and functions normally.
Low-Voltage Detection
Low-Voltage Detection Register—LVD(D)0Ch
Voltage detection does not work at STOP mode.
Do not modify register P01M while checking a low-voltage condition. Switching noise of
both Ports 0 and 1 together might trigger the LVD Flag.
Table 16. EPROM Selectable Options
Port 00–03 Pull-Ups ON/OFF
Port 04–07 Pull-Ups ON/OFF
Port 10–13 Pull-Ups ON/OFF
Port 14–17 Pull-Ups ON/OFF
Port 20–27 Pull-Ups ON/OFF
EPROM Protection ON/OFF
Watchdog Timer at Power-On Reset ON/OFF
Field Bit Position Description
LVD 76543--- Reserved
No Effect
-----2-- R 1
0*
HVD Flag set
HVD Flag reset
------1- R 1
0*
LVD Flag set
LVD Flag reset
-------0 R/W 1
0*
Enable VD
Disable VD
*Default after POR
Note:
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
59
Voltage Detection and Flags
The Voltage Detection register (LVD, register 0Ch at the expanded register bank 0Dh)
offers an option of monitoring the VCC voltage. The Voltage Detection is enabled when bit
0 of LVD register is set. Once Voltage Detection is enabled, the VCC level is monitored in
real time. The HVD Flag (bit 2 of the LVD register) is set only if VCC is higher than
VHVD. The LVD Flag (bit 1 of the LVD register) is set only if VCC is lower than the VLVD.
When Voltage Detection is enabled, the LVD Flag also triggers IRQ5. The IRQ bit 5
latches the low-voltage condition until it is cleared by instructions or reset. The IRQ5
interrupt is served if it is enabled in the IMR register. Otherwise, bit 5 of IRQ register is
latched as a Flag only.
If it is necessary to receive an LVD interrupt upon power-up at an operating voltage lower
than the low battery detect threshold, enable interrupts using the Enable Interrupt (EI)
instruction prior to enabling the voltage detection.
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
60
Expanded Register File Control Registers (0D)
The expanded register file control registers (0D) are displayed in Figure 37 through
Figure 41.
Figure 37. TC8 Control Register ((0D)O0H: Read/Write Except Where Noted)
CTR0(0D)00H
D7 D6 D5 D4 D3 D2 D1 D0
0 P34 as Port Output *
1 Timer8 Output
0 Disable T8 Timeout Interrupt**
1 Enable T8 Timeout Interrupt
0 Disable T8 Data Capture Interrupt**
1 Enable T8 Data Capture Interrupt
00 SCLK on T8**
01 SCLK/2 on T8
10 SCLK/4 on T8
11 SCLK/8 on T8
R 0 No T8 Counter Timeout**
R 1 T8 Counter Timeout Occurred
W 0 No Effect
W 1 Reset Flag to 0
0 Modulo-N*
1 Single Pass
R 0 T8 Disabled *
R1 T8 Enabled
W0 Stop T8
W 1 Enable T8
*Default setting after reset.
**Default setting after reset. Not reset with a Stop Mode Recovery.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
61
Figure 38. T8 and T16 Common Control Functions ((0D)01H: Read/Write)
CTR1(0D)01H
D7 D6 D5 D4 D3 D2 D1 D0
TRANSMIT Mode*
R/W 0 T16_OUT is 0 initially*
1 T16_OUT is 1 initially
DEMODULATION Mode
R 0 No Falling Edge Detection
R 1 Falling Edge Detection
W 0 No Effect
W 1 Reset Flag to 0
TRANSMIT Mode*
R/W 0 T8_OUT is 0 initially*
1 T8_OUT is 1 initially
DEMODULATION Mode
R 0 No Rising Edge Detection
R 1 Rising Edge Detection
W 0 No Effect
W 1 Reset Flag to 0
TRANSMIT Mode*
0 0 Normal Operation*
01PING-PONG Mode
1 0 T16_OUT = 0
1 1 T16_OUT = 1
DEMODULATION Mode
0 0 No Filter
0 1 4 SCLK Cycle Filter
1 0 8 SCLK Cycle Filter
1 1 Reserved
TRANSMIT Mode/T8/T16 Logic
0 0 AND**
01OR
1 0 NOR
11NAND
DEMODULATION Mode
0 0 Falling Edge Detection
01Rising Edge Detection
1 0 Both Edge Detection
1 1 Reserved
TRANSMIT Mode
0 P36 as Port Output *
1 P36 as T8/T16_OUT
DEMODULATION Mode
0 P31 as Demodulator Input
1 P20 as Demodulator Input
TRANSMIT/DEMODULATION Mode
0 TRANSMIT Mode *
1 DEMODULATION Mode
*Default setting after reset
**Default setting after Reset. Not reset with a Stop Mode
Recovery.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
62
1. Ensure to differentiate the TRANSMIT mode from DEMODULATION
mode. Depending on which of these two modes is operating, the CTR1 bit
has different functions.
2. Changing from one mode to another cannot be performed without disabling the
counter/timers.
CTR2(0D)02H
Figure 39. T16 Control Register ((0D) 2H: Read/Write Except Where Noted)
D7 D6 D5 D4 D3 D2 D1 D0
0 P35 is Port Output *
1 P35 is TC16 Output
0 Disable T16 Timeout Interrupt*
1 Enable T16 Timeout Interrupt
0 Disable T16 Data Capture Interrupt**
1 Enable T16 Data Capture Interrupt
0 0 SCLK on T16**
0 1 SCLK/2 on T16
1 0 SCLK/4 on T16
1 1 SCLK/8 on T16
R 0 No T16 Timeout**
R 1 T16 Timeout Occurs
W 0 No Effect
W 1 Reset Flag to 0
TRANSMIT Mode
0 Modulo-N for T16*
1 Single Pass for T16
DEMODULATOR Mode
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
R 0 T16 Disabled *
R 1 T16 Enabled
W 0 Stop T16
W1Enable T16
*Default setting after reset
**Default setting after reset. Not reset with a Stop Mode
Recovery.
Notes:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
63
CTR3(0D)03H
Figure 40. T8/T16 Control Register (0D)03H: Read/Write (Except Where Noted)
If Sync Mode is enabled, the first pulse of T8 carrier is always synchronized with T16
(demodulated signal). It can always provide a full carrier pulse.
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
No effect when written
Always reads 11111
Sync Mode
0* Disable Sync Mode**
1 Enable Sync Mode
T8 Enable
R 0* T8 Disabled
R 1 T8 Enabled
W0 Stop T8
W1 Enable T8
T16 Enable
R 0* T16 Disabled
R 1 T16 Enabled
W 0 Stop T16
W 1 Enable T16
*Default setting after reset.
**Default setting after reset. Not reset with a Stop Mode
Recovery.
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
64
LVD(0D)0CH
Figure 41. Voltage Detection Register
Do not modify register P01M while checking a low-voltage condition. Switching noise of
both Ports 0 and 1 together might trigger the LVD Flag.
D7 D6 D5 D4 D3 D2 D1 D0
Voltage Detection
0: Disable *
1: Enable
LVD Flag (Read only)
0: LVD Flag reset *
1: LVD Flag set
HVD Flag (Read only)
0: HVD Flag reset *
1: HVD Flag set
Reserved (Must be 0)
*Default setting after reset.
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
65
Expanded Register File Control Registers (0F)
The expanded register file control registers (0F) are displayed in Figure 42 through
Figure 55 on page 74.
PCON(0F)00H
Figure 42. Port Configuration Register (PCON)(0F)00H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output *
1 P34, P37 Comparator Output
Port 1
0: Open-Drain
1: Push-Pull*
Port 0
0: Open-Drain
1: Push-Pull *
Reserved (Must be 1)
*Default setting after reset
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
66
SMR(0F)0BH
Figure 43. Stop Mode Recovery Register ((0F)0BH: D6–D0=Write Only, D7=Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF *
1 ON
Reserved (Must be 0)
Stop Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0–3
111 P2 NOR 0–7
Stop Delay
0OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR * * * * *
1 Stop Recovery * *
*Default setting after Reset
* *Set after Stop Mode Recovery
* * *At the XOR gate input
* * * *Default setting after Reset. Must be 1 if using a crystal or resonator clock source.
* * * * *Default setting after Power-On Reset. Not Reset with a Stop Mode Recovery.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
67
SMR2(0F)0DH
Figure 44. Stop Mode Recovery Register 2 ((0F)0DH:D2–D4, D6 Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0Low
1 High
Reserved (Must be 0)
If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery.
*Default setting after reset. Not Reset with a Stop Mode Recovery.
* *At the XOR gate input
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
68
WDTMR(0F)0FH
Figure 45. Watchdog Timer Register ((0F) 0FH: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC
00 5 ms min.
01* 10 ms min.
10 20 ms min.
11 80 ms min.
WDT During HALT
0OFF
1ON *
WDT During Stop
0OFF
1ON *
Reserved (Must be 0)
*Default setting after reset. Not Reset with a Stop Mode Recovery.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
69
Standard Control Registers
The standard control registers are displayed in Figure 46 through Figure 55 on page 74.
R246 P2M(F6H)
Figure 46. Port 2 Mode Register (F6H: Write Only)
R247 P3M(F7H)
Figure 47. Port 3 Mode Register (F7H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
P27–P20 I/O Definition
0 Defines bit as OUTPUT
1 Defines bit as INPUT *
*Default setting after reset. Not Reset with a Stop Mode Recovery.
D7 D6 D5 D4 D3 D2 D1 D0
0: Port 2 Open Drain *
1: Port 2 Push-Pull
0= P31, P32 DIGITAL Mode*
1= P31, P32 ANALOG Mode
Reserved (Must be 0)
*Default setting after reset. Not Reset with a Stop Mode Recovery.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
70
R248 P01M(F8H)
Figure 48. Port 0 and 1 Mode Register (F8H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
P00–P03 Mode
0: Output
1: Input *
Reserved (Must be 0)
Reserved (Must be 1)
P17–P10 Mode
0: Byte Output
1: Byte Input*
Reserved (Must be 0)
P07–P04 Mode
0: Output
1: Input *
Reserved (Must be 0)
*Default setting after reset; only P00, P01 and P07 are available on Crimzon ZLP32300 20-pin con-
figurations.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
71
R249 IPR(F9H)
Figure 49. Interrupt Priority Register (F9H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B >C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4, Priority
(Group C)
0: IRQ1 > IRQ4
1: IRQ4 > IRQ1
IRQ0, IRQ2, Priority
(Group B)
0: IRQ2 > IRQ0
1: IRQ0 > IRQ2
IRQ3, IRQ5, Priority
(Group A)
0: IRQ5 > IRQ3
1: IRQ3 > IRQ5
Reserved; must be 0
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
72
R250 IRQ(FAH)
Figure 50. Interrupt Request Register (FAH: Read/Write)
R251 IMR(FBH)
Figure 51. Interrupt Mask Register (FBH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = T16
IRQ4 = T8
IRQ5 = LVD
Inter Edge
P31↓P32↓ = 00
P31↓P32↑ = 01
P31↑P32↓ = 10
P31↑↓ P32↑↓ = 11
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ5–IRQ0
(D0 = IRQ0)
Reserved (Must be 0)
0 Master Interrupt Disable *
1 Master Interrupt Enable * *
*Default setting after reset
* *Only by using EI, DI instruction; DI is required before changing the IMR register
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
73
R252 Flags(FCH)
Figure 52. Flag Register (FCH: Read/Write)
R253 RP(FDH)
Figure 53. Register Pointer (FDH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Bank Pointer
Working Register Pointer
Default setting after reset = 0000 0000
Crimzon® ZLP32300
Product Specification
PS020823-0208 Functional Description
74
R254 SPH(FEH)
Figure 54. Stack Pointer High (FEH: Read/Write)
R255 SPL(FFH)
Figure 55. Stack Pointer Low (FFH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
General-Purpose Register
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Low
Byte (SP7–SP0)
Crimzon® ZLP32300
Product Specification
PS020823-0208 Electrical Characteristics
75
Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than those listed in Table 18 might cause permanent damage to the device.
This rating is a stress rating only. Functional operation of the device at any condition
above those indicated in the operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for an extended period might affect
device reliability.
Standard Test Conditions
The characteristics listed in this product specification apply for standard test conditions as
noted. All voltages are referenced to GND. Positive current flows into the referenced pin
(see Figure 56).
Figure 56. Test Load Diagram
Table 17. Absolute Maximum Ratings
Parameter Minimum Maximum Units Notes
Ambient temperature under bias 0 +70 C
Storage temperature –65 +150 C
Voltage on any pin with respect to VSS –0.3 +5.5 V 1
Voltage on VDD pin with respect to VSS –0.3 +3.6 V
Maximum current on input and/or inactive output pin –5 +5 µA
Maximum output current from active output pin –25 +25 mA
Maximum current into VDD or out of VSS 75 mA
1This voltage applies to all pins except the following: VDD, P32, P33 and RESET.
From Output
Under Test
150 pF
Crimzon® ZLP32300
Product Specification
PS020823-0208 Electrical Characteristics
76
Capacitance
Table 18 lists the capacitances.
DC Characteristics
Table 19 describes the DC characteristics.
Table 18. Capacitance
Parameter Maximum
Input capacitance 12 pF
Output capacitance 12 pF
I/O capacitance 12 pF
TA = 25 °C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured
pins returned to GND
Table 19. DC Characteristics
TA= 0 °C to +70 °C
Units Conditions NotesSymbol Parameter VCC Min Typ(7) Max
VCC Supply Voltage 2.0 3.6 V See Notes 5
VCH Clock Input High
Voltage
2.0-3.6 0.8 VCC VCC+0.3 V Driven by External
Clock Generator
VCL Clock Input Low
Voltage
2.0-3.6 VSS–0.3 0.4 V Driven by External
Clock Generator
VIH Input High Voltage 2.0-3.6 0.7 VCC VCC+0.3 V
VIL Input Low Voltage 2.0-3.6 VSS–0.3 0.2 VCC V
VOH1 Output High Voltage 2.0-3.6 VCC–0.4 V IOH = –0.5 mA
VOH2 Output High Voltage
(P36, P37, P00,
P01)
2.0-3.6 VCC–0.8 V IOH = –7 mA
VOL1 Output Low Voltage 2.0-3.6 0.4 V IOL = 4.0 mA
VOL2 Output Low Voltage
(P00, P01, P36,
P37)
2.0-3.6 0.8 V IOL = 10 mA
VOFFSET Comparator Input
Offset Voltage
2.0-3.6 25 mV
VREF Comparator
Reference
Voltage
2.0-3.6 0 VCC
-1.75
V
Crimzon® ZLP32300
Product Specification
PS020823-0208 Electrical Characteristics
77
IIL Input Leakage 2.0-3.6 –1 1 µAV
IN = 0 V, VCC
Pull-ups disabled
RPU Pull-Up Resistance 2.0
3.6
225
75
675
275
kΩ
kΩ
VIN = 0 V, Pull-ups
selected by
mask option
IOL Output Leakage 2.0-3.6 –1 1 µAV
IN = 0 V, VCC
ICC Supply Current 2.0
3.6
1
5
3
10
mA
mA
at 8.0 MHz
at 8.0 MHz
1, 2
1, 2
ICC1 Standby Current
(HALT Mode)
2.0
3.6
0.5
0.8
1.6
2.0
mA VIN = 0V, VCC at 8.0
MHz
Same as above
1, 2, 6
1, 2, 6
ICC2 Standby Current
(STOP Mode)
2.0
3.6
2.0
3.6
1.6
1.8
5
8
8
10
20
30
µA
µA
µA
µA
VIN = 0 V, VCC WDT is
not Running
Same as above
VIN = 0 V, VCC WDT is
Running
Same as above
3
3
3
3
ILV Standby Current
(Low Voltage)
1.2 6 µA Measured at 1.3 V 4
VBO VCC Low Voltage
Protection
1.9 2.0 V 8 MHz maximum
Ext. CLK Freq.
VLVD Vcc Low Voltage
Detection
2.4 V
VHVD Vcc High Voltage
Detection
2.7 V
Notes
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF.
3. Oscillator stopped.
4. Oscillator stops when VCC falls below VBO limit.
5. It is strongly recommended to add a filter capacitor (minimum 0.1 µF), physically close to VDD and VSS pins if
operating voltage fluctuations are anticipated, such as those resulting from driving an infrared LED.
6. Comparator and Timers are on. Interrupt disabled.
7. Typical values shown are at 25 ºC.
Table 19. DC Characteristics (Continued)
TA= 0 °C to +70 °C
Units Conditions NotesSymbol Parameter VCC Min Typ(7) Max
Crimzon® ZLP32300
Product Specification
PS020823-0208 Electrical Characteristics
79
Table 20. AC Characteristics
TA=0 °C to +70 °C
8.0 MHz
Watchdog
Timer
Mode
Register
(D1, D0)No Symbol Parameter VCC Minimum Maximum Units Notes
1 TpC Input Clock Period 2.0–3.6 121 DC ns 1
2 TrC,TfC Clock Input Rise and
Fall Times
2.0–3.6 25 ns 1
3 TwC Input Clock Width 2.0–3.6 37 ns 1
4 TwTinL Timer Input
Low Width
2.0
3.6
100
70
ns 1
5 TwTinH Timer Input High
Width
2.0–3.6 3TpC 1
6 TpTin Timer Input Period 2.0–3.6 8TpC 1
7 TrTin,TfTin Timer Input Rise and
Fall Timers
2.0–3.6 100 ns 1
8 TwIL Interrupt Request
Low Time
2.0
3.6
100
70
ns 1, 2
9 TwIH Interrupt Request
Input High Time
2.0–3.6 5TpC 1, 2
10 Twsm Stop Mode Recovery
Width Spec
2.0–3.6 12
10TpC
ns 3
4
11 Tost Oscillator
Start-Up Time
2.0–3.6 5TpC 4
12 Twdt Watchdog Timer
Delay Time
2.0–3.6
2.0–3.6
2.0–3.6
2.0–3.6
5
10
20
80
ms
ms
ms
ms
0, 0
0, 1
1, 0
1, 1
13 TPOR Power-on reset 2.0–3.6 2.5 10 ms
Notes
1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request through Port 3 (P33–P31).
3. SMR–D5 = 1.
4. SMR–D5 = 0.
Crimzon® ZLP32300
Product Specification
PS020823-0208 Packaging
81
Figure 59. 20-Pin SOIC Package Diagram
Crimzon® ZLP32300
Product Specification
PS020823-0208 Packaging
82
Figure 60. 20-Pin SSOP Package Diagram
Crimzon® ZLP32300
Product Specification
PS020823-0208 Packaging
83
Figure 61. 28-Pin SOIC Package Diagram
Crimzon® ZLP32300
Product Specification
PS020823-0208 Packaging
84
Figure 62. 28-Pin PDIP Package Diagram
Crimzon® ZLP32300
Product Specification
PS020823-0208 Packaging
85
Figure 63. 28-Pin SSOP Package Diagram
Figure 64. 40-Pin PDIP Package Diagram
SYMBOL
A
A1
B
C
A2
e
MILLIMETER INCH
MIN MAX MIN MAX
1.73
0.05
1.68
0.25
5.20
0.65 TYP
0.09
10.07
7.65
0.63
1.86
0.0256 TYP
0.13
10.20
1.73
7.80
5.30
1.99
0.21
1.78
0.75
0.068
0.002
0.066
0.010
0.205
0.004
0.397
0.301
0.025
0.073
0.005
0.068
0.209
0.006
0.402
0.307
0.030
0.078
0.008
0.070
0.015
0.212
0.008
0.407
0.311
0.037
0.38
0.20
10.33
5.38
7.90
0.95
NOM NOM
D
E
H
L
CONTROLLING DIMENSIONS: MM
LEADS ARE COPLANAR WITHIN .004 INCHES.
H
C
DETAIL A
E
D
28 15
114
SEATING PLANE
A2
e
A
Q1
A1
B
L
0 - 8
DETAIL 'A'
Crimzon® ZLP32300
Product Specification
PS020823-0208 Packaging
86
Figure 65. 48-Pin SSOP Package Design
Contact Zilog® on the actual bonding diagram and coordinate for chip-on-board assem-
bly.
CONTROLLING DIMENSIONS : MM
LEADS ARE COPLANAR WITHIN .004 INCH
D
E H
A1
A2 A
e
SEATING PLANE
b
48 25
c
Detail A
Detail A
0-8˚
L
1 24
Note:
Crimzon® ZLP32300
Product Specification
PS020823-0208 Ordering Information
87
Ordering Information
The Crimzon ZLP32300 is available for the following parts:
Device Part Number Description
Crimzon
ZLP32300
ZLP32300H4832G 48-pin SSOP 32 K OTP
ZLP32300P4032G 40-pin PDIP 32 K OTP
ZLP32300H2832G 28-pin SSOP 32 K OTP
ZLP32300P2832G 28-pin PDIP 32 K OTP
ZLP32300S2832G 28-pin SOIC 32 K OTP
ZLP32300H2032G 20-pin SSOP 32 K OTP
ZLP32300P2032G 20-pin PDIP 32 K OTP
ZLP32300S2032G 20-pin SOIC 32 K OTP
ZLP32300H4816G 48-pin SSOP 16 K OTP
ZLP32300P4016G 40-pin PDIP 16 K OTP
ZLP32300H2816G 28-pin SSOP 16 K OTP
ZLP32300P2816G 28-pin PDIP 16 K OTP
ZLP32300S2816G 28-pin SOIC 16 K OTP
ZLP32300H2016G 20-pin SSOP 16 K OTP
ZLP32300P2016G 20-pin PDIP 16 K OTP
ZLP32300S2016G 20-pin SOIC 16 K OTP
ZLP32300H4808G 48-pin SSOP 8 K OTP
ZLP32300P4008G 40-pin PDIP 8 K OTP
ZLP32300H2808G 28-pin SSOP 8 K OTP
ZLP32300P2808G 28-pin PDIP 8 K OTP
ZLP32300S2808G 28-pin SOIC 8 K OTP
ZLP32300H2008G 20-pin SSOP 8 K OTP
Crimzon® ZLP32300
Product Specification
PS020823-0208 Ordering Information
88
For fast results, contact your local Zilog® sales office for assistance in ordering the part(s)
desired.
ZLP32300P2008G 20-pin PDIP 8 K OTP
ZLP32300S2008G 20-pin SOIC 8 K OTP
ZLP32300H4804G 48-pin SSOP 4 K OTP
ZLP32300P4004G 40-pin PDIP 4 K OTP
ZLP32300H2804G 28-pin SSOP 4 K OTP
ZLP32300P2804G 28-pin PDIP 4 K OTP
ZLP32300S2804G 28-pin SOIC 4 K OTP
ZLP32300H2004G 20-pin SSOP 4 K OTP
ZLP32300P2004G 20-pin PDIP 4 K OTP
ZLP32300S2004G 20-pin SOIC 4 K OTP
ZLP323ICE01ZAC* 40-PDIP/48-SSOP Accessory Kit
Note: *ZLP323ICE01ZAC has been replaced by an improved version,
ZCRMZNICE02ZACG.
ZLP128ICE01ZEMG In-Circuit Emulator
Note: *ZLP128ICE01ZEMG has been replaced by an improved version,
ZCRMZNICE01ZEMG.
ZCRMZNICE01ZEMG Crimzon In-Circuit Emulator
ZCRMZN00100KITG Crimzon In-Circuit Emulator
Development Kit
ZCRMZNICE01ZACG 20-Pin Accessory Kit
ZCRMZNICE02ZACG 40/48-Pin Accessory Kit
Notes
1. Replace C with G for Lead-Free Packaging.
2. Contact www.zilog.com for the die form.
Device Part Number Description
Crimzon® ZLP32300
Product Specification
PS020823-0208 Ordering Information
89
Part Number Description
Zilog® part numbers consist of a number of components, as shown below.
ZLP32300H2832G is a Crimzon ZLP32300 OTP product in a 28-pin SSOP package, with
32 KB of OTP and built with lead-free solder.
Z LP 32300 H 28 32 G
Environmental Flow
G = Lead Free
Memory Size
32 = 32 KB
16 = 16 KB
8 = 8 KB
4 = 4 KB
Number of Pins in Package
48 = 48 Pins
40 = 40 Pins
28 = 28 Pins
20 = 20 Pins
Package Type
H = SSOP
P = PDIP
S = SOIC
Product Number
32300
Product Line
Crimzon ZLP32300 OTP
Zilog Product Prefix
Crimzon® ZLP32300
Product Specification
PS020823-0208 Ordering Information
90
Crimzon® ZLP32300
Product Specification
PS020823-0208 Index
91
Index
Numerics
16-bit counter/timer circuits 40
20-pin DIP package diagram 80
20-pin SSOP package diagram 82
28-pin DIP package diagram 84
28-pin SOIC package diagram 83
28-pin SSOP package diagram 85
40-pin DIP package diagram 85
48-pin SSOP package diagram 86
8-bit counter/timer circuits 36
A
absolute maximum ratings 75
AC
characteristics 78
timing diagram 78
address spaces, basic 1
architecture 1
expanded register file 22
B
basic address spaces 1
block diagram, ZLP32300 functional 3
C
capacitance 76
characteristics
AC 78
DC 76
clock 46
comparator inputs/outputs 18
configuration
port 0 12
port 1 13
port 2 14
port 3 15
port 3 counter/timer 17
counter/timer
16-bit circuits 40
8-bit circuits 36
brown-out voltage/standby 58
clock 46
demodulation mode count capture flowchart 38
demodulation mode flowchart 39
EPROM selectable options 58
glitch filter circuitry 34
halt instruction 47
input circuit 33
interrupt block diagram 44
interrupt types, sources and vectors 45
oscillator configuration 46
output circuit 43
port configuration register 48
resets and WDT 57
SCLK circuit 50
stop instruction 47
stop mode recovery register 49
stop mode recovery register 2 54
stop mode recovery source 52
T16 demodulation mode 41
T16 transmit mode 40
T16_OUT in modulo-N mode 41
T16_OUT in single-pass mode 41
T8 demodulation mode 37
T8 transmit mode 34
T8_OUT in modulo-N mode 37
T8_OUT in single-pass mode 37
transmit mode flowchart 35
voltage detection and flags 59
watch-dog timer mode register 55
watch-dog timer time select 56
CTR(D)01h T8 and T16 Common Functions 29
D
DC characteristics 76
demodulation mode
count capture flowchart 38
flowchart 39
T16 41
Crimzon® ZLP32300
Product Specification
PS020823-0208 Index
92
T8 37
description
functional 19
general 3
pin 5
E
EPROM
selectable options 58
expanded register file 20
expanded register file architecture 22
expanded register file control registers 64
flag 73
interrupt mask register 72
interrupt priority register 71
interrupt request register 72
port 0 and 1 mode register 70
port 2 configuration register 69
port 3 mode register 69
port configuration register 69
register pointer 73
stack pointer high register 74
stack pointer low register 74
stop mode recovery register 66
stop mode recovery register 2 67
T16 control register 62
T8 and T16 common control functions register
61
T8/T16 control register 63
TC8 control register 60
watchdog timer register 68
F
features
standby modes 2
ZLP32300 2
functional description
counter/timer functional blocks 33
CTR(D)01h register 28
CTR0(D)00h register 27
CTR2(D)02h register 31
CTR3(D)03h register 33
expanded register file 20
expanded register file architecture 22
HI16(D)09h register 26
HI8(D)0Bh register 25
L08(D)0Ah register 26
L0I6(D)08h register 26
program memory map 20
RAM 19
register description 58
register file 24
register pointer 23
register pointer detail 25
SMR2(F)0D1h register 33
stack 25
TC16H(D)07h register 26
TC16L(D)06h register 26
TC8H(D)05h register 27
TC8L(D)04h register 27
G
glitch filter circuitry 34
H
halt instruction, counter/timer 47
I
input circuit 33
interrupt block diagram, counter/timer 44
interrupt types, sources and vectors 45
L
low-voltage detection register 58
M
memory, program 19
modulo-N mode
T16_OUT 41
T8_OUT 37
Crimzon® ZLP32300
Product Specification
PS020823-0208 Index
93
O
oscillator configuration 46
output circuit, counter/timer 43
P
package information
20-pin DIP package diagram 80
20-pin SSOP package diagram 82
28-pin DIP package diagram 84
28-pin SOIC package diagram 83
28-pin SSOP package diagram 85
40-pin DIP package diagram 85
48-pin SSOP package diagram 86
part number format 89
pin configuration
20-pin DIP/SOIC/SSOP 5
28-pin DIP/SOIC/SSOP 6
40- and 48-pin 8
40-pin DIP 7
48-pin SSOP 8
pin functions
port 0 (P07 - P00) 11
port 0 (P17 - P10) 12
port 0 configuration 12
port 1 configuration 13
port 2 (P27 - P20) 13
port 2 (P37 - P30) 14
port 2 configuration 14
port 3 configuration 15
port 3 counter/timer configuration 17
reset) 18
XTAL1 (time-based input 10
XTAL2 (time-based output) 10
port 0 configuration 12
port 0 pin function 11
port 1 configuration 13
port 1 pin function 12
port 2 configuration 14
port 2 pin function 13
port 3 configuration 15
port 3 pin function 14
port 3counter/timer configuration 17
port configuration register 48
power connections 1
power supply 5
program memory 19
map 20
R
ratings, absolute maximum 75
register 54
CTR(D)01h 28
CTR0(D)00h 27
CTR2(D)02h 31
CTR3(D)03h 33
flag 73
HI16(D)09h 26
HI8(D)0Bh 25
interrupt priority 71
interrupt request 72
interruptmask 72
L016(D)08h 26
L08(D)0Ah 26
LVD(D)0Ch 58
pointer 73
port 0 and 1 70
port 2 configuration 69
port 3 mode 69
port configuration 48, 69
SMR2(F)0Dh 33
stack pointer high 74
stack pointer low 74
stop mode recovery 49
stop mode recovery 2 54
stop mode recovery 66
stop mode recovery 2 67
T16 control 62
T8 and T16 common control functions 61
T8/T16 control 63
TC16H(D)07h 26
TC16L(D)06h 26
TC8 control 60
TC8H(D)05h 27
TC8L(D)04h 27
voltage detection 64
watch-dog timer 68
Crimzon® ZLP32300
Product Specification
PS020823-0208 Index
94
register description
Counter/Timer2 LS-Byte Hold 26
Counter/Timer2 MS-Byte Hold 26
Counter/Timer8 Control 27
Counter/Timer8 High Hold 27
Counter/Timer8 Low Hold 27
CTR2 Counter/Timer 16 Control 31
CTR3 T8/T16 Control 33
Stop Mode Recovery2 33
T16_Capture_LO 26
T8 and T16 Common functions 28
T8_Capture_HI 25
T8_Capture_LO 26
register file 24
expanded 20
register pointer 23
detail 25
reset pin function 18
resets and WDT 57
S
SCLK circuit 50
single-pass mode
T16_OUT 41
T8_OUT 37
stack 25
standard test conditions 75
standby modes 2
stop instruction, counter/timer 47
stop mode recovery
2 register 54
source 52
stop mode recovery 2 54
stop mode recovery register 49
T
T16 transmit mode 40
T16_Capture_HI 26
T8 transmit mode 34
T8_Capture_HI 25
test conditions, standard 75
test load diagram 75
timing diagram, AC 78
transmit mode flowchart 35
V
VCC 5
voltage
brown-out/standby 58
detection and flags 59
voltage detection register 64
W
watchdog timer
mode register watchdog timer mode register 55
time select 56
X
XTAL1 5
XTAL1 pin function 10
XTAL2 5
XTAL2 pin function 10
Z
ZLP32300 family members 2
Crimzon® ZLP32300
Product Specification
PS020823-0208 Customer Support
95
Customer Support
For answers to technical questions about the product, documentation, or any other issues
with Zilog’s offerings, please visit Zilog’s Knowledge Base at
http://www.zilog.com/kb.
For any comments, detail technical questions, or reporting problems, please visit Zilog’s
Technical Support at http://support.zilog.com.
