GS2978-INE3 - Gennum Corp. - Datasheet.Directory

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XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

2013 REV. 2013

GENERAL DESCRIPTION

The XRT86VX38 is an eight-channel 1.544 Mbit/s or

2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Short-

hual LIU integrated solution featuring R3 technology

(Relayless, Reconfigurable, Redundancy) and BITS

Timing element. The physical interface is optimized

with internal impedance, and with the patented pad

structure, the XRT86VX38 provides protection from

power failures and ho t swapping.

The XRT86VX38 contains an integrated DS1/E1/J1

framer and LIU which provide DS1/E1/J1 framing and

error accumulation in accordance with ANSI/ITU_T

specifications. Each framer has its own framing

synchronizer and transmit-receive slip buffers. The

slip buffe rs can be independently enab led or disabled

as required and can be configured to frame to the

common DS1/E1/J1 signal formats.

Each Framer block contains its own Transmit and

Receive T1/E1/J1 Framing function. There are 3

Transmit HDLC controllers per channel which

encapsulate contents of the Transmit HDLC buffers

into LAPD Message frames. There are 3 Receive

HDLC controllers per channel which extract the

payload content of Receive LAPD Message frames

from the incoming T1 /E1/J1 dat a str eam and write the

contents into the Receiv e HDLC b uffers. Each fram er

also contains a Transmit and Overhead Data Input

port, which permits Data Link Terminal Equipment

direct access to the outbound T1/E1/J1 frames.

Likewise, a Receive Overhead output data port

permits Data Link Terminal Equipment direct access

to the Data Link bits of the inbound T1/E1/J1 frames.

The XRT86VX38 fully meets all of the latest T1/E1/J1

specifications: ANSI T1/E1.107-1988, ANSI T1/

E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/

E1.408-1990, AT&T TR 62411 (12-90) TR54016, and

ITU G-703, G.704, G706 and G.733, AT&T Pub.

43801, and ETS 300 011, 300 233, JT G.703, JT

G.704, JT G706, I.431. Ex tensive test and d iagnostic

functions include Loop-backs, Boundary scan,

Pseudo Random bit sequence (PRBS) test pattern

generation, Performance Monitor, Bit Error Rate

(BER) meter, forced error insertion, and LAPD

unchannelized data payload processing according to

ITU-T standar d Q.921.

Applications and Features (next page)

FIGURE 1. XRT86VX38 EIGHT CHANNEL E1 (T1/E1/J1) FRAMER/LIU COMBO

Performance

Monitor

PRBS

Generator &

Analyser

HDLC/LAPD

Controllers

LIU &

Loopback

Control

DMA

Interface

Signaling &

Alarms JTAG

ALE_AS

RDY_DTACK

P

Select

A[14:0]

D[7:0]

Microprocessor

Interface

Tx Serial

Clock

Rx Serial

Clock

8kHz sync

OSC

Back Plane

1 .544 -16.384 Mbit/s

Local P C M

Highway

ST-BUS

2-Frame

Slip Buffer

Elastic Store

Tx S erial

Data In Tx LIU

Interface

2-Frame

Slip Buffer

Elastic Store

Rx LIU

Interface

R x Fram er

Rx Serial

Data Out

RTIP

RRING

TTIP

TRING

External Data

Link C ontroll er

Tx Ov erhead In R x Ov erhead O ut

XRT86VX38

1 of 8-channels

Tx Framer

LLB LB

System (Terminal ) Side

Li ne Si de

1: 1 Turns Ratio

1: 2 Turns Ratio

Memory

Intel/Motorola µP

Configuration, Control &

Stat us Monit or

RxLOS

TxON

INT

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

APPLICATIONS

High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems

SONET/SDH terminal or Add/Drop multiplexers (ADMs)

T1/E1/J1 add/drop multiplexers (MUX)

Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1

BITS Timing

Digital Access Cross-connect System (DACs)

Digital Cross-connect Systems (DCS)

Frame Relay Switches and Access Devices (FRADS)

ISDN Primary Rate Interfaces (PRA)

PBXs and PCM channel bank

T3 channelized access concentrators and M13 MUX

Wireless base stations

ATM equipme nt with integrated DS1 interfaces

Multichannel DS1 Test Equipment

T1/E1/J1 Performance Monitoring

Voice over packet gatewa ys

Routers

FEATURES

Supports Section 13 - Synchronization Interface in ITU G.703 for both Transmit and Receive Paths

Supports SSM Synchronous Messaging Generation (BOC for T1, National Bits for E1) on the Transmit Path

Supports SSM Synchronous Messaging Extraction (BOC for T1, National Bits for E1) on the Receive Path

Supports BITS timing generation on the Transmit Outputs

Supports BITS timing extraction from NRZ data on the Analog Receive Path

DS-0 Monitoring on both Transmit and Receive Time Slots

Supports SSM Synchronization Messaging per ANSI T1.101-1999 and ITU G.704

Supports a Customized Section 13 - Synchronization Interface in G.703 at 1.544MHz

Independent, full duplex DS1 Tx and Rx Framer/LIUs

Each channel has full featured Long-haul/Short-haul LIU

Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz

asynchronous back plane connections with jitter and wander attenuation

Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel

multiplexed 12.3 52 /1 6. 38 4 (HMVIP/H.100) Mbit/s on the back plane bus

Programmable output clocks for Fractional T1/E1/J1

Supports Channel Associated Signaling (CAS)

Supports Common Channel Signalling (CCS)

Supports ISDN Primary Rate Interface (ISDN PRI) signaling

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

Extracts and inserts robbed bit signaling (RBS)

3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 /

buffer 1)

HDLC Controllers Support SS7

Timeslot assignable HDLC

V5.1 or V5.2 Interface

Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface

every 1 second or for a single transmission

Supports SPRM and NPRM

Alarm Indication Signal with Customer Installation signature (AIS-CI)

Remote Alarm Indication with Customer Installation (RAI-CI)

Gapped Clock interface mode for Transmit and Receive.

Intel/Motorola and Power PC interfaces for configuration, control and status monitoring

Parallel search algorithm for fast frame synchronization

Wide choice of T1 framing structures: SF/D4, ESF, SLC®96, T1DM and N-Frame (non-signaling)

Direct access to D and E channels for fast transmission of data link information

Full BERT Controller for generation and detection on system and line side of the chip

PRBS, QRSS, and Network Loop Code generation and detection

Seven Independen t, simultaneous Loop Code Detectors per Channel

Programmabl e Interrupt output pin

Supports programmed I/O and DMA modes of Read-Write access

The framer block encodes and decodes the T1/E1/J1 Frame serial data

Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms

Detects OOF, LOF, LOS errors and COFA conditio ns

Loopbacks: Local (LLB) and Line remote (LB)

Facilitates Inverse Multiplexing for ATM

Performance monitor with one second polling

Boundary scan (IEEE 1149.1) JTAG test port

Accepts external 8kHz Sync reference

1.8V Inner Core

3.3V CMOS operatio n with 5V tolerant inputs

256-pin fpBGA and 329-pin fpBGA package with -40C to +85C operation

ORDERING INFORMATION

PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE

XRT86VX38IB256 256 PIn Fine Pitch Ball Grid Array -40C to +85C

XRT86VX38IB329 329 PIn Fine Pitch Ball Grid Array -40C to +85C

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

LIST OF TABLES

Table 1:: Register Summary ..............................................................................................................................................4

Table 2:: Clock Select Register (CSR) Hex Address: 0xN100 ..................10

Table 3:: Line Interface Control Register (LICR) Hex Address: 0xN101 ....................12

Table 4:: General Purpose Input/Output 0 Control Register(GPIOCR0) Hex Address: 0x0102 ...........................14

Table 5:: General Purpose Input/Output 1 Control Register(GPIOCR1) Hex Address: 0x4102 ........................15

Table 6:: Framing Select Register (FSR) Hex Address: 0xN107 ................16

Table 7:: Alarm Generation Register (AGR) Hex Address: 0xN108 ..................20

Table 8:: Synchronization MUX Register (SMR) Hex Address: 0xN109 .................22

Table 9:: Transmit Signaling and Data Link Select Register (TSDLSR) Hex Address:0xN10A ....................25

Table 10:: Framing Control Register (FCR) Hex Address: 0xN10B ...............28

Table 11:: Receive Signaling & Data Link Select Register (RSDLSR) Hex Address: 0xN10C ................30

Table 12:: Receive Signaling Cha nge Register 0 (RSCR 0) Hex Address: 0xN10D ...........32

Table 13:: Receive Signaling Cha nge Register 1 (RSCR 1) Hex Address: 0xN10E ...........32

Table 14:: Receive Signaling Cha nge Register 2 (RSCR 2) Hex Address: 0xN10F ...........32

Table 15:: Receive Signaling Cha nge Register 3 (RSCR 3) Hex Address: 0xN110 ...........33

Table 16:: Receive National Bits Regi ster (RNBR) Hex Address: 0xN111 ...............34

Table 17:: Receive Extra Bits Register (REBR) Hex Address: 0xN112 ..............35

Table 18:: Data Link Control Register (DLCR1) Hex Address: 0xN113 ..................37

Table 19:: Transmit Data Link Byte Count Reg ister (TDLBCR1) Hex Address: 0xN114 ................39

Table 20:: Receive Data Link Byte Count Register (RDLBCR1) Hex Address: 0xN115 ...............40

Table 21:: Slip Buffer Control Register (SBCR) Hex Address: 0xN116 ..................41

Table 22:: FIFO Latency Register (FFOLR) Hex Address: 0xN117 ...............42

Table 23:: DMA 0 (Write) Configuration Register (D0WC R) Hex Address: 0xN118 .................43

Table 24:: DMA 1 (Read) Configuration Register (D1RCR) Hex Address: 0xN119 ...............44

Table 25:: Interrupt Control Register (ICR) Hex Address: 0xN11A ..................45

Table 26:: LAPD Select Register (LAPDSR) Hex Address: 0xN11B ...............46

Table 27:: Performance Report Control Register (PRCR) Hex Address: 0xN11D ..................46

Table 28:: Gapped Clock Control Registe r (GCCR) Hex Address: 0xN11E .................47

Table 29:: Transmit Inte rface Control Register (TICR) Hex Address:0xN120 ..................48

Table 30:: Transmit Interface Speed When Multiplexed Mode is Disabled (TxMUXEN = 0) .... ... .............. ... .............. ... ..50

Table 31:: Transmit Interface Speed when Multiplexed Mode is Enabled (TxMUXEN = 1) ............................................51

Table 32:: PRBS Contro l And Status Register 0 (PRBSCSR0) Hex Address: 0xN121 ................52

Table 33:: Receive Interface Control Register (RICR ) Hex Address: 0xN122 ..................54

Table 34:: Receive Interface Speed When Multiplexed Mode is Disabled (TxMUXEN = 0) ............................................55

Table 35:: Receive Interface Speed when Multiplexed Mode is Enabled (TxMUXEN = 1) .............................................56

Table 36:: PRBS Control and Status Register 1 (PRBSCSR1) Hex Address: 0xN123 ................57

Table 37:: Loopback Code Control Register (LCCR) Hex Address: 0xN124 ..................59

Table 38:: Transmit Loopback Coder Register (TLCR) Hex Address: 0xN125 ................59

Table 39:: Receive Loopback Activation Code Register (RLACR) Hex Address: 0xN126 ..............59

Table 40:: Receive Loopback Deactivation Code Register (RLDCR) Hex Address: 0xN127 ...................59

Table 41:: Defect Detection Enable Register (DDER) Hex Address: 0xN129 ..................59

Table 42:: Transmit Sa Select Register (TSASR) Hex Address: 0xN130 ................60

Table 43:: Transmit Sa Auto Control Register 1 (TSACR1) Hex Address: 0xN131 ...................62

Table 44:: Conditions on Receive side When TSACR1 bits Are enabled ........................................................................63

Table 45:: Transmit Sa Auto Control Register 2 (TSACR2) Hex Address: 0xN132 ......................64

Table 46:: Conditions on Receive side When TSACR2 bits enabled ..............................................................................65

Table 47:: Transmit Sa4 Register (TSA4R) Hex Address: 0xN133 ............66

Table 48:: Transmit Sa5 Register (TSA5R) Hex Address: 0xN134 ............66

Table 49:: Transmit Sa6 Register (TSA6R) Hex Address: 0xN135 ............66

Table 50:: Transmit Sa7 Register (TSA7R) Hex Address: 0xN136 ............66

Table 51:: Transmit Sa8 Register (TSA8R) Hex Address: 0xN137 ............67

Table 52:: Receive Sa4 Register (RSA4R) Hex Address: 0xN13B ............68

Table 53:: Receive Sa5 Register (RSA5R) Hex Address: 0xN13C ............68

Table 54:: Receive Sa6 Register (RSA6R) Hex Address: 0xN13D ............68

Table 55:: Receive Sa7 Register (RSA7R) Hex Address: 0xN13E ............69

Table 56:: Receive Sa8 Register (RSA8R) Hex Address: 0xN13F .............69

Table 57:: Data Link Control Register (DLCR2) Hex Address: 0xN143 ..............70

Table 58:: Transmit Data Link Byte Count Reg ister (TDLBCR2) Hex Address: 0xN144 ................72

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

Table 59:: Receive Data Link Byte Count Register (RDLBCR2) Hex Address: 0xN145 ...............73

Table 60:: Data Link Control Register (DLCR3) Hex Address: 0xN153 ...............74

Table 61:: Transmit Data Link Byte Count Register (TDLBCR3) Hex Address: 0xN154 ................. 76

Table 62:: Receive Data Link Byte Count Register (RDLBCR3) Hex Address: 0xN155 ...............77

Table 63:: BERT Control Register (BCR) Hex Address: 0xN163 ............... 78

Table 64:: E1 SSM Messages .........................................................................................................................................79

Table 65:: SSM BOC Control Register (BOCCR 0xN170h) ............................................................................................80

Table 66:: Receive SSM Register (RSSMR 0xN171h) ....................................................................................................81

Table 67:: Receive SSM Match 1 Register (RSSMMR1 0xN17 2h) .................................................................................82

Table 68:: Receive SSM Match 2 Register (RSSMMR2 0xN17 3h) .................................................................................82

Table 69:: Receive SSM Match 3 Register (RSSMMR3 0xN17 4h) .................................................................................82

Table 70:: Transmit SSM Register (TSSMR 0xN175h) ...................................................................................................83

Table 71:: Transmit SSM Byte Count Register (TSSMBCR 0xN176h) ...........................................................................83

Table 72:: Receive FAS Si Register (RFASSiR 0xN177h) ..............................................................................................84

Table 73:: Transmit FAS Si Register (RFASSiR 0xN178h) .............................................................................................84

Table 74:: Receive DS-0 Monitor Registers (RDS0MR) Hex Address:

0xN15F to 0xN16F (not including 0xN163) and 0xN1C0 to 0xN1CF ................................................................85

Table 75:: Transmit DS-0 Monitor Registers (TDS0MR) Hex Address: 0xN1D0 to 0xN1EF .......................................86

Table 76:: Device ID Register (DEVID) Hex Address: 0x1FE ...............86

Table 77:: Revision ID Register (REVID) Hex Address: 0x1FF ............86

Table 78:: Transmit Cha nnel Control Register 0-31 (TCCR 0-31) Hex Address: 0xN300 to 0xN31F .................. 87

Table 79:: Transmit User Code Register 0 - 31 (TUCR 0-31) Hex Address: 0xN320 to 0xN33F ...............89

Table 80:: Transmit Signaling Control Register 0-31 (TSCR 0-31) Hex Address: 0xN340 to 0xN35F ....................90

Table 81:: Receive Channel Control Register x (RCCR 0-31) Hex Address: 0xN360 to 0xN37F .................93

Table 82:: Receive User Code Register 0-31 (RUCR 0-31) Hex Address: 0xN380 to 0xN39F .............95

Table 83:: Receive Signaling Contro l Register 0-31 (RSCR 0-31) Hex Address: 0xN3A0 to 0xN3BF ...................95

Table 84:: Receive Substitu tion Signaling Register 0-31 (RSSR 0-31) Hex Address 0xN3C0 to 0xN3DF ..................97

Table 85:: Receive Signaling Array Regi ster 0 - 31 (RSAR 0-31) Hex Address: 0xN500 to 0xN51F .................97

Table 86:: LAPD Buffer 0 Control Register (LAPDBCR0) Hex Address: 0xN600 ...................................98

Table 87:: LAPD Buffer 1 Control Register (LAPDBCR1) Hex Address: 0xN700 ...................................99

Table 88:: PMON Receive Line Code Viola ti on Counter MSB (RLCVCU) Hex Address: 0xN900 ................99

Table 89:: PMON Receive Line Code Violation Counter LSB (RLCVCL) Hex Address: 0xN901 ..............100

Table 90:: PMON Receive Framing Alignment Bit Error Counter MSB (RFAECU) Hex Address: 0xN902 ..................100

Table 91:: PMON Receive Framing Alignment Bit Error Counter LSB (RFAECL) Hex Address: 0xN903 ..................100

Table 92:: PMON Receive Severely Erro red Frame Counter (RSEFC) Hex Address: 0xN904 .................101

Table 93:: PMON Receive CRC-4 Bit Error Counter - MSB (RSBBECU) Hex Address: 0xN905 ................ 101

Table 94:: PMON Receive CRC-4 Block Error Counter - LSB (RSBBECL) Hex Address: 0xN906 .................101

Table 95:: PMON Receive Far-End BLock Error Counter - MSB (RFEBECU) Hex Address: 0xN907 .. .............. 102

Table 96:: PMON Receive Far End Block Error Counter -LSB (RFEBECL) Hex Address: 0xN908 ..................102

Table 99:: PMON Receive Change of Fr ame Alignment Counter (RCFAC) Hex Address: 0xN90B ..............103

Table 97:: PMON Receive Slip Counter (RSC) Hex Address: 0xN909 ..........103

Table 98:: PMON Receive Loss of Frame Counter (RLFC) Hex Address: 0xN90A ............103

Table 100:: PMON LAPD Frame Check Sequence Error Counter 1 (LFCSEC1) Hex Address: 0xN90C .............104

Table 101:: PMON PRBS Bit Error Counter MSB (PBECU) Hex Address: 0xN90D ..........104

Table 102:: PMON PRBS Bit Error Counter LSB (PBECL) Hex Address: 0xN90E ..........105

Table 103:: PMON Transmit Slip Counter (TSC) Hex Address: 0xN90F ........105

Table 104:: PMON Excessive Zero Violation Counter MSB (EZVCU) Hex Address: 0xN910 .............105

Table 105:: PMON Excessive Zero Violation Counter LSB (EZVCL) Hex Address: 0xN911 .............106

Table 106:: PMON Frame Check Sequence Erro r Counter 2 (LFCSEC2) Hex Address: 0xN91C ..............106

Table 107:: PMON Frame Check Sequence Erro r Counter 3 (LFCSEC3) Hex Address: 0xN92C ..............106

Table 108:: Block Interrupt Status Register (BISR) Hex Address: 0xNB00 .................107

Table 109:: Block Interrupt Enable Register (BIER) Hex Address: 0xNB01 ................109

Table 110:: Alarm & Error Interrupt Status Register (AEISR) Hex Address: 0xNB02 ...................111

Table 111:: Alarm & Error Interrupt Enable Register (AEIER) Hex Address: 0xNB03 ..................114

Table 112:: Framer Interrupt Status Register (FISR) Hex Address: 0xNB04 .............116

Table 113:: Framer Interrupt Enable Register (FIER) Hex Address: 0xNB05 .............119

Table 114:: Data Link Status Register 1 (DLSR1) Hex Address: 0xNB06 ............121

Table 115:: Data Link Interrupt Enable Register 1 (DLIER1) Hex Address: 0xNB07 ................ 123

Table 116:: Slip Buffer Interrupt Status Register (SBISR) Hex Address: 0xNB08 ................125

Table 117:: Slip Buffer Interrupt Enable Register (SBIER) Hex Address: 0xNB09 ...................128

XRT86VX38

III

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

Table 118:: Receive Loopback Code Interrupt and Status Register (RLCISR) Hex Address: 0xNB0A ...................130

Table 119:: Receive Loopback Code Interrupt Enable Register (RLCIER) Hex Address: 0xNB0B ................131

Table 120:: Receive SA Interrupt Status Registe r (RSAISR) Hex Address: 0xNB0C .............132

Table 121:: Receive SA Interrupt Enabl e Register (RSAIER) Hex Address: 0xNB0D .............135

Table 122:: Excessive Zero Status Register (EXZSR) Hex Address: 0xNB0E ...........138

Table 123:: Excessive Zero Enable Register (EXZER) Hex Address: 0xNB0F ............139

Table 124:: RxLOS/CRC Interrupt Status Register (RLCISR) Hex Address: 0xNB12 ..............140

Table 125:: RxLOS/CRC Interrupt Enable Register (RLCIER) Hex Address: 0xNB13 .............142

Table 126:: Data Link Status Register 2 (DLSR2) Hex Address: 0xNB16 ..............143

Table 127:: Data Link Interrupt Enable Register 2 (DLIER2) Hex Address: 0xNB17 ...............145

Table 128:: Data Link Status Register 3 (DLSR3) Hex Address: 0xNB26 ..............147

Table 129:: Data Link Interrupt Enable Register 3 (DLIER3) Hex Address: 0xNB27 ..............149

Table 130:: E1 BOC Interrupt Status Register (BOCISR 0xNB70h) .............................................................................151

Table 131:: E1 BOC Interrupt Enable Register (BOCIER 0xNB71h) ............................................................................152

Table 132:: E1 BOC Unstable Interrupt Status Register (BOCUISR 0xNB74h) ................. ... .. .....................................153

Table 133:: E1 BOC Unstable Interrupt Enable Register (BOCUIER 0xNB75h) ..........................................................154

Table 134:: LIU Channel Control Register 0 (LIUCCR0) Hex Address: 0x0FN0 ............155

Table 135:: Equalizer Control and Transmit Line Build Out ...........................................................................................157

Table 136:: LIU Channel Control Register 1 (LIUCCR1) Hex Address: 0x0FN1 ............158

Table 137:: LIU Channel Control Register 2 (LIUCCR2) Hex Address: 0x0x0FN2 ............160

Table 138:: LIU Channel Control Register 3 (LIUCCR3) Hex Address: 0x0FN3 ............162

Table 139:: LIU Channel Contro l Interrupt Enable Register (LIUCCIER) Hex Address: 0x0FN4 ...................164

Table 140:: LIU Channel Contro l Status Register (LIUCCSR) Hex Address: 0x0FN5 ................165

Table 141:: LIU Channel Contro l Interrupt Status Register (LIUCCISR) Hex Address: 0x0FN6 ....................169

Table 142:: LIU Channel Control Cable Loss Register (LIUCCCCR) Hex Address: 0x0FN7 ................171

Table 143:: LIU Channel Control Arbitrary Register 1 (LIUCCAR1) Hex Address: 0x0FN8 ..................171

Table 144:: LIU Channel Control Arbitrary Register 2 (LIUCCAR2) Hex Address: 0x0FN9 ..................172

Table 145:: LIU Channel Control Arbitrary Register 3 (LIUCCAR3) Hex Address: 0x0FNA ...................172

Table 146:: LIU Channel Control Arbitrary Register 4 (LIUCCAR4) Hex Address:0x0FNB ...................172

Table 148:: LIU Channel Control Arbitrary Register 6 (LIUCCAR6) Hex Address: 0x0FND ..................173

Table 149:: LIU Channel Control Arbitrary Register 7 (LIUCCAR7) Hex Address: 0x0FNE ..................173

Table 147:: LIU Channel Control Arbitrary Register 5 (LIUCCAR5) Hex Address: 0x0FNC ..................173

Table 151:: LIU Global Control Register 0 (LIUGCR0) Hex Address: 0x0FE0 ..............174

Table 150:: LIU Channel Control Arbitrary Register 8 (LIUCCAR8) Hex Address:0x0FNF ...................174

Table 152:: LIU Global Control Register 1 (LIUGCR1) Hex Address: 0x0FE1 ..............176

Table 153:: LIU Global Control Register 2 (LIUGCR2) Hex Address: 0x0FE2 ..............177

Table 154:: LIU Global Control Register 3 (LIUGCR3) Hex Address: 0x0FE4 ..............178

Table 155:: LIU Global Control Register 4 (LIUGCR4) Hex Address: 0x0FE9 ..............178

Table 156:: LIU Global Control Register 5 (LIUGCR5) Hex Address: 0x0FEA ..............179

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

DESCRIPTION OF THE CONTROL REGISTERS - E1 MODE

All address on this register descr iption is shown in HEX format.

TABLE 1: REGISTER SUMMARY

FUNCTION SYMBOL HEX

Control Registers (0xN100 - 0xN1FF)

Clock and Select Register CSR 0xN100

Line Interface Control Register LICR 0xN101

General Purpose Input/Output Con trol 0 GPIOCR0 0x0102

General Purpose Input/Output Con trol 1 GPIOCR1 0x4102

Reserved - 0xN103 - 0xN106

Framing Select Register FSR 0xN107

Alarm Generation Register AGR 0xN108

Synchronization MUX Register SMR 0xN109

Transmit Signaling and Data Link Select Register TSDLSR 0xN10A

Framing Control Register FCR 0xN10B

Receive Signaling & Data Link Select Register RSDLSR 0xN10C

Receive Signaling Change Register 0 RSCR0 0xN10D

Receive Signaling Change Register 1 RSCR1 0xN10E

Receive Signaling Change Register 2 RSCR2 0xN10F

Receive Signaling Change Register 3 RSCR3 0xN0xN110

Receive National Bits Register RNBR 0xN111

Receive Extra Bits Register REBR 0xN112

Data Link Control Register 1 DLCR1 0xN113

Transmit Data Link Byte Count Register 1 TDLBCR1 0xN114

Receive Data Link Byte Count Register 1 RDLBCR1 0xN115

Slip Buffer Control Register SBCR 0xN116

FIFO Latency Register FIFOLR 0xN117

DMA 0 (Wri te ) Configurat ion Register D0WCR 0xN118

DMA 1 (Read) Configuration Register D1RCR 0xN119

Interrupt Control Register ICR 0xN11A

LAPD Select Register LAPDSR 0xN11B

Reserved - T1 mode only - 0xN11C

Performance Report Control Register PRCR 0xN11D

Gapped Clock Control Register GCCR 0xN11E

Transmit Interface Control Register TICR 0xN120

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

BERT Control & Status Register 0 BERTCSR0 0xN121

Receive Interface Control Register RICR 0xN122

BERT Control & Status Register 1 BERTCSR1 0xN123

For T1 mode only - 0xN124 - 0xN127

Defect Detection Enable Register DDER 0xN129

Transmit Sa Select Register TSASR 0xN130

Transmit Sa Auto Control Register 1 TSACR1 0xN131

Transmit Sa Auto Control Register 2 TSACR2 0xN132

Transmit Sa4 Register TSA4R 0xN133

Transmit Sa5 Register TSA5R 0xN134

Transmit Sa6 Register TSA6R 0xN135

Transmit Sa7 Register TSA7R 0xN136

Transmit Sa8 Register TSA8R 0xN137

Receive Sa4 Register RSA4R 0xN13B

Receive Sa5 Register RSA5R 0xN13C

Receive Sa6 Register RSA6R 0xN13D

Receive Sa7 Register RSA7R 0xN13E

Receive Sa8 Register RSA8R 0xN13F

Reserved - T1 mode only - 0xN142

Data Link Control Register 2 DLCR2 0xN143

Transmit Data Link Byte Count Register 2 TDLBCR2 0xN144

Receive Data Link Byte Count Register 2 RDLBCR2 0xN145

Data Link Control Register 3 DLCR3 0xN153

Transmit Data Link Byte Count Register 3 TDLBCR3 0xN154

Receive Data Link Byte Count Register 3 RDLBCR3 0xN155

BERT Control Register BCR 0xN163

SSM BOC Control Register BOCCR 0xN170

Receive SSM Register RSSMR 0xN171

Receive SSM Match 1 Register RSSMMR1 0xN172

Receive SSM Match 2 Register RSSMMR2 0xN173

Receive SSM Match 3 Register RSSMMR3 0xN174

Transmit SSM Register TSSMR 0xN175

Transmit SSM Byte Count Register TSSMBCR 0xN176

TABLE 1: REGISTER SUMMARY

FUNCTION SYMBOL HEX

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

Receive FAS Si Register RFASSiR 0xN177

Transmit FAS Si Register TFASSiR 0xN178

Receive DS-0 Monitor Registers RDS0MR 0xN15F - 0xN1CF

Transmit DS-0 Monitor Registers TDS0MR 0xN1D0 - 0xN1EF

Device ID Register DEVID 0x1FE

Revision Number Register REVID 0x1FF

Time Slot (payload) Control (0xN300 - 0xN3FF)

Transmit Channel Control Register 0-31 TCCR 0-31 0xN300 -

0xN31F

User Code Register 0-31 TUCR 0-31 0xN320 -

0xN33F

Transmit Signaling Control Register 0 -31 TSCR 0-31 0xN340 -

0xN35F

Receive Channel Control Register 0-31 RCCR 0-31 0xN360 -

0xN37F

Receive User Code Register 0-31 RUCR 0-31 0xN380 -

0xN39F

Receive Signaling Control Register 0-31 RSCR 0-31 0xN3A0 -

0xN3BF

Receive Substitution Signaling Register 0-31 RSSR 0-31 0xN3C0 -

0xN3DF

Receive Signaling Array (0xN500 - 0xN51F)

Receive Signaling Array Register 0 RSAR0-31 0xN500 -

0xN51F

LAPDn Buffer 0

LAPD Buffer 0 Control Register LAPDBCR0 0xN600 -

0xN660

LAPDn Buffer 1

LAPD Buffer 1 Control Register LAPDBCR1 0xN700 -

0xN760

Performance Monitor

Receive Line Code Violation Counter: MSB RLCVCU 0xN900

Receive Line Code Violation Counter: LSB RLCVCL 0xN901

Receive Frame Alignment Error Counter: MSB RFAECU 0xN902

Receive Frame Alignment Error Counter: LSB RFAECL 0xN903

Receive Severely Errored Frame Counter RSEFC 0xN904

TABLE 1: REGISTER SUMMARY

FUNCTION SYMBOL HEX

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

Receive Synchronization Bit (CRC-6 (T1) CRC-4 (E1) Block) Error

Counter: MSB RSBBECU 0xN905

Receive Synchronization Bit (CRC-6 (T1) CRC-4 (E1) Block) Error

Counter: LSB RSBBECL 0xN906

Receive Far-End Block Error Counter: MSB RFEBECU 0xN907

Receive Far-End Block Error Counter: LSB RFEBECL 0xN908

Receive Slip Counter RSC 0xN909

Receive Loss of Frame Counter RLFC 0xN90A

Receive Change of Frame Alignment Counter RCFAC 0xN90B

LAPD Frame Check Sequence Error counter 1 LFCSEC1 0xN90C

PRBS bit Error Counter: MSB PBECU 0xN90D

PRBS bit Error Counter: LSB PBECL 0xN90E

Transmit Slip Counter TSC 0xN90F

Excessive Zero Violation Counter: MSB EZVCU 0xN910

Excessive Zero Violation Counter: LSB EZVCL 0xN911

LAPD Frame Check Sequence Error counter 2 LFCSEC2 0xN91C

LAPD Frame Check Sequence Error counter 3 LFCSEC3 0xN92C

Interrupt Generation/Enable Register Address Map (0xNB00 - 0xNB41)

Block Interrupt Status R egi ste r BISR 0xNB00

Block Interrupt Enable Register BIER 0xNB01

Alarm & Error Interrupt Status Register AEISR 0xNB02

Alarm & Error Interrupt Enable Register AEIER 0xNB03

Framer Interrupt Status Register FISR 0x NB04

Framer Interrupt Enable Register FIER 0 x NB05

Data Link Status Register 1 DLSR1 0xNB06

Data Link Interrupt Enable Register 1 DLIER1 0xNB07

Slip Buffer Interrupt Status Register SBISR 0xNB08

Slip Buffer Interrupt Enable Register SBIER 0xNB09

Receive Loopback code Interrupt and Status Register RLCISR 0xNB0A

Receive Loopback code Interrupt Enable Register RLCIER 0xNB0B

Receive SA (Sa6) Interrupt Status Register RSAISR 0xNB0C

Receive SA (Sa6) Interrupt Enable Register RSAIER 0xNB0D

Excessive Zero Status Register EXZSR 0xNB0E

Excessive Zero Enable Register EXZER 0xNB0F

TABLE 1: REGISTER SUMMARY

FUNCTION SYMBOL HEX

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

Reserved - T1 mode only - 0xNB10 - 0xNB11

RxLOS/CRC Interrupt Status Register RLCISR 0xNB12

RxLOS/CRC Interrupt Enable Register RLCIER 0xNB13

Data Link Status Register 2 DLSR2 0xNB16

Data Link Interrupt Enable Register 2 DLIER2 0xNB17

Reserved - T1 mode only - 0xNB18 - 0xNB19

Data Link Status Register 3 DLSR3 0xNB26

Data Link Interrupt Enable Register 3 DLIER3 0xNB27

Reserved - T1 mode only - 0xNB28 - 0xNB29

Reserved - T1 mode only CIAIER 0xNB40 - 0xNB41

E1 BOC Interrupt Status Register BOCISR 0xNB70

E1 BOC Interrupt Enable Register BOCIER 0xNB71

Reserved 0xNB72

Reserved 0xNB73

E1 BOC Unstable Interrupt Status Register BOCUSR 0xNB74

E1 BOC Unstable Interrupt Enable Register BOCUER 0xNB75

LIU Register Summary - Channel Control Registers

LIU Channel Control Register 0 LIUCCR0 0x0FN0

LIU Channel Control Register 1 LIUCCR1 0x0FN1

LIU Channel Control Register 2 LIUCCR2 0x0FN2

LIU Channel Control Register 3 LIUCCR3 0x0FN3

LIU Channel Control Interrupt Enable Register LIUCCIER 0x0FN4

LIU Channel Control Status Register LIUCCSR 0x0FN5

LIU Channel Control Interrupt Status Register LIUCCISR 0x0FN6

LIU Channel Control Cable Loss Register LIUCCCCR 0x0FN7

LIU Channel Control Arbitrary Register 1 LIUCCAR1 0x0FN8

LIU Channel Control Arbitrary Register 2 LIUCCAR2 0x0FN9

LIU Channel Control Arbitrary Register 3 LIUCCAR3 00x0FNA

LIU Channel Control Arbitrary Register 4 LIUCCAR4 0x0FNB

LIU Channel Control Arbitrary Register 5 LIUCCAR5 0x0FNC

LIU Channel Control Arbitrary Register 6 LIUCCAR6 0x0FND

LIU Channel Control Arbitrary Register 7 LIUCCAR7 0x0FNE

LIU Channel Control Arbitrary Register 8 LIUCCAR8 0x0FNF

TABLE 1: REGISTER SUMMARY

FUNCTION SYMBOL HEX

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

Reserved -0x0F80 -

0x0FDF

LIU Register Summary - Global Control Registers

LIU Global Control Register 0 LIUGCR0 0x0FE0

LIU Global Control Register 1 LIUGCR1 0x0FE1

LIU Global Control Register 2 LIUGCR2 0x0FE2

LIU Global Control Register 3 LIUGCR3 0x0FE4

LIU Global Control Register 4 LIUGCR4 0x0FE9

LIU Global Control Register 5 LIUGCR5 0 x 0FEA

Reserved -0x0FEB -

0x0FFF

TABLE 1: REGISTER SUMMARY

FUNCTION SYMBOL HEX

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

1.0

2.0 REGISTER DESCRIPTIONS - E1 MODE

All address on this register descr iption is shown in HEX format.

TABLE 2: CLOCK SELECT REGISTER (CSR) HEX ADDRESS: 0XN100

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7LCV Insert R/W 0 Line Code Violation Insertion

This bit is used to force a Line Code Violation (LCV) on the transmit

output of TTIP/TRING.

A “0” to “1” transition on this bit will cause a single LCV to be inserted

on the transmit output of TTIP/TRING.

6 Set T1 Mode R/W 0 T1/E1 Mode select

This bit is used to program the individual channel to operate in either

T1 or E1 mode.

0 = Configures the selected channel to operate in E1 mode .

1 = Configures the selected channel to operate in T 1 mode.

5 Sync All Transmit-

ters to 8kHz R/W 0 Sync All Transmit Framers to 8kHz

This bit permits the user to configure the Transmit E1 Framer block to

synchronize its “transmit output” frame alignment with the 8kHz signal

that is derived from the MCLK PLL, as described below.

0 - Disables the “Sync all Transmit Framers to 8kHz” feature.

1 - Enables the “Sync all Transmit Framers to 8kHz” feature.

NOTE: This bit is only active if the MCLK PLL is used as the “Timing

Source” for the Transmit E1 Framer” blocks. CSS[1:0] of this

framer.

4 Clock Loss Detect R/W 1 Clock Loss Detect Enable /Disable Select

This bit enables a clock loss protection feature for the Framer when-

ever the recovered line clock is used as the timing source for the trans-

mit section. If the LIU loses clock recovery, the Clock Distribution Block

will detect this occurrence and automati cally begin to use the internal

clock derived from MCLK PLL as the Transmit source, until the LIU is

able to regain clock recovery.

0 = Disables the clock loss protection feature.

1 = Enables the clock loss protection feature.

NOTE: This bit needs to be enabled in order to detect the clock loss

detection interrupt status (address: 0xNB00, bit 5)

3:2 Reserved R/W 00 Reserved

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

1:0 CSS[1:0] R/W 01 Clock Source Select

These bits select the timing source for the Transmit E1 Framer block.

These bits can also determine the direction of TxSERC LK, T xSYNC ,

and TxMSYNC in base rate operation mode (2.048MHz Clock mode).

In Base Rate (2.048MHz Clock Mode):

TABLE 2: CLOCK SELECT REGISTER (CSR) HEX ADDRESS: 0XN100

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

NOTE: TxSYNC/TxMSYNC can be programmed as input or output

depending on the setting of SYNC INV bit in Register Ad dress

0xN109, bit 4. Please see Register Description for the

Synchronization Mux Register (SMR - 0xN109).

NOTES: In High-Speed or multiplexed mode s, TxSERCLK, TxSYNC,

and TxMSYNC are all configured as INPUTS only.

CSS[1:0] TRANSMIT SOURCE FOR THE

TRANSMIT E1 FRAMER BLOCK DIRECTION OF

TXSERCLK

00/11 Loop Timing Mode

The recovered line clock is cho-

sen as the timing source.

Output

01 External Timing Mode

The Transmit Serial Input Clock

from the TxSERCLK_n input pin is

chosen as the timing source.

Input

10 Internal Timing Mode

The MCLK PLL is chosen as the

timing source.

Output

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 3: LINE INTERFACE CONTROL REGISTER (LICR) HEX ADDRESS: 0XN101

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7FORCE_LOS R/W 0 Force Transmit LOS (To the Line Side)

This bit permits the user to configure the transmit direction circuitry

(within the channel) to transmit the LOS pattern to the remote terminal

equipment, as described below.

0 - Configures t he tran smit dire ction c ircuitry to tran smit “nor mal” tra f fic.

1 - Configures the transmit direction circuitry to transmit the LOS

Pattern.

6SR R/W 0 Single Rail Mode

This bit can only be set if the LIU Block is also set to single rail mode.

See Register 0xNFE0, bit 7.

0 - Dual Rail

1 - Single Rail

5:4 LB[1:0] R/W 00 Framer Loopback Selection

These bits are used to select any of the following loop-back modes for

the framer section. For LIU loopback modes, see the LIU configuration

registers.

3:2 Reserved R/W 0 Reserved

LB[1:0] TYPES OF LOOPBACK SELECTED

00 Normal Mode (No LoopBack)

01 Framer Local LoopBack:

When framer local loopback is enabled , the transmit

PCM input data is looped back to the receive PCM out-

put data. The receive input data at RTIP/RRING is

ignored while an All Ones Signal is transmitted out to

the line interface.

10 Framer Far-End (Remote) Line LoopBack:

When framer remote loopback is enable d, the digital

data enters the framer interface, however does not

enter the framing blocks. The receive digital data from

the LIU is allowed to pass through the LIU Decoder/

Encoder circuitry before returning to the line interface.

11 Framer Payload LoopBack:

When framer payload loopback is enabled, the raw

data within the receive time slots are looped back to the

transmit framer block where the data is re-framed

according to the transmit timing.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

1 Encode B8ZS R/W 0 Encode AMI or B8ZS/HDB3 Line Code Select

This bit enables or disables the B8ZS/HDB3 enco der on the transmit

path.

0 = Enables the B8ZS encoder.

1 = Disables the B8ZS encoder.

NOTE: When B8ZS encoder is disabled, AMI line code is used.

0 Decode AMI/B8ZS R/W 0 Decode AMI or B8ZS/HDB3 Line Code Select

This bit enables or disables the B8ZS/HDB3 decoder on the receive

path.

0 = Enables the B8ZS decoder.

1 = Disables the B8ZS decoder.

NOTE: When B8ZS decoder is disabled, AMI line code is received.

TABLE 3: LINE INTERFACE CONTROL REGISTER (LICR) HEX ADDRESS: 0XN101

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 4: GENERAL PURPOSE INPUT/OUTPUT 0 CONTROL REGISTER(GPIOCR0) HEX ADDRESS: 0X0102

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-4 GPIO0_3DIR

GPIO0_2DIR

GPIO0_1DIR

GPIO0_0DIR

R/W 1111 GPIO0_3/G PIO0_2/GPIO0_1/GPIO0_0 Direction

These bits permit the user to define the General Purpose I/O Pins,

GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_0 as either Input pins or Output

pins, as described below.

0 – Configures GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_0 to function as

input pins.

1 – Configures GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_0 to function as

output pins.

1. If GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_0 are confi gured to

function as input pins, then the user can monitor th e state of

these input pins by reading out the state of Bit 3-0 (GPIO0_3/

GPIO0_2/GPIO0_1/GPIO0_0) within this register.

2. If GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_0 are configured to

function as output pins, then the user can control the state of

these output pins by writing the appro priate value into Bit 3-0

(GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_0) within this register.

3-0 GPIO0_3

GPIO0_2

GPIO0_1

GPIO0_0

R/W 0000 GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_ 0 Control

The exact function of this bit depends upon whether General Purpose I/

O Pins, GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_ 0 have been configured

to function as input or output pins, as described below.

If GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_0 are configured to function

as input pins:

If GPIO0_3/GPIO0_2/GP IO0_1/GPIO0_0 are config ured to funct ion as

input pins, then the user can mo nitor the state of the corresponding

input pin by reading out the state of these bits.

NOTE: If GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_0 are configured to

function as input pins, the n writin g to this particular register will

have no effect on the state of this pin.

If GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_0 are configured to function

as output pins:

If GPIO0_3/GPIO0_2/GP IO0_1/GPIO0_0 are config ured to funct ion as

output pins, then the user can control the state of the corresponding

output pin by writing the appropriate value to these bits.

NOTE: GPIO0_3/GPIO0_2/GPIO0_1/GPIO0_0 can be configured to

function as input or output pins, by writing the appropriate

value to Bit 7-4 (GPIO0_3DIR/GPIO0_2DIR/GPIO0_1DIR/

GPIO0_0DIR) wi thin this register.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 5: GENERAL PURPOSE INPUT/OUTPUT 1 CONTROL REGISTER(GPIOCR1) HEX ADDRESS: 0X4102

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-4 GPIO1_3DIR

GPIO1_2DIR

GPIO1_1DIR

GPIO1_0DIR

R/W 0000 GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0 Direction

These bits permit the user to define the General Purpose I/O Pins,

GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0 as either Input pins or Output

pins, as described below.

0 – Configures GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0 to function as

input pins.

1 – Configures GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0 to function as

output pins.

1. If GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0 are con fi g ured to

function as input pins, then the user can monitor th e state of

these input pins by reading out the state of Bit 3-0 (GPIO1_3/

GPIO1_2/GPIO1_1/GPIO1_0) within this register.

2. If GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0 are configured to

function as output pins, then the user can control the state of

these output pins by writing the appropriate valu e into Bit 3-0

(GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0) within this register.

3-0 GPIO1_3

GPIO1_2

GPIO1_1

GPIO1_0

R/W 0000 GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_ 0 Control

The exact function of this bit depends upon whether General Purpose I/

O Pins, GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_ 0 have been configured

to function as input or output pins, as described below.

If GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0 are configured to function

as input pins:

If GPIO1_3/GPIO1_2/GP IO1_1/GPIO1_0 are confi gured to fu nction as

input pins, then the user can mo nitor the state of the corresponding

input pin by reading out the state of these bits.

NOTE: If GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0 are configured to

function as input pins, the n writin g to this particular register will

have no effect on the state of this pin.

If GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0 are configured to function

as output pins:

If GPIO1_3/GPIO1_2/GP IO1_1/GPIO1_0 are confi gured to fu nction as

output pins, then the user can control the state of the corresponding

output pin by writing the app ropriate value to these bits.

NOTE: GPIO1_3/GPIO1_2/GPIO1_1/GPIO1_0 can be configured to

function as input or output pins, by writing the appropriate

value to Bit 7-4 (GPIO1_3DIR/GPIO1_2DIR/GPIO1_1DIR/

GPIO1_0DIR) wi thin this register.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

86VX38

TABLE 6: FRAMING SELECT REGISTER (FSR) HEX ADDRESS: 0XN107

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 G.706 Annex B

CRC-4 Calcula-

tion Enable

R/W 0 G.706 Annex B CRC-4 Calculation Enable

This bit con figures the E1 Receive F ramer Block to be compliant with ITU-T

G.706 Annex B for CRC-to-non-CRC interworking detection. If Annex B is

enabled, G.706 Annex B CRC-4 multiframe alignment algorithm is imple-

mented. If CRC-4 alignment is enabled and not achieved in 400msec while

the basic frame alignment signal is present, it is assumed that the remote

end is a non CRC-4 equipment. A CRC-to-Non-CRC interworking interrupt

will be generated. The CRC-to-Non-CRC interworking interrupt Status can

be read from Regist er Ad dre ss 0xN B0 A .

0 - Configures the Receive E1 Framer block to NOT support the “G.706

Annex B” CRC-4 Multiframe Alignment algorithm.

1 - Configures the Receive E1 Framer block to support the “G.706 Annex B”

CRC-4 Multiframe Alignment algorithm.

6 Transmit CRC-4

Error R/W 0 Transmit CRC-4 Error

This bit is used to force a continuous errored CRC pattern in the outbound

CRC multiframe to be sent on the transmissi on line. The Transmit E1

Framer Block will implement this error by inverting the value of CRC bit

(C1).

0 = Disables the Transmit E1 Framer Block to transmit errored CRC bit.

1 = Forces the Transmit E1 Framer Block to transmit continuous errored

CRC bit.

NOTE: This bit is ignored if CRC multi-Framing is disabled.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

5-4 CAS MF Align

Sel[1:0] R/W 00 CAS Multiframe Alignment Declaration Algori th m Select[1:0]

These bits allow the user to select which CAS Multiframe Alignment Decla-

ration algorithm the Receive E1 Framer block will employ, according to the

tab l e be low.

NOTE: For information on the criteria that the Receive E1 Framer block

uses in order to declare the “Loss of CAS Multiframe” defect

condition, please see register description for the Framing Control

TABLE 6: FRAMING SELECT REGISTER (FSR) HEX ADDRESS: 0XN107

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

CAS MF

ALIGN

SEL[1:0]

CAS MULTIFRAME ALIGNMENT DECLARATION ALGORITHM

SELECTED

00/11 CAS Multiframe Alignment is Disabled

01 The “16-Frame” Algorithm

If this alignment algorithm is selected, then the Receive

E1 Framer block will monitor the 16th timeslot of each

incoming E1 frame and will declare CAS Multiframe align-

ment (e.g., clear the Loss of CAS Multiframe” defect) con-

dition; anytime that it detects 15 consecutive E1 frames in

which bits 1 - 4 (of timeslot 16) do not contain the “CAS

Multiframe Alignment” pattern; which is immediately fol-

lowed by an E1 frame that DOES contain the “CAS Multi-

frame Alignment” pattern.

10 The “2-Frame” (ITU-T G.732) Algorithm

If this alignment algorithm is selected, then the Receive

E1 Framer block will monitor the 16th timeslot of each

incoming E1 frame and will declare CAS Multiframe align-

ment (e.g., clear the Loss of CAS Multiframe” defect) con-

dition; anytime that it detects a single E1 frame in which

bits 1 - 4 (of timeslot 16) do not contain the “CAS Multi-

frame Alignment” pattern; which is immediately followed

by an E1 frame that DOES contain the “CAS Multiframe

Alignment” pattern.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3-2 CRC MF Align

Sel[1:0] R/W 00 CRC Multiframe Alignment Declaration Criteria Select [1:0]

These two bits allow the user to select which CRC-Multiframe Alignment

Declaration criteria the Receive E1 Framer block will employ. The Receive

E1 Framer block will check for CRC Multiframe Alignmen t by checking the

incoming E1 data-stream and determining whether the international bits (bit

1 of timeslot 0) of non-FAS frames match the CRC multiframe alignment

pattern (0,0,1,0,1,1,E1,E2). The table below provides more details on the

three different CRC Multiframe Alignment Declaration Criteria.

NOTE: For information on the criteria that the Receive E1 Framer block

uses to declare the “Loss of CRC Multiframe Alignment” defect

condition, please see register description for the Framing Control

1 Additional Frame

Check Enable -

FAS

R/W 0 Additional Frame Check Enab le - FAS Frame Alignment Declaration

This bit permits the user to configure the Receive E1 Framer block to per-

form some “additional FAS frame synchronization checking” prior to declar-

ing “FAS Frame Alignment”. If the user implements this feature, then the

Receive E1 Framer block will perform some more testing on two additional

E1 frames, prior to declaring the “FAS Frame Ali gnment” condition.

0 - Disables this additional FAS frame checking.

1 - Enables this additional FAS frame checking.

TABLE 6: FRAMING SELECT REGISTER (FSR) HEX ADDRESS: 0XN107

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

CRC MF

ALIGN SEL

[1:0]

CRC MULTIFRAME ALIGNMENT DECLARATION CRITERIA

SELECTED

00 CRC Multiframe Alignment is Disabled

01 CRC Multiframe Alignment is Enabled. Alignment is

declared if at least 1 valid CRC multiframe alignment

signal (0,0,1,0,1,1,E1,E2) is observed within 8ms.

10 CRC Multiframe Alignment is Enabled. Alignment is

declared if at least 2 valid CRC multiframe alignment

signals (0,0,1,0,1,1,E1,E2) are observed within 8ms.

11 CRC Multiframe Alignment is Enabled. Alignment is

declared if at least 3 valid CRC multiframe alignment

signals (0,0,1,0,1,1,E1,E2) are observed within 8ms.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

0 FAS Frame Align

Sel R/W 0 FAS Alignment Declaration Algorithm Select

This bit specifies which algorithm the Receive E1 Framer block uses in its

search for the FAS Alignment.

0 = Selects the FAS Alignment Algorithm 1

1 = Selects the FAS Alignment Algorith m 2

FAS Alignment Algorithm 1

If the Receive E1 Framer block has been configured to use “FAS Alignment

Algorithm # 1", then it will acquire FAS alignmen t by performing the follow-

ing three steps:

Step 1 - The Receive E1 Framer block begins by searching for the correct

7-bit FAS pattern. Go to Step 2 if found.

Step 2 - Check if the FAS is absent in the following frame by verifying that

bit 2 of the assumed timeslot 0 of the Non-FAS frame is a one. Go back to

Step 1 if failed, otherwise, go to step 3.

Step 3 - Check if the FAS is present in the assumed timeslot 0 of the third

frame. Go back to Step 1 if failed.

After the first three steps (if they all passed), the Receive E1 Framer Block

will declare F AS in SYNC if Frame Check Sequence (Bit 1 of this register) is

disabled. If Frame Check Sequence (Bit 1 of this register) is enabled, then

the Receive E1 Framer Block will need to verify the correct frame alignment

for an additional two frames.

FAS Alignment Algorithm 2

If the Receive E1 Framer block has been configured to support “FAS Align-

ment Algorithm # 2, then it will perform the following 3 steps in order to

acquire and declare FAS Frame Alignment with the incoming E1 data-

stream. Algorithm 2 is similar to Algorithm 1 but adds a one-frame hold off

time after the second step fails. After the second step fails, it waits for the

next assumed F AS in the next frame before it begins the new search for the

correct FAS pattern.

Step 1 - Algorithm 1 begins by searching for the c orr ect 7-b it FAS patt ern .

Go to Step 2 if found.

Step 2 - Check if the FAS is absent in the following frame by verifying that

bit 2 of the assumed timeslot 0 of the Non-FAS frame is a one. Go back to

Step 4 if failed, otherwise, go to step 3.

Step 3 - Check if the FAS is present in the assumed timeslot 0 of the third

frame. Go back to Step 1 if failed, otherwise, proce ed to check for Frame

Check Sequence.

Step 4 - Wait for assumed FAS in th e next frame, then go back to Step 1

After the first three steps (if they all passed), the Receive E1 Framer Block

will declare F AS in SYNC if Frame Check Sequence (Bit 1 of this register) is

disabled. If Frame Check Sequence (Bit 1 of this register) is enabled, then

the Receive E1 Framer Block will need to verify the correct frame alignment

for an additional two frames.

TABLE 6: FRAMING SELECT REGISTER (FSR) HEX ADDRESS: 0XN107

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 7: ALARM GENERATION REGISTER (AGR) HEX ADDRESS: 0XN108

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Transmit AUXP

Pattern R/W 0 Transmit Auxiliary (AUXP) Pattern

This bit permits the user to command the Transmit E1 Framer block to

transmit the AUXP Pattern to the remote terminal equipment, as depicted

below.

0 - Configures the Transmit E1 Framer block to NOT transmit the AUXP

Pattern (which is an unframed, repeating 1010... pattern).

1 - Configures the Transmit E1 Framer block to transmit the AUXP Pattern.

The device also supports AUXP pattern detection, please read register

(address 0xNB0A) for more detail.

6 Loss of Frame

Declaration Crite-

ria

R/W 0 Loss of Frame Declaration Criteria

This bit permits the user to select the “Loss of Frame Declaration Criteria”

for the Receive E1 Framer block, as depicted below.

0 = Loss of Frame is declared immediately if either CRC Multiframe Align-

ment or FAS Alignment is lost.

1 = Loss of Frame is declared immediately if FAS Alignment is lost. If CRC

Multiframe Alignment is lost for more than 8ms, E1 receive framer will

force a frame search.

5-4 T ransmit YEL And

Multi-YEL[1:0] R/W 00 Yellow Alarm and Multiframe Yellow Alarm Generation [1:0]

These bits activate or deactivate the transmission of yellow and multiframe

yellow alarm. The Yellow alarm and multiframe Yellow alarm can be forced

to transmit as’1’, or be inserted upon detection of loss of alignment. The

decoding of these bits are explained as follows:

YEL[1:0] YELLOW ALARM TRANSMITTED

00/10 Y ellow Alarm and Multiframe Y ellow Alarm transmission

is disabled.

01 Automatic Transmission of Yellow and CAS Multiframe

Yellow Alarms are enabled, as described below:

1. Whenever the Receive E1 Framer block declares the

LOF (Loss of FAS Framing) defe ct condition:

The corresponding Transmit E1 Framer block will automati-

cally transmit the Yellow Alarm indicator (by setting Bit 3 of

Time-Slot 0, within the non-FAS frames) to 1" whenever

(and for the duration that) the Receive E1 Framer block

declares the LOF defect condition.

2. Whenever the Receive E1 Framer block declares the

“Loss of CAS Multiframe Alignment” defect condition:

The corresponding Transmit E1 Framer block will automati-

cally transmit the CAS Multiframe Yellow Alarm indicator (by

setting Bit 6 within “Frame 0" of Time-slot 16) to “1” when-

ever (and for the duration that) the Receive E1 Framer block

declares the Loss of CAS Multiframe Defect condition.

11 Force Transmission of Yellow and Multiframe Yellow

Alarm

Both Yellow and Multiframe Yellow Alarm are transmitted as

‘1’ when this is enabled.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

3-2 Transmit AIS Pat-

tern Select[1:0] R/W 00 Types of AIS Pattern Gene ration Select

These bits permit the user to do the following.

a. To select the type of AIS Pattern that the Transmit E1 Framer block will

transmit.

b. To force (via Software-control) the transmission of the “selected” AIS

Pattern.

NOTE: For “normal” operation, the user should set these bits to “[0, 0]”.

1-0 AIS Defect Decla-

ration Criteria[1:0] R/W 00 AIS Defect Declaration Criteria[1:0]:

These bits permit the user to specify the types of AIS Patterns that the

Receive E1 Framer block must detect before it will declare the AIS defect

condition.

TABLE 7: ALARM GENERATION REGISTER (AGR) HEX ADDRESS: 0XN108

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

AISG[1:0] TYPES OF AIS PATTERN TRANSMITTED

00 Transmission of AIS Indicator is Disabled

The Tr ansmit E1 Framer block will transmit “nor-

mal” E1 traffic to the remote terminal equipment.

01 Unframed AIS alarm

Transmit E1 Framer block will transmit an

Unframed All Ones Pattern, as an AIS Pattern.

10 The AIS-16 Pattern

In this case, Time-slot 16 (within each outbound

E1 frame) will be set to an “All Ones” Pattern.

11 Framed AIS alarm

Transmit E1 Framer block will transmit a Framed

All Ones Pattern, as an AIS Pattern.

AISD[1:0] AIS Defect Declaration Criteria

00 AIS Defect Condition will NOT be declared.

01 Receive E1 Framer block will detect both

Unframed and Framed AIS pattern

10 Receive E1 Framer block will detect AIS16 (Time

Slot 16 AIS) pattern*.

11 Receive E1 Framer block will detect only Framed

AIS pattern

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 8: SYNCHRONIZATION MUX REGISTER (SMR) HEX ADDRESS: 0XN109

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-6 E Bit Source Sel[1:0] R/W 00 Source for E bits [1:0]

These bits permit the user to specify the source of the E-bits, within

each outbound E1 frame, as depicted below.

NOTE: This bit is only active if the Transmit E1 Framer block has

been configured to inte rnally generate an d in sert th e vario us

Framing Alignment bits within the outbo und E1 data-stream.

In other words, whenever the “Framing Alignment Pattern

Source Select” bit (within Bit 0 of this Register) is set to “0”.

5 MSYNC R/W O Transmit CRC Multi Frame Boundary

This bit provides an option to use the transmit single frame boundary

(TxSYNC) as the transmit multi-frame boundary (TxMSYNC) in high

speed or multiplexed modes. In 2.048MHz clock mode (base rate),

the TxMSYNC is used as the transmit CRC Multi frame boundary , in

other clock modes (i.e. high speed or multiplexed modes), TxM-

SYNC is used as an input transmit clock for the backplane interface.

0 = Configures the TxSYNC as a single frame boundary.

1 = Configures the TxSYNC as a CRC Multi frame boundary (TxM-

SYNC) in high-speed or multiplexed mode.

NOTE: This bit is not used in base rate (2.048MHz Clock) mode.

ESRC[1:0] SOURCE FOR E-BITS

00 The corresponding Receive E1 Framer block:

In this case, the E-bits will be used to indicate

whether the Receive E1 Framer block has

detected a CRC error within the most recently

received Sub-Multiframe.

The Receive E1 Framer will indica te a received

errored sub-multiframe by setting the binary state

of E bit from ‘1’ to ‘0’ for each errored sub-multi-

frame.

01 All E bits (within the outbound E1 data-stream) are

set to “0”.

10 All E bits (within the outbound E1 data-stream) are

set to “1”.

11 The ou tgoing E bits will be used to carry data link

information.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

4 Transmit Frame Sync

Select R/W 0 Transmit Frame Sync Select

This bit permits the user to configure the System-Side Terminal

Equipment or the E1 Transmit Framer to dictate whenever the Trans-

mit E1 Framer block will initiate its generation and transmission of

the very next E1 frame. If the system side controls, then all of the fol-

lowing will be true.

1. The corresponding TxSync_n and TxMSync_n pins will function

as input pins.

2. The Transmit E1 Framer block will initiate its generation of a new

E1 frame whenever it samples the corresponding “TxSync_n” inpu t

pin “high” (via the TxSerClk_n input clock signal).

3. The Transmit E1 Framer block will initiate its generation of a new

CRC Multiframe whenever it samples the corresponding

“TxMSync_n” input pin “high”.

This bit can also be used to select the direction of the transmit single

frame boundary (TxSYNC) and multi-frame boundary (TxMSYNC)

depending on whether TxSERCLK is chosen as the timing source for

the transmit section of the framer. (CSS[1:0] = 01 in register 0xN100)

If TxSERCLK is chosen as the timing source:

0 = Configures TxSYNC and TxMSYNC as inputs. (System Side

Controls)

1 = Configures TxSYNC and TxMSYNC as outputs. (Chip Controls)

If either Recovered Line Clock, MCLK PLL is chosen as the tim-

ing source:

0 = Configures TxSYNC and TxMSYNC as outputs. (Chip Controls)

1 = Configures TxSYNC and TxMSYNC as inputs. (System Side

Controls)

NOTE: TxSERCLK is chosen as the transmit clock if CSS[1:0] of the

Clock Select Register (Register Address: 0xN100) is set to

b01. Recovered Clock is chosen as the transmit clock if

CSS[1:0] is set to b00 or b11; Internal Clock is chosen as the

transmit clock if CSS[1:0] is set to b10.

3-2 Data Link Source

Select [1:0] R/W 00 Data Link Source Select

These bits are used to specify the source of the Data Link bits that

will be inserted in the outbound E1 frames. The table below

describes the three different sources from which the Data Link bits

can be inserted .

TABLE 8: SYNCHRONIZATION MUX REGISTER (SMR) HEX ADDRESS: 0XN109

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

DLSRC[1:0] SOURCE OF DATA LINK BITS

00/11 TxSER Input - The transmit serial input from the

transmit payload data input block will be the

source for data link bits

01 Transmit HDLC Controller - The Transmit HDLC

Controller will generate either BOS (Bit Oriented

Signaling) or MOS (Message Oriented Signaling)

messages which will be inserted into the Data Link

bits in the outbound E1frames.

10 TxOH Input - The Transmit Overhead data Input

Port will be the source for the Data Link bits.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

1 CRC-4 Bits Source Sel R/W 0 CRC-4 Bit s Source Select

This bit permits the user to specify the source of the CRC-4 bits,

within the outbound E1 data-stream, as dep icted below.

0 - Configures the Transmit E1 Framer block to internally compute

and insert the CRC-4 bits within the outbound E1 data-stream.

1 - Configures the Transmit E1 Framer block to externally accept

data from the TxSer_n input pin, and to insert this data into the CRC-

4 bits within the outbound E1 data-stream.

NOTE: This bit is ignored if CRC Multiframe Alignment is disabled

0 Framing Alignment Pat-

tern Source Select R/W 0 Framing Alignment Pattern Source Select

This bit permits the user to specify the source of the various “Fram-

ing Alignment” bits (which includes the F AS bit s, the CRC Multiframe

Alignment bits, the E and A bits).

0 - Configures the Transmit E1 Framer block to internally generate

and insert these various framing alignment bits into the outbound E1

data-stream.

1 - Configures the Transmit E1 Framer block to externally accept

data from the TxSer_n input pin, and to insert this data into the FAS,

CRC Multiframe, E and A bits within the outbound E1 data-stream.

NOTE: Users can specify the source for E-bits in register bits 6-7

within this register if Transmit E1 Framer is configured to

internally generate the various framing alignment bits (i.e.

this bit set to’0’).

TABLE 8: SYNCHRONIZATION MUX REGISTER (SMR) HEX ADDRESS: 0XN109

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 9: TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) HEX ADDRESS:0XN10A

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 TxSa8ENB R/W 0 Transmit Sa8 Enable

This bit specifies if the Sa8 bits (bit 7 within timeslot 0 of non-FAS frames) will be

involved in the transmission of Data Link Information.

0 = Sa8 will NOT be used to transport Data Link Information. Sa8 bits will be set to

“1” within the outbound E1 data-stream if the Sa8 bits are inserted fro m the trans-

mit serial input.

1 = Sa8 WILL be used to transport Data Link Information.

NOTE: Sa8 bits can be inserted from either the transmit serial input or register

depending on the Transmit SA Select Register (Register Address:

0xN130) setting. The data link interface uses Sa8 bits for transmission

only if Data Link source is from HDLC controller (DLSRC = b01 from

input (TxSa8SEL = 0 from Register 0xN130).

6 TxSa7ENB R/W 0 Transmit Sa7 Enable

This bit specifies if the Sa7 bits (bit 6 within timeslot 0 of non-FAS frames) will be

involved in the transmission of Data Link Information.

0 = Sa7 will NOT be used to transport Data Link Information. Sa7 bits will be set to

“1” within the outbound E1 data-stream if the Sa7 bits are inserted fro m the trans-

mit serial input.

1 = Sa7 WILL be used to transport Data Link Information.

NOTE: Sa7 bits can be inserted from either the transmit serial input or register

depending on the Transmit SA Select Register (Register Address:

0xN130) setting. The data link interface uses Sa8 bits for transmission

only if Data Link source is from HDLC controller (DLSRC = b01 from

input (TxSa7SEL = 0 from Register 0xN130).

5 TxSa6ENB R/W 0 Transmit Sa6 Enable

This bit specifies if the Sa6 bits (bit 5 within timeslot 0 of non-FAS frames) will be

involved in the transmission of Data Link Information.

0 = Sa6 will NOT be used to transport Data Link Information. Sa6 bits will be set to

“1” within the outbound E1 data-stream if the Sa6 bits are inserted fro m the trans-

mit serial input.

1 = Sa6 WILL be used to transport Data Link Information.

NOTE: Sa6 bits can be inserted from either the transmit serial input or register

depending on the Transmit SA Select Register (Register Address:

0xN130) setting. The data link interface uses Sa6 bits for transmission

only if Data Link source is from HDLC controller (DLSRC = b01 from

input (TxSa6SEL = 0 from Register 0xN130).

4 TxSa5ENB R/W 0 Transmit Sa5 Enable

This bit specifies if the Sa5 bits (bit 4 within timeslot 0 of non-FAS frames) will be

involved in the transmission of Data Link Information.

0 = Sa5 will NOT be used to transport Data Link Information. Sa5 bits will be set to

“1” within the outbound E1 data-stream if the Sa5 bits are inserted fro m the trans-

mit serial input.

1 = Sa5 WILL be used to transport Data Link Information.

Sa5 bits can be inserted from either the transmit serial input or register depending

on the Transmit SA Select Register (Register Address: 0xN130) setting. The data

link interface uses Sa5 bits for transmission only if Data Link source is from HDLC

controller (DLSRC = b01 from Register 0xN109) and if Sa5 bits are inserted from

the transmit serial input (TxSa5SEL = 0 from Register 0xN130).

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3 TxSa4ENB R/W 0 Transmit Sa4 Enable

This bit specifies if the Sa4 bits (bit 3 within timeslot 0 of non-FAS frames) will be

involved in the transmission of Data Link Information.

0 = Sa4 will NOT be used to transport Data Link Information. Sa4 bits will be set to

“1” within the outbound E1 data-stream if the Sa4 bits are inserted from the trans-

mit serial input.

1 = Sa4 WILL be used to transport Data Link Information.

Sa4 bits can be inserted from either the transmit serial input or register depending

on the Transmit SA Select Register (Register Address: 0xN130) setting. The data

link interface uses Sa4 bits for transmission only if Data Link source is from HDLC

controller (DLSRC = b01 from Register 0xN109) and if Sa4 bits are inserted from

the transmit serial input (TxSa5SEL = 0 from Register 0xN130).

TABLE 9: TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) HEX ADDRESS:0XN10A

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

2-0 TxSIGDL[2:0] R/W 000 Transmit Signaling an d Data Link Select[2:0]:

These bits a re used to sp ecify the source for D/E chann el, National Bit s in

timeslot 0 of the non-FAS frames, and Timeslot 16 of the outbound E1

frames. The table below presents the settings of these three bits in detail.

TABLE 9: TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) HEX ADDRESS:0XN10A

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

TXSIGDL

[2:0] SOURCE OF

D/E CHANNEL

SOURCE OF

NATIONAL

BITS

SOURCE OF

TIMESLOT 16

000 TxFrTD_n or

TxSer_n

input pin

Data link TxSer_n inp ut pin

001 TxFrTD_n or

TxSer_n

input pin

Data link CAS signaling is enabled. Time Slot

16 can be inserted from any of the fol-

lowing:

•TxSer_n input pin

•TSCR Register (0xN340-0xN35F)

•TxOH_n input pin on time slot 16

only

•TxSIG_n input pin on every slot

010 TxFrTD_n or

TxSer_n

input pin

Forced to

All Ones TxSER_n input pin or

TxSIG_n input pin on time slot 16 only

011 TxFrTD_ n or

TxSer_n

input pin

Forced to

All Ones CAS signaling is enabled. Time Slot

16 can be inserted from any of the fol-

lowing:

•TxSer_n input pin

•TSCR Register (0xN340-0xN35F)

•TxOH_n input pin on time slot 16

only

•TxSIG_n input pin on every slot

100 TxSIG_n or

TxSer_n

input pin

Data link TxSer_n inp ut pin

101/

110/ Not Used Not Used Not Used

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 10: FRAMING CONTROL REGISTER (FCR) HEX ADDRESS: 0XN10B

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reframe R/W 0 Force Reframe

A ‘0’ to ‘1’ transition will force the Receive E1 Framer to restart the syn-

chronization pr oce ss. This bit field is automatically cleared (set to 0)

after frame synchronization is reached.

6-5 Loss of CAS MF

Align_Sel [1:0] R/W 10 Loss of CAS Multiframe Alignment Defect Declaration Criteria

Select [1:0]

These two bits permit the user to select the “Loss of CAS Multiframe

Alignment” defect declaration criteria. Loss of CAS Multiframe Align-

ment defect is declared based on the number of consecutive CAS mul-

tiframes with Multiframe Alignment signal received in error as indicated

in the table below.

NOTE: These bits are active only if CAS Multiframe Alignment is

enabled.

4-3 Loss of CRC Multi-

frame Align_Sel[1:0] R/W 00 Loss of CRC-4 Multiframe Alignment Defec t Declaration Criteria

Select [1:0]

These two bits permit the user to select the “Loss of CRC-4 Multiframe

Alignment” defect declaration criteria fo r the Channel. The following

table presents the different CRC-4 Multiframe Algorithms in terms of

the number of consecutive erred CRC-4 multiframe alignments that the

E1 Receiver Framer will receive before it declares the “Loss of CRC-4

Multiframe Alignment” defect condition.

NOTE: These bits are only active if CRC Multiframe Alignment is

enabled. If CRC multiframe align ment is not found in 8ms, the

E1 receive framer will restart the synchronization process.

NOTE: TBR-4 standard is enabled by writing to 0xN112, bit 6.

CASC[1:0] LOSS OF CAS MULTIFRAME ALIGNMENT

DECLARATION CRITERIA

00 2 consecutive CAS Multiframes

01 3 consecutive CAS Multiframes

10 4 consecutive CAS Multiframes

11 8 consecutive CAS Multiframes

CRCC[1:0] LOSS OF CRC-4 MULTIFRAME ALIGNMENT

DECLARATION CRITERIA

00 4 consecutive CRC-4 Multiframes Alignment

01 2 consecutive CRC-4 Multiframes Alignment

10 8 consecutive CRC-4 Multiframes Alignment

11 If TBR-4 Standard is Enabled*:

4 consecutive CRC-4 Multiframe Alignment or 915

or more CRC-4 errors

If TBR-4 Standard is Disabled*:

915 or more CRC-4 errors

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

2-0 FASC [2:0] R/W 011 Loss of FAS Alignment Defect Declaration Criteria Select [2:0]

These bits permit the user to specify the Loss of FAS Alignment defect

declaration criteria. The following table presents the different FAS

Alignment Algorithms in terms of the number of consecutive erred FAS

patterns within a multiframe that the E1 Receiver Framer will receive

before it declares the “Loss of FAS Alignment” defect conditions

NOTE: Loss of FAS alignment will force the E1 receive framer to

declare the loss of CAS multiframe alignment and loss of CRC

multiframe alignment.

TABLE 10: FRAMING CONTROL REGISTER (FCR) HEX ADDRESS: 0XN10B

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

FASC[2:0] LOSS OF FAS ALIGNMENT DECLARATION CRITERIA

000 Setting these bits to ‘b000’ is illegal. Do not use

this configuration.

001 1 FAS Alignment pattern

010 2 consecutive FAS Alig nment patterns

011 3 consecutive FAS Alignment patterns

100 4 consecutive FAS Alig nment patterns

101 5 consecutive FAS Alig nment patterns

110 6 consecutive FAS Alignment patterns

111 7 consecutive FAS Alignment patterns

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 11: RECEIVE SIGNALING & DATA LINK SELECT REGISTER (RSDLSR) HEX ADDRESS: 0XN10C

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RxSa8ENB R/W 0 Receive Sa8 Enable

This bit is used to specify whether or not Sa 8 (bit 7 within timeslot 0 of non-F AS

frames) will be used to receive data link informa tion

0 = Sa8 is not used to receive data link information

1 = Sa8 is used to receive data link information

NOTE: This bit is valid only if the RxSIGDL[2:0] = “000”, “001”, or “100”. (The

National bits have been configured to receive data link bits).

6 RxSa7ENB R/W 0 Receive Sa7 Enable

This bit is used to specify whether or not Sa 7 (bit 6 within timeslot 0 of non-F AS

frames) will be used to receive data link informa tion

0 = Sa7 is not used to receive data link information

1 = Sa7 is used to receive data link information

NOTE: This bit is valid only if the RxSIGDL[2:0] = “000”, “001”, or “100”. (The

National bits have been configured to receive data link bits).

5 RxSa6ENB R/W 0 Receive Sa6 Enable

This bit is used to specify whether or not Sa 6 (bit 5 within timeslot 0 of non-F AS

frames) will be used to receive data link informa tion

0 = Sa6 is not used to receive data link information

1 = Sa6 is used to receive data link information

NOTE: This bit is valid only if the RxSIGDL[2:0] = “000”, “001”, or “100”. (The

National bits have been configured to receive data link bits).

4 RxSa5ENB R/W 0 Receive Sa5 Enable

This bit is used to specify whether or not Sa 5 (bit 4 within timeslot 0 of non-F AS

frames) will be used to receive data link informa tion

0 = Sa5 is not used to receive data link information

1 = Sa5 is used to receive data link information

NOTE: This bit is valid only if the RxSIGDL[2:0] = “000”, “001”, or “100”. (The

National bits have been configured to receive data link bits).

3 RxSa4ENB R/W 0 Receive Sa4 Enable

This bit is used to specify whether or not Sa 4 (bit 3 within timeslot 0 of non-F AS

frames) will be used to receive data link informa tion

0 = Sa4 is not used to receive data link information

1 = Sa4 is used to receive data link information

NOTE: This bit is valid only if the RxSIGDL[2:0] = “000”, “001”, or “100”. (The

National bits have been configured to receive data link bits).

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

2-0 RxSIGDL[2:0] R/W 000 Receive Signaling and Datalink Select[2:0]:

These bits specify the destination for the data that is to be extracted via D/E

channel, National Bits in timeslot 0 of the non-FAS frames, and Timeslot 16 in

the outbound frames. The table below presents the settings of these three

RxSIGDL bits in detail.

TABLE 11: RECEIVE SIGNALING & DATA LINK SELECT REGISTER (RSDLSR) HEX ADDRESS: 0XN10C

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

RXSIGDL

[2:0] D/E CHANNEL NATIONAL BITS TIME SLOT 16

000 RxFrTD_n or the

RxSer_n

output pin

Data Link RxSER_n output pin

001 RxFrTD_n or the

RxSer_n

output pin

Data Link CAS signaling is enabled. Time

Slot 16 can be extracte d to any

of the following:

•RxSer_n output pin

•RSAR Register

(0xN500-0xN51F)

•RxOH_n output pin on time

slot 16 only

•RxSIG_n output pin on every

time slot

010 RxFrTD_n or the

RxSer_n

output pin

Dat a Li nk

forced to All

Ones

Time Slot 16 can be extracted

to any of the following:

•RxSer_n output pin

•RSAR Register

(0xN500-0xN51F)

•RxOH_n output pin on time

slot 16 only

•RxSIG_n output pin on time

slot 16 only

011 RxFrTD_n or the

RxSer_n

output pin

Dat a Li nk

forced to All

Ones

CAS signaling is enabled. Time

Slot 16 can be extracte d to any

of the following:

•RxSer_n output pin

•RSAR Register

(0xN500-0xN51F)

•RxOH_n output pin on time

slot 16 only

RxSIG_n output pin on every

time slot

100 RxSIG_n or the

RxSer_n

output pin

Data Link RxSER_n output pin

101/110/

111 Not Used Not Used Not Used

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 12: RECEIVE SIGNALING CHANGE REGISTER 0 (RSCR 0) HEX ADDRESS: 0XN10D

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Ch. 0 RUR 0 These bits indicate whether the Channel Associated signaling data,

associated with Time-Slots 0 through 7 within the incoming E1 data-

stream, has changed since the last read of this registe r, as depicted

below.

0 - CAS data (for Time-slots 0 through 7) has NOT changed since the

last read of this register.

1 - CAS data (for Time-slots 0 through 7) HAS changed since the last

read of this register.

NOTES: 1. Bit 7 (Time-Slot 0) is NOT active, since it carries the F AS and

National Bits.

NOTE: 2. This register is only active if the incoming E1 data-stream is

using Channel Associated Signaling.

6 Ch. 1 RUR 0

5 Ch.2 RUR 0

4 Ch.3 RUR 0

3 Ch.4 RUR 0

2 Ch.5 RUR 0

1 Ch.6 RUR 0

0 Ch.7 RUR 0

TABLE 13: RECEIVE SIGNALING CHANGE REGISTER 1 (RSCR 1) HEX ADDRESS: 0XN10E

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Ch.8 RUR 0 These bits indicate whether the Channel Associated signaling data,

associated with Time-Slots 8 through 15 within the incoming E1 data-

stream, has changed since the last read of this register, as depicted

below.

0 - CAS data (for Time-slots 8 through 15) has NOT changed since the

last read of this register.

1 - CAS data (for Time-slots 8 through 15) HAS changed since the last

read of this register.

NOTE: This register is only active if the incoming E1 data-stream is

using Channel Associated Signaling.

6 Ch.9 RUR 0

5 Ch.10 RUR 0

4 Ch.11 RUR 0

3 Ch.12 RUR 0

2 Ch.13 RUR 0

1 Ch.14 RUR 0

0 Ch.15 RUR 0

TABLE 14: RECEIVE SIGNALING CHANGE REGISTER 2 (RSCR 2) HEX ADDRESS: 0XN10F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Ch.16 RUR 0 These bits indicate whether the Channel Associated signaling data,

associated with Time-Slots 16 through 23 within the incoming E1 data-

stream, has changed since the last read of this register, as depicted

below.

0 - CAS data (for Time-slots 16 through 23) has NOT changed since

the last read of this register.

1 - CAS data (for Time-slots 16 through 23) HAS changed since the

last read of this register.

NOTE: This register is only active if the incoming E1 data-stream is

using Channel Associated Signaling.

6 Ch.17 RUR 0

5 Ch.18 RUR 0

4 Ch.19 RUR 0

3 Ch.20 RUR 0

2 Ch.21 RUR 0

1 Ch.22 RUR 0

0 Ch.23 RUR 0

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 15: RECEIVE SIGNALING CHANGE REGISTER 3 (RSCR 3) HEX ADDRESS: 0XN110

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Ch.24 RUR 0 These bits indicate whether the Channel Associated signaling data,

associated with Time-Slots 24 through 31 within the incoming E1

data-stream, has changed since the last read of this register, as

depicted below.

0 - CAS data (for Time-slots 24 through 31) has NOT changed since

the last read of this register.

1 - CAS data (for Time-slots 24 through 31) HAS changed since the

last read of this register.

NOTE: This register is only active if the incoming E1 data-stream is

using Channel Associated Signaling.

6 Ch.25 RUR 0

5 Ch.26 RUR 0

4 Ch.27 RUR 0

3 Ch.28 RUR 0

2 Ch.29 RUR 0

1 Ch.30 RUR 0

0 Ch.31 RUR 0

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 16: RECEIVE NATIONAL BITS REGISTER (RNBR) HEX ADDRESS: 0XN111

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7Si_FAS RO x Received Internatio nal Bit - FAS Frame

This Read Only bit contains the value of the International Bit (e.g.,

the Si bit) in the most recently received FAS frame.

6 Si_nonFAS RO x Received International Bit - Non FAS Frame

This Read Only bit contains the value of the International Bit (e.g.,

the Si bit) in the most recently received non-FAS frame

5 R_ALARM RO x Received A bit - Non FAS Frame

This Read Only bit contains the value in the Remote Alarm Indication

bit (A bit, or bit 3 of non-F AS frame) within the most recently received

non-FAS frame.

4Sa4 RO x Received National Bits

These Read Only bits contain the values of the National bits (Sa4-

Sa8) within the mo st recently received non-FAS frame.

3Sa5 RO x

2Sa6 RO x

1Sa7 RO x

0Sa8 RO x

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 17: RECEIVE EXTRA BITS REGISTER (REBR) HEX ADDRESS: 0XN112

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7In-Frame RO 0 In Frame State:

This READ-ONLY bit indicates whether the Receive E1 Framer block is

currently decla r i ng th e “In -Frame” conditi o n wi th the incoming E1 data-

stream.

0 - Indicates that the Receive E1 Framer block is currently declaring the

LOF (Loss of Frame) Defect condition.

1 - Indicates that the Receive E1 Framer block is currently declaring itself

to be in the “In-Frame” condition.

6 TBR4_Std R/W 0 TBR4 Standard

Setting this bit will force the XRT86VX38 to be compliant with the TBR-4

standard for “Loss of CRC-4 Multiframe Alignment Criteria”.

0 - Backward compatible with XRT86L38 for Loss of CRC-4 Multiframe

Criteria. When CRCC[1:0] (from register 0xN10B) is set to’11’, Loss of

CRC-4 Multiframe Alignment will declare if 915 or more CRC-4 errors

have been detected in 1 second.

1 - “TBR-4 Compliant” Loss of CRC-4 Multiframe Alignment Criteria -

When CRCC[1:0] (from register 0xN1 0B) is set to’11’, Loss of CRC-4

Multiframe Alignment will declare if 4 consecutive CRC-4 Multiframe

Alignment have been received in error OR if 915 or more CRC-4 errors

have been detected in 1 second.

5 AIS_Ingress R/W 0 AIS Ingress Generation

This bit is used to send an AIS signal (unframed all ones) on the receiver

output RxSER.

0 - Disabled

1 - Rx AIS Ingress Generation Enabled

4 FRAlarmMask R/W 0 Framer Alarm Mask

This bit can be used to mask the alarms associated with the Framing

Mode that is selected. Regardless of the framing mode, this bit will mask

to following alarms: LOF, IF, COFA, COMFA, FE, SE, and FMD. By

default, the alarms are NOT masked.

0 - Disabled

1 - Framing Alarms Masked

3 EX1 RO x Extra Bit 1

This READ ONLY bit field indicates the value of the most recently

received Extra Bit value (bit 5 within timeslot 16 of frame 0 of the signal-

ing multiframe).

NOTE: This bit only has meaning if the framer is using Channel

Associated Signaling.

2 ALARMFE RO x CAS Multi-Frame Yellow Alarm

This READ ONLY bit field indicates the value of the most recently

received CAS Multiframe Yellow Alarm Bit (bit 6 within timeslot 16 of

frame 0 of the signaling multiframe).

0 = Indicates that the E1 receive framer block is NOT receiving the CAS

Multiframe Yellow Alarm.

1 = Indicates that the E1 receive fram er block is currently receivi n g th e

CAS Multiframe Yellow Alarm.

NOTE: This bit only has meaning if the framer is using Channel

Associated Signaling.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

1 EX2 RO x Extra Bit 2

This READ ONLY bit field indicates the value of the most recently

received Extra Bit value (bit 7 within timeslot 16 of frame 0 of the signal-

ing multiframe).

NOTE: This bit only has meaning if the framer is using Channel

Associated Signaling.

0 EX3 RO x Extra Bit 3

This READ ONLY bit field indicates the value of the most recently

received Extra Bit value (bit 8 within timeslot 16 of frame 0 of the signal-

ing multiframe).

NOTE: This bit only has meaning if the framer is using Channel

Associated Signaling.

TABLE 17: RECEIVE EXTRA BITS REGISTER (REBR) HEX ADDRESS: 0XN112

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 18: DATA LINK CONTROL REGISTER (DLCR1) HEX ADDRESS: 0XN113

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved - - Reserved. Please set this bit to’0’ for normal operation.

6 MOS ABORT Disable R/W 0 MOS ABORT Disable:

This bit permits the user to either enable or disable the “Automatic

MOS ABORT” feature within Transmit HDLC Controller # 1. If the

user enables this feature, then Transmit HDLC Controller block # 1

will automatically transmit the ABORT Sequence (e.g., a zero fol-

lowed by a string of 7 consecutive “1s”) whenever it abruptly transi-

tions from transmitting a MOS type of message, to transmitting a

BOS type of message.

If the user disables this feature, then the Transmit HDLC Controller

Block # 1 will NOT transmit the ABORT sequence, whenever it

abruptly transitions from transmitting a MOS-type of message to

transmitting a BOS-type of message.

0 - Enables the “Automatic MOS Abort” feature

1 - Disables the “Automatic MOS Abort” feature

5 Rx_FCS_DIS R/W 0 Receive Frame Check Sequence (FCS) Verification Enable/Dis-

able

This bit permits the user to configure the Receive HDLC Controller

Block # 1 to compute and verify the FCS value within each incoming

LAPD message frame.

0 - Enables FCS Verification

1 - Disables FCS Verification

4 AutoRx R/W 0 Auto Receive LAPD Message

This bit configures the Receive HDLC Controller Block #1 to discard

any incoming BOS or LAPD Message frame that exactly match

which is currently stored in the Receive HDLC1 buffer.

0 = Disables this “AUTO DISCARD” feature

1 = Enables this “AUTO DISCARD” feature.

3 Tx_ABORT R/W 0 Tr ansmit ABORT

This bit configures the Transmit HDLC Controller Block #1 to trans-

mit an ABORT sequence (string of 7 or more consecutive 1’s) to the

Remote terminal.

0 - Configures the Transmit HDLC Controller Block # 1 to function

normally (e.g., not transmit the ABORT sequence).

1 - Configures the Transmit HDLC Controller block # 1 to transmit

the ABORT Sequence.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

2Tx_IDLE R/W 0 Transmit Idle (Flag Sequence Byte)

This bit configures the Transmit HDLC Controller Block #1 to uncon-

ditionally transmit a repeating string of Flag Sequence octets (0X7E)

in the data link channel to the Remote terminal. In normal condi-

tions, the Transmit HDLC Controller block will repeatedly transmit

the Flag Sequence octet whenever there is no MOS messa ge to

transmit to the remote terminal equipment. However, if the user

invokes this “Transmit Idle Sequence” feature, then the Transmit

HDLC Controller block will UNCONDITIONALLY transmit a repeat-

ing stream of the Flag Sequence octet (thereby overwriting all out-

bound MOS data-link messages).

0 - Configures the Transmit HDLC Controller Block # 1 to transmit

data-link information in a “normal” manner.

1 - Configures the Transmit HDLC Controller block # 1 to transmit a

repeating string of Flag Sequence Octets (0x7E).

NOTE: This bit is ignored if the Transmit HDLC1 controller is

operating in the BOS Mode - bit 0 (MOS/BOS) within this

1Tx_FCS_EN R/W 0 Transmit LAPD Message with Frame Check Sequence (FCS)

This bit permits the user to configure the Transmit HDLC Controller

block # 1 to compute and append FCS octets to the “back-end” of

each outbound MOS data-link message.

0 - Configures the Transmit HDLC Controller block # 1 to NOT com-

pute and append the FCS octets to the back-end of each outbound

MOS data-link message.

1 - Configures the Transmit HDLC Controller block # 1 TO COM-

PUTE and append the FCS octets to the back-end of each outbound

MOS data-link message.

NOTE: This bit is ignored if the transmit HDLC1 controller has been

configured to operate in the BOS mode - bit 0 (MOS/BOS)

within this register is set to 0.

0 MOS/BOS R/W 0 Mess age Oriented Signaling/Bit Oriented Signaling Send

This bit permits the user to enable LAPD transmission through

HDLC Controller Block # 1 using either BOS (Bit-Oriented Signaling)

or MOS (Message-Oriented Signaling) frames.

0 - Transmit HDLC Controller block # 1 BOS message Send.

1 - Transmit HDLC Controller block # 1 MOS message Send.

NOTE: This is not an Enable bit. This bit must be set to "0" each time

a BOS is to be sent.

TABLE 18: DATA LINK CONTROL REGISTER (DLCR1) HEX ADDRESS: 0XN113

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 19: TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR1) HEX ADDRESS: 0XN114

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 TxHDLC1 BUFAvail/

BUFSel R/W 0 Transmit HDLC1 Buffer Available/Buffer Select

This bit has different functions, depending upon whether the user is

writing to or reading from this register, as depicted below.

If the user is writing data into this register bit:

0 - Configures the Transmit HDLC1 Controller to read out and trans-

mit the data, residing within “Transmit HDLC1 Buffer # 0", via the

Data Link channel to the remote terminal equipment.

1 - Configures the Transmit HDLC1 Controller to read out and trans-

mit the data, residing within the “Transmit HDLC1 Buf fer #1”, via the

Data Link channel to the remote terminal equipment.

If the user is reading data from this register bit:

0 - Indicates that “Transmit HDLC1 Buffer # 0" is the next available

buffer. In this case, if the user wishes to write in the contents of a

new “outbound” Data Link Message into the Transmit HDLC1 Mes-

sage Buffer, he/she should proceed to write this message into

“Transmit HDLC1 Buffer # 0" - Address location: 0xN600.

1 - Indicates that “Transmit HDLC1 Buffer # 1" is the next available

buffer. In this case, if the user wishes to write in the contents of a

new “outbound” Data Link Message into the Transmit HDLC1 Mes-

sage Buffer, he/she should proceed to write this message into

“Transmit HDLC1 Buffer # 1" - Address location: 0xN700.

NOTE: If one of these Transmit HDLC1 buffers contain a message

which has yet to be completely read-in and processed for

transmission by the Transmit HDLC1 controller, then this bit

will automatically reflect the value corresponding to the next

available buffer when it is read. Changing this bit to the in-

use buffer is not permitted.

6-0 TDLBC[6:0] R/W 0000000 Trans mit HDLC1 Message - Byte Count

The exact function of these bits depends on whether the Transmit

HDLC 1 Controller is configured to transmit MOS or BOS messages

to the Remote Terminal Equipment.

In BOS MODE:

These bit fields contain the number of repetitions the BOS message

must be transmitted before the Transmit HDLC1 controller gener-

ates the Transmit End of Transfer (TxEOT) interru pt and halts trans-

mission. If these fields are set to 00000000, then the BOS message

will be transmitted for an indefinite number of times.

In MOS MODE:

These bit fields contain the length, in number of octets, of the mes-

sage to be transmitted. The length of MOS message specified in

these bits include header bytes such as the SAPI, TEI, Control field,

however, it does not include the FCS bytes.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 20: RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR1) HEX ADDRESS: 0XN115

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RBUFPTR R/W 0 Receive HDLC1 Buffer-Pointer

This bit Identifies which Receive HDLC1 buffer contains the most

recently received HDLC1 messa ge.

0 - Indicates that Receive HDLC1 Buffer # 0 cont ains the contents of

the most recently received HDLC message.

1 - Indicates that Receive HDLC1 Buffer # 1 cont ains the contents of

the most recently received HDLC message.

6-0 RDLBC[6:0] R/W 0000000 Receive HDLC Message - byte count

The exact function of these bits depends on whether the Receive

HDLC Controller Block #1 is configured to receive MOS or BOS

messages.

In BOS Mode:

These seven bits contain the number of repetitions the BOS mes-

sage must be received before the Receive HDLC1 contro ller gener-

ates the Receive End of T ransfer (RxEOT) interrupt. If these bits are

set to “0000000”, the message will be received indefinitely and no

Receive End of Transfer (RxEOT) interrupt will be generated.

In MOS Mode:

These seven bits contain the size in bytes of the HDLC1 message

that has been received and writte n into the Receive HDLC buffer.

The length of MOS message shown in these bits include header

bytes such as the SAPI, TEI, Control field, AND the FCS bytes.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 21: SLIP BUFFER CONTROL REGISTER (SBCR) HEX ADDRESS: 0XN116

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 TxSB_ISFIFO R/W 0 Transmit Slip Buffer Mode

This bit permits the user to configure the Transmit Slip Buffer to function

as either “Slip-Buffer” Mode, or as a “FIFO”, as depicted belo w.

0 - Configures the Transmit Slip Buffer to function as a “Slip-Buffer”.

1 - Configures the Transmit Slip Buffer to fu nction as a “FIFO”.

NOTE: Transmit slip buffer is only used in high-speed or multiplexed mode

where TxSERCLKn must be configured as inputs only. Users

must make sure that the “Transmit Direction” timing (i.e.

TxMSYNC) and the TxSerClk input clock signal are synchronous

to prevent any transmit slips from occurring.

NOTE: The data latency is dictated by FIFO Latency in the FIFO Latency

6-5 Reserved - - Reserved

4 SB_FORCESF R/W 0 Force Signaling Freeze

This bit permits the user to freeze any signaling update on the RxSIGn

output pin as well as the Receive Signaling Array Register -RSAR

(0xN500-0xN51F) until this bit is cleared .

0 = Signaling on RxSIG and RSAR is updated immediately.

1 = Signaling on RxSIG and RSAR is not updated until this bit is set to ‘0’.

3 SB_SFENB R/W 0 Signal Freeze Enable Upon Buffer Slips

This bit enables signaling freeze for one multiframe after the receive buf fer

slips.

If signaling freeze is enabled, th en the “Receive Channel” will freeze all

signaling updates on RxSIG pin and RSAR (0xN500-0xN5 1F) for at le ast

“one-multiframe” period, after a “slip-event” has been detected within the

“Receive Slip Buffer”.

0 = Disables signaling freeze for one multi-frame after receive buffer slips.

1 = Enables signaling freeze for on e multi-frame after receive buffer slips.

2 SB_SDIR R/W 1 Slip Buffer (RxSync) Direction Select

This bit permits user to select the direction of the receive frame boundary

(RxSYNC) signal if the receive buffer is enabled. (i.e. SB_ENB[1:0] = 01 or

10). If slip buffer is bypassed, RxSYNC is always an output pin.

0 = Selects the RxSync signal as an output

1 = Selects the RxSync signal as an input

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

1-0 SB_ENB[1:0] R/W 01 Receive Slip Buffer Mode Select

These bits select modes of operation for the receive slip buffer. These two

bits also select the direction of RxSERCLK and RxSYNC in base clock

rate (2.048MHz). The following table shows the corresponding slip buffer

modes as well as the direction of the RxSYNC/RxSERCLK according to

the setting of these two bits.

NOTE: If the user configures the Receive Slip Buffer to operate in the

“FIFO Mode”, then the user must make sure that the RxSerClk

input pin is synchronized to the Recovered Clock signal for this

particular channel.

TABLE 22: FIFO LATENCY REGISTER (FFOLR) HEX ADDRESS: 0XN117

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-5 Reserved - - Reserved

4-0 Rx Slip Buffer FIFO

Latency[4:0] R/W 00100 Receive Slip Buffer FIFO Latency[4:0]:

These bits permit the user to specify the “Receive Data” Latency (in

terms of RxSerClk_n clock periods), whenever the Receive Slip

Buffer has been configured to operate in the “FIFO” Mode.

NOTE: These bits are only active if the Receive Slip Buffer has been

configured to operate in the FIFO Mode.

TABLE 21: SLIP BUFFER CONTROL REGISTER (SBCR) HEX ADDRESS: 0XN116

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

SB_ENB

[1:0] RECEIVE SLIP BUFFER

MODE SELECT DIRECTION OF

RXSERCLK DIRECTION OF

RXSYNC

00/1 1 Receive Slip Buffer is

bypassed Output Output

01 Slip Buffer Mode Input Depends on the

setting of SB_SDIR

(bit 2 of this register)

If SB_SDIR = 0:

RxSYNC = Output

If SB_SDIR = 1:

RxSYNC = Input

10 FIFO Mode.

FIFO data latency

can be programmed

by the 'FIFO Latency

0xN117).

Input Depends on the

setting of SB_SDIR

(bit 2 of this register)

If SB_SDIR = 0:

RxSYNC = Output

If SB_SDIR = 1:

RxSYNC = Input

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 23: DMA 0 (WRITE) CONFIGURATION REGISTER (D0WCR) HEX ADDRESS: 0XN118

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7DMA0 RST R/W 0 DMA_0 Reset

This bit resets the transmit DMA (Write) channel 0.

0 = Normal operation.

1 = A zero to one transition resets the transmit DMA (Write) channel 0.

6DMA0 ENB R/W 0 DMA_0 Enable

This bit enables the transmit DMA_0 (Write) interface. After a transmit

DMA is enabled, DMA transfers are only requested when the transmit

buffer status bits indicate that there is space for a complete message

or cell.

The DMA write ch an n el is used by the externa l DMA co ntroller to

transfer data from the external memory to the HDLC buffers within the

E1 Framer. The DMA Write cycle starts by E1 Framer asserting the

DMA Request (REQ0) ‘low’, then the external DMA controller should

drive the DMA Acknowledge (ACK0) ‘low’ to indicate that it is ready to

start the transfer. The external DMA controller should place new data

on the Microprocessor data bus each time the Write Signal is Strobed

low if the WR is configured as a Write Strobe. If WR is configured as a

direction signal, then the exte rnal DMA controller would place new

data on the Microprocessor data bus each time the Read Signal (RD)

is Strobed low.

0 = Disables the transmit DMA_0 (Write) interface

1 = Enables the transmit DMA_0 (Write) interface

5 WR TYPE R/W 0 Write Type Select

This bit selects the function of the WR signal.

0 = WR functions as a direction signal (indicates whether the current

bus cycle is a read or write operation) and RD functions as a da ta

strobe signal.

1 =WR functions as a write strobe signal

4 - 3 Reserved - - Reserved

2 DMA0_CHAN(2) R/W 0 Channel Select

These three bits select which T/E1 channel within the XRT86VX38

uses the Transmit DMA_0 (Write) interface.

000 = Channel 0

001 = Reserved

001 = Channel 2

011 = Reserved

1xx = Reserved

1 DMA0_CHAN(1) R/W 0

0 DMA0_CHAN(0) R/W 0

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 24: DM A 1 ( READ) CONFIGURATION REGISTER (D1RCR) HEX ADDRESS: 0XN119

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-6 Reserved - - Reserved

7DMA1 RST R/W 0 DMA_1 Reset

This bit resets the Receive DMA (Read) Channel 1

0 = Normal operation.

1 = A zero to one transition resets the Receive DMA (Read) channel 1.

6DMA1 ENB R/W 0 DMA1_ENB

This bit enables the Receive DMA_1 (Read) interface. After a receive

DMA is enabled, DMA transfers are only requested when the receive

cell buffer contains a complete message or cell.

The DMA read channel is used by the E1 Framer to transfer data from

the HDLC buffers within the E1 Framer to external memory. The DMA

Read cycle starts by E1 Framer asserting the DMA Request (REQ1)

‘low’, then the external DMA controller should drive the DMA Acknowl-

edge (ACK1) ‘low’ to indicate that it is ready to receive the data. The

E1 Framer should place new data on the Microprocessor data bus

each time the Read Signal is Strobed low if the RD is configured as a

Read Strobe. If RD is configured as a direction signal, then the E1

Framer would place new data on the Microprocessor data bus each

time the Write Signal (WR) is Strobed low.

0 = Disables the DMA_1 (Read) interface

1 = Enables the DMA_1 (Read) interface

5 RD TYPE R/W 0 READ Type Select

This bit selects the function of the RD signal.

0 = RD functions as a Read Strobe signal

1 = RD acts as a direction signal (indicates whether the current bus

cycle is a read or write operation), and WR works as a data strobe.

4 - 3 Reserved - - Reserved

2 DMA1_CHAN(2) R/W 0 Ch annel Select

These three bits select which T/E1 channel within the chip uses the

Receive DMA_1 (Read) interface.

000 = Channel 0

001 = Reserved

001 = Channel 2

011 = Reserved

1xx = Reserved

1 DMA1_CHAN(1) R/W 0

0 DMA1_CHAN(0) R/W 0

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 25: INTERRUPT CONTROL REGISTER (ICR) HEX ADDRESS: 0XN11A

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-3 Reserved - - Reserved

2 INT_WC_RUR R/W 0 Interrupt Write-to-Clear or Reset-upon-Read Select

This bit configures all Interrupt Status bits to be either Reset Upon

Read or Write-to-Clear

0 = Configures all Interrupt Status bits to be Reset Upon Read

(RUR).

1= Configures all Interrupt Status bits to be Write-to-Clear (WC).

1 ENBCLR R/W 0 Interrupt Enable Auto Clear

This bit configures all interrupt enable bits to clear or not clear after

reading the i nt errupt statu s bi t.

0= Configures all Interrupt Enable bits to not cleared after reading

the interrupt status bit. The corresponding Interrupt Enable bit will

stay ‘high’ after reading the interrupt status bit.

1= Configures all interrupt Enable bits to clear after reading the

interrupt status bit. The corresponding interrupt enable bit will be set

to ‘low’ after reading the interrupt status bit.

0 INTRUP_ENB R/W 0 Interrupt Enable for Framer_n

This bit enables the entire E1 Framer Block for Interrupt Generation.

0 = Disables the E1 framer block for Interrupt Generation

1 = Enables the E1 framer block for Interrupt Generation

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 26: LAPD SELECT REGISTER (LAPDSR) HEX ADDRESS: 0XN11B

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

[7:5] Reserved - - Reserved

4 HDLC3en R/W 1 HDLC Controller 3 Enable

This bit is used to enable or disable HDLC Controller 3. By default,

the HDLC controller is Enabled, this bit set to "1". If the HDLC con-

troller is disabled while transmitting a message, BOS will disrupt the

transmission and send all ones, MOS will send the flag sequence.

0 - Disabled

1 - Enabled

3 HDLC2en R/W 1 HDLC Controller 2 Enable

This bit is used to enable or disable HDLC Controller 2. By default,

the HDLC controller is Enabled, this bit set to "1". If the HDLC con-

troller is disabled while transmitting a message, BOS will disrupt the

transmission and send all ones, MOS will send the flag sequence.

0 - Disabled

1 - Enabled

2 HDLC1en R/W 1 HDLC Controller 1 Enable

This bit is used to enable or disable HDLC Controller 1. By default,

the HDLC controller is Enabled, this bit set to "1". If the HDLC con-

troller is disabled while transmitting a message, BOS will disrupt the

transmission and send all ones, MOS will send the flag sequence.

0 - Disabled

1 - Enabled

[1:0] HDLC Controller

Select[1:0] R/W 0 HDLC Controller Selec t[1:0]:

These bits permit the user to select any of the three (3) HDLC Con-

trollers that he/she will use within this particular channel, as

depicted below.

00 & 11 - Selects HDLC Controller # 1

01 - Selects HDLC Controller # 2

10 - Selects HDLC Controller # 3

TABLE 27: PERFORMANCE REPORT CONTROL REGISTER (PRCR) HEX ADDRESS: 0XN11D

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved - - For T1 mode only

6 RLOS_OUT_ENB R/W 1 RLOS Output Enable:

This bit is used to enable or disable the Receive LOS (RLOS_n) out-

put pins. When this bit is set "Low", the RLOS_n pin will be tri-stated

for all conditions. When this bit is set "High", the RLOS_n pin will

pull "High" during a LOS condition and pull "Low" when data is

present on RTIP/RRING.

0 - Disables the RLOS output pin.

1 - Enables the RLOS output pin.

5-0 Reserved - - Reserved.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 28: GAPPED CLOCK CONTROL REGISTER (GCCR) HEX ADDRESS: 0XN11E

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 FrOutclk R/W 0 Framer Output Clock Reference

This bit is used to enable or disable high-speed T1/E1 rate on the

T1OSCCLK and the E1OSCCLK output pins.

By default, the output clock reference on T1OSC CLK and

E1OSCCLK output pins is 1.544MHz/2.048MHz respectively. By set-

ting this bit to a “1”, the output clock reference on the T1OSCLK and

the E1OSCCLK is 49.408MHz/65.536MHz for T1/E1 respectively.

0 = Disables high-speed rate to be output on th e T1OSCCLK and

E1OSCCLK output pins. St andard T1/E1 Rate - 1.544MHz/2.048Mhz

will be output to the T1OSCCLK and E1OSCCLK output pins respec-

tively.

1 = Enables high-speed rate to be output on the T1OSCCLK and

E1OSCCLK output pins.

6-0 Reserved - - Reserved

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 29: TRANSMIT INTERFACE CONTROL REGISTER (TICR) HEX ADDRESS:0XN120

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 TxSyncFrD R/W 0 Transmit Synchronous frac tion data interface

This bit selects whether TxCHCLK or TxSERCLK will be used for frac-

tional data input if the transmit fractional interface is enabled. If TxSER-

CLK is selected to clock in fractional data input, TxCHCLK will be used

as an enable signal

0 = Fractional data Is clocked into the chip using T xChCLK if the trans-

mit fractional data interface is enabled.

1 = Fractional data is clocked into the chip using TxSerClk if the trans-

mit fractional data interface is enabled. TxChClk is used as fractional

data enable.

NOTE: The Time Slot Identifier Pins (TxChn[4:0]) still indicates the time

slot number if the transmit fractional data interface is not

enabled. Fractional Interface can be enabled by setting

TxFr2048 to 1

6 Reserved - - Reserved

5 TxPLClkEnb R/W 0 Transmit payload clock enable

This bit configures the E1 framer to output a regular clock or a payload

clock on the transmit serial clock (TxSERCLK) pin when TxSERCLK is

configured to be an output.

0 = Configures the framer to output a 2.048MHz clock on the TxSER-

CLK pin when TxSERCLK is configured as an output.

1 = Configures the framer to output a 2.048MHz clock on the TxSER-

CLK pin when transmitting payload bits. There will be gaps on the

TxSERCLK output pin when transmitting overhead bits.

4 TxFr2048 R/W 0 Transmit Fractional/Signaling Interface Enabled

This bit is used to enable or disable the transmit fractional data inter-

face, signaling input, as well as the 32MHz transmit clock and the trans-

mit overhead Signal output. This bit only functions when the device is

configured in non-high speed or multiplexed modes of operations.

If the device is configured in base rate:

0 = Configures the 5 time slot identifier pins (TxChn[4:0]) to output the

channel number as usual.

1 = Configures the 5 time slot identifier pins (TxChn[4:0]) into the follow-

ing different functions:

TxChn[0] becomes the Transmit Serial SIgnaling pin (TxSIG_n) for sig-

naling inputs. Signaling data can now be input from the TxSIG pin if

configured appropriately.

TxChn[1] becomes the Transmit Fractional Data Input pin (TxFrTD_n)

for fractional data input. Fractional data can now be input from the

TxFrTD pin if configured appropriately.

TxChn[2] becomes the 32 MHz transmit clock output

TxChn[3] becomes the Transmit Overhead Signal which pulses high on

the first bit of each multi-frame.

NOTE: This bit has no function in the high speed or multiplexed modes

of operation. In high-speed or multiplexed modes, TxCHN[0]

functions as TxSIGn for signaling input.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

3 TxICLKINV R/W 0 Trans mit Clock Inversion (Backplane Interface)

This bit selects whether data transition will happen on the rising or fall-

ing edge of the transmit clock.

0 = Selects data transition happen on the rising edge of the transmit

clocks.

1 = Selects data transition happen on the falling edge of the transmit

clocks.

NOTE: This feature is only available for base rate configuration (i.e.

non-highspeed, or non-multiplexed modes).

2 TxMUXEN R/W 0 Transmit Multiplexed Mode Enable

This bit enables or disables the multiplexed mode on the transmit side.

When multiplexed mode is enable, four-cha nnel data from the back-

plane interface are multiplexed onto one serial stream and output to the

line side. The backplane speed will be running at 16.384MHz once mul-

tiplexed mode is enabled.

0 = Disables the multiplexed mode.

1 = Enables the multiplexed mode.

TABLE 29: TRANSMIT INTERFACE CONTROL REGISTER (TICR) HEX ADDRESS:0XN120

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

1 TxIMODE[1] R/W 0 Transmit Inter fa ce Mode selection

This bit determines the transmit interface speed. The exact function of

these two bits depends on whether Multiplexed mode is enabled or dis-

abled. Table 30 and Table 31shows the functions of these bits for non-

multiplexed and multiplexed modes.:

0 TxIMODE[0] R/W 0

TABLE 29: TRANSMIT INTERFACE CONTROL REGISTER (TICR) HEX ADDRESS:0XN120

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

TABLE 30: TRANSMIT INTERFACE SPEED WHEN MULTIPLEXED MODE

IS DISABLED (TXMUXEN = 0)

TXIMODE[1:0] TRANSMIT INTERFACE SPEED

00 2.048Mbit/s. (Base Rate)

Transmit Backplane interface signals include:

TxSERCLK is an input or output clock at

2.048MHz

TxMSYNC is the superframe boundary at 2ms

TxSYNC is the single frame boundary at 125 us

TxSER is the base-rate data input

01 2.048Mbit/ (High-speed MVIP Mod e)

Transmit Backplane interface signals include:

TxSERCLK is an input clock at 2.048MHz

TxMSYNC will become the high speed input clock

at 2.048MHz to input high-speed data

TxSYNC indicates the single frame bounda ry

TxSER is the high-speed data input

10 4.096Mbit/s High-speed mode:

Transmit Backplane interface signals include:

TxSERCLK is an input clock at 2.048MHz

TxMSYNC will become the high speed input clock

at 4.096MHz to input high-speed data

TxSYNC indicates the single frame bounda ry

TxSER is the high-speed data input

11 8.192Mbit/s High-speed mode:

Transmit Backplane interface signals include:

TxSERCLK is an input clock at 2.048MHz

TxMSYNC will become the high speed input clock

at 8.192MHz to input high-speed data

TxSYNC indicates the single frame bounda ry

TxSER is the high-speed data input

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

1-0 TxIMODE[1:0] R/W 0 (Continued):

Transmit Backplane interface signals include:

TxSERCLK is an input clock at 2.048MHz

TxMSYNC will become the high speed input clock at 16.384MHz to

input high-speed multiplexed data on the back-plane interface

TxSYNC is the single multiplexed frame boundary

TxSER is the high-speed data input

NOTE: In high speed mode, transmit data is sampled on the rising edge

of the 16MHz clock edge.

TABLE 29: TRANSMIT INTERFACE CONTROL REGISTER (TICR) HEX ADDRESS:0XN120

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

TABLE 31: TRANSMIT INTERFACE SPEED WHEN MULTIPLEXED MODE

IS ENABLED (TXMUXEN = 1)

TXIMODE[1:0] TRANSMIT INTERFACE SPEED

00 Reserved

01 Reserved

10 HMVIP High-Speed Multiplexed Mode Enabled:

Transmit interface is taking four-channel multi-

plexed data at a rate of 16.384Mbit/s from channel

0 and byte-demultiplexing the serial data into 4

channels and output to the line on channels 0

through 3. The TxSYNC signal pulses “High” during

the last two bits of the previous E1 frame and the

first two bits of the current E1 frame.

11 H.100 High-Speed Multiplexed Mode Enabled:

Transmit interface is taking four-channel multi-

plexed data at a rate of 16.384Mbit/s from channel

0 and byte-demultiplexing the serial data into 4

channels and output to the line on channels 0

through 3. The TxSYNC signal pulses “High” during

the last bit of the previous E1 frame and the first bit

of the current E1 frame.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 32: PRBS CONTROL AND STATUS REGISTER 0 (PRBSCSR0) HEX ADDRESS: 0XN121

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-4 Reserved - - These bits are not used

3 BERT_Switch R/W 0 BERT Switch

This bit enables or disables the BERT switch function within the

XRT86VX38 device.

By enabling the BERT switch function, BERT functionality will be

switched between the receive and transmit framer. E1 Receive

framer will generate the BERT pattern and insert it onto the receive

backplane interface, and E1 Transmit Framer will be monitoring the

transmit backplane interface for BERT pattern and declare BERT

LOCK if BERT has locked onto the input pattern.

If BERT switch is disabled, E1 Tr ansmit framer will generate the

BERT pattern to the line interface and the receive framer will be

monitoring the line for BERT pattern and declare BERT LOCK if

BERT has locked onto the input pattern.

0 = Disables the BERT Switch Feature.

1 = Enables the BERT Switch Feature.

2 BER[1] R/W 0 Bit Error Rate

This bit is used to insert BERT bit error at the rates presented at the

table below . The exact function of this bit depends on whether BERT

switch function is enabled or not. (bit 3 within this register).

If the BERT switch function is disabled, bit error will be inserted by

the E1 transmit framer out to the line interface if this bit is enabled.

If the BERT switch function is enabled, bit error will be inserted by

the E1 receive framer out to the receive backplane interface if this

bit is enabled.

1 BER[0] R/W 0

BER[1:0] BIT ERROR RATE

00 Disable Bit Error insertion to the transmi t outpu t

or receive backplane interface

01 Bit Error is inserted to the transmit output or

receive backplane inte rface at a rate of 1/1000

(one out of one Thousand)

10 Bit Error is inserted to the transmit output or

receive backplane inte rface at a rate of 1/

1,000,000 (one out of one million)

11 Disable Bit Error insertion to the transmit output

or receive backplane interface

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

0 UnFramedBERT R/W 0 Unframe d BERT Pattern

This bit enables or disables unframed BERT pattern generation (i.e.

All timeslots and framing bits are all BERT dat a). The exact function

of this bit depends on whether BERT switch function is enabled or

not. (bit 3 within this register).

If BERT switch function is disabled, E1 T ransmit Framer will gener-

ate an unframed BERT pattern to the line side if this bit is enabled.

If PRBS switch function is enabled, E1 Receive Framer will gener-

ate an unframed BERT pattern to the receive backplane interface if

this bit is enabled.

0 - Disables an unframed BERT pattern generation

1 - Enables an unframed BERT pattern generation

TABLE 32: PRBS CONTROL AND STATUS REGISTER 0 (PRBSCSR0) HEX ADDRESS: 0XN121

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 33: RECEIVE INTERFACE CONTROL REGISTER (RICR) HEX ADDRESS: 0XN122

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RxSyncFrD R/W 0 Reserved

6 Reserved - - Reserved

5 RxPLClkEnb R/W 0 Receive payload clock enable

This bit configures the E1 framer to either output a regular clock or a payload

clock on the receive serial clock (RxSERCLK) pin when RxSERCLK is config-

ured to be an output.

0 = Configures the framer to output a 2.048MHz clock on the RxSERCLK pin

when RxSERCLK is configured as an output.

1 = Configures the framer to output a 2.048MHz clock on the RxSERCLK pin

when receiving payload bits. There will be gaps on the RxSERCLK output pin

when receiving overhead bits.

4 RxFr2048 R/W 0 Receive Fractional/Signaling Interface Enabled

This bit is used to enable or disable the receive signaling output and the

received recovered clock output. This bit only functions when the device is

configured in non-high speed or multiplexed modes of operations.

If the device is configured in base rate:

0 = Disabled

1 = Enabled

RxSIG_n for signaling outputs. Signaling data can now be output to the RxSIG

pin if configured appropriately.

RxSCLK outputs the received recovered clock signal (1.544MHz for T1)

NOTE: This bit has no effect in the high speed or multiplexed modes of

operation. In high-speed or multiplexed modes, RxSIG outputs the

Signaling data and RxSCLK outputs the recovered clock.

3 RxICLKINV N/A 0 Receive Clock Inversion (Backplane Interface)

This bit selects whether data transition will happen on the rising or falling edge

of the receive clock.

0 = Selects data transition happen on the rising edge of the receive clocks.

1 = Selects data transition happen on the falling edge of the receive clocks.

NOTE: This feature is only available for base rate configuration (i.e. non-

highspeed, or non-multiplexed modes).

2 RxMUXEN R/W 0 Receive Multiplexed Mode Enable

This bit enables or disables the multiplexed mode on the receive side. When

multiplexed mode is enable, four channels data from the line side are multi-

plexed onto one serial stream and output to the back-plane interface on

RxSER. The backplane speed will become 16.384MHz once multiplexed

mode is enabled.

0 = Disables the multiplexed mode.

1 = Enables the multiplexed mode.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

1 RxIMODE[1] R/W 0 Receive Interface Mode Selection

This bit determines the receive interface speed. The exact fun c tion of these

two bits depends on whether Receive Multiplexed mode is enabled or dis-

abled. Table 34 and Table 35 shows the functions of these two bits for non-

multiplexed and multiplexed modes.:

0 RxIMODE[0] R/W 0

TABLE 33: RECEIVE INTERFACE CONTROL REGISTER (RICR) HEX ADDRESS: 0XN122

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

TABLE 34: RECEIVE INTERFACE SPEED WHEN MULTIPLEXED MODE IS

DISABLED (TXMUXEN = 0)

RXIMODE[1:0] RECEIVE INTERFACE SPEED

00 2.048Mbit/s. (Base Rate Mode)

Receive backplane interface signals include:

RxSERCLK is an input or output clock at 2.048MHz

RxSYNC is an input or output signal which indicates the

receive singe frame boundary

RxSER is the base-rate data output

01 2.048Mbit/s (High-speed MVIP Mode)

Receive Backplane Interface signals include:

RxSERCLK is an input clock at 2.048MHz

RxSYNC is an input signal which indicates the receive

singe frame boundary

RxSER is the high-speed data output

10 4.096Mbit/s High-speed Mode:

Receive Backplane Interface signals include:

RxSERCLK is an input clock at 4.096MHz

RxSYNC is an input signal which indicates the receive

singe frame boundary

RxSER is the high-speed data output

11 8.192Mbit/s High-speed Mode:

Receive Backplane Interface signals include:

RxSERCLK is an input clock at 8.192MHz

RxSYNC is an input signal which indicates the receive

singe frame boundary

RxSER is the high-speed data output

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

1-0 RxIMODE R/W 0 (Continued):

Receive Backplane Interface signals include:

RxSERCLK is an input clock at 16.384MHz

RxSYNC is an input signal which indicates the multiplexed frame boundary.

The length of RxSYNC depends on the multiplexed mode selected .

RxSER is the high-speed data output

NOTE: In high speed mode, receive data is clocked out on the rising edge of

the 16MHz clock edge.

TABLE 33: RECEIVE INTERFACE CONTROL REGISTER (RICR) HEX ADDRESS: 0XN122

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

TABLE 35: RECEIVE INTERFACE SPEED WHEN MULTIPLEXED MODE IS

ENABLED (TXMUXEN = 1)

TXIMODE[1:0] TRANSMIT INTERFACE SPEED

00 Reserved

01 Reserved

10 HMVIP High-Speed Multiplexed Mode:

Receive interface is taking data from the four LIU input

channels 0 through 3 and byte-multiplexing the four-

channel data into one 16.384MHz serial stream and out-

put to channel 0 of the Receive Serial Outp ut (RxSER).

The RxSYNC signal pulses “High” during the last two

bits of the previous E1 frame and the first two bits of the

current E1 frame.

11 H.100 High-Speed Multiplexed Mode:

Receive interface is taking data from the four LIU input

channels 0 through 3 and byte-multiplexing the four-

channel data into one 16.384MHz serial stream and out-

put to channel 0 of the Receive Serial Outp ut (RxSER).

The RxSYNC signal pulses “High” during the last bit of

the previous E1 frame and the first bit of the current E1

frame.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 36: PRBS CONTROL AND STATUS REGISTER 1 (PRBSCSR1) HEX ADDRESS: 0XN123

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 PRBSTyp R/W 0 PRBS Pattern Type

This bit selects the type of PRBS pattern that the E1 Transmit/

Receive framer will generate or detect. PRBS 15 (X 15 + X14 +1)

Polynomial or QRTS (Quasi-Random Test Signal) Pattern can be

generated by the transmit or receive framer depending on whether

PRBS switch function is enabled or not (bit 3 in register 0xN121).

If the PRBS Switch function is disabled, E1 transmit framer will gen-

erate either PRBS 15 or QRTS pattern and output to the line inter-

face. PRBS 15 or QRTS pattern depends on the setting of this bit.

If the PRBS Switch function is enabled, E1 receive framer will gen-

erate either PRBS 15 or QRTS pattern and output to the receive

back plane interface. PRBS 15 or QRTS pattern depends on the

setting of this bit.

0 = Enables the PRBS 15 (X15 + X14 +1) Polynomial generation.

1 = Enables the QRTS (Quasi-Random Test Signal) pattern genera-

tion.

6 ERRORIns R/W 0 Error Insertion

This bit is used to insert a single BERT error to the transmit or

receive output depending on wheth er BERT switch function is

enabled or not. (bit 3 in register 0xN121).

If the BERT Switch function is disabled, E1 transmit framer will

insert a single BERT error and output to the line interface if this bit is

enabled.

If the BERT Switch function is enabled, E1 receive framer will insert

a single BERT error and output to the receive back plane interface if

this bit is enabled.

A ‘0’ to ‘1’ transition will cause one output bit inverted in the BERT

stream.

NOTE: This bit only works if BERT generation is enab led.

5DATAInv R/W 0 BERT Data Invert:

This bit inverts the Transmit BERT output data and the Receive

BERT input data. The exact function of this bit depends on whether

BERT switch function is enabled or not. (bit 3 in register 0xN121).

If the BERT Switch function is disabled and if this bit is enabled, E1

transmit framer will invert the BERT data before it outputs to the line

interface, and the E1 receive framer will invert the incoming BERT

data before it receives it.

If the BERT Switch function and this bit are both enabled, E1 receive

framer will invert the BERT data before it outputs to the line inter-

face, and the E1 transmit framer will invert the incoming BERT data

before it receives it.

0 - Transmit and Receive Framer will NOT invert the Transmit and

Receive BERT data.

1 - Transmit and Receive Framer will invert the Transmit and

Receive BERT data.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

4 RxBERTLock RO 0 Lock Status

This bit indicates whether or not the Receive or Transmit BER T lock

has obtained. The exact function of this bit depends on whether

BERT switch function is enabled or not. (bit 3 in register 0xN121).

If the BERT Switch function is disabled, E1 receive framer will

declare LOCK if BERT has locked onto the input pattern.

If the BERT Switch function is disabled, E1 transmit framer will

declare LOCK if BERT has locked onto the input pattern.

0 = Indicates the Receive BERT has not Locked onto the input pat-

terns.

1 = Indicates the Receive BERT has locked onto the input patterns.

3 RxBERTEnb R/W 0 Receive BERT Detection/Generation Enable

This bit enables or disables the receive BERT pattern detection or

generation. The exact function of this bit depends on whether BERT

switch function is enabled or not. (bit 3 in register 0xN121).

If the BERT switch function is disabled and if this bit is enabled, E1

Receive Framer will detect the incoming BERT pattern from the line

side and declare BERT lock if incoming data locks onto the BERT

pattern.

If the BERT switch function and this bit are both enabled, E1 Trans-

mit Framer will detect the incoming BERT pattern from the transmit

backplane interface and declare BERT lock if incoming data locks

onto the BERT pattern.

0 = Disables the Receive BERT pattern detection.

1 = Enables the Receive BERT pattern detection.

2TxBERTEnb R/W 0 Transmit BERT Generation Enable

This bit enables or disables the Transmit BERT pattern generator.

The exact function of this bit depends on whether BERT switch func-

tion is enabled or not. (bit 3 in register 0xN121).

If BERT switch function is disabled, E1 T ransmit Framer will gener-

ate the BERT pattern to the line side if this bit is enabled.

If BERT switch function is enabled, E1 Receive Framer will generate

the BERT pattern to the receive backplane interface if this bit is

enabled.

0 = Disables the Transmit BERT pattern generator.

1 = Enables the Transmit BERT pattern generator.

1 RxBypass R/W 0 Receive Frame r Bypass

This bit enables or disables the Receive E1 Framer bypass.

0 = Disables the Receive E1 framer Bypass.

1 - Enables the Receive E1 Framer Bypass

0 TxBypass R/W 0 Transmit Framer Bypass

This bit enables or disables the Transmit E1 Framer bypass.

0 = Disables the Transmit E1 framer Bypass.

1 - Enables the Transmit E1 Framer Bypass

TABLE 36: PRBS CONTROL AND STATUS REGISTER 1 (PRBSCSR1) HEX ADDRESS: 0XN123

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 37: LOOPBACK CODE CONTROL REGISTER (LCCR) HEX ADDRESS: 0XN124

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 Reserved - - For T1 mode only

TABLE 38: TRANSMIT LOOPBACK CODER REGISTER (TLCR) HEX ADDRESS: 0XN125

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 Reserved - - For T1 mode only

TABLE 39: RECEIVE LOOPBACK ACTIVATION CODE REGISTER (RLACR) HEX ADDRESS:

0XN126

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 Reserved For T1 mode only

TABLE 40: RECEIVE LOOPBACK DEACTIVATION CODE REGISTER (RLDCR) HEX ADDRESS: 0XN127

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 Reserved For T1 mode only

TABLE 41: DEFECT DETECTION ENABLE REGISTER (DDER) HEX ADDRESS: 0XN129

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 DEFDET R/W 1 For defect detection per ANSI T1.231-1997 and T1.403-1999, user

should leave this bit set to ‘1’.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 42: TRANSMIT Sa SELECT REGISTER (TSASR) HEX ADDRESS: 0XN130

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 TxSa8SEL R/W 0 Transmit Sa8 bit select

This bit determines whether National Bit (Sa8) is inserted from the

transmit serial input (TxSER_n) pin or from the Transmit Sa8 regis-

ter (Register address = 0xN137).

0 = Selects Sa 8 to be inserted from the Transmit Serial input

(TxSER_n) input pin.

1 = Selects Sa 8 to be inserted from the Transmit Sa8 Reg ister

(Register address = 0xN137)

6 TxSa7SEL R/W 0 Transmit Sa7 bit select

This bit determines whether National Bit (Sa7) is inserted from the

transmit serial input (TxSER_n) pin or from the Transmit Sa7 regis-

ter (Register address = 0xN136).

0 = Selects Sa 7 to be inserted from the Transmit Serial input

(TxSER_n) input pin.

1 = Selects Sa 7 to be inserted from the Transmit Sa7 Reg ister

(Register address = 0xN136)

5 TxSa6SEL R/W 0 Transmit Sa6 bit select

This bit determines whether National Bit (Sa6) is inserted from the

transmit serial input (TxSER_n) pin or from the Transmit Sa6 regis-

ter (Register address = 0xN135).

0 = Selects Sa 6 to be inserted from the Transmit Serial input

(TxSER_n) input pin.

1 = Selects Sa 6 to be inserted from the Transmit Sa6 Reg ister

(Register address = 0xN135)

4 TxSa5SEL R/W 0 Transmit Sa5bit select

This bit determines whether National Bit (Sa5) is inserted from the

transmit serial input (TxSER_n) pin or from the Transmit Sa5 regis-

ter (Register address = 0xN134).

0 = Selects Sa 5 to be inserted from the Transmit Serial input

(TxSER_n) input pin.

1 = Selects Sa 5 to be inserted from the Transmit Sa5 Reg ister

(Register address = 0xN134)

3 TxSa4SEL R/W 0 Transmit Sa4 bit select

This bit determines whether National Bit (Sa4) is inserted from the

transmit serial input (TxSER_n) pin or from the Transmit Sa4 regis-

ter (Register address = 0xN133).

0 = Selects Sa 4 to be inserted from the Transmit Serial input

(TxSER_n) input pin.

1 = Selects Sa 4 to be inserted from the Transmit Sa4 Reg ister

(Register address = 0xN133)

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

2 LB1ENB R/W 0 Local L oopback 1 auto enable

This bit enables or disables local loopback mode when the National

bits (Sa5, Sa6) and the A bit (remote alarm bit) received from the

transmit backplane interface follows a specific pattern.

Local loopback is activated when the National Bits (Sa5, Sa 6) and

A bit (remot e alarm bi t) follow t he following pattern from the transmit

serial input. (TxSER_n pin)

Sa5 = 00000000 occur for 8 consecutive times

Sa6 = 11111111 occur for 8 consecutive times

A = 11111111 occur for 8 consecutive times

NOTE: This feature only works if Sa bits are provided from the

transmit serial input pin (TxSER_n)

1 LB2ENB R/W 0 Local L oopback 2 auto enable

This bit enables or disables local loopback mode when the National

bits (Sa5, Sa6) received from the transmit backplane interface fol-

lows a specific pattern.

Local loopback is activated when the National Bits (Sa5, Sa 6) and

A bit (remot e alarm bi t) follow t he following pattern from the transmit

serial input. (TxSER_n pin)

Sa5 = 00000000 occur for 8 consecutive times, and

Sa6 = 10101010 occur for 8 consecutive times, and

A = 11111111 occur for 8 consecutive times

NOTE: This feature only works if Sa bits are provided from the

transmit serial input pin (TxSER_n)

0 LBRENB R/W 0 Local Loopback release enable

This bit releases the local loopback mode when the National bits

(Sa5, Sa6) received from the transmit backplane interface follows a

specific pattern .

Local loopback is released when the National Bits (Sa5, Sa 6) follow

the following pattern from the transmit serial input. (TxSER_n pin)

Sa5 = 00000000 occur for 8 consecutive times

Sa6 = 00000000 occur for 8 consecutive times

NOTE: This feature only works if Sa bits are provided from the

transmit serial input pin (TxSER_n)

TABLE 42: TRANSMIT Sa SELECT REGISTER (TSASR) HEX ADDRESS: 0XN130

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 43: TRANSMIT Sa AUTO CONTROL REGISTER 1 (TSACR1) HEX ADDRESS: 0XN131

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 LOSLFA_1_ENB R/W 0 LOS/LFA 1 automatic transmission

This bit enables the automatic Sa-bit transmission upon detecting

Loss of Signal (LOS) or Loss of frame alignment (LFA) condition.

Upon detecting Loss of Signal or Loss of Frame alignment condi-

tion, E1 framer will transmit the Sa5 bit as ‘1’, and Sa6 bit as ‘0’ pat-

tern.

See Table 44 for the transmit Sa5, Sa6, and A bit pattern upon

detecting LOS or LFA conditions.

6 LOS_1_ENB R/W 0 L OS 1 au tomatic transmission

This bit enables the auto Sa-bit transmission upon detecting Loss of

Signal (LOS) condition.

Upon detecting Loss of Signal condition, E1 framer will transmit the

Alarm bit (A bit) as ‘1’, Sa5 bit as ‘1’, and Sa6 bit as ‘1110’ pattern.

See Table 44 for the transmit Sa5, Sa6, and A bit pattern upon

detecting LOS condition .

5 LOSLFA_2_ENB R/W 0 LOS/LFA 2 automatic transmission

This bit enables the auto Sa-bit transmission upon detecting Loss of

Signal (LOS) or Loss of frame alignment (LFA) condition.

Upon detecting Loss of Signal or Loss of Frame alignment condi-

tion, E1 framer will transmit the Alarm bit (A bit) as ‘1’, Sa5 bit as ‘0’,

and Sa6 bit as ‘0’ pattern.

See Table 44 for the transmit Sa5, Sa6, and A bit pattern upon

detecting LOS or LFA conditions.

4 LOSLFA_3_ENB R/W 0 LOS/LFA 3 automatic transmission

This bit enables the auto Sa-bit transmission upon detecting Loss of

Signal (LOS) or Loss of frame alignment (LFA) condition.

Upon detecting Loss of Signal or Loss of Frame alignment condi-

tion, E1 framer will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit as ‘1’,

and Sa6 bit as ‘1100’ pattern.

See Table 44 for the transmit Sa5, Sa6, and A bit pattern upon

detecting LOS/LFA conditions.

3 LOSLFA_4_ENB R/W 0 LOS/LFA 4 automatic transmission

This bit enables the auto Sa-bit transmission upon detecting Loss of

Signal (LOS) or Loss of frame alignment (LFA) condition.

Upon detecting Loss of Signal or Loss of Frame alignment condi-

tion, E1 framer will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit as ‘1’,

and Sa6 bit as ‘1110’ pattern.

See Table 44 for the transmit Sa5, Sa6, and A bit pattern upon

detecting LOS/LFA conditions.

2 NOP_ENB R/W 0 Reserved

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

The following table demonstrates the conditions on the receive side which trigger the Automatic Sa, and A bit

transmission when TSACR1 bits are enabled.

1 NOP_LOSLFA_ENB R/W 0 Reserved

0 LOS_2_ENB R/W 0 L OS 3 auto matic tran smission

This bit enables the auto Sa-bit transmission upon detecting Loss of

Signal (LOS) condition.

Upon detecting Loss of Signal condition, E1 framer will transmit the

Sa5 and Sa6 bit as an Auxiliary (10101010...) pattern

See Table 44 for the transmit Sa5, Sa6, and A bit format upon

detecting LOS condition.

TABLE 44: CONDITIONS ON RECEIVE SIDE WHEN TSACR1 BITS ARE ENABLED

CONDITIONS ACTIONS - SENDING PATTERN COMMENTS

A SA5 SA6

LOSLFA_1_ENB: Loss of signal or Loss of

frame alignment X 1 0000 LOS/LFA at TE (FC2)

LOS_1_ENB: Loss of signal 1 1 1110 LOS (FC3)

LOSLFA_2_ENB: LOS or LFA 1 0 0000 LOS/LFA (FCL)

LOSLFA_3_ENB: LOS or LFA 0 1 1100 LOS/LFA (FC4)

LOSLFA_4_ENB: LOS or LFA 0 1 1110 LOS/LFA (FC3&FC4)

NOP_ENB: Loss of power 0 1 1000 Loss of power at NT1

NOP_LOSLFA_ENB: Loss of power and LOS

or LFA 1 1 1000 Loss of power and LOS/LF A

LOS_2_ENB: LOS AUXP pattern LOS (FC1). Transmit AUXP pattern

TABLE 43: TRANSMIT Sa AUTO CONTROL REGISTER 1 (TSACR1) HEX ADDRESS: 0XN131

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 45: TRANSMIT Sa AUTO CONTROL REGISTER 2 (TSACR2) HEX ADDRESS: 0XN132

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 AIS_1_ENB R/W 0 AIS reception

This bit enables the automatic Sa-bit transmission upon detecting

AIS condition.

Upon detectin g the AIS condition, E1 framer will transmit the Alar m

bit (A bit) as ‘1’, Sa5 bit as ‘1’, and Sa6 bit as ‘1’.

See Table 46 for the transmit Sa5, Sa6, and A bit pattern upon

detecting AIS condition.

6 AIS_2_ENB R/W 0 AIS reception

This bit enables the automatic Sa-bit transmission upon detecting

AIS condition.

Upon detectin g the AIS condition, E1 framer will transmit the Alar m

bit (A bit) as ‘0’, Sa5 bit as ‘1’, and Sa6 bit as ‘1’.

See Table 46 for the transmit Sa5, Sa6, and A bit pattern upon

detecting AIS condition.

5 Reserved - - Reserved

4 Reserved - - Reserved

3 CRCREP_ENB[1] R/W 0 CRC report

These two bits enable the automatic Sa-bit transmission upon

detecting Far End Block Error (i.e. received E bit = 0).

Upon detecting the Far End Block Error (FEBE) condition, E1 framer

will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit as ‘1’, Sa6 bit as

‘0000’, and E bit as ‘0’ pattern if these two bits are set to ‘01’.

If these two bits are set to ‘10’, E1 framer will transmit the Alarm bit

(A bit) as ‘0’, Sa5 bit as ‘0’, Sa6 bit as ‘0000’, and E bit as ‘0’ pattern

upon detecting the Far End Block Error (FEBE).

If these two bits are set to ‘11’, E1 framer will transmit the Alarm bit

(A bit) as ‘0’, Sa5 bit as ‘1’, Sa6 bit as ‘0001’, and E bit as ‘1’ pattern

upon detecting the Far End Block Error (FEBE).

See Table 46 for the transmit Sa5, Sa6, E, and A bit pattern upon

detecting FEBE condition.

2 CRCREP_ENB[0] R/W 0

1 CRCDET_ENB R/W 0 CRC detection

This bit enables the automatic Sa-bit transmission upon detecting

CRC-4 error condition.

Upon detecting CRC-4 error condition, E1 framer will transmit the

Alarm bit (A bit) as ‘0’, Sa5 bit as ‘1’, Sa6 bit as ‘0010’, and E bit as

‘1’ pattern.

See Table 46 for the transmit Sa5, Sa6, E, and A bit pattern upon

detecting CRC-4 error condition.

0 CRCREC AND

DET_ENB R/W 0 CRC report and detect

This bit enables automatic Sa-bit transmission upon detecting both

Far End Block Error (FEBE) and CRC-4 error conditions.

Upon detecting both Far End Block Error (FEBE) and CRC-4 error

condition, E1 framer will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit

as ‘1’, Sa6 bit as ‘0011’, and E bit as ‘1’ pattern.

See Table 46 for the transmit Sa5, Sa6, E, and A bit pattern upon

detecting both FEBE and CRC-4 error conditions.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

The following table demonstrates the conditions on receive side which trigger the Automatic Sa, E, and A bits

transmission when TSACR2 bits are enabled.

TABLE 46: CONDITIONS ON RECEIVE SIDE WHEN TSACR2 BITS ENABLED

CONDITIONS ACTIONS - SENDING PATTERN FOR

ASA5SA6E

AIS_1_ENB 1 1 1111 X

AIS_2_ENB 0 1 1111 x

CRCREP_ENB = 01, CRC reported (E = 0) 0 1 0000 0

CRCREP_ENB = 10, CRC reported 0 0 0000 0

CRCREP_ENB = 11, CRC reported 0 1 0001 1

CRCDET_ENB 0 1 0010 1

CRCDET/REP_ENB 0 1 0011 1

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 47: TRANSMIT Sa4 REGISTER (TSA4R) HEX ADDRESS: 0XN133

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 TxSa4[7:0] R/W 11111111 Transmit Sa4 Sequence

The content of this register sources the transmit Sa4 bits if data link

selects Sa 4 bit for transmission and if Sa4 is inserted from register.

(i.e. TxSa4ENB bit in register 0xN10A = 1 and TxSa 4SEL bit in reg-

ister 0xN130 = 1).

Bit 7 of this register is transmitted in the Sa4 position in frame 2 of

the CRC-4 multiframe, and bit 6 of this register is transmitted in the

Sa4 position in frame 4 of the CRC-4 multiframe,...etc.

TABLE 48: TRANSMIT Sa5 REGISTER (TSA5R) HEX ADDRESS: 0XN134

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 TxSa5[7:0] R/W 11111111 Transmit Sa5 Sequence

The content of this register sources the transmit Sa5 bits if data link

selects Sa 5 bit for transmission and if Sa5 is inserted from register.

(i.e. TxSa5ENB bit in register 0xN10A = 1 and TxSa 5SEL bit in reg-

ister 0xN130 = 1).

Bit 7 of this register is transmitted in the Sa5 position in frame 2 of

the CRC-4 multiframe, and bit 6 of this register is transmitted in the

Sa5 position in frame 4 of the CRC-4 multiframe,...etc.

TABLE 49: TRANSMIT Sa6 REGISTER (TSA6R) HEX ADDRESS: 0XN135

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 TxSa6[7:0] R/W 11111111 Transmit Sa6 Sequence

The content of this register sources the transmit Sa6 bits if data link

selects Sa 6 bit for transmission and if Sa6 is inserted from register.

(i.e. TxSa6ENB bit in register 0xN10A = 1 and TxSa 6SEL bit in reg-

ister 0xN130 = 1).

Bit 7 of this register is transmitted in the Sa6 position in frame 2 of

the CRC-4 multiframe, and bit 6 of this register is transmitted in the

Sa6 position in frame 4 of the CRC-4 multiframe,...etc.

TABLE 50: TRANSMIT Sa7 REGISTER (TSA7R) HEX ADDRESS: 0XN136

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 TxSa7[7:0] R/W 11111111 Transmit Sa7 Sequence

The content of this register sources the transmit Sa7 bits if data link

selects Sa 7 bit for transmission and if Sa7 is inserted from register.

(i.e. TxSa7ENB bit in register 0xN10A = 1 and TxSa 7SEL bit in reg-

ister 0xN130 = 1).

Bit 7 of this register is transmitted in the Sa7 position in frame 2 of

the CRC-4 multiframe, and bit 6 of this register is transmitted in the

Sa7 position in frame 4 of the CRC-4 multiframe,...etc.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 51: TRANSMIT Sa8 REGISTER (TSA8R) HEX ADDRESS: 0XN137

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 TxSa8[7:0] R/W 11111111 Transmit Sa8 Sequence

The content of this register sources the transmit Sa8 bits when data

link selects Sa 8 bit for transmission and if Sa8 is inserted from reg-

ister.

(i.e. TxSa8ENB bit in register 0xN10A = 1 and TxSa 8SEL bit in reg-

ister 0xN130 = 1).

Bit 7 of this register is transmitted in the Sa8 position in frame 2 of

the CRC-4 multiframe, and bit 6 of this register is transmitted in the

Sa8 position in frame 4 of the CRC-4 multiframe,...etc.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 52: RECEIVE SA4 REGISTER (RSA4R) HEX ADDRESS: 0XN13B

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 RxSa4[7:0] RO 00000000 Received Sa4 Sequence

The content of this register stores the Sa 4 bits in the most recently

received CRC-4 multiframe. This register is updated when the entire

multiframe is received.

This register will show the contents of the received Sa4 bits if data

link selects Sa4 bit for reception. (i.e.RxSa4ENB bit in register

0xN10Ch = 1).

Bit 7 of this register indicates the received Sa4 bit in frame 2 of the

CRC-4 multiframe, and bit 6 of this register indicates the received

Sa4 bit in frame 4 of the CRC-4 multiframe,...etc.

TABLE 53: RECEIVE SA5 REGISTER (RSA5R) HEX ADDRESS: 0XN13C

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 RxSa5[7:0] RO 00000000 Received Sa5 Sequence

The content of this register stores the Sa 5 bits in the most recently

received CRC-4 multiframe. This register is updated when the entire

multiframe is received.

This register will show the contents of the received Sa5 bits if data

link selects Sa5 bit for reception. (i.e.RxSa5ENB bit in register

0xN10Ch = 1).

Bit 7 of this register indicates the received Sa5 bit in frame 2 of the

CRC-4 multiframe, and bit 6 of this register indicates the received

Sa5 bit in frame 4 of the CRC-4 multiframe,...etc.

TABLE 54: RECEIVE SA6 REGISTER (RSA6R) HEX ADDRESS: 0XN13D

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 RxSa6[7:0] RO 00000000 Received Sa6 Sequence

The content of this register stores the Sa 6 bits in the most recently

received CRC-4 multiframe. This register is updated when the entire

multiframe is received.

This register will show the contents of the received Sa6 bits if data

link selects Sa6 bit for reception. (i.e.RxSa6ENB bit in register

0xN10Ch = 1).

Bit 7 of this register indicates the received Sa6 bit in frame 2 of the

CRC-4 multiframe, and bit 6 of this register indicates the received

Sa6 bit in frame 4 of the CRC-4 multiframe,...etc.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 55: RECEIVE SA7 REGISTER (RSA7R) HEX ADDRESS: 0XN13E

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 RxSa7[7:0] RO 00000000 Received Sa7 Sequence

The content of this register stores the Sa 7 bits in the most recently

received CRC-4 multiframe. This register is updated when the entire

multiframe is received.

This register will show the contents of the received Sa7 bits if data

link selects Sa7 bit for reception. (i.e.RxSa7ENB bit in register

0xN10Ch = 1).

Bit 7 of this register indicates the received Sa7 bit in frame 2 of the

CRC-4 multiframe, and bit 6 of this register indicates the received

Sa7 bit in frame 4 of the CRC-4 multiframe,...etc.

TABLE 56: RECEIVE SA8 REGISTER (RSA8R) HEX ADDRESS: 0XN13F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 RxSa8[7:0] RO 00000000 Received Sa8 Sequence

The content of this register stores the Sa 8 bits in the most recently

received CRC-4 multiframe. This register is updated when the entire

multiframe is received.

This register will show the contents of the received Sa8 bits if data

link selects Sa8 bit for reception. (i.e.RxSa8ENB bit in register

0xN10Ch = 1).

Bit 7 of this register indicates the received Sa8 bit in frame 2 of the

CRC-4 multiframe, and bit 6 of this register indicates the received

Sa8 bit in frame 4 of the CRC-4 multiframe,...etc.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 57: DATA LINK CONTROL REGISTER (DLCR2) HEX ADDRESS: 0XN143

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved - - Reserved. Please set this bit to’0’ for normal operation.

6 MOS ABORT Disable R/W 0 MOS ABORT Disable:

This bit permits the user to either enable or disable the “Automatic

MOS ABORT” feature within Transmit HDLC Controller # 2. If the

user enables this feature, then Transmit HDLC Controller block # 2

will automatically transmit the ABORT Sequence (e.g., a zero fol-

lowed by a string of 7 consecutive “1s”) whenever it abruptly transi-

tions from transmitting a MOS type of message, to transmitting a

BOS type of message.

If the user disables this feature, then the Transmit HDLC Controller

Block # 2 will NOT transmit the ABORT sequence, whenever it

abruptly transitions from transmitting a MOS-type of message to

transmitting a BOS-type of message.

0 - Enables the “Automatic MOS Abort” feature

1 - Disables the “Automatic MOS Abort” feature

5 Rx_FCS_DIS R/W 0 Receive Frame Check Sequence (FCS) Verification Enable/Dis-

able

This bit permits the user to configure the Receive HDLC Controller

Block # 2 to compute and verify the FCS value within each incoming

LAPD message frame.

0 - Enables FCS Verification

1 - Disables FCS Verification

4 AutoRx R/W 0 Auto Receive LAPD Message

This bit configures the Receive HDLC Controller Block #2 to discard

any incoming BOS or LAPD Message frame that exactly match

which is currently stored in the Receive HDLC2 buffer.

0 = Disables this “AUTO DISCARD” feature

1 = Enables this “AUTO DISCARD” feature.

3 Tx_ABORT R/W 0 Transmit ABORT

This bit configures the Transmit HDLC Controller Block #2 to trans-

mit an ABORT sequence (string of 7 or more consecutive 1’s) to the

Remote terminal.

0 - Configures the Transmit HDLC Controller Block # 2 to function

normally (e.g., not transmit the ABORT sequence).

1 - Configures the Transmit HDLC Controller block # 2 to transmit

the ABORT Sequence.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

2Tx_IDLE R/W 0 Transmit Idle (Flag Sequence Byte)

This bit configures the Transmit HDLC Controller Block #2 to uncon-

ditionally transmit a repeating string of Flag Sequence octets (0X7E)

in the data link channel to the Remote terminal. In normal condi-

tions, the Transmit HDLC Controller block will repeatedly transmit

the Flag Sequence octet whenever there is no MOS message to

transmit to the remote terminal equipment. However, if the user

invokes this “Transmit Idle Sequence” feature, then the Transmit

HDLC Controller block will UNCONDITIONALLY transmit a repeat-

ing stream of the Flag Sequence octet (thereby overwriting all out-

bound MOS data-link messages).

0 - Configures the Transmit HDLC Controller Block # 2 to transmit

data-link information in a “normal” manner.

1 - Configures the Transmit HDLC Controller block # 2 to transmit a

repeating string of Flag Sequence Octets (0x7E).

NOTE: This bit is ignored if the Transmit HDLC2 controller is

operating in the BOS Mode - bit 0 (MOS/BOS) within this

1Tx_FCS_EN R/W 0 Transmit LAPD Message with Frame Check Sequ ence (FCS)

This bit permits the user to configure the Transmit HDLC Controller

block # 2 to compute and append FCS octets to the “back-end” of

each outbound MOS data-link message.

0 - Configures the Transmit HDLC Controller block # 2 to NOT com-

pute and append the FCS octets to the back-end of each outbound

MOS data-link message.

1 - Configures the Transmit HDLC Controller block # 2 TO COM-

PUTE and append the FCS octets to the back-end of each outbound

MOS data-link message.

NOTE: This bit is ignored if the transmit HD LC2 controlle r has been

configured to operate in the BOS mode - bit 0 (MOS/BOS)

within this register is set to 0.

0 MOS/BOS R/W 0 Mess age Oriented Signaling/Bit Oriented Signaling Send

This bit permits the user to enable LAPD transmission through

HDLC Controller Block # 2 using either BOS (Bit-Oriented Signaling)

or MOS (Message-Oriented Signaling) frames.

0 - Transmit HDLC Controller block # 2 BOS message Send.

1 - Transmit HDLC Controller block # 2 MOS message Send.

NOTE: This is not an Enable bit. This bit must be set to "0" each

time a BOS is to be sent.

TABLE 57: DATA LINK CONTROL REGISTER (DLCR2) HEX ADDRESS: 0XN143

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 58: TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR2) HEX ADDRESS: 0XN144

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 TxHDLC2 BUFAvail/

BUFSel R/W 0 Transmit HDLC2 Buffer Available/Buffer Select

This bit has different functions, depending upon whether the user is

writing to or reading from this register, as depicted below.

If the user is writing data into this register bit:

0 - Configures the Transmit HDLC2 Controller to read out and trans-

mit the data, residing within “Transmit HDLC2 Buffer # 0", via the

Data Link channel to the remote terminal equipment.

1 - Configures the Transmit HDLC2 Controller to read out and trans-

mit the data, residing within the “Transmit HDLC2 Buf fer #1”, via the

Data Link channel to the remote terminal equipment.

If the user is reading data from this register bit:

0 - Indicates that “Transmit HDLC2 Buffer # 0" is the next available

buffer. In this case, if the user wishes to write in the contents of a

new “outbound” Data Link Message into the Transmit HDLC2 Mes-

sage Buffer, he/she should proceed to write this message into

“Transmit HDLC2 Buffer # 0" - Address location: 0xN600.

1 - Indicates that “Transmit HDLC2 Buffer # 1" is the next available

buffer. In this case, if the user wishes to write in the contents of a

new “outbound” Data Link Message into the Transmit HDLC2 Mes-

sage Buffer, he/she should proceed to write this message into

“Transmit HDLC2 Buffer # 1" - Address location: 0xN700.

NOTE: If one of these Transmit HDLC2 buffers contain a message

which has yet to be completely read-in and processed for

transmission by the Transmit HDLC2 controller, then this bit

will automatically reflect the value corresponding to the next

available buffer when it is read. Changing this bit to the in-

use buffer is not permitted.

6-0 TDLBC[6:0] R/W 0000000 Tran smit HDLC2 Message - Byte Count

The exact function of these bits depends on whether the Transmit

HDLC 2 Controller is configured to transmit MOS or BOS messages

to the Remote Terminal Equipment.

In BOS MODE:

These bit fields contain the number of repetitions the BOS message

must be transmitted before the Transmit HDLC2 controller gener-

ates the Transmit End of Transfer (TxEOT) interru pt and halt s trans-

mission. If these fields are set to 00000000, then the BOS message

will be transmitted for an indefinite number of times.

In MOS MODE:

These bit fields contain the length, in number of octets, of the mes-

sage to be transmitted. The length of MOS message specified in

these bits include header bytes such as the SAPI, TEI, Control field,

however, it does not include the FCS bytes.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 59: RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR2) HEX ADDRESS: 0XN145

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RBUFPTR R/W 0 Receive HDLC2 Buffer-Pointer

This bit Identifies which Receive HDLC2 buffer contains the most

recently received HDLC2 messa ge.

0 - Indicates that Receive HDLC2 Buffer # 0 contains the contents of

the most recently received HDLC message.

1 - Indicates that Receive HDLC2 Buffer # 1 contains the contents of

the most recently received HDLC message.

6-0 RDLBC[6:0] R/W 0000000 Receive HDLC Message - byte count

The exact function of these bits depends on whether the Receive

HDLC Controller Block #2 is configured to receive MOS or BOS

messages.

In BOS Mode:

These seven bits contain the number of repetitions the BOS mes-

sage must be received before the Receive HDLC2 contro ller gener-

ates the Receive End of T ransfer (RxEOT) interrupt. If these bits are

set to “0000000”, the message will be received indefinitely and no

Receive End of Transfer (RxEOT) interrupt will be generated.

In MOS Mode:

These seven bits contain the size in bytes of the HDLC2 message

that has been received and writte n into the Receive HDLC buffer.

The length of MOS message shown in these bits include header

bytes such as the SAPI, TEI, Control field, AND the FCS bytes.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 60: DATA LINK CONTROL REGISTER (DLCR3) HEX ADDRESS: 0XN153

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved - - Reserved. Please set this bit to’0’ for normal operation.

6 MOS ABORT

Disable R/W 0 MOS ABORT Disable:

This bit permits the user to either enable or disable the “Automatic MOS

ABORT” feature within T ransmit HDLC Controller # 3. If the user enables this

feature, then Transmit HDLC Controller block # 3 will automatically transmit

the ABORT Sequence (e.g., a zero followed by a string of 7 consecutive

“1s”) whenever it abruptly transitions from transmitting a MOS type of mes-

sage, to transmitting a BOS type of message.

If the user disables this feature, then the T ransmit HDLC Controller Block # 3

will NOT transmit the ABORT sequence, whenever it abruptly transitions

from transmitting a MOS-type of message to transmitting a BOS-type of

message.

0 - Enables the “Automatic MOS Abort” feature

1 - Disables the “Automatic MOS Abort” feature

5 Rx_FCS_DIS R/W 0 Receive Frame Check Sequence (FCS) Verification Enable/Disable

This bit permits the user to configure the Receive HDLC Controller Block # 3

to compute and verify the FCS value within each incoming LAPD message

frame.

0 - Enables FCS Verification

1 - Disables FCS Verification

4 AutoRx R/W 0 Auto Receive LAPD Message

This bit configures the Receive HDLC Controller Block #3 to discard any

incoming BOS or LAPD Message frame that exactly match which is currently

stored in the Receive HDLC1 buffer.

0 = Disables this “AUTO DISCARD” feature

1 = Enables this “AUTO DISCARD” feature.

3 Tx_ABORT R/W 0 Transmit ABORT

This bit configures the Transmit HDLC Controller Block #3 to transmit an

ABORT sequence (string of 7 or more consecutive 1’s) to the Remote termi-

nal.

0 - Configures the Transmit HDLC Controller Block # 3 to function normally

(e.g., not transmit the ABORT sequence).

1 - Configures the Transmit HDLC Controller block # 3 to transmit the

ABORT Sequence.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

2Tx_IDLE R/W 0 Transmit Idle (Flag Sequence Byte)

This bit configures the T ransmit HDLC Controller Block #3 to unconditionally

transmit a repeating string of Flag Sequence octets (0X7E) in the data link

channel to the Remote terminal. In normal conditions, the Transmit HDLC

Controller block will repeatedly transmit the Flag Sequence octet whenever

there is no MOS message to transmit to the remote terminal equipment.

However, if the user invokes this “Transmit Idle Sequence” feature, then the

Transmit HDLC Controller block will UNCONDITIONALLY transmi t a repeat-

ing stream of the Flag Sequence octet (thereb y overwriting all outbound

MOS data-link messages).

0 - Configures the Transmit HDLC Controller Block # 3 to transmit data-link

information in a “normal” manner.

1 - Configures the Transmit HDLC Controller block # 3 to transmit a repeat-

ing string of Flag Sequence Octets (0x7E).

NOTE: This bit is ignored if the Transmit HDLC3 controller is operating in the

BOS Mode - bit 0 (MOS/BOS) within this register is set to 0.

1Tx_FCS_EN R/W 0 Transmit LAPD Messag e with Frame Check Sequence (FCS)

This bit permits the user to configure the Transmit HDLC Controller block # 3

to compute and append FCS octets to the “back-end” of each outbound

MOS data-link message.

0 - Configures the Transmit HDLC Controller block # 3 to NOT compute and

append the FCS octets to the back-end of each outbound MOS data-link

message.

1 - Configures the Transmit HDLC Controller block # 3 TO COMPUTE and

append the FCS octets to the back-end of each outbound MOS data-link

message.

NOTE: This bit is ignored if the transmit HDLC3 controller has been

configured to operate in the BOS mode - bit 0 (MOS/BOS) within this

0 MOS/BOS R/W 0 Message Oriented Sign aling/Bit Oriented Signaling Send

This bit permits the user to enable LAPD transmission through HDLC Con-

troller Block # 3 using either BOS (Bit-Oriented Signa ling) or MOS (Mes-

sage-Oriented Signaling) frames.

0 - Transmit HDLC Controller block # 3 BOS message Send.

1 - Transmit HDLC Controller block # 3 MOS message Send.

NOTE: This is not an Enable bit. This bit must be set to "0" each time a BOS

is to be sent.

TABLE 60: DATA LINK CONTROL REGISTER (DLCR3) HEX ADDRESS: 0XN153

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 61: TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR3) HEX ADDRESS: 0XN154

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 TxHDLC3 BUFAvail/

BUFSel R/W 0 Transmit HDLC3 Buffer Available/Buffer Select

This bit has different functions, depending upon whether the user is

writing to or reading from this register, as depicted below.

If the user is writing data into this register bit:

0 - Configures the Transmit HDLC3 Controller to read out and trans-

mit the data, residing within “Transmit HDLC3 Buffer # 0", via the

Data Link channel to the remote terminal equipment.

1 - Configures the Transmit HDLC3 Controller to read out and trans-

mit the data, residing within the “Transmit HDLC3 Buf fer #1”, via the

Data Link channel to the remote terminal equipment.

If the user is reading data from this register bit:

0 - Indicates that “Transmit HDLC3 Buffer # 0" is the next available

buffer. In this case, if the user wishes to write in the contents of a

new “outbound” Data Link Message into the Transmit HDLC3 Mes-

sage Buffer, he/she should proceed to write this message into

“Transmit HDLC3 Buffer # 0" - Address location: 0xN600.

1 - Indicates that “Transmit HDLC3 Buffer # 1" is the next available

buffer. In this case, if the user wishes to write in the contents of a

new “outbound” Data Link Message into the Transmit HDLC3 Mes-

sage Buffer, he/she should proceed to write this message into

“Transmit HDLC3 Buffer # 1" - Address location: 0xN700.

NOTE: If one of these Transmit HDLC3 buffers contain a message

which has yet to be completely read-in and processed for

transmission by the Transmit HDLC3 controller, then this bit

will automatically reflect the value corresponding to the next

available buffer when it is read. Changing this bit to the in-

use buffer is not permitted.

6-0 TDLBC[6:0] R/W 0000000 Tran smit HDLC3 Message - Byte Count

The exact function of these bits depends on whether the Transmit

HDLC 3 Controller is configured to transmit MOS or BOS messages

to the Remote Terminal Equipment.

In BOS MODE:

These bit fields contain the number of repetitions the BOS message

must be transmitted before the Transmit HDLC3 controller gener-

ates the Transmit End of Transfer (TxEOT) interru pt and halt s trans-

mission. If these fields are set to 00000000, then the BOS message

will be transmitted for an indefinite number of times.

In MOS MODE:

These bit fields contain the length, in number of octets, of the mes-

sage to be transmitted. The length of MOS message specified in

these bits include header bytes such as the SAPI, TEI, Control field,

however, it does not include the FCS bytes.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 62: RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR3) HEX ADDRESS: 0XN155

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RBUFPTR R/W 0 Receive HDLC3 Buffer-Pointer

This bit Identifies which Receive HDLC3 buffer contains the most

recently received HDLC1 messa ge.

0 - Indicates that Receive HDLC3 Buffer # 0 contains the contents of

the most recently received HDLC message.

1 - Indicates that Receive HDLC3 Buffer # 1 contains the contents of

the most recently received HDLC message.

6-0 RDLBC[6:0] R/W 0000000 Receive HDLC Message - byte count

The exact function of these bits depends on whether the Receive

HDLC Controller Block #3 is configured to receive MOS or BOS

messages.

In BOS Mode:

These seven bits contain the number of repetitions the BOS mes-

sage must be received before the Receive HDLC3 contro ller gener-

ates the Receive End of T ransfer (RxEOT) interrupt. If these bits are

set to “0000000”, the message will be received indefinitely and no

Receive End of Transfer (RxEOT) interrupt will be generated.

In MOS Mode:

These seven bits contain the size in bytes of the HDLC3 message

that has been received and writte n into the Receive HDLC buffer.

The length of MOS message shown in these bits include header

bytes such as the SAPI, TEI, Control field, AND the FCS bytes.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

BERT Pattern Definitions

3 in 24

0001 0001 0000 00 01 0000 0000 ...

1 in 8

0000 0010 ...

55 Octet (Unframed)

This pattern is shown in HEX format for simplification purposes.

01 01 01 01 01 01 80 01 01 0 1 01 01 01 03 01 01 01 01 07 01 01 01 01 55 55 55 55 AA AA AA AA 01 01 01 01

01 01 FF FF FF FF FF FF 80 01 80 01 80 01 80 01 80 01 80 01 ...

Daly Pattern (Framed)

This pattern is shown in HEX format for simplification purposes.

01 01 01 01 01 01 80 01 01 0 1 01 01 01 03 01 01 01 01 07 01 01 01 01 55 55 55 55 AA AA AA AA 01 01 01 01

01 01 FF FF FF FF FF FF 80 01 80 01 80 01 80 01 80 01 80 01 ...

TABLE 63: BERT CONTROL REGISTER (BCR) HEX ADDRESS: 0XN163

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-4 Reserved R/W 0 Reserved

3-0 BERT[3:0] R/W 0000 BERT Pattern Select

0010 =PRBS X20 + X3 + 1

0011 = QRSS X20 + X17 + 1

0100 = All Ones

0101 = All Zeros

0110 = 3 in 24

0111 = 1 in 8

1000 = 55 Octet Pattern

1001 = Daly Pattern

1010 = PRBS X20 + X17 + 1

Others = Invalid

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

2.1 E1 Synchronization status message

E1 synchronization messages are sent through the National Bits (Sa4, Sa5, Sa6, Sa7, or Sa8) bits or the Si

Internationa l bit by using a BO C (Bit Orient ed Code) co ntroller within the XRT86VX38 device. The MSB o f the

BOC code is sent first in frame 2 of the CRC multi frame. The SSM message that are used in typical BITS

applications are shown below.

2.2 E1 BOC Receiver

If enabled, the E1 BOC receiver will monitor the National bits or the Si bit for SSM messages with various

features being supported. Some of these features are Change of Status Alarm, 3 independent pre-set codes

for matching validation (each having its own alarm), filter settings for consecutive pattern qualification, and

many more.

2.3 E1 BOC Transmitter

The E1 BOC transmitter will automatically insert an SSM message in the correct National bit or Si bit that is

selected. Once the message is stored in the TSSM register, Bit 0=1 sends the message.

TABLE 64: E1 SSM MESSAGES

QUALITY LEVEL DESCRIPTION BOC CODE

0 Quality unknown (existing sync network) 0000

1 Reserved 0001

2 Rec. G.811 (Traceable to PRS) 0010

3 Reserved 0011

4 SSU-A (Traceable to SSU type A, see G.812) 0100

5 Reserved 0101

6 Reserved 0110

7 Reserved 0111

8 SSU-B (Traceable to SSU type B, see G.12) 1000

9 Reserved 1001

10 Reserved 1010

11 Synchronous Equipment Timing Source 1011

12 Reserved 1100

13 Reserved 1101

14 Reserved 1110

15 Do not use for synchro ni za ti o n 1111

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

BIT 7 - BOC Source Select

This bit is used to select the source and destination of the BOC message. By default, the BOC will use the National Bits.

To use the Si International Bit, set this bit to ’1’. When a BOC message is enabled, it takes priority over the normal SaN

transmission. In addition, only one SaN register bit can be enabled at one time when transmitting BOC messages.

} 0 - Sa National Bits (Only one of the five Sa bits can be chosen for SSM transmission at a time, see register 0xN10Ah)

} 1 - Si International Bits (CRC Multi-Frame must be enabled and bits CRCC[1:0] in register 0xn11B cannot be 2’b11)

BITS [6:5] - Receive Match Filter Bits

These bits are used to set the number of consecutive error free patterns that must be received before the receive Match

Event is set. This filter applies to all three Match Event alarms, but not for the RSSM alarm.

} 00 - None

} 01 - 3 consecutive patterns

} 10 - 5 consecutive patterns

} 11 - 7 consecutive patterns

BIT 4 - Receive BOC Enable

This bit is used to enable the BOC receiver. For clarification, BOC messages can only be processed through the

National bits or Si International bit.

} 0 - Disabled

} 1 - Enable Receive BOC

BIT 3 - BOC Reset

This bit is used to reset the receive BOC controller. The function of this bit is to reset all the BOC register values to their

default values, except the BOC Interrupt registers. This register bit is automatically set back to ’0’ so that the user only

needs to write ’1’ to send a subsequent reset.

} 1 - Reset BOC

BITS [2:1] -Receive BOC Filter Bits

These bits are used to set the number of consecutive error free patterns th at must be received be fore th e receive BOC

alarm indication is set and the RSSM Valid Register is updated. This filter does NOT apply to the RSSM Matching Event

registers. The 3 RSSM Matching Event Registers have a separate filter that applies equally to all three matching

registers. Therefore, there are a total of 2 filters.

} 00 - None

} 01 - 3 consecutive patterns

} 10 - 5 consecutive patterns

} 11 - 7 consecutive patterns

BIT 0 - Send BOC Message

This bit is used to transmit the stored BOC message in the transmit SSM register. This register bit is automatically set

back to ’0’ so that the user only needs to write ’1’ to send a subsequent BOC message.

} 0 - Normal Operation

} 1 - Send BOC Message

TABLE 65: SSM BOC CONTROL REGISTER (BOCCR 0XN170H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

BOCSource RMF[1:0] RBOCE BOCR RBF[1:0] SBOC

R/W R/W R/W R/W Auto Clear R/W R/W Auto Clear

00000000

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

BITS [7:4] - Previous BOC Message

These bits contain the previous SSM message that was received for storage purposes. For the most recently received

message, see Bits[3:0] in this register.

BITS [3:0] - Receive BOC Message

These bits contain the most recently received BOC message if the filter setting has been meet in bits[2:1] of register

0xn170h. Once these bits have been updated, the previous message moves to bits[7:4] for storage purposes.

TABLE 66: RECEIVE SSM REGISTER (RSSMR 0XN171H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

PrevRBOC[3:0] RBOC[3:0]

RO RO RO RO RO RO RO RO

00000000

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

BITS [7:4] - Reserved

BITS [3:0] - Receive SSM Match 1

These bits can be used to set an expected value to be compared to the actual receive SSM message. This registe r is

one of three possible expected values that can be set. Upon a match of this register, an independent alarm will be set.

In addition, this register has a filter for consecutive message validation.

BITS [7:4] - Reserved

BITS [3:0] - Receive SSM Match 2

These bits can be used to set an expected value to be compared to the actual receive SSM message. This registe r is

one of three possible expected values that can be set. Upon a match of this register, an independent alarm will be set.

In addition, this register has a filter for consecutive message validation.

BITS [7:4] - Reserved

BITS [3:0] - Receive SSM Match 3

These bits can be used to set an expected value to be compared to the actual receive SSM message. This registe r is

one of three possible expected values that can be set. Upon a match of this register, an independent alarm will be set.

In addition, this register has a filter for consecutive message validation.

TABLE 67: RECEIVE SSM MATCH 1 REGISTER (RSSMMR1 0XN172H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

Reserved RSSMM1[3:0]

R/W R/W R/W R/W R/W R/W R/W R/W

00000000

TABLE 68: RECEIVE SSM MATCH 2 REGISTER (RSSMMR2 0XN173H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

Reserved RSSMM2[3:0]

R/W R/W R/W R/W R/W R/W R/W R/W

00000000

TABLE 69: RECEIVE SSM MATCH 3 REGISTER (RSSMMR3 0XN174H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

Reserved RSSMM3[3:0]

R/W R/W R/W R/W R/W R/W R/W R/W

00000000

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

BITS [7:4] - Reserved

BITS [3:0] - Transmit BOC Message

These bits are used to store the BOC message to be transmitted out the National bits or Si International bit. Once the

message has been stored in this register, Bit 0 within the BOC Control Register is used to automatically transmit the

message.

NOTE: The TxBYTE Coun t register 0xN176h is used to set the number of rep etitions for this BOC message befo re the all

ones sequence is sent out. The default is one repetition. To send a continuous pattern, set the TxBTYE Count to

zero.

BITS [7:0] - Transmit Byte Count Value

These bits are used to store the amount of repetitions the Transmit BOC message will be sent before an all ones

sequence. The default value is "1". If "0" is programmed into this register, the transmit BOC will be set continuously. To

stop a continuous transmission, the TxBYTE count should be progammed to a definite value, and then re-send the BOC

message.

TABLE 70: TRANSMIT SSM REGISTER (TSSMR 0XN175H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

Reserved TBOC[3:0]

RW RW RW RW RW RW RW RW

00000000

TABLE 71: TRANSMIT SSM BYTE COUNT REGISTER (TSSMBCR 0XN176H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

TBCR[7:0]

RW RW RW RW RW RW RW RW

00000001

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

BITS [7:0] - Receive FAS Si Bits

These bits are used to store the most recently received International Bits (Si) from the FAS frames within the E1 multi-

frame. These bits are updated on the multi-frame boundary.

BITS [7:0] - Transmit FAS Si Bits

These bits are used to store the International Bits (Si) to be transmitted in the FAS frames within the E1 multi-frame.

These bits are transmitted, starting on the multi-frame boundary. If the BOC source is set to Si, then it will take priority

over this register when enabled.

TABLE 72: RECEIVE FAS SI REGISTER (RFASSIR 0XN177H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

RFASSi[7:0]

RO RO RO RO RO RO RO RO

00000000

TABLE 73: TRANSMIT FAS SI REGISTER (RFASSIR 0XN178H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

TFASSi[7:0]

RW RW RW RW RW RW RW RW

00000000

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 74: RECEIVE DS-0 MONITOR REGISTERS (RDS0MR)

HEX ADDRESS: 0XN15F TO 0XN16F (NOT INCLUDING 0XN163) AND 0XN1C0 TO 0XN1CF

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 RxDS-0[7:0] RO 00000000 Receive DS-0 Monitor

The contents of these registers will display a direct copy of the value

currently being processed by the receive fram er within the selected

time slot. This value will reflect the data present at RTIP/RRING

before any conditioning occurs.

TS0 = 0xN15F

TS1 = 0xN160

TS2 = 0xN161

TS3 = 0xN162

TS4 = 0xN164 (Note: 0xN163 is not used)

TS5 = 0xN165

TS6 = 0xN166

TS7 = 0xN167

TS8 = 0xN168

TS9 = 0xN169

TS10 = 0xN16A

TS11 = 0xN16B

TS12 = 0xN16C

TS13 = 0xN16D

TS14 = 0xN16E

TS15 = 0xN16F

TS16 = 0xN1C0

TS17 = 0xN1C1

TS18 = 0xN1C2

TS19 = 0xN1C3

TS20 = 0xN1C4

TS21 = 0xN1C5

TS22 = 0xN1C6

TS23 = 0xN1C7

TS24= 0xN1C8

TS25 = 0xN1C9

TS26 = 0xN1CA

TS27 = 0xN1CB

TS28 = 0xN1CC

TS29 = 0xN1CD

TS30 = 0xN1CE

TS31 = 0xN1CF

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 75: TRANSMIT DS-0 MONITOR REGISTERS (TDS0MR) HEX ADDRESS: 0XN1D0 TO 0XN1EF

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 TxDS-0[7:0] RO 00000000 Tr ansmit DS-0 Monitor

The contents of these registers will display a direct copy of the value

currently being processed by the transmit framer within the selected

time slot. This value will reflect the data present at TxSER before

any conditioning occurs. For time slot 0, read register 0xN1D1, for

time slot 1, read 0xN1D2, etc. up to time slot 23 which is 0xN1F0.

TABLE 76: DEVICE ID REGISTER (DEVID) HEX ADDRESS: 0X1FE

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 DEVID[7:0] RO 0x3C DEVID

This register is used to identify the XRT86VX38 Framer/LIU. Th e

value of this register is 0x3Ch.

TABLE 77: REVISION ID REGISTER (REVID) HEX ADDRESS: 0X1FF

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 REVID[7:0] RO 00000010 REVID

This register is used to identify the revision number of the XRT86VX38.

The value of this register for the first revision is A - 0x01h.

NOTE: The content of this register i s subject to change when a newer

revision of the device is issued.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 78: TRANSMIT CHANNEL CONTROL REGISTER 0-31 (TCCR 0-31) HEX ADDRESS: 0XN300 TO 0XN31F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 LAPDcntl[1] R/W 1 Transmit LAPD Control

These bits select which one of the three Transmit LAPD controller is config-

ured to use D/E time slot (Octets 0-31) for transmitting LAPD messages.

The following table presents the different settings of these two bits.

NOTE: All three Transmit LAPD Controllers can use D/E timeslots for

transmission. However, only Transmit LAPD Controller 1 can use

datalink for transmission. Register 0xN300 repre sents D/E time slot

0, and 0xN31F represents D/E time slot 31.

6 LAPDcntl[0] 0

5-4 Reserved - - Reserved (For T1 mode only)

LAPDCNTL[1:0] LAPD CONTROLLER SELECTED

00 Transmit LAPD Controller 1

01 Transmit LAPD Controller 2

10 The TxDE[1:0] bits in the T ransmit Signaling and

Data Link Select Register (TSDLSR - Register

Address - 0xN10A, bit 3-2) determine the data

source for D/E time slots.

11 Transmit LAPD Controller 3

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3-0 TxCond(3:0) R/W 0000 Transmit Channel Conditioning for Timeslot 0 to 31

These bits allow the user to substitute the input PCM data (Octets 0-31) with

internally generated Conditioning Codes prior to transmission to the remote

terminal equipment on a per-channel basis. The table below presents the

different conditioning codes based on the setting of these bits.

NOTE: Register address 0xN300 represents time slot 0, and address

0xN31F represents time slot 31.

TABLE 78: TRANSMIT CHANNEL CONTROL REGISTER 0-31 (TCCR 0-31) HEX ADDRESS: 0XN300 TO 0XN31F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

TXCOND[1:0] CONDITIONING CODES

0xN / 0xE Contents of timeslot octet are unchanged.

0x1 All 8 bits of the selected timeslot octet are inverted (1’s

complement)

OUTPUT = (TIME_SLOT_OCTET) XOR 0xFF

0x2 Even bits of the selected timeslot octet are inverted

OUTPUT = (TIME_SLOT_OCTET) XOR 0xAA

0x3 Odd bits of the selected time slot octet are inverted

OUTPUT = (TIME_SLOT_OCTET) XOR 0x55

0x4 Contents of the selected timeslot octet will be substituted

with the 8 -bit value in the Transmit

Programmable User Code Register (0xN320-0xN337),

0x5 Contents of the timeslot octet will be substituted with the

value 0x7F (BUSY Code)

0x6 Contents of the timeslot octet will be substituted with the

value 0xFF (VACANT Code )

0x7 Contents of the timeslot octet will be substituted with the

BUSY time slot code (111#_####), where ##### is the

Timeslot number

0x8 Contents of the timeslot octet will be substituted with the

MOOF code (0x1A)

0x9 Contents of the timeslot octet will be substituted with the

A-Law Digital Milliwatt pattern

0xA Contents of the timeslot octet will be substituted with the

-Law Digital Milliwatt pattern

0xB The MSB (bit 1) of input data is inverted

0xC All input data except MSB is inverted

0xD Contents of the timeslot octet will be substituted with the

PRBS X15 + X 14 + 1/QRTS pattern

NOTE: PRBS X15 + X 14 + 1 or QRTS pattern depends on

PRBSType selected in the register 0xN123 - bit 7

0xF D/E time slot - The TxSIGDL[2:0] bits in the Transmit Sig-

naling and Data Link Select Register (0xN10A) will deter-

mine the data source for D/E time slots.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 79: TRANSMIT USER CODE REGISTER 0 - 31 (TUCR 0-31) HEX ADDRESS: 0XN320 TO 0XN33F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 TUCR[7:0] R/W b00010111 Transmit Programmable User code.

These eight bits allow users to program any code in this register to

replace the input PCM data when the Transmit Channel Control

grammable user code. (i.e. if TCCR is set to ‘0x4’)

The default value of this register is an IDLE Code (b00010111).

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 80: TRANSMIT SIGNALING CONTROL REGISTER 0-31 (TSCR 0-31) HEX ADDRESS: 0XN340 TO 0XN35F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 A (x) R/W See Note Transmit Signaling bit A or x bit

This bit allows users to provide signaling Bit A for octets 0-31 if

Channel Associated Signalin g (CAS) is enabled and if signaling

data is inserted from TSCR registe r (T xSIGSRC[1:0] = 01 in this

NOTE: Users must write to TSCR0 (Address 0xN340) the correct

CAS alignmen t b i ts (0 bits) in order to get C AS SYN C at th e

remote terminal. The xyxx bits can be programmed by

writing to TSCR16 (0xN350) and programming the

TxSIGSRC[1:0] bits within this register to ‘b11’.

6 B (y) R/W See Note Transmit Signaling bit B or y bit

This bit allows users to provide signaling Bit B for octets 0-31 if

Channel Associated Signalin g (CAS) is enabled and if signaling

data is inserted from TSCR registe r (T xSIGSRC[1:0] = 01 in this

NOTE: Users must write to TSCR0 (Address 0xN340) the correct

CAS alignmen t b i ts (0 bits) in order to get C AS SYN C at th e

remote terminal. The xyxx bits can be programmed by

writing to TSCR16 (0xN350) and programming the

TxSIGSRC[1:0] bits within this register to ‘b11’.

5 C (x) R/W See Note Transmit Signaling bit C or x bit

This bit allows users to provide signaling Bit C for octets 0-31 if

Channel Associated Signalin g (CAS) is enabled and if signaling

data is inserted from TSCR registe r (T xSIGSRC[1:0] = 01 in this

NOTE: Users must write to TSCR0 (Address 0xN340) the correct

CAS alignmen t b i ts (0 bits) in order to get C AS SYN C at th e

remote terminal. The xyxx bits can be programmed by

writing to TSCR16 (0xN350) and programming the

TxSIGSRC[1:0] bits within this register to ‘b11’.

4 D (x) R/W See Note Transmit Signaling bit D or x bit

This bit allows users to provide signaling Bit D in for octets 0-31 if

Channel Associated Signalin g (CAS) is enabled and if signaling

data is inserted from TSCR registe r (T xSIGSRC[1:0] = 01 in this

NOTE: Users must write to TSCR0 (Address 0xN340) the correct

CAS alignmen t b i ts (0 bits) in order to get C AS SYN C at th e

remote terminal. The xyxx bits can be programmed by

writing to TSCR16 (0xN350) and programming the

TxSIGSRC[1:0] bits within this register to ‘b11’.

3 Reserved - See Note Reserved

2 Reserved - See Note Reserved

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

NOTE: The default value for register address 0xN340 = 0xN1, 0xN341-0xN34F = 0xD0, 0xN350 = 0xB3, 0xN351-0xN35F =

0xD0

1 TxSIGSRC[1] R/W See Note Channel signaling contro l

These bits determine the source for signaling information. The table

below presents the different sources for signaling information corre-

sponding to different settings of these two bits.

0 TxSIGSRC[0] R/W See Note

TABLE 80: TRANSMIT SIGNALING CONTROL REGISTER 0-31 (TSCR 0-31) HEX ADDRESS: 0XN340 TO 0XN35F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

TXSIGSRC[1:0] SIGNALING SOURCE SELECTED

00 Signaling data is inserted from input PCM

data (TxSERn pin)

01 Signaling data is inserted from this register

(TSCRs).

10 Signaling data is inserted from the transmit

Overhead input pin (TxOH_n) if XRT86VX38

is configured in the base rate configuration

and if the Transmit Signali ng Interface bit is

disabled. (i.e. TxMUXEN bit = 0, TxI-

MODE[1:0] = 00, and TxFr2048 bit = 0 in the

Transmit Interface Control Register (TICR)

If the T ransmit Signaling Interface bit is

enabled (i.e. TxFr2048 bit = 1 in the Trans-

mit Interface Control Regi ster (TICR) Regis-

ter 0xN120), signaling data will be inserted

from the Transmit Signaling input pin

(TxSIG_n)

11 No signaling data is inserted into the input

PCM data. Setting these two bits to ‘11’ will

configure the xyxx bits only, where x bit s are

inserted from this register (TSCR) and y bit

reflects the alarm condition.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 81: RECEIVE CHANNEL CONTROL REGISTER X (RCCR 0-31) HEX ADDRESS: 0XN360 TO 0XN37F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 LAPDcntl[1] R/W 1 Receive LAPD Control

These bits select which one of the three Receive LAPD controller will be con-

figured to use D/E time slot (Octets 0-23) for receiving LAPD messages.

NOTE: All three LAPD Controller can use D/E timeslots for receiving LAPD

messages. However, only LAPD Controller 1 can use datalink for

reception.

NOTE: Register 0xN360 represen ts D/E time slot 0, and 0xN37F represents

D/E time slot 31.

6 LAPDcntl[0] R/W 0

5-4 Reserved - - Reserved

LAPDCNTL[1:0] RECEIVE LAPD CONTROLLER SELECTED

00 Receive LAPD Controller 1

01 Receive LAPD Controller 2

10 The RxSIGDL[1:0] bits in the Receive Sig-

naling and Data Link Select Register

(RSDLSR - Address - 0xN10C) determine

the data source for Receive D/E time slots.

11 Receive LAPD Controller 3

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3-0 RxCOND[3:0] R/W 0000 Receive Channel Conditioning for Timeslot 0 to 31

These bits allow the user to substitute the input line data (Octets 0-31) with

internally generated Conditioning Codes prior to transmission to the back-

plane interface on a per-chann el basis. The table below presents the differ-

ent conditioning codes based on the setti ng of these bits.

NOTE: Register address 0xN300 represents time slot 0, and address

0xN31F represents time slot 31.

TABLE 81: RECEIVE CHANNEL CONTROL REGISTER X (RCCR 0-31) HEX ADDRESS: 0XN360 TO 0XN37F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

RXCOND[1:0] CONDITIONING CODES

0xN / 0xE Contents of timeslot octet are unchanged.

0x1 All 8 bits of the selected timeslot octet are inverted (1’s

complement)

OUTPUT = (TIME_SLOT_OCTET) XOR 0xFF

0x2 Even bits of the selected timeslot octet are inverted

OUTPUT = (TIME_SLOT_OCTET) XOR 0xAA

0x3 Odd bits of the selected time slot octet are inverted

OUTPUT = (TIME_SLOT_OCTET) XOR 0x55

0x4 Contents of the selected timeslot octet will be substituted

with the 8 -bit value in the Receive

Programmable User Code Register (0xN380-0xN397),

0x5 Contents of the timeslot octet will be substituted with the

value 0x7F (BUSY Code)

0x6 Contents of the timeslot octet will be substituted with the

value 0xFF (VACANT Code)

0x7 Contents of the timeslot octet will be substituted with the

BUSY time slot code (111#_####), where ##### is the

Timeslot number

0x8 Contents of the timeslot octet will be substituted with the

MOOF code (0x1A)

0x9 Contents of the timeslot octet will be substituted with the

A-Law Digital Milliwatt pattern

0xA Contents of the timeslot octet will be substi tuted with the

-Law Digital Milliwatt pattern

0xB The MSB (bit 1) of input data is inverted

0xC All input data except MSB is inverted

0xD Contents of the timeslot octet will be substituted with the

PRBS X15 + X 14 + 1/QRTS pattern

NOTE: PRBS X15 + X 14 + 1 or QRTS pattern depends on

PRBSType selected in the register 0xN123 - bit 7

0xF D/E time slot - The RxSIGDL[2:0] bits in the Transmit Sig-

naling and Data Link Select Register (0xN10C) will deter-

mine the data source for Receive D/E time slots.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 82: RECEIVE USER CODE REGISTER 0-31 (RUCR 0-31) HEX ADDRESS: 0XN380 TO 0XN39F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 RxUSER[7:0] R/W 11111111 Receive Programmab le User code.

These eight bits allow users to program any code in this register to

replace the received data when the Receive Channel Control Regis-

ter (RCCR) is configured to replace timeslot octet with the receive

programmable user code. (i.e. if RCCR is set to ‘0x4’)

TABLE 83: RECEIVE SIGNALING CONTROL REGISTER 0-31 (RSCR 0-31) HEX ADDRESS: 0XN3A0 TO 0XN3BF

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

6 SIGC_ENB R/W 0 Signaling substitution enable

This bit enables or disables signaling substitution on the receive

side. Once signaling substitu tion is enabled, received signa ling bits

ABCD will be substituted with the ABCD values in the Rece ive Sub-

stitution Signaling Registe r (RSSR).

Signaling substitution only occurs in the output PCM data

(RxSERn). Receive Signaling Array Register (RSAR - Address

0xN500-0xN51F) and the exte rnal Signaling bus (RxSIG_n) output

pin will not be affected.

0 = Disables signaling substitution on the receive side.

1 = Enables signaling substitution on the receive side.

5OH_ENB R/W 0 Signaling OH interface output enable

This bit enables or disables signaling information to output via the

Receive Overhead pin (RxOH_n). The signaling information in the

receive signaling array registers (RSAR - Address 0xN500-0xN51F)

is output to the receive overhead ou tput pin (RxOH_n) if this bit is

enabled.

0 = Disables signaling information to output via RxOH_n.

1 = Enables signaling information to output via RxOH_n.

4 DEB_ENB R/W 0 Per-channel debounce enable

This bit enables or disables the signaling debounce feature.

When this feature is enabled, the per-channel signaling state must

be in the same state for 2 superframes befo re the Receive Framer

updates signaling information on the Receive Signaling Array Regis-

ter (RSAR) and the Signaling Pin (RxSIGn). If the signaling bits for

two consecutive superframes are not the same, the current state of

RSAR and RxSIG will not change.

When this feature is disabled, RSAR and RxSIG will be updated as

soon as the receive signaling bits have changed.

0 = Disables the Signaling Debounce feature.

1 = Enables the Signaling Debounce feature.

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3 RxSIGC[1] R/W 0 Signaling condi tioning

These bits allow user to select the format of signaling substitution on

a per-channel basis, as presented in the table below.

2 RxSIGC[0] R/W 0

1RxSIGE[1] R/W 0 Receive Signaling Extraction.

These bits control per-channel signaling extraction as presented in

the table below. Signaling information can be extracted to the

Receive Signaling Arra y Register (RSAR), the Receive Signaling

Output pin (RxSIG_n) if the Receive SIgnaling Interface is enable,

or the Receive Overhead Interface output (RxOH_n) if OH_ENB bi t

is enabled. (bit 5 of this register).

0RxSIGE[0] R/W 0

TABLE 83: RECEIVE SIGNALING CONTROL REGISTER 0-31 (RSCR 0-31) HEX ADDRESS: 0XN3A0 TO 0XN3BF

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

RXSIGC[1:0] SIGNALING SUBSTITUTION SCHEMES

00 Substitutes all s ign a lin g bits with one.

01 Enables 16-code (A,B,C,D) signaling substi-

tution.

Users must write to bits 3-0 in the Receive Sig-

naling Substitution Register (RSSR) to provide

the 16-code (A,B,C,D) signaling substitution val-

ues.

10 Enables 4-code (A,B) signaling substitution.

Users must write to bits 4-5 in the Receive Sig-

naling Substitution Register (RSSR) to provide

the 4-code (A,B) signaling substitution values.

11 Enables 2-code (A) signal ing substitution.

Users must write to bit 6 in the Receive Signal-

ing Substitution Register (RSSR) to provide the

2-code (A) signaling substitution values.

RXSIGE[1:0] SIGNALING EXTRACTION SCHEMES

00 No signaling information is extracted.

01 Enables 16-code (A,B,C,D) signaling

extraction.

All signaling bits A,B,C,D will be extracted.

10 Enables 4-code (A,B) signaling extraction

Only signaling bits A,B will be extracted.

11 Enables 2-code (A) signaling extraction

Only signaling bit A will be extracted.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 84: RECEIVE SUBSTITUTION SIGNALING REGISTER 0-31 (RSSR 0-31 ) HEX ADDRESS 0XN3C0 TO 0XN3DF

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

6 SIG2-A R/W 0 2-code signaling A

This bit provides the value of signaling bit A to substitute the receive

signaling bit A when 2-code signaling substitution is enabled. Regis-

ter address 0xN3C0 represents time slot 0, and 0xN3DF represents

time slot 31.

5 SIG4-B R/W 0 4-code signaling B

This bit provides the value of signaling bit B to substitute the receive

signaling bit B when 4-code signaling substitution is enabled. Regis-

ter address 0xN3C0 represents time slot 0, and 0xN3DF represents

time slot 31.

4 SIG4-A R/W 0 4-code signaling A

This bit provides the value of signaling bit A to substitute the receive

signaling bit A when 4-code signaling substitution is enabled. Regis-

ter address 0xN3C0 represents time slot 0, and 0xN3DF represents

time slot 31.

3SIG16-D R/W 0 16-code signaling D

This bit provides the value of signaling bit D to substitute the receive

signaling bit D when 16-code sign aling substitution is enabled. Reg-

ister address 0xN3C0 represents time slot 0, and 0xN3DF repre-

sents time slot 31.

2SIG16-C R/W 0 16-code signaling C

This bit provides the value of signaling bit C to substitute the receive

signaling bit C when 16-code sign aling substitution is enabled. Reg-

ister address 0xN3C0 represents time slot 0, and 0xN3DF repre-

sents time slot 31.

1SIG16-B R/W 0 16-code signaling B

This bit provides the value of signaling bit B to substitute the receive

signaling bit B when 16-code signalin g substitution is enabled. Reg-

ister address 0xN3C0 represents time slot 0, and 0xN3DF repre-

sents time slot 31.

0SIG16-A R/W 0 16-code signaling A

This bit provides the value of signaling bit A to substitute the receive

signaling bit A when 16-code signalin g substitution is enabled. Reg-

ister address 0xN3C0 represents time slot 0, and 0xN3DF repre-

sents time slot 31.

TABLE 85: RECEIVE SIGNALING ARRAY REGISTER 0 - 31 (RSAR 0-31) HEX ADDRESS: 0XN500 TO 0XN51F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-4 Reserved - - Reserved

XRT86VX38

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3 A RO 0 These READ ONLY registers reflect the most recently received sig-

naling value (A,B,C,D) associated with timeslot 0 to 31. If signaling

debounce feature is enabled, th e received signaling state must be

the same for 2 superframes before this register is updated. If the

signaling bits for two consecutive superframes are not the same, the

current value of this register will not be changed.

If the signaling debounce or sig feature is disabled, this register is

updated as soon as the received signalin g bits have changed.

NOTE: The content of this register only has meaning when the

framer is using Channel Associated Signalin g.

2B RO 0

1C RO 0

0D RO 0

TABLE 86: LAPD BUFFER 0 CONTROL REGISTER (LAPDBCR0) HEX ADDRESS: 0XN600

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 LAPD Buffer 0 R/W 0 LAPD Buffer 0 (96-Bytes) Auto Incrementing

This register is used to transmit and receive LAPD messages within

buffer 0 of the HDLC controller. Any one of the HDLC controller can

be is chosen in the LAPD Select Register (0xN11B). Users should

determine the next availa ble buffer by reading the BUFAVAL bit (bit

7 of the Transmit Data Link Byte Count Register 1 (address

0xN114), Register 2 (0xN144) and Register 3 (0xN154) depending

on which HDLC controller is selected. If buffer 0 is available, writing

to buffer 0 will insert the message into the outgoing LAPD frame

after the LAPD message is sent and the data from the transmit

buffer cannot be retrieved.

After detecting the Receive end of transfer interrupt (RxEOT), users

should read the RBUFPTR bit (bit 7 of the Receive Data Link Byte

Count Register 1 (address 0xN115), Register 2 (0xN145), or Regis-

ter 3 (0xN155) depending on which HDLC controller is selected ) to

determine which buffer contains the received LAPD message ready

to be read. If RBUFPTR bit indicates that buffer 0 is available to be

read, reading buffer 0 (Register 0xN600) continuously will retrieve

the entire received LAPD message.

NOTE: When writing to or reading from Buffer 0, the register is

automatically incremented such that the entire 96 Byte

LAPD message can be written into or read from buffer 0

(Register 0xN600) continuously.

TABLE 85: RECEIVE SIGNALING ARRAY REGISTER 0 - 31 (RSAR 0-31) HEX ADDRESS: 0XN500 TO 0XN51F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 87: LAPD BUFFER 1 CONTROL REGISTER (LAPDBCR1) HEX ADDRESS: 0XN700

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 LAPD Buffer 1 R/W 0 LAPD Buffer 1 (96-Bytes) Auto Incrementing

This register is used to transmit and receive LAPD messages within

buffer 1 of the HDLC controller. Any one of the HDLC controller can

be is chosen in the LAPD Select Register (0xN11B). Users should

determine the next available buffer by reading the BUFAVAL bit (bit

7 of the Transmit Data Link Byte Count Register 1 (address

0xN114), Register 2 (0xN144) and Register 3 (0xN154) depending

on which HDLC controller is selected. If buffer 1 is available, writing

to buffer 1 will insert the message into the outgoing LAPD frame

after the LAPD message is sent and the data from the transmit

buffer 1 cannot be retrieved.

After detecting the Receive end of transfer interrupt (RxEOT), users

should read the RBUFPTR bit (bit 7 of the Receive Data Link Byte

Count Register 1 (address 0xN115), Register 2 (0xN145), or Regis-

ter 3 (0xN155) depending on which HDLC controller is selected ) to

determine which buffer contains the received LAPD message ready

to be read. If RBUFPTR bit indicates that buffer 1 is available to be

read, reading buffer 1 (Register 0xN700) continuously will retrieve

the entire received LAPD message.

NOTE: When writing to or reading from Buffer 0, the register is

automatically incremented such that the entire 96 Byte

LAPD message can be written into or read from buffer 0

(Register 0xN600) continuously.

TABLE 88: PMON RECEIVE LINE CODE VIOLATION COUNTER MSB (RLCVCU) HEX ADDRESS: 0XN900

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RLCVC[15] RUR 0 Performance Monitor “Receive Line Code Violation” 16-Bit

Counter - Upper Byte:

These RESET-upon-READ bits, along with that within the PMON

Receive Line Code Violation Counte r Register LSB combine to

reflect the cumulative numb er of in stances that Line Code Violation

has been detected by the Receive E1 Framer bloc k since the last

read of this register.

This register contains the Most Significant byte of this 16-bit of the

Line Code Violation counter.

NOTE: For all 16-bit wide PMON registers, us er must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 RLCVC[14] RUR 0

5 RLCVC[13] RUR 0

4 RLCVC[12] RUR 0

3 RLCVC[11] RUR 0

2 RLCVC[10] RUR 0

1 RLCVC[9] RUR 0

0 RLCVC[8] RUR 0

XRT86VX38

100

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 89: PMON RECEIVE LINE CODE VIOLATION COUNTER LSB (RLCVCL) HEX ADDRESS: 0XN901

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RLCVC[7] RUR 0 Performance Monitor “Receive Line Cod e Violation” 16-Bit

Counter - Lower Byte:

These RESET-upon-READ bits, along with that within the PMON

Receive Line Code Violation Counter Register MSB combine to

reflect the cumulative numb er of instances that Line Code Violation

has been detected by the Receive E1 Framer bloc k since the last

read of this register.

This register contains the Least Significant byte of this 16-bit of the

Line Code Violation counter.

NOTE: For all 16-bit wide PMON registers, us er must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 RLCVC[6] RUR 0

5 RLCVC[5] RUR 0

4 RLCVC[4] RUR 0

3 RLCVC[3] RUR 0

2 RLCVC[2] RUR 0

1 RLCVC[1] RUR 0

0 RLCVC[0] RUR 0

TABLE 90: PMON RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER MSB (RFAECU) HEX ADDRESS: 0XN902

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RFAEC[15] RUR 0 Performance Monitor “Receive Framing Alignment Error 16-Bit

Counter” - Upper Byte:

These RESET-upon-READ bits, along with that within the “PMON

Receive Framing Alignment Error Counter Register LSB” combine

to reflect the cumulative number of instances that the Receive

Framing Alignment errors has been detected by the Receive E1

Framer block since the last read of this register.

This register contains the Most Significant byte of this 16-bit of the

Receive Framing Alignment Error counter.

NOTE: For all 16-bit wide PMON registers, us er must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 RFAEC[14] RUR 0

5 RFAEC[13] RUR 0

4 RFAEC[12] RUR 0

3 RFAEC[11] RUR 0

2 RFAEC[10] RUR 0

1 RFAEC[9] RUR 0

0 RFAEC[8] RUR 0

TABLE 91: PMON RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER LSB (RFAECL) HEX ADDRESS: 0XN903

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RFAEC[7] RUR 0 Performance Monitor “Receive Framing Alignment Error 16-Bit

Counter” - Lower Byte:

These RESET-upon-READ bits, along with that within the “PMON

Receive Framing Alignment Error Counter Register MSB” combine

to reflect the cumulative number of instances that the Receive

Framing Alignment errors has been detected by the Receive E1

Framer block since the last read of this register.

This register contains the Least Significant byte of this 16-bit of the

Receive Framing Alignment Error counter.

NOTE: For all 16-bit wide PMON registers, us er must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 RFAEC[6] RUR 0

5 RFAEC[5] RUR 0

4 RFAEC[4] RUR 0

3 RFAEC[3] RUR 0

2 RFAEC[2] RUR 0

1 RFAEC[1] RUR 0

0 RFAEC[0] RUR 0

XRT86VX38

101

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 92: PMON RECEIVE SEVERELY ERRORED FRAME COUNTER (RSEFC) HEX ADDRESS: 0XN904

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RSEFC[7] RUR 0 Performance Monitor - Receive Severely Errored frame Counter

(8-bit Counter)

These Reset-Upon-Read bit fields reflect the cumulative number of

instances that Receive Severely Errored Frames have been

detected by the E1 Framer since the last read of thi s reg i ste r.

Severely Errored Frame is defined as the occurrence of two consec-

utive errored frame alignment signal s without causing loss of frame

condition.

6 RSEFC[6] RUR 0

5 RSEFC[5] RUR 0

4 RSEFC[4] RUR 0

3 RSEFC[3] RUR 0

2 RSEFC[2] RUR 0

1 RSEFC[1] RUR 0

0 RSEFC[0] RUR 0

TABLE 93: PMON RECEIVE CRC-4 BIT ERROR COUNTER - MSB (RSBBECU) HEX ADDRESS: 0XN905

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RSBBEC[15] RUR 0 Performance Monitor “Receive Synchronization Bit Error 16-Bit

Counter” - Upper Byte:

These RESET-upon-READ bits, along with that within the “PMON

Receive Synchronization Bit Error Counter Register LSB” combine

to reflect the cumulative number of instances that the Receive Syn-

chronization Bit errors has been detected by the Receive E1 Framer

block since the last read of this register.

This register contains the Most Significant byte of this 16-bit of the

Receive Synchronization Bit Error cou nter.

NOTE: For all 16-bit wide PMON registers, us er must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 RSBBEC[14] RUR 0

5 RSBBEC[13] RUR 0

4 RSBBEC[12] RUR 0

3 RSBBEC[11] RUR 0

2 RSBBEC[10] RUR 0

1 RSBBEC[9] RUR 0

0 RSBBEC[8] RUR 0

TABLE 94: PMON RECEIVE CRC-4 BLOCK ERROR COUNTER - LSB (RSBBECL) HEX ADDRESS: 0XN906

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RSBBEC[7] RUR 0 Performance Monitor “Receive Synchronization Bit Error 16-Bit

Counter” - Lower Byte:

These RESET-upon-READ bits, along with that within the “PMON

Receive Synchronization Bit Error Counter Register MSB” combine

to reflect the cumulative number of instances that the Receive Syn-

chronization Bit errors has been detected by the Receive E1 Framer

block since the last read of this register.

This register contains the Least Significant byte of this 16-bit of the

Receive Synchronization Bit Error cou nter.

NOTE: For all 16-bit wide PMON registers, us er must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 RSBBEC[6] RUR 0

5 RSBBEC[5] RUR 0

4 RSBBEC[4] RUR 0

3 RSBBEC[3] RUR 0

2 RSBBEC[2] RUR 0

1 RSBBEC[1] RUR 0

0 RSBBEC[0] RUR 0

XRT86VX38

102

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 95: PMON RECEIVE FAR-END BLOCK ERROR COUNTER - MSB (RFEBECU) HEX ADDRESS: 0XN907

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RFEBEC[15] RUR 0 Performance Monitor - Receive Far-End Block Error 16-Bit

Counter - Upper Byte:

These RESET-upon-READ bits, along with that within the “PMON

Receive Far-End Bl ock Error Counter Register LSB” comb ine to

reflect the cumulative number of instances that the Receive Far-End

Block errors has been detected by the Receive E1 Framer block

since the last rea d of thi s reg i ste r.

This register contains the Most Significant byte of this 16-bit of the

Receive Far-End Block Error counter.

NOTE: The Receive Far-End Block Error Counter will increment

once each time the received E-bit is set to zero. This

counter is disabled during l oss of sync at either the FAS or

CRC-4 level and it will continue to count if loss of multiframe

sync occurs at the CAS level.

NOTE: For all 16-bit wide PMON registers, u ser must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 RFEBEC[14] RUR 0

5 RFEBEC[13] RUR 0

4 RFEBEC[12] RUR 0

3 RFEBEC[11] RUR 0

2 RFEBEC[10] RUR 0

1 RFEBEC[9] RUR 0

0 RFEBEC[8] RUR 0

TABLE 96: PMON RECEIVE FAR END BLOCK ERROR COUNTER -LSB (RFEBECL) HEX ADDRESS: 0XN908

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RFEBEC[7] RUR 0 Performance Monitor - Receive Far-End Block Erro r 16-Bit

Counter - Lower Byte:

These RESET-upon-READ bits, along with that within the “PMON

Receive Far-End Block Error Counter Register MSB” combine to

reflect the cumulative number of instances that the Receive Far-End

Block errors has been detected by the Receive E1 Framer block

since the last rea d of thi s reg i ste r.

This register contains the Least Significant byte of this 16-bit of the

Receive Far-End Block Error counter.

NOTE: The Receive Far-End Block Error Counter will increment

once each time the received E-bit is set to zero. This

counter is disabled during l oss of sync at either the FAS or

CRC-4 level and it will continue to count if loss of multiframe

sync occurs at the CAS level.

NOTE: For all 16-bit wide PMON registers, u ser must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 RFEBEC[6] RUR 0

5 RFEBEC[5] RUR 0

4 RFEBEC[4] RUR 0

3 RFEBEC[3] RUR 0

2 RFEBEC[2] RUR 0

1 RFEBEC[1] RUR 0

0 RFEBEC[0] RUR 0

XRT86VX38

103

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 97: PMON RECEIVE SLIP COUNTER (RSC) HEX ADDRESS: 0XN909

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RSC[7] RUR 0 Performance Monitor - Receive Slip Counter (8-bit Counter)

These Reset-Upon-Read bit fields reflect the cumulative number of

instances that Receive Slip events have been detected by the E1

Framer since the last read of this register.

NOTE: A slip event is defined as a replication or deletion of a E1

frame by the receive slip buffer.

6 RSC[6] RUR 0

5 RSC[5] RUR 0

4 RSC[4] RUR 0

3 RSC[3] RUR 0

2 RSC[2] RUR 0

1 RSC[1] RUR 0

0 RSC[0] RUR 0

TABLE 98: PMON RECEIVE LOSS OF FRAME COUNTER (RLFC) HEX ADDRESS: 0XN90A

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RLFC[7] RUR 0 Performance Monitor - Receive Loss of Frame Counter (8-b it

Counter)

These Reset-Upon-Read bit fields reflect the cumulative number of

instance s that Receive Loss of Frame condition ha ve been detected

by the E1 Framer since the last read of this register.

NOTE: This counter counts once every time the Loss of Frame

condition is declared. This counter provides the capability to

measure an accumulation of short failure events.

6 RLFC[6] RUR 0

5 RLFC[5] RUR 0

4 RLFC[4] RUR 0

3 RLFC[3] RUR 0

2 RLFC[2] RUR 0

1 RLFC[1] RUR 0

0 RLFC[0] RUR 0

TABLE 99: PMON RECEIVE CHANGE OF FRAME ALIGNMENT COUNTER (RCF AC) HEX ADDRESS: 0XN90B

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RCFAC[7] RUR 0 Performa nce Monitor - Receive Change of Frame Alignment

Counter (8-bit Counter)

These Reset-Upon-Read bit fields reflect the cumulative number of

instances that Receive Change of Framing Alignment have been

detected by the E1 Framer since the last read of thi s reg i ste r.

NOTE: Change of Framing Alignment (COFA) is declared when the

newly-locked framing pattern is different from the one

offered by off-line framer.

6 RCFAC[6] RUR 0

5 RCFAC[5] RUR 0

4 RCFAC[4] RUR 0

3 RCFAC[3] RUR 0

2 RCFAC[2] RUR 0

1 RCFAC[1] RUR 0

0 RCFAC[0] RUR 0

XRT86VX38

104

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 100: PMON LAPD FRAME CHECK SEQUENCE ERROR COUNTER 1 (LFCSEC1) HEX ADDRESS:

0XN90C

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 FCSEC1[7] RUR 0 Performance Monitor - LAPD 1 Frame Check Sequence Error

Counter (8-bit Counter)

These Reset-Upon-Read bit fie lds reflect the cumulative numbe r of

instances that Frame Check Sequence Error have been detected by

the LAPD Controller 1 since the last read of this register.

6 FCSEC1[6] RUR 0

5 FCSEC1[5] RUR 0

4 FCSEC1[4] RUR 0

3 FCSEC1[3] RUR 0

2 FCSEC1[2] RUR 0

1 FCSEC1[1] RUR 0

0 FCSEC1[0] RUR 0

TABLE 101: PMON PRBS BIT ERROR COUNTER MSB (PBECU) HEX ADDRESS:

0XN90D

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 PRBSE[15] RUR 0 Performance Monitor - E1 PRBS Bit Error 16-Bit Counter -

Upper Byte:

These RESET-upon-READ bits, along with that within the “PMON

E1 PRBS Bit Error Counter Register LSB” combine to reflect the

cumulative number of instances that the ReceiveE1 PRBS Bit errors

has been detected by the Receive E1 Framer bloc k since the last

read of this register.

This register contains the Most Significant byte of this 16-bit of the

Receive E1 PRBS Bit Error counter.

NOTE: For all 16-bit wide PMON registers, us er must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 PRBSE[14] RUR 0

5 PRBSE[13] RUR 0

4 PRBSE[12] RUR 0

3 PRBSE[11] RUR 0

2 PRBSE[10] RUR 0

1 PRBSE[9] RUR 0

0 PRBSE[8] RUR 0

XRT86VX38

105

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 102: PMON PRBS BIT ERROR COUNTER LSB (PBECL) HEX ADDRESS:

0XN90E

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 PRBSE[7] RUR 0 Performance Monitor - E1 PRBS Bit Error 16-Bit Counter -

Lower Byte:

These RESET-upon-READ bits, along with that within the “PMON

E1 PRBS Bit Error Counter Register MSB” combine to reflect the

cumulative number of instances that the ReceiveE1 PRBS Bit errors

has been detected by the Receive E1 Framer bloc k since the last

read of this register.

This register contains the Least Significant byte of this 16-bit of the

Receive E1 PRBS Bit Error counter.

NOTE: For all 16-bit wide PMON registers, us er must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 PRBSE[6] RUR 0

5 PRBSE[5] RUR 0

4 PRBSE[4] RUR 0

3 PRBSE[3] RUR 0

2 PRBSE[2] RUR 0

1 PRBSE[1] RUR 0

0 PRBSE[0] RUR 0

TABLE 103: PMON TRANSMIT SLIP COUNTER (TSC) HEX ADDRESS: 0XN90F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 TxSLIP[7] RUR 0 Performance Monitor - Transmit Slip Counter (8-bit Counter)

These Reset-Upon-Read bit fields reflect the cumulative number of

instances that Transmit Slip events have been detected by the E1

Framer since the last read of this register.

NOTE: A slip event is defined as a replication or deletion of a E1

frame by the transmit slip buffer.

6 TxSLIP[6] RUR 0

5 TxSLIP[5] RUR 0

4 TxSLIP[4] RUR 0

3 TxSLIP[3] RUR 0

2 TxSLIP[2] RUR 0

1 TxSLIP[1] RUR 0

0 TxSLIP[0] RUR 0

TABLE 104: PMON EXCESSIVE ZERO VIOLATION COUNTER MSB (EZVCU) HEX ADDRESS: 0XN910

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 EZVC[15] RUR 0 Performance Monitor - E1 Excessive Zero Violation 16-Bit

Counter - Upper Byte:

These RESET-upon-READ bits, along with that within the “PMON

E1 Excessive Zero Violation Counter Register LSB” combine to

reflect the cumulative numb er of in stances that the ReceiveE1

Excessive Zero Violation has been detected by the Receive E1

Framer block since the last read of this register.

This register contains the Most Significant byte of this 16-bit of the

Receive E1 Excessiv e Zero Violation counter.

NOTE: For all 16-bit wide PMON registers, us er must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 EZVC[14] RUR 0

5 EZVC[13] RUR 0

4 EZVC[12] RUR 0

3 EZVC[11] RUR 0

2 EZVC[10] RUR 0

1 EZVC[9] RUR 0

0 EZVC[8] RUR 0

XRT86VX38

106

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 105: PMON EXCESSIVE ZERO VIOLATION COUNTER LSB (EZVCL) HEX ADDRESS: 0XN911

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 EZVC[7] RUR 0 Performance Monitor - E1 Excessive Zero Violation 16-Bit

Counter - Lower Byte:

These RESET-upon-READ bits, along with that within the “PMON

E1 Excessive Zero Violation Counter Register MSB” combine to

reflect the cumulative numb er of instances that the ReceiveE1

Excessive Zero Violation has been detected by the Receive E1

Framer block since the last read of this register.

This register contains the Least Significant byte of this 16-bit of the

Receive E1 Excessive Zero Violation counter.

NOTE: For all 16-bit wide PMON registers, us er must read th e MSB

counter first before reading the LSB counter in order to read

the accurate PMON counts. To clear PMON count, user

must read the MSB counter first before reading the LSB

counter in order to clear the PMON count.

6 EZVC[6] RUR 0

5 EZVC[5] RUR 0

4 EZVC[4] RUR 0

3 EZVC[3] RUR 0

2 EZVC[2] RUR 0

1 EZVC[1] RUR 0

0 EZVC[0] RUR 0

TABLE 106: PMON FRAME CHECK SEQUENCE ERROR COUNTER 2 (LFCSEC2) HEX ADDRESS: 0XN91C

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 FCSEC2[7] RUR 0 Performance Monitor - LAPD 2 Frame Check Sequence Error

Counter (8-bit Counter)

These Reset-Upon-Read bit fie lds reflect the cumulative numbe r of

instances that Frame Check Sequence Error have been detected by

the LAPD Controller 2 since the last read of this register.

6 FCSEC2[6] RUR 0

5 FCSEC2[5] RUR 0

4 FCSEC2[4] RUR 0

3 FCSEC2[3] RUR 0

2 FCSEC2[2] RUR 0

1 FCSEC2[1] RUR 0

0 FCSEC2[0] RUR 0

TABLE 107: PMON FRAME CHECK SEQUENCE ERROR COUNTER 3 (LFCSEC3) HEX ADDRESS: 0XN92C

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 FCSEC3[7] RUR 0 Performance Monitor - LAPD 3 Frame Check Sequence Error

Counter (8-bit Counter)

These Reset-Upon-Read bit fie lds reflect the cumulative numbe r of

instances that Frame Check Sequence Error have been detected by

the LAPD Controller 3 since the last read of this register.

6 FCSEC3[6] RUR 0

5 FCSEC3[5] RUR 0

4 FCSEC3[4] RUR 0

3 FCSEC3[3] RUR 0

2 FCSEC3[2] RUR 0

1 FCSEC3[1] RUR 0

0 FCSEC3[0] RUR 0

XRT86VX38

107

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 108: BLOCK INTERRUPT STATUS REGISTER (BISR) HEX ADDRESS: 0XNB00

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7Sa6 RO 0 Sa6 Block Interrupt Stat us

This bit Indicates whether or not the SA 6 block has an interrupt

request awaiting service.

0 - Indicates no outstanding SA 6 block interrupt request is awaiting

service

1 - Indicates the SA 6 block has an interrupt request awaiting ser-

vice. Interrupt Service routine should branch to the interrupt source

and read the SA6 block Interrupt Status register (address 0xNB0C)

to clear the interrupt

NOTE: This bit will be reset to 0 after the microprocessor has

performed a read to the SA6 Interrupt Status Register

6 Reserved For T1 mode only

5RxClkLOS RO 0 Loss of Recovered Clock Interrupt Status

This bit indicates whether or not the E1 receive framer is currently

declaring the "Loss of Recovered Clock" interrupt.

0 = Indicates that the E1 Receive Framer Block is NOT currently

declaring the "Loss of Recovered Clock" interrupt.

1 = Indicates that the E1 Receive Framer Block is currently declar-

ing the "Loss of Recovered Clock" interrupt.

NOTE: This bit is only active if the clock loss detection feature is

enabled (Register - 0xN100)

4 ONESEC RO 0 One Second Interrupt Status

This bit indicates whether or not the E1 receive framer block is cur-

rently declaring the "One Second" interrupt.

0 = Indicates that the E1 Receive Framer Block is NOT currently

declaring the "One Second" interrupt.

1 = Indicates that the E1 Receive Framer Block is currently declar-

ing the "One Second" interrupt.

3 HDLC RO 0 HDLC Block Interrupt Status

This bit indicates whether or not the HDLC block has any interrupt

request awaiting service.

0 = Indicates no outstanding HDLC block interrupt request is await-

ing service

1 = Indicates HDLC Block has an interrupt request awaiting service.

Interrupt Service routi n e sh ou l d b ran ch to the i nt err up t so urce an d

read the corresponding Data Link Status Registers (address

0xNB06, 0xNB16, 0xNB2 6, 0xNB10, 0xNB18, 0xNB28) to clear the

interrupt.

NOTE: This bit will be reset to 0 after the microprocessor has

performed a read to the corresponding Data Link Status

Registers that generated the interrupt.

XRT86VX38

108

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

2SLIP RO 0 Slip Buffer Block Interrupt St atus

This bit indicates whether or not the Slip Buffer block has any out-

standing interrupt request awaiting service.

0 = Indicates no outstanding Slip Buffer Block interrupt request is

awaiting service

1 = Indicates Slip Buffer block has an interrupt request awaiting ser-

vice. Interrupt Service routine should branch to the interrupt source

and read the Slip Buffer Interrupt Status register (address 0xNB08)

to clear the interrupt

NOTE: This bit will be reset to 0 after the microprocessor has

performed a read to the Slip Buffer Interrupt Status

1 ALARM RO 0 Alarm & Error Bloc k Interrupt Status

This bit indicates whether or not the Alarm & Error Block has any

outstanding interrupt request awaiting service.

0 = Indicates no outstanding interrupt request is awaiting service

1 = Indicates the Alarm & Error Block has an interrupt request await-

ing service. Interrupt service routine should branch to the interrupt

source and read the corresponding alarm an d error status registers

(address 0xNB02, 0xNB0E, 0xNB40) to clear the interrupt.

NOTE: This bit will be reset to 0 after the microprocessor has

performed a read to the corresponding Alarm & Error

Interrupt Status register that generated the interrupt.

0E1 FRAME RO 0 E1 Framer Block Interrupt Status

This bit indicates whether or not the E1 Framer block has any out-

standing interrupt request awaiting service.

0 = Indicates no outstanding interrupt request is awaiting service.

1 = Indicates the E1 Framer Block has an interrupt request awaiting

service. Interrupt service routine should branch to the interrupt

source and read the E1 Framer status register (address 0xNB04) to

clear the interrupt

NOTE: This bit will be reset to 0 after the microprocessor has

performed a rea d to th e E1 Framer Interrupt Status regist er.

TABLE 108: BLOCK INTERRUPT STATUS REGISTER (BISR) HEX ADDRESS: 0XNB00

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

109

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 109: BLOCK INTERRUPT ENABLE REGISTER (BIER) HEX ADDRESS: 0XNB01

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 SA6_ENB R/W 0 SA6 Block interrupt enable

This bit permits the user to either enable or disable the SA 6 Block

for interrupt generation.

If the user writes a “0” to this register bit and disables the SA 6 Block

for interrupt generation, then all SA 6 interrupts will be disabled for

interrupt generation.

If the user writes a “1” to this register bit, the SA6 Block interrupt at

the “Block Level” will be enabled. However , the individual SA 6 inter-

rupts at the “Source Level” still need to be enabled in order to gener-

ate that particular interrupt to the interrupt pin.

0 - Disables all SA6 Block interrupt within the device.

1 - Enables the SA6 interrupt at the “Block-Level”.

6 Reserved For T1 mode only

5 RXCLKLOSS R/W 0 Loss of Recovered Clock Interrupt Enable

This bit permits the user to either enable or disable the Loss of

Recovered Clock Interrupt for interrupt generation.

0 - Disables the Loss of Recovered Clock Interrupt within the device.

1 - Enables the Loss of Recovered Clock interrupt at the “Source-

Level”.

4 ONESEC_ENB R/W 0 One Second Interrupt Enable

This bit permits the user to either enable or disable the One Second

Interrupt for interrupt generation.

0 - Disables the One Second Interru pt within the device.

1 - Enables the One Second interrupt at the “Source-Level”.

3 HDLC_ENB R/W 0 HDLC Block Interrupt Enable

This bit permits the user to either enable or disable the HDLC Block

for interrupt generation.

If the user writes a “0” to this register bit and disables the HDLC

Block for interrupt generation, then all HDLC interrupts will be dis-

abled for interrupt generation.

If the user writes a “1” to this register bit, the HDLC Block interrupt at

the “Block Level” will be enabled. However, the individual HDLC

interrupts at the “Source Level” still need to be enabled in order to

generate that particular interrupt to the interrupt pin.

0 - Disables all SA6 Block interrupt within the device.

1 - Enables the SA6 interrupt at the “Block-Level”.

2 SLIP_ENB R/W 0 Sl ip Buffer Block Interrup t Enable

This bit permits the user to either enable or disable the Slip Buffer

Block for interrupt generation.

If the user writes a “0” to this register bit and disables the Slip Buffer

Block for interrupt generation, then all Slip Buffer interrupts will be

disabled for inte rrupt generation.

If the user writes a “1” to this register bit, the Slip Buffer Block inter-

rupt at the “Block Level” will be enabled. However, the individual Slip

Buffer interrupts at the “Source Level” still need to be enabled in

order to generate that particular interrupt to the interrupt pin.

0 - Disables all Slip Buffer Block interrupt within the device.

1 - Enables the Slip Buffer interrupt at the “Block-Level”.

XRT86VX38

110

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

1 ALARM_ENB R/W 0 Alarm & Error Block Interrupt Enable

This bit permits the user to either enable or disable the Alarm &

Error Block for interrupt generation.

If the user writes a “0” to this register bit and disables the Alarm &

Error Block for interrupt generation, then all Alarm & Error interrupts

will be disabled for interrupt generation.

If the user writes a “1” to this register bit, the Alarm & Error Block

interrupt at the “Block Level” will be enabled. However , the individual

Alarm & Error interrupts at the “Source Level” still need to be

enabled in order to generate that particular interrupt to the interrupt

pin.

0 - Disables all Alarm & Error Block interrupt within the device.

1 - Enables the Alarm & Error interrupt at the “Block-Level”.

0 E1FRAME_ENB R/W 0 E1 Framer Block Enable

This bit permits the user to either enable or disable the E1 Framer

Block for interrupt generation.

If the user writes a “0” to this register bit and disables the E1 Framer

Block for interrupt generation, then all E1 Framer interrupts will be

disabled for inte rrupt generation.

If the user writes a “1” to this register bit, the E1 Framer Block inter-

rupt at the “Block Level” will be enabled. However, the individual E1

Framer interrupts at the “Source Level” still need to be enabled in

order to generate that particular interrupt to the interrupt pin.

0 - Disables all E1 Framer Block interrupt within the device.

1 - Enables the E1 Framer interrupt at the “Block-Level”.

TABLE 109: BLOCK INTERRUPT ENABLE REGISTER (BIER) HEX ADDRESS: 0XNB01

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

111

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 110: ALARM & ERROR INTERRUPT STATUS REGISTER (AEISR) HEX ADDRESS: 0XNB02

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7Rx OOF State RO 0 Receive Out of Frame Defect State

This READ-ONLY bit indicates whether or not the Receive E1 Framer block

is currently declaring the “Out of Frame” defect condition within the incom-

ing E1 data-stream, as described below.

Out of Frame defect condition is declared when “FASC” number of consecu-

tive errored FAS patterns are detected, where “FASC” indicates the Loss of

FAS Alignment Criteria in the Fra ming Control Register (0xN10B), bit 2-0.

0 – The Receive E1 Framer block is NOT currently declaring the “Out of

Frame” defect cond i ti o n.

1 – The Receive E1 Framer block is currently declaring the “Ou t of Frame”

defect condition.

6RxAIS State RO 0 Receive Alarm Indication St atus Defect State

This READ-ONLY bit indicates whether or not the Receive E1 Framer block

is currently declaring the AIS defect condition within the incoming E1 data-

stream, as described below.

AIS defect is declared when AIS condition persists for 250 microseconds (2

frames). AIS defect is cleared when more than 2 zeros are detected in two

consecutive frames (250us)

0 – The Receive E1 Framer block is NOT currently declaring the AIS defect

condition.

1 – The Receive E1 Framer block is currently declaring the AIS defect con-

dition.

5 RxMYEL Status RUR/

WC 0Change of CAS Multiframe Yellow Alarm Interrupt Status.

This Reset-Upon-Read bit field indicates whether or not the CAS multiframe

yellow alarm interrupt has occurred since the last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will gene rate

an interrupt in response to either one of the following conditions.

1. Whenever the Receive E1 Framer block declares the CAS Multiframe

Yellow Alarm.

2. Whenever the Receive E1 Framer block clears the CAS Multiframe

Yellow Alarm

CAS Multiframe Yellow Alarm is declared whenever the received ‘y’ bit in

Time Slot 16 of Frame 0 is set to ‘1’.

0 = Indicates that the “Change of CAS Multiframe Yellow Alarm” interrupt

has not occurred since the last read of this register.

1 = Indicates that the “Change of CAS Multiframe Yellow Alarm” interrupt

has occurred since the last read of this register.

4 LOS State RO 0 Framer Receive Loss of Signal (LOS) State

This READ-ONLY bit indicates whether or not the Receive E1 framer is cur-

rently declaring the Loss of Signal (LOS) condition within the incoming DS1

data-stream, as described below

LOS defect is declared when LOS condition persists for 175 consecutive

bits. LOS defect is cleared when LOS condition is absent or when the

received signal reaches a 12.5% ones den sity for 175 consecutive bits.

0 = The Receive DS1 Framer block is NOT currently declaring the Loss of

Signal (LOS) condition.

1 = The Receive DS1 Framer block is currently declaring the Loss of Signal

(LOS) condition.

XRT86VX38

112

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3 LCV Int Status RUR/

WC 0Line Code Violation Interrupt Status.

This Reset-Upon-Read bit field indicates whether or not the Receive E1 LIU

block has detected a Line Code Violation interrupt since the last read of this

0 = Indicates that the Line Code Violation interrupt has not occurred since

the last read of this register.

1 = Indicates that the Line Code Violation interrupt has occurred since the

last read of this register.

2 Rx OOF State

Change RUR/

WC 0Change in Out of Frame Defect Condition Interrupt Status.

This Reset-Upon-Read bit field indicates whether or not the “Change in

Receive Out of Frame Defect Conditi on” interrupt has occurred since the

last read of this register.

Out of Frame defect condition is declared when “F ASC” number of consecu-

tive errored FAS p a tterns are dete cted, where “FASC” indicates the Loss of

FAS Alignment Criteria in the Fra ming Control Register (0xN10B), bit 2-0.

If this interrupt is enabled, then the Receive E1 Framer block will generate

an interrupt in response to either one of the following conditions.

1. Whenever the Receive E1 Framer block declares the Out of Frame

defect condition.

2. Whenever the Receive E1 Framer block clears the Out of Frame

defect condition

0 = Indicates that the “Change in Receive Out of Frame defect condition”

interrupt has not occurred since the last read of this register

1 = Indicates that the “Change in Receive Out of Frame defect condition”

interrupt has occurre d since the last read of this register

1 RxAIS State

Change RUR/

WC 0Change in Receive AIS Condition In terrupt Status.

This Reset-Upon-Read bit field indicates whether or not the “Change in

Receive AIS Condition” interrupt has occurred since the last read of this reg-

ister.

If this interrupt is enabled, then the Receive E1 Framer block will generate

an interrupt in response to either one of the following conditions.

1. Whenever the Receive E1 Framer block declares the AIS condition.

2. Whenever the Receive E1 Framer block clears the AIS condition

0 = Indicates that the “Change in Receive AIS condition” interrupt has not

occurred since the last read of this register

1 = Indicates that the “Change in Receive AIS condition” interrupt has

occurred since the last read of this register

TABLE 110: ALARM & ERROR INTERRUPT STATUS REGISTER (AEISR) HEX ADDRESS: 0XNB02

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

113

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

0 RxYEL State

Change RUR/

WC 0Change in Receive Yellow Alarm Interrupt Status.

This Reset-Upon-Read bit field indicates whether or not the “Change in

Receive Yellow Alarm Condition” interrupt has occurred since the last read

of this register.

If this interrupt is enabled, then the Receive E1 Framer block will gene rate

an interrupt in response to either one of the following conditions.

1. Whenever the Receive E1 Framer block declares the Yellow Alarm

condition.

2. Whenever the Receive E1 Framer block clears the Yellow Alarm

condition

0 = Indicates that the “Change in Receive Yellow Alarm condition” interrupt

has not occurred since the last read of this register

1 = Indicates that the “Change in Receive Yellow Alarm condition” interrupt

has occurred since the last read of this register

TABLE 110: ALARM & ERROR INTERRUPT STATUS REGISTER (AEISR) HEX ADDRESS: 0XNB02

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

114

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 111: ALARM & ERROR INTERRUPT ENABLE REGISTER (AEIER) HEX ADDRESS: 0XNB03

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Rx_YEL_STATE RO 0 Receive Ye llow Alarm S tate

This READ-ONL Y bit indicates whether or not the Receive E1 Framer block

is currently declaring the Yellow Alarm condition within the incoming E1

data-stream, as described below.

Yellow alarm or Remote Alarm Indication (RAI) is declared when the ‘A’ bit

of two consecutive non-FAS frames is set to ‘1’, which is equi valent to tak-

ing 375us to declare a RAI condition. Yellow alarm is cleared when the ‘A’

bit of two consecutive non-FAS frame s is set to 0, which is equivalent to

taking 375us to clear a RAI condition.

0 – The Receive E1 Framer block is NOT currently declaring the Yellow

Alarm condition.

1 – The Receive E1 Framer block is currently declaring the Yellow Alarm

condition.

6 Reserved - - Reserved

5 RxMYEL ENB R/W 0 Change of CAS Multiframe Yellow Alarm Interrupt Enable.

This bit permits the user to either enable or disable the “Change in CAS

Multiframe Yellow Alarm”

Interrupt, within the XRT86VX38 device. If the user enables this interrupt,

then the Receive E1 Framer block will generate an interrupt in response to

either one of the following conditions.

1. The instant that the Receive E1 Framer block declares CAS

Multiframe Yellow Alarm.

2. The instant that the Receive E1 Framer block clears the CAS

Multiframe Yellow Alarm.

0 – Disables the “Change in CAS Multiframe Yellow Alarm” Interrupt.

1 – Enables the “Change in CAS Multiframe Yellow Alarm” Interrupt.

4- R/W 0 This bit should be set to’0’ for proper operation.

3 LCV ENB R/W 0 Line Code violation interrupt enable

This bit permits the user to either enable or disable the “Line Cod e Viola-

tion” interrupt within the XRT86VX38 device. If the user enables this inter-

rupt, then the Receive E1 Framer block will generate an interrupt when

Line Code Violation is detected.

0 = Disables the interrupt generation when Line Code Violation is detected.

1 = Enables the interrupt generation when Line Code Violation is detected.

2 RxOOF ENB R/W 0 Change in Out of Frame Defect Condition Interrupt enable

This bit permits the user to either enable or disable the “Change in Out of

Frame Defect Condition” Interrupt, within the XRT86VX38 device. If the

user enables this interrupt, then the Receive E1 Framer block will generate

an interrupt in response to either one of the fol lowing conditions.

1. The instant that the Receive E1 Framer block declares the Out of

Frame defect condition.

2. The instant that the Receive E1 Framer block clears the Out of

Frame defect condition.

0 – Disables the “Change in Out of Frame Defect Condition” Interrupt.

1 – Enables the “Change in Out of Frame Defect Condition” Interrupt.

XRT86VX38

115

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

1 RxAIS ENB R/W 0 Change in AIS Condition interrupt enable

This bit permits the user to either enable or disable the “Change in AIS

Condition” Interrupt, within the XRT86VX38 device. If the user enables this

interrupt, then the Receive E1 Framer block will generate an interrupt in

response to either one of the following conditions.

1. The instant that the Receive E1 Framer block declares the AIS

condition.

2. The instant that the Receive E1 Framer block clears the AIS

condition.

0 – Disables the “Change in AIS Condition” Interrupt.

1 – Enables the “Change in AIS Condition” Interrupt.

0 RxYEL ENB R/W 0 Change in Yellow alarm Condition interrupt enable

This bit permits the user to either enable or disable the “Change in Yellow

Alarm Condition” Interrupt, within the XRT86VX38 device. If the user

enables this interrupt, then the Receive E1 Framer block will generate an

interrupt in response to either one of the following conditions.

1. The instant that the Receive E1 Framer block declares the Yellow

Alarm condition.

2. The instant that the Receive E1 Framer block clears the Yellow

Alarm condition.

0 – Disables the “Change in Yellow Alarm Condition” Interrupt.

1 – Enables the “Change in Yellow Alarm Condition” Interrupt.

TABLE 111: ALARM & ERROR INTERRUPT ENABLE REGISTER (AEIER) HEX ADDRESS: 0XNB03

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

116

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 112: FRAMER INTERRUPT STATUS REGISTER (FISR) HEX ADDRESS: 0XNB04

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 COMFA Status RUR/

WC 0Change of CAS Multiframe Alignment Interrupt Status

This Reset-Upon-Read bit field indicates whether or not the “Change of

CAS multiframe alignment” interrupt has occurred since the last read of

this register.

If this interrupt is enabled, then the Receive E1 Framer block will generate

an interrupt in response to either one of the following conditions.

1. Whenever the Receive E1 Framer bl ock declares the “Loss of CAS

Multiframe Alignment”.

2. Whenever the Receive E1 Framer block clears the “Loss of CAS

Multiframe Alignment”

Loss CAS Multiframe Alignment is declared when the “CASC” number of

consecutive CAS Multiframe Alignment signals have been received in

error, where CASC sets the criteria for Loss of CAS multiframe. CASC can

ben programmed through Framing Control Register (FCR - addre ss

0xN10B, bit 6-5)

0 = Indicates that the “Change of CAS Multiframe Alignment” interrupt has

not occurred since the last read of this register.

1 = Indicates that the “Change of CAS Multiframe Alignment” interrupt has

occurred since the last read of this register.

NOTES: This bit only has meaning when Channel Associated Signaling

(CAS) is enabled.

6 NBIT Status RUR/

WC 0Change in National Bits Interrupt Status

This Reset-Upon-Read bit field indicates whether or not the “Change in

National Bits” interrupt has occurred since the last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt whenever any one of the National Bits (Sa4-Sa8)

within the incoming non-FAS E1 frames has changed.

0 = Indicates that the “Change in National Bits” interrupt has not occurred

since the last rea d of thi s reg i ste r.

1 = Indicates that the “Change in National Bits” interrupt has occu rred

since the last rea d of thi s reg i ste r.

5 SIG Status RUR/

WC 0Change in CAS Signaling Bits Interrupt Status

This Reset-Upon-Read bit field indicates whether or not the “Change in

CAS Signaling Bits” interrupt has occurred since the last read of this regis-

ter.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt whenever any one of the four signaling bits values

(A,B,C,D) has changed in any one of the 30 channels within the incoming

E1 frames. Users can read the signaling change registers (address

0xN10D-0xN110) to determine which signalling channel has changed.

0 = Indicates that the “Change in CAS Signaling Bits” interrupt has not

occurred since the last read of this register.

1 = Indicates that the “Change in CAS Signaling Bits” interrupt has

occurred since the last read of this register.

NOTE: This bit only has meaning when Channel Associated Signaling

(CAS) is enabled.

XRT86VX38

117

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

4 COFA Status RUR/

WC 0Change of FAS Framing Alig nment (COFA) Interru pt Status

This Reset-Upon-Read bit field indicates whether or not the “Change of

FAS Framing Alignment” interrupt has occurred since the last read of this

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt whenever the Receive E1 Framer block detects a

Change of FAS Framing Align ment Signal (e.g., the FAS bits have

appeared to move to a different location within the incoming E1 data

stream).

0 = Indicates that the “Change of FAS Framing Alignment (COFA)” inter-

rupt has not occurred since the last read of this register.

1 = Indicates that the “Change of FAS Framing Alignment (COFA)” inter-

rupt has occurred since the last read of this register.

3 OOF Status RUR/

WC 0Change in Out of Frame Defect Condition Interrupt Status.

This Reset-Upon-Read bit field indicates whether or not the “Change in

Receive Out of Frame Defect Conditi on” interrupt has occurred since the

last read of this register.

Out of Frame defect condition is declared when “F ASC” number of consec-

utive errored FAS patterns are detected, where “FASC” indicates the Loss

of FAS Alignment Criteria in the Framing Control Register (0xN10B), bit 2-

If this interrupt is enabled, then the Receive E1 Framer block will generate

an interrupt in response to either one of the following conditions.

1. Whenever the Receive E1 F ramer block declares the Out of Frame

defect condition.

2. Whenever the Receive E1 Framer block clears the Out of Frame

defect condition

0 = Indicates that the “Change in Receive Out of Frame defect condition”

interrupt has not occurred since the last read of this register

1 = Indicates that the “Change in Receive Out of Frame defect condition”

interrupt has occurre d since the last read of this register

2 FMD Status RUR/

WC 0Frame Mimic Detection Interrupt Status

This Reset-Upon-Read bit field indicates whether or not the “Frame Mimic

Detection” interrupt has occurred since the last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt whenever the Receive E1 Framer block detects the

presence of Frame Mimic bits (i.e., the Payload bits have appeared to

mimic the Framing pattern within the incoming E1 data stream).

0 = Indicates that the “Frame Mimic Detection” interrupt has not occurred

since the last rea d of thi s reg i ste r.

1 = Indicates tha t the “Frame Mimic Detectio n” interrupt has occurr ed since

the last read of this register.

TABLE 112: FRAMER INTERRUPT STATUS REGISTER (FISR) HEX ADDRESS: 0XNB04

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

118

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

1 Sync Error Status RUR/

WC 0CRC-4 Error Interrupt Status.

This Reset-Upon-Read bit field indicates whether or not the “CRC-4 Error”

interrupt has occurre d since the last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt whenever the Receive E1 Framer block detects a

CRC-4 Error within the incoming E1 sub-multiframe.

0 = Indicates that the “CRC-4 Error” interrupt has not occurred since the

last read of this register.

1 = Indicates that the “CRC-4 Error” interrupt has occu rred since the last

read of this register.

0 Framing Error Sta-

tus RUR/

WC 0Framing Error Interrupt Status

This Reset-Upon-Read bit field indicates whether or not a “Framing Error”

interrupt has occurre d since the last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt whenever the Receive E1 Framer block detects one

or more Framing Alignment Bit Error within the incoming E1 data stream.

0 = Indicates that the “Framing Error” interrupt has not occurred since the

last read of this register.

1 = Indicates that the “Framing Error” interrupt has occurred since the last

read of this register.

NOTE: This bit doesn't not necessarily indicate that synchronization has

been lost.

TABLE 112: FRAMER INTERRUPT STATUS REGISTER (FISR) HEX ADDRESS: 0XNB04

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

119

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 113: FRAMER INTERRUPT ENABLE REGISTER (FIER) HEX ADDRESS: 0XNB05

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7COMFA ENB R/W 0 Change in CAS Multiframe Alignment Interrupt Enable

This bit permits the user to either enab le or disable the “Change in CAS

Multiframe Alignment” Interrupt, within the XRT86VX38 device. If the user

enables this interrupt, then the Receive E1 Framer block will generate an

interrupt in response to either one of the following conditions.

1. The instant that the Receive E1 Framer block declares the Loss of

CAS Multiframe Alignment condition.

2. The instant that the Receive E1 Framer block clears the Loss of

CAS Multiframe Alignment condition.

0 – Disables the “Change in CAS Multiframe Alignment” Interrupt.

1 – Enables the “Change in CAS Multiframe Alignment” Interrupt.

6 NBIT ENB R/W 0 Change in National Bits Interrupt Enable

This bit permits the user to either enable or disable the “Change in

National Bits” Interrupt, within the XRT86VX38 device. If the user enables

this interrupt, then the Receive E1 Framer block will generate an interrupt

when it detects a change in the National Bits (Sa4-Sa8) within the channel.

0 = Disables the Change in National Bits Interrupt

1 - Enables the Change in National Bits Interrupt

5 SIG ENB R/W 0 Change in CAS Signaling Bits Interrupt Enable

This bit permits the user to either enab le or disable the “Change in CAS

Signaling Bits” Interrupt, within the XRT86VX38 device. If the user enables

this interrupt, then the Receive E1 Framer block will generate an interrupt

when it detects a change in the any four signaling bits (A,B,C,D) in any one

of the 30 signaling channels. Users can read the signaling change regis-

ters (address 0xN10D-0xN110) to determine which signalling channel has

changed state.

0 = Disables the Change in Signali ng Bits Interrupt

1 - Enables the Change in Signaling Bits Interrupt

NOTE: This bit has no meaning when Channel Associated Signaling is

disabled.

4 COFA ENB R/W 0 Change of FAS Framing Alignment (COFA) Interrupt Enable

This bit permits the user to either enab le or disable the “Change in FAS

Framing Alignment (COF A)” Interrupt, within the XRT86VX38 device. If the

user enables this interrupt, then the Receive E1 Framer block will generate

an interrupt when it detects a Change of FAS Framing Alignment Signal

(e.g., the FAS bits have appeared to move to a different location within the

incoming E1 data stream).

0 – Disables the “Change of FAS Framing Alignment (COFA)” Interrupt.

1 – Enables the “Change of FAS Framing Alignment (COFA)” Interrupt.

XRT86VX38

120

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3 OOF ENB R/W 0 Change in Out of Frame Defect Condition interrupt enable

This bit permits the user to either enab le or disable the “Change in Out of

Frame Defect Condition” Interrupt, within the XRT86VX38 device. If the

user enables this interrupt, then the Receive E1 Framer block will generate

an interrupt in response to either one of the following condition s.

1. The instant that the Receive E1 Framer block declares the Out of

Frame defect condition.

2. The instant that the Receive E1 Framer block clears the Out of

Frame defect condition.

0 – Disables the “Change in Out of Frame Defect Condi tion” Interrupt.

1 – Enables the “Change in Out of Frame Defect Condition” Interrupt.

2FMD ENB R/W 0 Frame Mimic Detection Interrupt Enable

This bit permits the user to either enable or disable the “Frame Mimic

Detection” Interrupt, within the XRT86VX38 device. If the user enables this

interrupt, then the Receive E1 Framer block will generate an interru pt

when it detects the presence of Frame mimic bits (i.e., the payload bits

have appeared to mimic the framing bit pattern within the incoming E1

data stream).

0 – Disables the “Frame Mimic Dete ction” Interrupt.

1 – Enables the “Frame Mimic Detection” Interrupt.

1 SE_ENB R/W 0 Sync hronization Bit (CRC-4) Error Interrupt Enable

This bit permits the user to either enable or disable the “CRC-4 Error

Detection” Interrupt, within the XRT86VX38 device. If the user enables this

interrupt, then the Receive E1 Framer block will generate an interru pt

when it detects a CRC-4 error within the incoming E1 sub-multiframe.

0 – disable the “CRC-4 Error Detectio n” Interrupt.

1 – enable the “CRC-4 Error Detection” Interrupt.

0 FE_ENB R/W 0 Framing Bit Error Interrupt Enable

This bit permits the user to either enable or disable the “Framing Alignment

Bit Error Detection” Interrupt, within the XRT86VX38 device. If the user

enables this interrupt, then the Receive E1 Framer block will generate an

interrupt when it detects one or more Framing Alignment Bit error within

the incoming E1 data stream.

0 – disable the “Framing Alignment Bit Error Detection” Interrupt.

1 – enable the “Framing Alignment Bit Error Detectio n” Interrupt.

NOTE: Detecting Framing Alignment Bit Error doesn't not necessarily

indicate that synchronization has been lost.

TABLE 113: FRAMER INTERRUPT ENABLE REGISTER (FIER) HEX ADDRESS: 0XNB05

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

121

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 114: DATA LINK STATUS REGISTER 1 (DLSR1) HEX ADDRESS: 0XNB06

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 MSG TYPE RO 0 HDLC1 Message Type Identifier

This READ ONLY bit indicates the type of data link message

received by Receive HDLC 1 Controller. Two types of data link mes-

sages are supported within the XRT86VX38 device: Message Ori-

ented Signaling (MOS) or Bit-Oriente d Signalling (BOS).

0 = Indicates Bit-Oriented Signaling (BOS) type data link message is

received

1 = Indicates Message Oriented Signaling (MOS) type data link

message is received

6 TxSOT RUR/

WC 0Transmit HDLC1 Controller Start of Transmission (TxSOT)

Interrupt Status

This Reset-Upon-Read bit indicates whether or not the “Transmit

HDLC1 Controller Start of Transmission (TxSOT) “Interrupt has

occurred since the last read of this register . Transmit HDLC1 Con-

troller will declare this interrupt when it has started to transmit a data

link message. For sending large HDLC messages, start loading the

next available buffer once this interrupt is detected.

0 = Transmit HDLC1 Controller Start of Transmission (TxSOT) inter-

rupt has not occurred since the last read of this register

1 = Transmit HDLC1 Controller Start of Transmission interrupt

(TxSOT) has occurred since the last read of this register.

5 RxSOT RUR/

WC 0Receive HDLC1 Controller St art of Reception (RxSOT) Interrupt

Status

This Reset-Up on -R e ad bi t in d i cat e s wh ether or not the Recei ve

HDLC1 Controller Start of Reception (RxSOT) interrupt has

occurred since the last read of this register. Receive HDLC1 Con-

troller will declare this interrupt when it has started to receive a data

link message.

0 = Receive HDLC1 Controller S t art of Reception (RxSOT) interrupt

has not occurred since the last read of this register

1 = Receive HDLC1 Controller S t art of Reception (RxSOT) interrupt

has occurred since the last read of this register

4 TxEOT RUR/

WC 0Transmit HDL C1 Controller End of Transmission (TxEOT) Inter-

rupt Status

This Reset-Upon-Read bit indicates whether or not the Transmit

HDLC1 Controller End of Transmission (TxEOT) Interrupt has

occurred since the last read of this register . Transmit HDLC1 Con-

troller will declare this interrupt when it has completed its transmis-

sion of a data link message. For sending large HDLC messages, it

is critical to load the next available buffer before this interrupt

occurs.

0 = Transmit HDLC1 Controller End of Transmission (TxEOT) inter-

rupt has not occurred since the last read of this register

1 = Transmit HDLC1 Controller End of Transmission (TxEOT) inter-

rupt has occurred since the last read of this register

XRT86VX38

122

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3 RxEOT RUR/

WC 0Receive HDLC1 Controller End of Reception (RxEOT) Interrupt

Status

This Reset-Up on -R e ad bi t in d i cat e s wh ether or not the Recei ve

HDLC1 Controller End of Reception (RxEOT) Interrupt has occurred

since the last read of this register. Receive HDLC 1 Controller will

declare this interrupt once it has completely received a full data link

message, or once th e bu ffer is full.

0 = Receive HDLC1 Controller End of Reception (RxEOT) interrupt

has not occurred since the last read of this register

1 = Receive HDLC1 Controller End of Reception (RxEOT) Interrupt

has occurred since the last read of this register

2 FCS Error RUR/

WC 0FCS Error Interrupt Status

This Reset-Upon -R e ad bit in d i cates whether or not th e FCS Error

Interrupt has occurred since the last read of this register. Receive

HDLC1 Controller will declare this interrupt when it has detected the

FCS error in the most recently received data link message.

0 = FCS Error interrupt has not occurre d si nce the la st re ad of th i s

1 = FCS Error interrupt has occurred since the last read of this regis-

ter

1 Rx ABORT RUR/

WC 0Receipt of Abort Sequence Inte rrupt Status

This Reset-Up on -R e ad bi t in d i cates whether or not th e Receipt of

Abort Sequence interrupt ha s occurred since last read of this regis-

ter. Receive HDLC1 Controlle r will declare this interrupt if it detects

the Abort Sequence (i.e. a string of seven (7) consecutive 1’s) in the

incoming data link channel.

0 = Receipt of Abort Sequence interrupt has not occurred since last

read of this register

1 = Receipt of Abort Sequence interrupt has occurre d since last

read of this register

0 RxIDLE RUR/

WC 0Receipt of Idle Sequen ce Interrupt Status

This Reset-Up on -R e ad bi t in d i cates whether or not th e Receipt of

Idle Sequence interrupt has occurred since the last read of this reg-

ister. The Receive HDLC1 Controller will declare this interrupt if it

detects the flag sequence octet (0x7E) in the incoming data link

channel. If RxIDLE "AND" RxEOT occur together, th en the entire

HDLC message has been receive d.

0 = Receipt of Idle Sequence interrupt has not occurred since last

read of this register

1 = Receipt of Idle Sequence interrupt has occurred since last read

of this register.

TABLE 114: DATA LINK STATUS REGISTER 1 (DLSR1) HEX ADDRESS: 0XNB06

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

123

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 115: DATA LINK INTERRUPT ENABLE REGISTER 1 (DLIER1) HEX ADDRESS: 0XNB07

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved - - Reserved

6 TxSOT ENB R/W 0 Transmit HDLC1 Controller Start of Transmission (TxSOT)

Interrupt Enable

This bit enables or disables the “Transmit HDLC1

Controller Start of Transmission (TxSOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Transmit

HDLC1 Controller will generate an interrupt when it has started to

transmit a data link message.

0 = Disables the Transmit HDLC1 Controller Start of Tra nsmission

(TxSOT) interrupt.

1 = Enables the Transmit HDLC1 Controller Start of Transmission

(TxSOT) interrupt.

5 RxSOT ENB R/W 0 Receive HDLC1 Controller Start of Reception (RxSOT) Interrupt

Enable

This bit enables or disables the “Receive HDLC1

Controller Start of Reception (RxSOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Receive

HDLC1 Controller will generate an interrupt when it has started to

receive a data link message.

0 = Disables the Receive HDLC1 Controller Start of Reception

(RxSOT) interrupt.

1 = Enables the Receive HDLC1 Controller Start of Reception

(RxSOT) interrupt.

4 TxEOT ENB R/W 0 Transmit HDL C1 Controller End of Transmission (TxEOT) Inter-

rupt Enable

This bit enables or disables the “Transmit HDLC1

Controller End of Transmission (TxEOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Transmit

HDLC1 Controller will generate an interrupt when it has finished

transmitting a data link message.

0 = Disables the Transmit HDLC1 Controller End of Transmission

(TxEOT) interrupt.

1 = Enables the Transmit HDLC1 Controller End of Transmission

(TxEOT) interrupt.

3 RxEOT ENB R/W 0 Re ceive HDLC1 Controller End of Reception (RxEOT) Interrupt

Enable

This bit enables or disables the “Receive HDLC1

Controller End of Reception (RxEOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Receive

HDLC1 Controller will generate an interrupt when it has finished

receiving a complete data link message.

0 = Disables the Receive HDLC1 Controller End of Reception

(RxEOT) interrupt.

1 = Enables the Receive HDLC1 Controller End of Reception

(RxEOT) interrupt.

XRT86VX38

124

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

2 FCS ERR ENB R/W 0 FCS Error Interrupt Enable

This bit enables or disables the “Received FCS Erro r “Interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

Receive HDLC1 Controller will generate an interrupt when it has

detected the FCS error within the incoming data link messag e.

0 = Disables the “Receive FCS Error” interrupt.

1 = Enables the “Receive FCS Error” interrupt.

1 RxABORT ENB R/W 0 Receipt of Ab ort Sequence Interrupt Enable

This bit enables or disables the “Receipt of Abort Sequence“ Inter-

rupt within the XRT86VX38 device. Once this interrupt is enabled,

the Receive HDLC1 Controller will generate an interrupt when it has

detected the Abort Sequence (i.e. a string of seven (7) consecutive

1’s) within the incoming data link channel.

0 = Disables the “Receipt of Abort Sequence” interrupt.

1 = Enables the “Receipt of Abort Sequence” interrupt.

0 RxIDLE ENB R/W 0 Receipt of Idle Sequence Interrupt Enable

This bit enables or disables the “Receipt of Idle Sequence“ Interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

Receive HDLC1 Controller will generate an interrupt when it has

detected the Idle Sequence Octet (i.e. 0x7E) within the incoming

data link channel.

0 = Disables the “Receipt of Idle Sequence” inte rrupt.

1 = Enables the “Receipt of Idle Sequence” in terrupt.

TABLE 115: DATA LINK INTERRUPT ENABLE REGISTER 1 (DLIER1) HEX ADDRESS: 0XNB07

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

125

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 116: SLIP BUFFER INTERRUPT STATUS REGISTER (SBISR) HEX ADDRESS: 0XNB08

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 TxSB_FULL RUR/

WC 0Transmit Slip buffer Full Interrupt Status

This Reset-Upon-Read bit indicates whether or not the Transmit Slip

Buffer Full interrupt has occurred since the last read of this register. The

transmit Slip Buffer Full interrupt is declared when the transmit slip buffer

is filled. If the transmit slip buffer is full and a WRITE operation occurs,

then a full frame of data will be deleted, and this interrupt bit will be set to

‘1’.

0 = Indicates that the Transmit Slip Buffer Full interr up t ha s no t occurred

since the last rea d of thi s reg i ste r.

1 = Indicates that the T ransmit Slip Buffer Full interrupt has occurred since

the last read of this register.

6 TxSB_EMPT RUR/

WC 0Transmit Slip buffer Empty Interrupt St atus

This Reset-Upon-Read bit indicates whether or not the Transmit Slip

Buffer Empty interrupt has occurred since the last read of this register . The

transmit Slip Buffer Empty interrupt is declared when the transmit slip

buffer is emptied. If the transmit slip buffer is emptied and a READ opera-

tion occurs, then a full frame of data will be repeated, and this interrupt bit

will be set to ‘1’.

0 = Indicates that the Transmit Slip Buffer Empty interrupt has not

occurred since the last read of this register.

1 = Indicates that the Transmit Slip Buffer Empty interrupt has occurred

since the last rea d of thi s reg i ste r.

5 TxSB_SLIP RUR/

WC 0Transmit Slip Buffer Slips Interrupt Statu s

This Reset-Upon-Read bit indicates whether or not the Transmit Slip

Buffer Slips interrupt has occurred since the last read of this register. The

transmit Slip Buffer Slips interrupt is declared when the transmit slip buffer

is either filled or emptied. This interrupt bit will be set to ‘1’ in either one of

these two conditions:

1. If the transmit slip buffer is emptied and a READ operation occurs,

then a full frame of data will be repeated, and this interrupt bit will be

set to ‘1’.

2. If the transmit slip buffer is full and a WRITE operation occurs, then

a full frame of data will be deleted, and this interrupt bit will be set to

‘1’.

0 = Indicates that the Transmit Slip Buffer Slips interrupt has not occurred

since the last rea d of thi s reg i ste r.

1 = Indicates that the Transmit Slip Buffer Slips interrupt has occurred

since the last rea d of thi s reg i ste r.

NOTE: Users still need to read the Transmit Slip Buffer Empty Interrupt (bit

6 of this register) or the Transmit Slip Buffer Full Interrupts (bit 7 of

this register) to determine whether transmit slip buffer empties or

fills.

XRT86VX38

126

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

4 CAS SYNC RO 0 CAS Multiframe Alignment is in SYNC

This READ ONLY bit field indicates whether or not the E1 Receive Framer

Block is declaring CAS Multiframe Alignment LOCK status.

The E1 Receive Framer Block will declare the CAS Multiframe Alignment

LOCK status according to the CAS Multiframe Alignmen t Al go ri th m as

described in the Framing Select Register (FSR - ad dress 0xN107).

The E1 Receive Framer Block will declare the CAS Multiframe Alignment

LOSS OF LOCK status when CASC number of consecutive CAS Multi-

frame Alignment Signals have been received in error, where CASC sets

the Loss of CAS Multiframe Alignment Criteria, as described in the Fram-

ing Control Register (FCR - address 0xN10B).

0 = Indicates that the E1 Receive Framer Block is currently declaring CAS

Multiframe LOSS OF LOCK status

1 = Indicates that the E1 Receive Framer Block is currently declaring CAS

Multiframe LOCK status

NOTE: In E1 mode, this bit has no meaning if Channel Associated

Signaling is disabled.

3 CRCMLOCK RO 0 CRC Multiframe is in SYNC

This READ ONLY bit field indicates whether or not the E1 Receive Framer

Block is declaring the E1 CRC Multiframe Alignment LOCK status.

The E1 Receive Framer declares the CRC Multiframe Alignment LOCK

status according to the CRC Multiframe Alignment Declaration Criteria

which can be selected in the Framing Select Register (FSR - address

0xN107)

The E1 Receive Framer declares the CRC Multiframe Alignment LOSS

OF LOCK status according to the Loss CRC Multiframe Alignment Criteria

selected in the Framing Control Register (FCR - address 0xN10B )

0 = Indicates that the E1 Receive Framer is currently declaring E1 CRC

Multiframe Alignment LOSS OF LOCK status

0 = Indicates that the E1 Receive Framer is currently declaring E1 Multi-

frame Alignment LOCK status

NOTE: In E1 mode, this bit has no meaning if CRC Multiframe Alignment

is disabled.

2 RxSB_FULL RUR/

WC 0Receive Slip buffer Full Interrupt St atus

This Reset-Upon-Read bit indicates whether or not the Receive Slip Buffer

Full interrupt has occurred since the last read of this register . The Receive

Slip Buffer Full interrupt is declared when the receive slip buffer is filled. If

the receive slip buffer is full and a WRITE operation occurs, then a full

frame of data will be deleted, and this interrupt bit will be set to ‘1’.

0 = Indicates that the Receive Slip Buffer Full interrupt has not occurred

since the last rea d of thi s reg i ste r.

1 = Indicates that the Receive Slip Buffer Full interrupt has occurred since

the last read of this register.

TABLE 116: SLIP BUFFER INTERRUPT STATUS REGISTER (SBISR) HEX ADDRESS: 0XNB08

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

127

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

1 RxSB_EMPT RUR/

WC 0Receive Slip buffer Empty Interrupt Status

This Reset-Upon-Read bit indicates whether or not the Receive Slip Buffer

Empty interrupt has occurred since the last read of this register. The

Receive Slip Buffer Empty interrupt is declared when the receive slip

buffer is emptied. If the receive slip buffer is emptied and a READ opera-

tion occurs, then a full frame of data will be repeated, and this interrupt bit

will be set to ‘1’.

0 = Indicates that the Receive Slip Buffer Empty interru pt has not occurred

since the last rea d of thi s reg i ste r.

1 = Indicates that the Receive Slip Buffer Empty interrupt has occurred

since the last rea d of thi s reg i ste r.

0 RxSB_SLIP RUR/

WC 0Receive Slip Buffer Slips Interrupt Status

This Reset-Upon-Read bit indicates whether or not the Receive Slip Buffer

Slips interrupt has occurred since the last read of this register. The

Receive Slip Buffer Slips interrupt is declared when the receive slip buffer

is either filled or emptied. This interrupt bit will be set to ‘1’ in either one of

these two conditions:

1. If the receive slip buffer is emptied and a READ operation occurs,

then a full frame of data will be repeated, and this interrupt bit will be

set to ‘1’.

2. If the receive slip buffer is full and a WRITE operation occurs, then a

full frame of data will be deleted, and this interrupt bit will be set to

‘1’.

0 = Indicates that the Receive Slip Buffer Slips interrupt has not occurred

since the last rea d of thi s reg i ste r.

1 = Indicates that the Receive Slip Buffer Slips interrupt has occurred

since the last rea d of thi s reg i ste r.

NOTE: Users still need to read the Receive Slip Buffer Empty Interrupt (bit

1 of this register) or the Receive Slip Buffer Full Interrupts (bit 2 of

this register) to determine whether transmit slip buffer empties or

fills.

TABLE 116: SLIP BUFFER INTERRUPT STATUS REGISTER (SBISR) HEX ADDRESS: 0XNB08

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

128

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 117: SLIP BUFFER INTERRUPT ENABLE REGISTER (SBIER) HEX ADDRESS: 0XNB09

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 TxFULL_ENB R/W 0 Transmit Slip Buffer Full Interrupt Enable

This bit enables or disables the Transmit Slip Buffer Full interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

transmit Slip Buffer Full interrupt is declared when the transmit slip

buffer is filled. If the transmit slip buffer is full and a WRITE opera-

tion occurs, then a full frame of data will be deleted, and the interrupt

status bit will be set to ‘1’.

0 = Disables the Transmit Slip Buffer Full interrupt when the Trans-

mit Slip Buffer fills

1 - Enables the Transmit Slip Buf fer Full interrupt when the Transmit

Slip Buffer fills.

6 TxEMPT_ENB R/W 0 Transmit Slip Buffer Empty Interrupt Enable

This bit enables or disables the T ransmit Slip Buffer Empty interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

transmit Slip Buffer Empty interrupt is declared when the transmit

slip buffer is emptied. If the transmit slip buffer is emptied and a

READ operation occurs, then a full frame of data will be repeated,

and the interrupt status bit will be set to ‘1’.

0 = Disables the Transmit Slip Buffer Empty interrupt when the

Transmit Slip Buffer empties

1 - Enables the Transmit Slip Buffer Empty interrupt when the T rans-

mit Slip Buffer empties.

5 TxSLIP_ENB R/W 0 Transmit Slip Buffer Slips Interrupt Enable

This bit enables or disables the Transmit Slip Buffer Slips interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

transmit Slip Buffer Slips interrupt is declared when either the trans-

mit slip buffer is filled or emptied. If the transmit slip buffer is emptied

and a READ operation occurs, then a full frame of data will be

repeated, and the interrupt status bit will be set to ‘1’.

The interrupt status bit will be set to ‘1’ in either one of these two

conditions:

1. If the transmit slip buffer is emptied and a READ operation

occurs, then a full frame of data will be repeated, and this

interrupt bit will be set to ‘1’.

2. If the transmit slip buffer is full and a WRITE operation occurs,

then a full frame of data will be deleted, and this interrupt bit

will be set to ‘1’.

0 = Disables the T ransmit Slip Buffer Slip s interrupt when the Trans-

mit Slip Buf fe r empties or fills

1 - Enables the Transmit Slip Buffer Slips interrupt when the Trans-

mit Slip Buf fe r empties or fills.

4-3 Reserved - - Reserved

XRT86VX38

129

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

2 RxFULL_ENB R/W 0 Receive Slip Buffer Full Interrupt Enable

This bit enables or disables the Receive Slip Buffer Full interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

Receive Slip Buffer Full interrupt is declared when the receive slip

buffer is filled. If the Receive slip buffer is full and a WRITE opera-

tion occurs, then a full frame of data will be deleted, and the interrupt

status bit will be set to ‘1’.

0 = Disables the Receive Slip Buffer Full interrupt when the Transmit

Slip Buffer fills

1 - Enables the Receive Slip Buffer Full interrupt when the Transmit

Slip Buffer fills.

1 RxEMPT_ENB R/W 0 Receive Slip buffer Empty Interrupt Enable

This bit enables or disables the Receives Slip Buffer Empty interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

Receive Slip Buffer Empty interrupt is declared when the Receive

slip buffer is emptied. If the Receive slip buffer is emptied and a

READ operation occurs, then a full frame of data will be repeated,

and the interrupt status bit will be set to ‘1’.

0 = Disables the Receive Slip Buffer Empty interrupt when the

Transmit Slip Buffer empties

1 - Enables the Receive Slip Buffer Empty interrupt when the Trans-

mit Slip Buffer empties.

0 RxSLIP_ENB R/W 0 Receive Slip buffer Slips Interrupt Enable

This bit enables or disables the Receive Slip Buffer Slips interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

Receive Slip Buffer Slips interrupt is declared when either the

Receive slip buffer is filled or emptied. If the Receive slip buffer is

emptied and a READ operation occurs, then a full frame of data will

be repeated, and the interrupt status bit will be set to ‘1’.

The interrupt status bit will be set to ‘1’ in either one of these two

conditions:

1. If the Receive slip buffer is emptied and a READ operation

occurs, then a full frame of data will be repeated, and this

interrupt bit will be set to ‘1’.

2. If the Receive slip buffer is full and a WRITE operation occurs,

then a full frame of data will be deleted, and this interrupt bit

will be set to ‘1’.

0 = Disables the Receive Slip Buffer Slips interrupt when the Trans-

mit Slip Buf fe r empties or fills

1 - Enables the Receive Slip Buffer Slips interrupt when the Trans-

mit Slip Buf fe r empties or fills.

TABLE 117: SLIP BUFFER INTERRUPT ENABLE REGISTER (SBIER) HEX ADDRESS: 0XNB09

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

130

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 118: RECEIVE LOOPBACK CODE INTERRUPT AND STATUS REGISTER (RLCISR) HEX ADDRESS: 0XNB0A

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 AUXPSTAT RO 0 AUXP state

This READ ONLY bit indicates whether or not the Receive E1

Framer Block is currently detecting Auxiliary (101010....) pattern.

0 = Indicates that the Receive E1 Framer Block is NOT currently

detecting the Auxiliary (101010....)Pattern.

1 = Indicates that the Receive E1 Framer Block is currently detect-

ing the Auxiliary (101010....)Pattern.

6 AUXPINT RUR/WC 0 Change in Auxiliary Pattern interrupt Status

This Reset-Upon-Read bit field indicates whether or not the

“Change in Auxiliary Pattern” interrupt has occurred since the last

read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the Auxiliary

Pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Auxiliary Pattern

0 = Indicates that the “Change in Auxiliary Pattern” interrupt has not

occurred since the last read of this register

1 = Indicates that the “Change in Auxiliary Pattern” interrupt has

occurred since the last read of this register

5 NONCRCSTAT RO 0 CRC-4-to-non-CRC-4 interworking state

This READ ONLY bit indicates the status of CRC-4 interworking sta-

tus when Annex B is enabled. (MODENB bit in registe r 0xN 107)

When Annex B is enabled, G.706 Annex B CRC-4 multiframe align-

ment algorithm is implemented. If CRC-4 alignment is enabled and

not achieved in 400msec while the basic frame alignment signal is

present, it is assumed that the remote end is a non CRC-4 equip-

ment. Then, a CRC-to-Non-CRC interworking interrupt status will be

generated.

0 = Indicates CRC-4 to non-CRC-4 interworking is NOT established.

1 = Indicates CRC-4 to non-CRC-4 interworking is established.

XRT86VX38

131

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

4 NONCRCINT RUR/WC 0 Change of CRC-4-to-non-CRC-4 interworking interrupt Status -

This Reset-Upon-Read bit field indicates whether or not the

“Change in CRC-4 to Non-CRC-4 interworking” interrupt has

occurred since the last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the CRC-4 to

non-CRC-4 interworking condition.

2. Whenever the Receive E1 Framer block detects the non-

CRC-4 to CRC-4 interworking condition.

0 = Indicates that the “Change in CRC-4 to non-CRC-4 interworking”

interrupt has not occurred since the last read of this register

1 = Indicates that the “Change in CRC-4 to non-CRC-4 interworking”

interrupt has occurred since the last read of this register

3-0 For T1 mode only

TABLE 119: RECEIVE LOOPBACK CODE INTERRUPT ENABLE REGISTER (RLCIER) HEX ADDRESS: 0XNB0B

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

6 AUXPINTENB R/W 0 Change in Auxiliary Pattern interrupt enable

This READ WRITE bit field enables or disables the “Change in Aux-

iliary Pattern” interrupt with in the E1 Receive Framer.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the Auxiliary

Pattern.

2. Whenever the Receive E1 Framer block no longer detects

the Auxiliary Pattern

0 = Disables the “Change in Auxiliary Pattern” interrupt within the

E1 Receive Framer.

1 - Enables the “Change in Auxiliary Pattern” interrupt within the E1

Receive Framer.

5 Reserved - - Reserved

4 NONCRCENB R/W 0 Change of CRC-4-to-non-CRC-4 interworking interrupt Enable

This bit enables or disables the “Change in CRC-4 to Non-CRC-4

interworking” interrupt within the E1 Receive Framer.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the CRC-4

to non-CRC-4 interworking condition.

2. Whenever the Receive E1 Framer block detects the non-

CRC-4 to CRC-4 interworking condition.

0 = Disables the “Change in CRC-4 to non-CRC-4 interworking”

interrupt within the E1 Receive Framer.

1 - Enables the “Change in CRC-4 to non-CRC-4 interworking”

interrupt within the E1 Receive Framer.

TABLE 118: RECEIVE LOOPBACK CODE INTERRUPT AND STATUS REGISTER (RLCISR) HEX ADDRESS: 0XNB0A

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

132

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3-2 Reserved - - Reserved

1-0 Reserved For T1 mode only

TABLE 120: RECEIVE SA INTERRUPT STATUS REGISTER (RSAISR) HEX ADDRESS: 0XNB0C

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 SA6_1111 RUR/

WC 0Change in Debounced Sa6 = 1111 Interrupt Status

This Reset-Upon-Read bit field indicates whether or not the

“Change in Debounced Sa6=1111” interrupt has occurred since the

last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 1111 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 1111 pattern.

0 = Indicates that the “Change in Debounced Sa6=1111” interrupt

has not occurred since the last read of this register

1 = Indicates that the “Change in Debounced Sa6=1111” interrupt

has occurred since the last read of this register

6 SA6_1110 RUR/

WC 0Change in Debounced Sa 6 = 1110 Interrupt S tatus

This Reset-Upon-Read bit field indicates whether or not the

“Change in Debounced Sa6=1110” interrupt has occurred since the

last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 1110 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 1110 pattern.

0 = Indicates that the “Change in Debounced Sa6=1110” interrupt

has not occurred since the last read of this register

1 = Indicates that the “Change in Debounced Sa6=1110” interrupt

has occurred since the last read of this register

TABLE 119: RECEIVE LOOPBACK CODE INTERRUPT ENABLE REGISTER (RLCIER) HEX ADDRESS: 0XNB0B

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

133

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

5 SA6_1100 RUR/

WC 0Change in Debounced Sa 6 = 1100 Interru pt Status

This Reset-Upon-Read bit field indicates whether or not the

“Change in Debounced Sa6=1100” interrupt has occurred since the

last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 1100 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 1100 pattern.

0 = Indicates that the “Change in Debounced Sa6=1100” interrupt

has not occurred since the last read of this register

1 = Indicates that the “Change in Debounced Sa6=1100” interrupt

has occurred since the last read of this register

4 SA6_1010 RUR/

WC 0Change in Debounced Sa6 = 1010 Interrupt Status

This Reset-Upon-Read bit field indicates whether or not the

“Change in Debounced Sa6=1010” interrupt has occurred since the

last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 1010 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 1010 pattern.

0 = Indicates that the “Change in Debounced Sa6=1010” interrupt

has not occurred since the last read of this register

1 = Indicates that the “Change in Debounced Sa6=1010” interrupt

has occurred since the last read of this register

3 SA6_1000 RUR/

WC 0Change in Debounced Sa6 = 1000 Interrupt Status

This Reset-Upon-Read bit field indicates whether or not the

“Change in Debounced Sa6=1000” interrupt has occurred since the

last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 1000 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 1000 pattern.

0 = Indicates that the “Change in Debounced Sa6=1000” interrupt

has not occurred since the last read of this register

1 = Indicates that the “Change in Debounced Sa6=1000” interrupt

has occurred since the last read of this register

TABLE 120: RECEIVE SA INTERRUPT STATUS REGISTER (RSAISR) HEX ADDRESS: 0XNB0C

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

134

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

2 SA6_001x RUR/

WC 0Change in Debounced Sa6 = 001x Interrupt Status

This Reset-Upon-Read bit field indicates whether or not the

“Change in Debounced Sa6=001x” interrupt has occurred since the

last read of this register, where x is don’t care.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 001x pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 001x pattern.

0 = Indicates that the “Change in Debounced Sa6=001x” interrupt

has not occurred since the last read of this register

1 = Indicates that the “Change in Debounced Sa6=001x” interrupt

has occurred since the last read of this register

1 SA6_other RUR/

WC 0Debounced Sa6 = oth er Combination Interrupt Status

This Reset-Upon-Read bit field indicates whether or not the

“Change in Debounced Sa6=other combination” interrupt has

occurred since the last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt when it detects the Debounced Sa 6 equals to

any other combinations.

0 = Indicates that the “Debounced Sa6 = other combination” inter-

rupt has not occurred since the last read of this register

1 = Indicates that the “Debounced Sa6 = other combination” inter-

rupt has occurred since the last read of this register

0 SA6_0000 RUR/

WC 0Change in Debounced Sa6 = 0000 Interrupt Status

This Reset-Upon-Read bit field indicates whether or not the

“Change in Debounced Sa6=0000” interrupt has occurred since the

last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 0000 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 0000 pattern.

0 = Indicates that the “Change in Debounced Sa6=0000” interrupt

has not occurred since the last read of this register

1 = Indicates that the “Change in Debounced Sa6=0000” interrupt

has occurred since the last read of this register

TABLE 120: RECEIVE SA INTERRUPT STATUS REGISTER (RSAISR) HEX ADDRESS: 0XNB0C

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

135

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 121: RECEIVE SA I NTERRUPT ENABLE REGISTER (RSAIER) HEX ADDRESS: 0XNB0D

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 SA6_1111_ENB R/W 0 Change in Debounced Sa6 = 1111 Interrupt Enable

This bit enables or disables the “Change in Debounced Sa6=1111”

interrupt within the E1 Receive Framer.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 1111 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 1111 pattern.

0 = Disables the “Change in Debou nced Sa6=1111” interrupt within

the Receive E1 Framer Block

1 - Enables the “Change in Debounced Sa6=1111” interrupt within

the Receive E1 Framer Block

6 SA6_1110_ENB R/W 0 Change in Debounced Sa6 = 1110 Interrupt Enable

This bit enables or disables the “C hange in Debounced Sa6=1110”

interrupt within the E1 Receive Framer.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 1110 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 1110 pattern.

0 = Disables the “Change in Debounced Sa6=1110” interrupt within

the Receive E1 Framer Block

1 - Enables the “Change in Debounced Sa6=1110” interrupt within

the Receive E1 Framer Block

5 SA6_1100_ENB R/W 0 Change in Debounced Sa6 = 1100 Interrupt Enable

This bit enables or disables the “C hange in Debounced Sa6=1100”

interrupt within the E1 Receive Framer.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 1100 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 1100 pattern.

0 = Disables the “Change in Debounced Sa6=1100” interrupt within

the Receive E1 Framer Block

1 - Enables the “Change in Debounced Sa6=1100” interrup t within

the Receive E1 Framer Block

XRT86VX38

136

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

4 SA6_1010_ENB R/W 0 Change in Debounced Sa6 = 1010 Interrupt Enable

This bit enables or disables the “Change in Debounced Sa6=1010 ”

interrupt within the E1 Receive Framer.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 1010 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 1010 pattern.

0 = Disables the “Change in Debounced Sa6=1010” interrupt within

the Receive E1 Framer Block

1 - Enables the “Change in Debounced Sa6=1010” interrup t within

the Receive E1 Framer Block

3 SA6_1000_ENB R/W 0 Change in Debounced Sa6 = 1000 Interrupt Enable

This bit enables or disables the “Change in Debounced Sa6=1000 ”

interrupt within the E1 Receive Framer.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 1000 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 1000 pattern.

0 = Disables the “Change in Debounced Sa6=1000” interrupt within

the Receive E1 Framer Block

1 - Enables the “Change in Debounced Sa6=1000” interrup t within

the Receive E1 Framer Block

2 SA6_001x_ENB R/W 0 Change in Debounced Sa6 = 001x Interrup t Enable

This bit enables or disables the “Change in Debounced Sa6=001x”

interrupt within the E1 Receive Framer, where x is don’t care.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 001x pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 001x pattern.

0 = Disables the “Change in Debounced Sa6=001x” interrupt within

the Receive E1 Framer Block

1 - Enables the “Change in Debounced Sa6=001x” interrupt within

the Receive E1 Framer Block

TABLE 121: RECEIVE SA I NTERRUPT ENABLE REGISTER (RSAIER) HEX ADDRESS: 0XNB0D

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

137

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

1 SA6_other_ENB R/W 0 Debounced Sa6 = Other Combination Interrup t enable

This bit enables or disables the “Debounced Sa6=other combina-

tion” interrupt with in the E1 Receive Framer.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt when it det ects the debounced Sa6 equals to

any other combination.

0 = Disables the “Debounced Sa6=other combination” interrupt

within the Receive E1 Framer Block

1 - Enables the “Debounced Sa6=other combination” interrupt within

the Receive E1 Framer Block

0 SA6_0000_ENB R/W 0 Change in Debounced Sa6 = 0000 Interrupt Enable

This bit enables or disables the “Change in Debounced Sa6=0000 ”

interrupt within the E1 Receive Framer.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Debounced Sa6 equals to the 0000 pattern.

2. Whenever the Receive E1 Framer block no longer detects the

Debounced Sa6 equals to the 0000 pattern.

0 = Disables the “Change in Debounced Sa6=0000” interrupt within

the Receive E1 Framer Block

1 - Enables the “Change in Debounced Sa6=0 000” interrupt within

the Receive E1 Framer Block

TABLE 121: RECEIVE SA I NTERRUPT ENABLE REGISTER (RSAIER) HEX ADDRESS: 0XNB0D

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

138

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 122: EXCESSIVE ZERO STATUS REGISTER (EXZSR) HEX ADDRESS: 0XNB0E

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

5 SA7_EQ_0_STAT RO 0 Received Sa7 Equals ‘0’ State

This READ ONLY bit field indicates whether or not the Rece ive E1

Framer is currently declaring the “Sa7 Equals 0” status within the

incoming E1 National Bits.

The “Received Sa7 Equals 0” status will be set to ‘1’ if the received

Sa7 is 0 for at least 2 out of 3 times.

0 = Indicates the E1 Receive Framer is currently not declaring the

“Received Sa7 Equals 0” status.

1 = Indicates the E1 Receive Framer is currently declaring the

“Received Sa7 Equals 0” status.

4-2 Reserved - - Reserved

1 SA7_EQ_0_INT RUR/

WC 0Change in “Sa 7 Equals 0” Interru pt Status

This Reset-Upon-Read bit field indicates whether or not the

“Change in Sa7 Equals 0” interrupt has occurred since the last read

of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the Received

Sa7 equals to 0 for at least 2 out of 3 times.

2. Whenever the Receive E1 Framer block no longer detects the

Received Sa7 equals to the 0.

0 = Indicates that the “Change in Sa7 Equals 0” interrupt has not

occurred since the last read of this register

1 = Indicates that the “Change in Sa7 Equals 0” interrupt has

occurred since the last read of this register

0 EXZ_STATUS RUR/

WC 0Change in Excessive Zero Conditio n Interrupt Status

This Reset-Upon-Read bit field indicates whether or not the

“Change in Excessive Zero Condition” interrupt within the E1

Receive Framer Block has occurred since the last read of this regis-

ter.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Excessive Zero Condition.

2. Whenever the Receive E1 Framer bl ock clears the Excessive

Zero Condition

0 = Indicates the “Change in Excessive Zero Condition” interrupt

has NOT occurred since the last read of this register

1 = Indicates the “Change in Excessive Zero Condition” interrupt

has occurred since the last read of this register

XRT86VX38

139

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 123: EXCESSIVE ZERO ENABLE REGISTER (EXZER) HEX ADDRESS: 0XNB0F

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

1 SA7_EQ_0_ENB R/W 0 Change in “Sa 7 Equals 0” Interrupt Enable

This bit enables or disables the “Change in Sa7 Equals 0” interrupt

within the Receive E1 Framer.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the Received

Sa7 equals to 0 for at least 2 out of 3 times.

2. Whenever the Receive E1 Framer block no longer detects the

Received Sa7 equals to the 0.

0 = Disables the “Change in Sa7 Equals 0” interrupt within the E1

Receive Framer Block.

1 = Enables the “Change in Sa7 Equals 0” interrupt within the E1

Receive Framer Block.

0 EXZ_ENB R/W 0 Change in Excessive Zero Condition Interrupt Enable

This bit enables or disables the “Change in Excessive Zero Condi-

tion” interrupt with in the E1 Receive Framer.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block detects the

Excessive Zero Condition.

2. Whenever the Receive E1 Framer bl ock clears the Excessive

Zero Condition

0 = Disables the “Change in Excessive Zero Condition” in terrupt

within the Receive E1 Framer Block

1 - Enables the “Change in Excessive Zero Condition” interrupt

within the Receive E1 Framer Block

XRT86VX38

140

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 124: RXLOS/CRC INTERRUPT STATUS REGISTER (RLCISR) HEX ADDRESS: 0XNB12

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

4AIS16 RO 0 AIS 16 State

This bit indicates whether or not the Receive E1 Framer is declaring

AIS 16 (Time slot 16 = All Ones Signal) alarm condition.

0 - Indicates the Receive E1 Framer is currently NOT declaring the

AIS16 alarm condition.

1 - Indicates the Receive E1 Framer is currently declaring the AIS16

alarm condition.

3 RxLOSINT RUR/

WC 0Change in Receive LOS condition Interrupt Status

This bit indicates whether or not the “Change in Receive LOS condi-

tion” interrupt has occu rred since the last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block declares the Receive

LOS condition.

2. Whenever the Receive E1 Framer block clears the Receive

LOS condition.

0 = Indicates that the “Change in Receive LOS Condition” interrupt

has not occurred since the last read of this register.

1 = Indicates that the “Change in Receive LOS Condition” interrupt

has occurred since the last read of this register.

2 CRCLOCK_INT RUR/

WC 0Change in CRC Multiframe Alignment In-Frame Interrupt Status

This bit indicates whether or not the E1 Receive Framer block has

lost or gained CRC Multiframe Alignment since the last read of this

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block declares CRC

Multiframe Alignment LOCK.

2. Whenever the Receive E1 Framer block declares Loss of

CRC Multiframe Alignment.

0 = Indicates that the “Change in CRC Multiframe Alignment In-

Frame” interrupt has not occurred since the last read of this register.

1 = Indicates that the “Change in CRC Multiframe Alignment In-

Frame” interrupt has occurred since the last read of this register.

XRT86VX38

141

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

1 CASLOCK_INT RUR/

WC 0Change in CAS Multiframe Alignment In-Frame Interrupt Status

This bit indicates whether or not the E1 Receive Framer block has

lost or gained CAS Multiframe Alignments since the last read of this

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block declares CAS

Multiframe Alignment LOCK.

2. Whenever the Receive E1 Framer block declares Loss of

CAS Multiframe Alignment.

0 = Indicates that the “Change in CAS Multiframe Alignment In-

Frame” interrupt has not occurred since the last read of this register.

1 = Indicates that the “Change in CAS Multiframe Alignment In-

Frame” interrupt has occurred since the last read of this register.

0 AIS16_INT RUR/

WC 0Change in AIS16 Alarm Condition Interrupt Status

This bit indicates whether or not the “Change in AIS16 Alarm Condi-

tion” interrupt has occu rred since the last read of this register.

If this interrupt is enabled, then the Receive E1 Framer block will

generate an interrupt in response to either one of the following

conditions.

1. Whenever the Receive E1 Framer block declares AIS16

(TimeSlot 16 = All Ones) condition.

2. Whenever the Receive E1 Framer block clears AIS16

(TimeSlot 16 = All Ones) condition.

0 = Indicates that the “Change in AIS16 Condition” interrupt has not

occurred since the last read of this register.

1 = Indicates that the “Change in AIS16 Condition” interrupt has

occurred since the last read of this register.

TABLE 124: RXLOS/CRC INTERRUPT STATUS REGISTER (RLCISR) HEX ADDRESS: 0XNB12

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

142

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 125: RXLOS/CRC INTERRUPT ENABLE REGISTER (RLCIER) HEX ADDRESS: 0XNB13

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

3 RxLOS_ENB R/W 0 Change in Receive LOS Condition Interrupt Enable

This bit enables the “Change in Receive LOS Condition” interrupt.

0 = Enables “Change in Receive LOS Conditi on” Interrupt.

1 = Disables “Change in Receive LOS Condition” Interrupt.

2 CRCLOCK_ENB R/W 0 Change in CRC Multiframe Alignment In-Frame Interrupt Enable

This bit enables the “Change in CRC Multiframe Alignment In-Frame”

interrupt.

0 = Enables “Change in CRC Multiframe Alignment In -Frame” Interrupt.

1 = Disables “Change in CRC Multiframe Alignment In-Frame” Interrupt.

1 CASLOCK_ENB R/W 0 Change in CAS Multiframe Alignment In-Frame Interrupt Enable

This bit enables the “Change in CAS Multiframe Alignment In-Frame”

interrupt.

0 = Enables “Change in CAS Multiframe Alignment In-Frame” Interrupt.

1 = Disables “Change in CAS Multiframe Alignment In-Frame” Interrupt.

0 AIS16_ENB R/W 0 Change in AIS16 Condition Interrupt Enable

This bit enables the “Chang e in AIS16 (Time Slot 16 = All Ones) Co ndi-

tion” interrupt.

0 = Enables “Change in AIS 16 Condition” Interrupt.

1 = Disables “Change in AIS 16 Condition” Interrupt.

XRT86VX38

143

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 126: DATA LINK STATUS REGISTER 2 (DLSR2) HEX ADDRESS: 0XNB16

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 MSG TYPE RO 0 HDLC2 Message Type Identifier

This READ ONLY bit indicates the type of data link message

received by Receive HDLC 2 Controller. Two types of data link mes-

sages are supported within the XRT86VX38 device: Message Ori-

ented Signaling (MOS) or Bit-Oriente d Signalling (BOS).

0 = Indicates Bit-Oriented Signaling (BOS) type data link message is

received

1 = Indicates Message Oriented Signaling (MOS) type data link

message is received

6 TxSOT RUR/

WC 0Transmit HDLC2 Controller Start of Transmission (TxSOT)

Interrupt Status

This Reset-Upon-Read bit indicates whether or not the “Transmit

HDLC2 Controller Start of Transmission (TxSOT) “Interrupt has

occurred since the last read of this register . Transmit HDLC2 Con-

troller will declare this interrupt when it has started to transmit a data

link message. For sending large HDLC messages, start loading the

next available buffer once this interrupt is detected.

0 = Transmit HDLC2 Controller Start of Transmission (TxSOT) inter-

rupt has not occurred since the last read of this register

1 = Transmit HDLC2 Controller Start of Transmission interrupt

(TxSOT) has occurred since the last read of this register.

5 RxSOT RUR/

WC 0Receive HDLC2 Controller St art of Reception (RxSOT) Interrupt

Status

This Reset-Up on -R e ad bi t in d i cat e s wh ether or not the Recei ve

HDLC2 Controller Start of Reception (RxSOT) interrupt has

occurred since the last read of this register. Receive HDLC2 Con-

troller will declare this interrupt when it has started to receive a data

link message.

0 = Receive HDLC2 Controller S t art of Reception (RxSOT) interrupt

has not occurred since the last read of this register

1 = Receive HDLC2 Controller S t art of Reception (RxSOT) interrupt

has occurred since the last read of this register

4 TxEOT RUR/

WC 0Transmit HDL C2 Controller End of Transmission (TxEOT) Inter-

rupt Status

This Reset-Upon-Read bit indicates whether or not the Transmit

HDLC2 Controller End of Transmission (TxEOT) Interrupt has

occurred since the last read of this register . Transmit HDLC2 Con-

troller will declare this interrupt when it has completed its transmis-

sion of a data link message. For sending large HDLC messages, it

is critical to load the next available buffer before this interrupt

occurs.

0 = Transmit HDLC2 Controller End of Transmission (TxEOT) inter-

rupt has not occurred since the last read of this register

1 = Transmit HDLC2 Controller End of Transmission (TxEOT) inter-

rupt has occurred since the last read of this register

XRT86VX38

144

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3 RxEOT RUR/

WC 0Receive HDLC2 Controller End of Reception (RxEOT) Interrupt

Status

This Reset-Up on -R e ad bi t in d i cat e s wh ether or not the Recei ve

HDLC2 Controller End of Reception (RxEOT) Interrupt has occurred

since the last read of this register. Receive HDLC 2 Controller will

declare this interrupt once it has completely received a full data link

message, or once th e bu ffer is full.

0 = Receive HDLC2 Controller End of Reception (RxEOT) interrupt

has not occurred since the last read of this register

1 = Receive HDLC2 Controller End of Reception (RxEOT) Interrupt

has occurred since the last read of this register

2 FCS Error RUR/

WC 0FCS Error Interrupt Status

This Reset-Upon -R e ad bit in d i cates whether or not th e FCS Error

Interrupt has occurred since the last read of this register. Receive

HDLC2 Controller will declare this interrupt when it has detected the

FCS error in the most recently received data link message.

0 = FCS Error interrupt has not occurre d si nce the la st re ad of th i s

1 = FCS Error interrupt has occurred since the last read of this regis-

ter

1 Rx ABORT RUR/

WC 0Receipt of Abort Sequence Inte rrupt Status

This Reset-Up on -R e ad bi t in d i cates whether or not th e Receipt of

Abort Sequence interrupt ha s occurred since last read of this regis-

ter. Receive HDLC2 Controlle r will declare this interrupt if it detects

the Abort Sequence (i.e. a string of seven (7) consecutive 1’s) in the

incoming data link channel.

0 = Receipt of Abort Sequence interrupt has not occurred since last

read of this register

1 = Receipt of Abort Sequence interrupt has occurre d since last

read of this register

0 RxIDLE RUR/

WC 0Receipt of Idle Sequen ce Interrupt Status

This Reset-Up on -R e ad bi t in d i cates whether or not th e Receipt of

Idle Sequence interrupt has occurred since the last read of this reg-

ister. The Receive HDLC2 Controller will declare this interrupt if it

detects the flag sequence octet (0x7E) in the incoming data link

channel. If RxIDLE "AND" RxEOT occur together, then the entire

HDLC message has been received.

0 = Receipt of Idle Sequence interrupt has not occurred since last

read of this register

1 = Receipt of Idle Sequence interrupt has occurred since last read

of this register.

TABLE 126: DATA LINK STATUS REGISTER 2 (DLSR2) HEX ADDRESS: 0XNB16

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

145

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 127: DATA LINK INTERRUPT ENABLE REGISTER 2 (DLIER2) HEX ADDRESS: 0XNB17

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved - - Reserved

6 TxSOT ENB R/W 0 Transmit HDLC2 Controller Start of Transmission (TxSOT)

Interrupt Enable

This bit enables or disables the “Transmit HDLC2

Controller Start of Transmission (TxSOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Transmit

HDLC2 Controller will generate an interrupt when it has started to

transmit a data link message.

0 = Disables the Transmit HDLC2 Controller Start of Tra nsmission

(TxSOT) interrupt.

1 = Enables the Transmit HDLC2 Controller Start of Transmission

(TxSOT) interrupt.

5 RxSOT ENB R/W 0 Receive HDLC2 Controller Start of Reception (RxSOT) Interrupt

Enable

This bit enables or disables the “Receive HDLC2

Controller Start of Reception (RxSOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Receive

HDLC2 Controller will generate an interrupt when it has started to

receive a data link message.

0 = Disables the Receive HDLC2 Controller Start of Reception

(RxSOT) interrupt.

1 = Enables the Receive HDLC2 Controller Start of Reception

(RxSOT) interrupt.

4 TxEOT ENB R/W 0 Transmit HDL C2 Controller End of Transmission (TxEOT) Inter-

rupt Enable

This bit enables or disables the “Transmit HDLC2

Controller End of Transmission (TxEOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Transmit

HDLC2 Controller will generate an interrupt when it has finished

transmitting a data link message.

0 = Disables the Transmit HDLC2 Controller End of Transmission

(TxEOT) interrupt.

1 = Enables the Transmit HDLC2 Controller End of Transmission

(TxEOT) interrupt.

3 RxEOT ENB R/W 0 Re ceive HDLC2 Controller End of Reception (RxEOT) Interrupt

Enable

This bit enables or disables the “Receive HDLC2

Controller End of Reception (RxEOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Receive

HDLC2 Controller will generate an interrupt when it has finished

receiving a complete data link message.

0 = Disables the Receive HDLC2 Controller End of Reception

(RxEOT) interrupt.

1 = Enables the Receive HDLC2 Controller End of Reception

(RxEOT) interrupt.

XRT86VX38

146

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

2 FCS ERR ENB R/W 0 FCS Error Interrupt Enable

This bit enables or disables the “Received FCS Erro r “Interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

Receive HDLC2 Controller will generate an interrupt when it has

detected the FCS error within the incoming data link messag e.

0 = Disables the “Receive FCS Error” interrupt.

1 = Enables the “Receive FCS Error” interrupt.

1 RxABORT ENB R/W 0 Receipt of Ab ort Sequence Interrupt Enable

This bit enables or disables the “Receipt of Abort Sequence“ Inter-

rupt within the XRT86VX38 device. Once this interrupt is enabled,

the Receive HDLC2 Controller will generate an interrupt when it has

detected the Abort Sequence (i.e. a string of seven (7) consecutive

1’s) within the incoming data link channel.

0 = Disables the “Receipt of Abort Sequence” interrupt.

1 = Enables the “Receipt of Abort Sequence” interrupt.

0 RxIDLE ENB R/W 0 Receipt of Idle Sequence Interrupt Enable

This bit enables or disables the “Receipt of Idle Sequence“ Interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

Receive HDLC2 Controller will generate an interrupt when it has

detected the Idle Sequence Octet (i.e. 0x7E) within the incoming

data link channel.

0 = Disables the “Receipt of Idle Sequence” inte rrupt.

1 = Enables the “Receipt of Idle Sequence” in terrupt.

TABLE 127: DATA LINK INTERRUPT ENABLE REGISTER 2 (DLIER2) HEX ADDRESS: 0XNB17

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

147

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 128: DATA LINK STATUS REGISTER 3 (DLSR3) HEX ADDRESS: 0XNB26

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 MSG TYPE RUR/

WC 0HDLC3 Message Type Identifier

This READ ONLY bit indicates the type of data link message received

by Receive HDLC 3 Controller. Two types of data link messages are

supported within the XRT86VX38 device: Message Oriented Signaling

(MOS) or Bit-Oriented Signalling (BOS).

0 = Indicates Bit-Oriented Signaling (BOS) type data link message is

received

1 = Indicates Message Oriented Signaling (MOS) type data link mes-

sage is received

6 TxSOT RUR/

WC 0Transmit HDLC3 Controller Start of Transmission (TxSOT) Inter-

rupt Status

This Reset-Upon -R e a d bi t in d i cat e s wh et he r or no t the “Transmit

HDLC3 Controller Start of Transmission (TxSOT) “Interrupt has

occurred since the last read of this register. Transmit HDLC3 Controller

will declare this interrupt when it has started to transmit a data link mes-

sage. For sending large HDLC messages, start loading the next avail-

able buffer once this interrupt is detected.

0 = T ransmit HDLC3 Controller S tart of T ransmission (TxSOT) interrupt

has not occurred since the last read of this register

1 = T ransmit HDLC3 Controller S tart of T ransmission interrupt (TxSOT)

has occurred since the last read of this register.

5 RxSOT RUR/

WC 0Receive HDLC3 Controller Start of Reception (RxSOT) Interrupt

Status

This Reset-Up on -R e a d bi t in d i cat e s wh ether or not the Recei ve

HDLC3 Controller Start of Reception (RxSOT) interrupt has occurred

since the last read of this register. Re ceive HDLC3 Controller will

declare this interrupt when it has started to receive a data link mes-

sage.

0 = Receive HDLC3 Controller Start of Reception (RxSOT) interrupt

has not occurred since the last read of this register

1 = Receive HDLC3 Controller Start of Reception (RxSOT) interrupt

has occurred since the last read of this register

4 TxEOT RUR/

WC 0T ransmit HDLC3 Contro ller End of T ransmission (TxEOT) Interrupt

Status

This Reset-Up on -R e a d bit in dicates whethe r or no t the Transmit

HDLC3 Controller End of Transmission (TxEOT) Interrupt has occurred

since the last read of this register. Transmit HDLC3 Controller will

declare this interrupt when it has completed its transmission of a data

link message. For sending large HDLC messages, it is critical to load

the next available buffer before this interrupt occurs.

0 = T ransmit HDLC3 Controller End of Transmission (TxEOT) interrupt

has not occurred since the last read of this register

1 = T ransmit HDLC3 Controller End of Transmission (TxEOT) interrupt

has occurred since the last read of this register

XRT86VX38

148

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

3 RxEOT RUR/

WC 0Receive HDLC3 Controller End of Reception (RxEOT) Interrupt

Status

This Reset-Up on -R e ad bi t in d i cat e s wh ether or not the Recei ve

HDLC3 Controller End of Reception (RxEOT) Interrupt has occurred

since the last read of this register. Receive HDLC3 Controller will

declare this interrupt once it has completely received a full data link

message, or once th e bu ffer is full.

0 = Receive HDLC3 Controller End of Reception (RxEOT) interrupt has

not occurred since the last read of this register

1 = Receive HDLC3 Controller End of Reception (RxEOT) Interrupt has

occurred since the last read of this register

2 FCS Error RUR/

WC 0FCS Error Interrupt Status

This Reset-Upon-Read bit indicates whether or not the FCS Error Inter-

rupt has occurred since the last read of this register. Receive HDLC3

Controller will declare this interrupt when it has detected the FCS error

in the most recently received data link message.

0 = FCS Error interrupt has not occurred since the last read of this reg-

ister

1 = FCS Error interrupt has occurred since the last read of this register

1 Rx ABORT RUR/

WC 0Receipt of Abort Sequence Inte rrupt Status

This Reset-Upon-Read bit indicates whether or not the Receipt of Abort

Sequence interrupt has occurred since last read of this register.

Receive HDLC3 Controller will declare this interrupt if it detects the

Abort Sequence (i.e. a string of seven (7) consecutive 1’s) in the

incoming data link channel.

0 = Receipt of Abort Sequence interrupt has not occurred since last

read of this register

1 = Receipt of Abort Sequence interrupt has occurred since last read of

this register

0 RxIDLE RUR/

WC 0Receipt of Idle Sequen ce Interrupt Status

This Reset-Up on -R e ad bi t in d i cates whether or not th e Receipt of Idle

Sequence interrupt has occurred since the la st read of this register.

The Receive HDLC3 Controller will declare this interrupt if it detects the

flag sequence octet (0x7E) in the incoming data link channel. If RxIDLE

"AND" RxEOT occur together, then the entire HDLC message has

been received.

0 = Receipt of Idle Sequence interrupt has not occurred since last read

of this register

1 = Receipt of Idle Sequence interrupt has occurred since last read of

this register.

TABLE 128: DATA LINK STATUS REGISTER 3 (DLSR3) HEX ADDRESS: 0XNB26

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

149

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 129: DATA LINK INTERRUPT ENABLE REGISTER 3 (DLIER3) HEX ADDRESS: 0XNB27

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved - - Reserved

6 TxSOT ENB R/W 0 Transmit HDLC3 Controller Start of Transmission (TxSOT)

Interrupt Enable

This bit enables or disables the “Transmit HDLC3

Controller Start of Transmission (TxSOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Transmit

HDLC3 Controller will generate an interrupt when it has started to

transmit a data link message.

0 = Disables the Transmit HDLC3 Controller Start of Tra nsmission

(TxSOT) interrupt.

1 = Enables the Transmit HDLC3 Controller Start of Transmission

(TxSOT) interrupt.

5 RxSOT ENB R/W 0 Receive HDLC3 Controller Start of Reception (RxSOT) Interrupt

Enable

This bit enables or disables the “Receive HDLC3

Controller Start of Reception (RxSOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Receive

HDLC3 Controller will generate an interrupt when it has started to

receive a data link message.

0 = Disables the Receive HDLC3 Controller Start of Reception

(RxSOT) interrupt.

1 = Enables the Receive HDLC3 Controller Start of Reception

(RxSOT) interrupt.

4 TxEOT ENB R/W 0 Transmit HDL C3 Controller End of Transmission (TxEOT) Inter-

rupt Enable

This bit enables or disables the “Transmit HDLC3

Controller End of Transmission (TxEOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Transmit

HDLC3 Controller will generate an interrupt when it has finished

transmitting a data link message.

0 = Disables the Transmit HDLC3 Controller End of Transmission

(TxEOT) interrupt.

1 = Enables the Transmit HDLC3 Controller End of Transmission

(TxEOT) interrupt.

3 RxEOT ENB R/W 0 Re ceive HDLC3 Controller End of Reception (RxEOT) Interrupt

Enable

This bit enables or disables the “Receive HDLC3

Controller End of Reception (RxEOT) “Interrupt within the

XRT86VX38 device. Once this interrupt is enabled, the Receive

HDLC3 Controller will generate an interrupt when it has finished

receiving a complete data link message.

0 = Disables the Receive HDLC3 Controller End of Reception

(RxEOT) interrupt.

1 = Enables the Receive HDLC3 Controller End of Reception

(RxEOT) interrupt.

XRT86VX38

150

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

2 FCS ERR ENB R/W 0 FCS Error Interrupt Enable

This bit enables or disables the “Received FCS Erro r “Interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

Receive HDLC3 Controller will generate an interrupt when it has

detected the FCS error within the incoming data link messag e.

0 = Disables the “Receive FCS Error” interrupt.

1 = Enables the “Receive FCS Error” interrupt.

1 RxABORT ENB R/W 0 Receipt of Ab ort Sequence Interrupt Enable

This bit enables or disables the “Receipt of Abort Sequence“ Inter-

rupt within the XRT86VX38 device. Once this interrupt is enabled,

the Receive HDLC3 Controller will generate an interrupt when it has

detected the Abort Sequence (i.e. a string of seven (7) consecutive

1’s) within the incoming data link channel.

0 = Disables the “Receipt of Abort Sequence” interrupt.

1 = Enables the “Receipt of Abort Sequence” interrupt.

0 RxIDLE ENB R/W 0 Receipt of Idle Sequence Interrupt Enable

This bit enables or disables the “Receipt of Idle Sequence“ Interrupt

within the XRT86VX38 device. Once this interrupt is enabled, the

Receive HDLC3 Controller will generate an interrupt when it has

detected the Idle Sequence Octet (i.e. 0x7E) within the incoming

data link channel.

0 = Disables the “Receipt of Idle Sequence” inte rrupt.

1 = Enables the “Receipt of Idle Sequence” in terrupt.

TABLE 129: DATA LINK INTERRUPT ENABLE REGISTER 3 (DLIER3) HEX ADDRESS: 0XNB27

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

151

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

BIT 7 - Receive SSM Match 3 Event

This bit is set when the receive SSM message is equal to the RSSM Match 3 message, and filter validation has

occured.

} 0 - No Match

} 1 - Match 3

BIT 6 - Receive SSM Match 2 Event

This bit is set when the receive SSM message is equal to the RSSM Match 2 message, and filter validation has

occured.

} 0 - No Match

} 1 - Match 2

BITS [5:4] - Reserved

BIT 3 - RSSM Register Full Event (Receive Start of Transfer)

This bit is set when the RSSM register is full. T his register is not gated by the filter. It is set any time a valid BOC

message has been received.

} 0 - Not Full

}1 - Full

BIT 2 - TSSM Register Empty Event (Transmit End of Transfer)

This bit is set when the TSSM register has been emptied according to amount of repetitions programmed into the

TxBYTE count register 0xn178h. This alarm is meant to be an indicator of a complete BOC transmission for system alert

or to initiate a response for future processing.

} 0 - Not Emptied

}1 - Emptied

BIT 1 - Receive SSM Match 1 Event

This bit is set when the receive SSM message is equal to the RSSM Match 1 message, and filter validation has

occured.

} 0 - No Match

} 1 - Match 1

BIT 0 - Receive BOC Detector Change of Status

This bit is set to 1 any time a change has occured with the RSSM message. This alarm will NOT be set unless the filter

setting has been satisfied.

} 0 - No Change

} 1 - Change of Status

TABLE 130: E1 BOC INTERRUPT STATUS REGISTER (BOCISR 0XNB70H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

RMTCH3 RMTCH2 Reserved RSSMF TSSME RMTCH1 RBOC

RUR RUR RUR RUR RUR RUR RUR RUR

00000000

XRT86VX38

152

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

BIT 7 - Receive SSM Match 3 Event

This bit is used to enable the RSSM Match 3 message Interrupt.

} 0 - Disabled

} 1 - Interrupt Enabled

BIT 6 - Receive SSM Match 2 Event

This bit is used to enable the RSSM Match 2 message Interrupt.

} 0 - Disabled

} 1 - Interrupt Enabled

BITS [5:4] - Reserved

BIT 3 - RSSM Register Full Event

This bit is used to enable the RSSM Full Interrupt.

} 0 - Disabled

} 1 - Interrupt Enabled

BIT 2 - TSSM Register Empty Event

This bit is used to enable the TSSM Empty Interrupt.

} 0 - Disabled

} 1 - Interrupt Enabled

BIT 1 - Receive SSM Match 1 Event

This bit is used to enable the RSSM Match 1 message Interrupt.

} 0 - Disabled

} 1 - Interrupt Enabled

BIT 0 - Receive BOC Detector Change of Status

This bit is used to enable the BOC detector change of status Interrupt.

} 0 - Disabled

} 1 - Interrupt Enabled

TABLE 131: E1 BOC INTERRUPT ENABLE REGISTER (BOCIER 0XNB71H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

RMTCH3 RMTCH2 Reserved RSSMF TSSME RMTCH1 RBOC

R/W R/W R/W R/W R/W R/W R/W R/W

00000000

XRT86VX38

153

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

BIT 7 - Reserved

BIT 6 - Unstable SSM Message Interrupt Stat us

This bit will be set to ’1’ anytime the receive SSM message has changed from its previous value, IF the SSM

message was va lid. Therefor e, this interrup t is only active once the BOC has received a valid SSM message.

This register is Reset Upon Read.

} 0 - No Change in SSM

} 1 - Change in SSM

BITS [5:0] - Reserved

TABLE 132: E1 BOC UNSTABLE INTERRUPT STATUS REGISTER (BOCUISR 0XNB74H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

Reserved Unstable Reserved

RUR RUR RUR RUR RUR RUR RUR RUR

00000000

XRT86VX38

154

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

BIT 7 - Reserved

BIT 6 - Unstable SSM Message Interrupt Enable

This bit is used to enable the Unstable SSM message Interrupt. Unstable is defined as anytime the receive

SSM message has changed from its pr evious value, IF the SSM message was valid. Therefore, this interrupt is

only active once the BOC ha s received a valid SSM message.

} 0 - Disabled

} 1 - Interrupt Enabled

BITS [5:0] - Reserved

TABLE 133: E1 BOC UNSTABLE INTERRUPT ENABLE REGISTER (BOCUIER 0XNB75H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

Reserved Unstable Reserved

R/W R/W R/W R/W R/W R/W R/W R/W

00000000

XRT86VX38

155

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

3.0 LINE INTERFACE UNIT (LIU SECTION) REGISTERS

TABLE 134: LIU CHANNEL CONTROL REGISTER 0 (LIUCCR0) HEX ADDRESS: 0X0FN0

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 QRSS_n/

PRBS_n R/W 0 QRSS/PRBS Select Bits

These bits are used to select between QRSS and PRBS.

0 = PRBS_n (215 - 1)

1 = QRSS_n (220 - 1)

6 PRBS_Rx_n/

PRBS_Tx_n

R/W 0 PRBS Receive/Transmit Select:

This bit is used to select where the output of the PRBS Generator is

directed if PRBS generation is enabled.

0 = Normal Operation - PRBS generator is output on TTIP and

TRING if PRBS generation is enabled.

1 = PRBS Generator is output on RPOS and RCLK.

5RXON_nR/W0Receiver ON:

This bit permits the user to either turn on or turn off the Receive Sec-

tion of XRT86VX38. If the user turns on the Receive Section, then

XRT86VX38 will begin to receive the incoming data-stream via the

RTIP and RRING input pins.

Conversely, if the user turns off the Receive Section, then the entire

Receive Section except the MCLKIN Phase Locked Loop (PLL) will

be powered down.

0 = Shuts off the Receive Section of XRT86VX38.

1 = Turns on the Receive Section of XRT86VX38.

PBRS

Generator Tx TTIP

TRING

Bit 6 = "0"

PBRS

Generator Rx RPOS

RNEG

Bit 6 = "1"

XRT86VX38

156

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

4-0 EQC[4:0] R/W 00000 Equalizer Control [4:0]:

These bits are used to control the transmit pulse shaping, transmit

line build-out (LBO) and receive sensi ti vi ty leve l.

The T ransmit Pulse Shape can be controlled by adjusting the Trans-

mit Line Build-Out Settings for different cable length in E1 mode.

Transmit pulse shape can also be controlled by using the Arbitrary

mode, where users can specify the amplitude of the pulse shape by

using the 8 Arbitrary Pulse Segments provided in the LIU registers

(0xNf08-0xNf0F), where n is the channel number.

The XRT86VX38 device supports both long haul and short haul

applications which can also be selected using the EQC[4:0] bits.

Table 135 presents the corresponding Transmit Line Build Out and

Receive Sensitivity settings using different combinations of these

five EQC[4:0] bits.

TABLE 134: LIU CHANNEL CONTROL REGISTER 0 (LIUCCR0) HEX ADDRESS: 0X0FN0

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

157

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 135: EQUALIZER CONTROL AND TRANSMIT LINE BUILD OUT

EQC[4:0] T1 MODE/RECEIVE SENSITIVITY TRANSMIT LBO CABLE

0x00h T1 Long Haul/36dB 0dB 100TP

0x01h T1 Long Haul/36dB -7.5dB 100 TP

0x02h T1 Long Haul/36dB -15dB 100TP

0x03h T1 Long Haul/36dB -22.5dB 100TP

0x04h T1 Long Haul/45dB 0dB 100TP

0x05h T1 Long Haul/45dB -7.5dB 100 TP

0x06h T1 Long Haul/45dB -15dB 100TP

0x07h T1 Long Haul/45dB -22.5dB 100TP

0x08h T1 Short Haul/15dB 0 to 133 feet (0.6dB) 100TP

0x09h T1 Short Haul/15dB 133 to 266 feet (1.2dB) 100TP

0x0Ah T1 Short Haul/15dB 266 to 399 feet (1.8dB) 100TP

0x0Bh T1 Short Haul/15dB 399 to 533 feet (2.4dB) 100TP

0x0Ch T1 Short Haul/15dB 533 to 655 feet (3.0dB) 100TP

0x0Dh T1 Short Haul/15dB Arbitrary Pulse 100TP

0x0h T1 Gain Mode/29dB 0 to 133 feet (0.6dB) 100TP

0x0Fh T1 Gain Mode/29dB 133 to 266 feet (1.2dB) 100TP

0x10h T1 Gain Mode /29dB 266 to 399 feet (1.8dB) 100TP

0x11h T1 Gain Mode/29dB 399 to 533 fe et (2.4dB) 100TP

0x12h T1 Gain Mode /29dB 533 to 655 feet (3.0dB) 100TP

0x13h T1 Gain Mode/29dB Arbitrary Pulse 100TP

0x14h T1 Gain Mode /29dB 0dB 100TP

0x15h T1 Gain Mode /29dB -7.5dB 100TP

0x16h T1 Gain Mode /29dB -15dB 10 0 TP

0x17h T1 Gain Mode /29dB -22.5dB 100TP

0x18h E1 Long Haul/36dB ITU G.703 7 5 Coax

0x19h E1 Long Haul/36dB ITU G.703 120 TP

0x1Ah E1 Long Hau l/45dB ITU G.703 75 Coax

0x1Bh E1 Long Hau l/45dB ITU G.703 120  TP

0x1Ch E1 Short Haul/15dB ITU G.703 75 Coax

0x1Dh E1 Short Haul/15dB ITU G.703 120 TP

0x1Eh E1 Gain Mode/29dB ITU G.703 75 Coax

0x1Fh E1 Gain Mode/29dB ITU G.703 120 TP

XRT86VX38

158

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 136: LIU CHANNEL CONTROL REGISTER 1 (LIUCCR1) HEX ADDRESS: 0X0FN1

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 RXTSEL_n R/W 0 Receiver Termination Select:

Upon power up, the receivers are in “High” impedance. The receive

termination can be selected by setting this bit according to the fol-

lowing table:

6 TXTSEL_n R/W 0 Transmit Terminatio n Select:

This bit is used to select between internal termination or “High”

impedance modes for the E1 transmitter according to the followin g

table:

5-4 TERSEL[1:0] R/W 00 Termination Impeda nce Select [1:0]:

These bits are used to control the transmit and receive termination

impedance when the LIU block is configured in Internal Termination

Mode.

In internal termination mode, (i.e., TXTSEL = “1” and RXTSEL =

“1”), internal transmit and receive termination can be selected

according to the following table:

NOTE: In the internal termination mode, the transmitter output

should be AC coupled to the transformer.

3 RxJASEL_n R/W 0 Re ceive Jitter Atten uato r Enab le

This bit permits the user to enable or disable the Jitter Attenuator in

the Receive Path within the XRT86VX38 device.

0 = Disables the Jitter Attenuator to operate in the Receive Path

within the Receive E1 LIU Block.

1 = Enables the Jitter Attenuator to operate in the Receive Path

within the Receive E1 LIU Block.

RXTSEL RX Te r mina t io n

"High" Impedance

Internal

TXTSEL TX Termination

"High" Impedance

Internal

TERSEL1 TERSEL0

0 0

0 1

1 0

1 1

Internal Transm it

and Receive

Termination

100

110

75

120

XRT86VX38

159

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

2 TxJASEL_n R/W 0 Transmit Jitter Attenuator Enable

This bit permits the user to enable or disable the Jitter Attenuator in

the Transmit Path within the XRT86VX38 device.

0 = Disables the Jitter Attenuator to operate in the Transmit Path

within the Transmit E1 LIU Block.

1 = Enables the Jitter Attenuator to operate in the Transmit Path

within the Transmit E1 LIU Block.

1 JABW_n R/W 0 Jitter Attenuator Bandwidth Select:

In E1 mode, this bit is used to select the Jitter Attenuator Bandwidth

as well as the FIFO size.

1 = Selects a 1.5Hz Bandwidth for the Jitter Attenuator. The FIFO

length will be automatically set to 64 bits.

0 = Setting this bit to “0” will select 10Hz Bandwidth for the Jitter

Attenuator. The FIFOS (bit D0 of this register) will be used to select

the FIFO size.

The table below presents the Jitter Attenuator and FIFO settings

corresponding to the combinations of this JABW and FIFOS bits in

both T1 and E1 mode.

0 FIFOS_n R/W 0 FIFO Size Select: See table of bit D1 above for the function of this

bit.

TABLE 136: LIU CHANNEL CONTROL REGISTER 1 (LIUCCR1) HEX ADDRESS: 0X0FN1

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

FIFOS_n

bit D0

JABW

bit D1

Mode

FIFO

Size

1.5

JA B-W

XRT86VX38

160

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 137: LIU CHANNEL CONTROL REGISTER 2 (LIUCCR2) HEX ADDRESS: 0X0X0FN2

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 INVQRSS_n R/W 0 Invert QRSS Pattern:

This bit inverts the output PRBS/QRSS pattern if the LIU Block is

configured to transmit a PRBS/QRSS pattern.

0 = The LIU will NOT invert the output PRBS/QRSS pattern

1 = The LIU will invert the output PRBS/QRSS pattern

6-4 TXTEST[2:0] R/W 000 Transmit Test Pattern [2:0]:

These bits are used to configure the Transmit E1 LIU Block to gen-

erate and transmit test patterns according to the following table.

Use of these bits automatically places the LIU section in Single Rail

mode. When this happens, the Framer section must be placed in

Single Rail mode in Reg 0xN101.

TDQRSS (Transmit/Detect Quasi-Random Signal):

QRSS pattern is a 215-1 pseudo-random bit sequence (PRBS) pat-

tern.

TAOS (Transmit All Ones):

Whenever the user implements this configuration setting, the Trans-

mit E1 LIU Block will ignore the data that it is accepting from the

Transmit E1 Framer block (as well as the upstream system-side ter-

minal equipment) and overwrite this data with the All Ones Pattern.

TLUC (Trans mit Network Loop-Up Code):

The Transmit E1 LIU Block will generate and transmit the Network

Loop-Up Code of “00001” to the line for the selected channel num-

ber n.

When Network Loop-Up code is being transmitted, the XRT86VX38

will ignore the “Automatic Loop-Code detection and Remote Loop-

Back activation” (NLCDE1 =“1”, NLCDE0 =“1” of register 0xFN3) in

order to avoid activating Remote Digital Loop-Back automatically

when the remote terminal responds to the Loop-Back request.

TLDC (Trans mit Network Loop-Down Code):

The Transmit E1 LIU Block will generate and transmit the Network

Loop-Down Code of “001” to the line for the selected channel num-

ber n.

0 0

0 1

1 0

1 1

X X0 No Pattern

TDQRSS

TAOS

TLUC

Test Pattern

TLDC

TXTEST1 TXTEST0TXTEST2

XRT86VX38

161

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

3TXON_nR/W0Transmitter ON:

This bit permits the user to either turn on or turn off the Transmit

Driver of XRT86VX38. If the user turns on the Tr ansmit Driver, then

XRT86VX38 will begin to transmit DS1 data (on the line) via the

TTIP and TRING output pins.

Conversely, if the user turns off the Transmit Driver, then the TTIP

and TRING output pins will be tri-stated.

0 = Shuts off the Tr ansmit Driver associated with the XRT86VX38

device and tri-states the TTIP and TRING output pins.

1 = Turns on the Transmit Driver associated with the XRT86VX38

device.

NOTE: If the user wishes to exercise software control over the state

of the Transmit Driver of the XRT86VX38, then it is

imperative that the user pull the TxON pin to a logic “HIGH”

level.

2-0 LOOP2_n R/W 000 Loop-Back control [2:0]:

These bits control the Loop-Back Modes of the LIU section, accord-

ing to the table below.

TABLE 137: LIU CHANNEL CONTROL REGISTER 2 (LIUCCR2) HEX ADDRESS: 0X0X0FN2

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

LOOP2

LOOP1

LOOP0

Loop-Back Mode

No Loop-Back

Dual Loop-Back

Analog Loop-Ba ck

Remote Loop-Back

Digital Loop- Ba ck

XRT86VX38

162

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 138: LIU CHANNEL CONTROL REGISTER 3 (LIUCCR3) HEX ADDRESS: 0X0FN3

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-6 NLCDE[1:0] R/W 00 Network Loop Code Detection Enable [1:0]:

These bits are used to control the Loop-Code detection on the

receive path, according to the table below. This p art must be in Sin-

gle Rail mode to detect.

Loop-Up Code Detection Enable:

The XRT86VX38 is configured to monitor the receive data for the

Loop-Up code Pattern (i.e. a string of four ‘0’s followed by one ‘1’

pattern). When the presence of the “00001” pattern is detected for

more than 5 seconds, the status of the NLCD bit (bit 3 of register

0xNf05) is set to “1” and if the NLCD interrupt is enabled (bit 3 of

Loop-Down Code Detection Enable:

The XRT86VX38 is configured to monitor the receive data for the

Loop-Down code Pattern (i.e. a string of two ‘0’s followed by one ‘1’

pattern). When the presence of the “001” pattern is detected for

more than 5 seconds, the status of the NLCD bit (bit 3 of register

0xNf05) is set to “1” and if the NLCD interrupt is enabled (bit 3 of

Automatic Loop-Up Code Detection and Remote Loop Back

Activation Enable:

When this mode is enabled, the state of the NLCD bit (bit 3 of regis-

ter 0xNf05) is reset to “0” and the XRT86VX38 is configured to mon-

itor the receive data for the Loop-Up code. If the “00001” pattern is

detected for longer than 5 seconds, then the NLCD bit (bit 3 of regis-

ter 0xNf05) is set “1”, and Remote Loop-Back is activated. Once the

remote loop-back is activated, the XRT86VX38 is automatically pro-

grammed to monitor the receive data for the Loop-Down code. The

NLCD bit stays set even after the chip stops receiving the Loop-Up

code.

The Remote Loop-Back condition is re moved only when the

XRT86VX38 receives the Loop-Down code for more than 5 seconds

or if the Automatic Loop-Code detection mode is terminated.

5 CODES_n R/W 0 Encoding and Decoding Sel e ct:

Writing a "0" to this bit selects HDB3 encoding and decoding for

channel n. Writting a "1" selects AMI coding scheme. This bit is

only active when in single rail operation.

4-3 Reserved R/W 00 These Bits are Not Used

NLCDE[1:0] NETWORK LOOP CODE DETECTION

ENABLE

00 Disables Loop Code Detection

01 Enables Loop-Up Code Detection on

the Receive Path.

10 Enables Loop-Down Code Detection

on the Receive Path.

11 Enables Automatic Loop-Up Code

Detection on the Receive Path and

Remote Loop-Back Activation upon

detecting Loop-Up Code.

XRT86VX38

163

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

2 INSBPV_n R/W 0 Insert Bipolar Violation: When this bit transitions from "0" to "1", a

bipolar violation is inserted in the transmitted data stream of the

selected channel number n. Bipolar violati on can be inserted either

in the QRSS pattern, or input data when operating in single-rail

mode. The state of this bit is sampled on the rising edge of the

respective TCLK _n .

NOTE: To e nsure th e i nsertion of a b ipo lar vi ola tion, a "0" should be

written in this bit location before writing a "1".

1 INSBER_n R/W 0 Insert Bit Error:

This bit is used to insert a single bit error on the transmitter of the E1

LIU Block.

When the E1 LIU Block is configured to transmit and detect the

QRSS pattern, (i.e., TxTEST[2:0] bits set to ‘b100’), a “0” to “1” tran-

sition of this bit will insert a bit error in the transmitted QRSS pattern

of the selected channel number n.

The state of this bit is sampled on the rising edge of the respective

TCLK_n.

NOTE: To ensure th e insertion of b it error, a “0” shou ld be written in

this bit location before writing a “1”.

0 Reserved R/W 0 This Bit Is Not Used

TABLE 138: LIU CHANNEL CONTROL REGISTER 3 (LIUCCR3) HEX ADDRESS: 0X0FN3

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

164

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 139: LIU CHANNEL CONTROL INTERRUPT ENABLE REGISTER (LIUCCIER) HEX ADDRESS: 0X0FN4

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved RO 0 This Bit Is Not Used

6DMOIE_nR/W0

Change of Transmit DMO (Drive Monitor Output) Condition Inter-

rupt Enable:

This bit permits the user to either enable or disable the “Change of

Transmit DMO Condition” Interrupt. If the user enables this interrupt,

then the XRT86VX38 device will generate an interrupt any time when

either one of the following events occur.

1. Whenever the T ransmit Section toggles the DMO Status bit (Bit 6

or Register 0x Nf 05 ) to “1”.

2. Whenever the T ransmit Section toggles the DMO Status bit (Bit 6

or Register 0x Nf 05 ) to “0”.

0 – Disables the “Change in the DMO Condition” Interrupt.

1 – Enables the “Change in the DMO Condition” Interrupt.

5 FLSIE_n R/W 0 FIFO Limit Status Interrupt Enable:

This bit permits the user to either enable or disable the “FIFO Limit Sta-

tus” Interrupt. If the user enables this interrupt, then the XRT86VX38

device will generate an interrupt when the jitter attenuator Read/Write

FIFO pointers are within +/- 3 bits.

0 = Disables the “FIFO Limit Status” Interrupt

1 = Enables the “FIFO Limit Status” Interrupt

4LCVIE_nR/W0

Line Code Violation Interrupt Enable: Writing a "1" to this bit enable s

Line Code Violation Interrupt generation, writing a "0" masks it.

NOTE: Only use for Framer Bypass operation. When framer is in path,

use Framer LCV interrupt enable in register 0xNB03.

3NLCDIE_nR/W0

Change in Network Loop-Code Detection Interrupt Enable:

This bit permits the user to either enable or disable the “Change in Net-

work Loop-Code Detection” Interrupt. If the user enables this interrupt,

then the XRT86VX38 device will generate an interrupt any time when

either one of the following events occur.

1. Whenever the Receive Section (within XRT86VX38) detects the

Network Loo p-Code (Loo p-Up o r Loo p-Down depend ing on w hich

Loop-Code the Receive LIU is configured to detect).

2. Whenever the Receive Section (within XRT86VX38) no longer

detects the Network Loop-Code (Loop-Up or Loop-Down

depending on which Loop-Code the Receive LIU is configured to

detect).

0 – Disables the “Change in Network Loop-Code Detection” Interrupt.

1 – Enables the “Change in Network Loop-Cod e Detection” Interrupt.

2 AISDIE_n R/W 0 AIS Detection Interrupt Enable: Writing a "1" to this bit enables Alarm

indication Signal detection interrupt generation, writing a "0" masks it.

NOTE: Only use for Framer Bypass operation. When framer is in path,

use Framer AIS interrupt enable in register 0xNB03.

XRT86VX38

165

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

NOTE: Register 0xNf04, 0xNf05 and 0xNf06 only work if the LIU is placed in Single Rail mode. If done so, the Framer block

must also be placed in Single Rail mode in Registe r 0xN101.

1 RLOSIE_n R/W 0 Chan ge of the Receive LOS (Loss of Signal) Defect Con dition Inter-

rupt Enable:

This bit permits the user to either enable or disable the “Change of the

Receive LOS Defect Condition” Interrupt. If the user enable s this inter-

rupt, then the XRT86VX38 device will generate an inte rrupt any time

when either one of the following events occur.

1. Whenever the Rece ive Section (within XRT86VX38) declares the

LOS Defect Condition.

2. Whenever the Receive Section (within XRT86VX38) clears the

LOS Defect condition.

0 – Disables the “Change in the LOS Defect Condition” Interrupt.

1 – Enables the “Change in the LOS Defect Condition” Interrupt.

0 QRPDIE_n R/W 0 Change in QRSS Pattern Detection Interrupt Enable:

This bit permits the user to either enable or disable the “Change in

QRSS Pattern Detection” Interrupt. If the user enables this interrupt,

then the XRT86VX38 device will generate an interrupt any time when

either one of the following events occur.

1. Whenever the Receive Section (within XRT86VX38) detects the

QRSS Pattern.

2. Whenever the Receive Section (within XRT86VX38) no longer

detects the QRSS Pattern.

0 – Disables the “Change in QRSS Pattern Detection” Interrupt.

1 – Enables the “Change in QRSS Pattern Detection” Interrupt.

TABLE 140: LIU CHANNEL CONTROL STATUS REGISTER (LIUCCSR) HEX ADDRESS: 0X0FN5

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved RO 0

6DMO_nRO0

Driver Monitor Output (DMO) Status:

This READ-ONLY bit indicates whether or not the Transmit Section

is currently declaring the DMO Alarm condition.

The Transmit Section will check the Transmit Output E1 Line signal

for bipolar pulses via the TTIP and TRING output signals. If the

Transmit Section were to detect no bipolar signal for 128 consecu-

tive bit-periods, then it will declare the Transmit DMO Alarm condi-

tion. This particular alarm can be used to check for fault condi tions

on the Transmit Output Line Signal path.

The Transmit Section will clear the Transmit DMO Alarm condition

the instant that it detects some bipolar activity on the Transmit Out-

put Line signal.

0 = Indicates that the Transmit Section of XRT86VX38 is NOT cur-

rently declaring the Transmit DMO Alarm condition.

1 = Indicates that the Transmit Section of XRT86VX38 is currently

declaring the Transmit DMO Alarm condition.

NOTE: If the DMO interrupt is enabled (DMOIE - bit D6 of register

0xNf04), any transition on this bit will generate an Interrupt.

TABLE 139: LIU CHANNEL CONTROL INTERRUPT ENABLE REGISTER (LIUCCIER) HEX ADDRESS: 0X0FN4

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

166

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

5 FLS_n RO 0 FIFO Limit Status:

This READ-ONLY bit indicates whether or not the XRT86VX38 is

currently declaring the FIFO Limit Status.

This bit is set to a “1” to indicate that the jitter attenuator Read/Write

FIFO pointers are within +/- 3 bits.

0 = Indicates that the XRT86VX38 is NOT currently declaring the

FIFO Limit Status.

1 = Indicates that the XRT86VX38 is currently declaring the FIFO

Limit Status.

NOTE: If the FIFO Limit Status Interrupt is enabled, (FLSIE bit - bit

D5 of register 0xNf04), any transition on this bit will

generate an Interrupt.

4 LCV_n RO 0 Line Code Violation: This bit is set to "1" to indicate that the receiver

of channel n is currently detecting a Line Code Violation or an

excessive number of zeros in the HDBs mode. If the LCVIE bit is

enabled any transition on this bit wil l generate an interrupt.

NOTE: Only use for Framer Bypass operation.

TABLE 140: LIU CHANNEL CONTROL STATUS REGISTER (LIUCCSR) HEX ADDRESS: 0X0FN5

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

167

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

3 NLCD_n RO 0 Netw ork Loop-Code Detect ion Status Bit:

This bit operates differently in the Manual or the Automatic Network

Loop-Code detection modes.

Manual Loop-Up Code detection mode

(.i.e If NLCDE1 = “0” and NLCDE0 = “1”), this bit gets set to “1” as

soon as the Loop-Up Code (“00001”) is detected in the receive data

for longer than 5 seconds.

This bit stays high as long as the Receive E1 LIU Block detects the

presence of the Loop-Up code in the receive data and it is reset to

“0” as soon as it stops receiving the Loop-Up Code.

If the NLCD interrupt is enabled, the XRT86VX38 will initiate an

interrupt on eve r y tra n s it i on of the NLCD status bit.

Manual Loop-Down Code detection mode

(i.e., If NLCDE1 = “1” and NLCDE0 = “0”), this bit gets set to “1” as

soon as the Loop-Down Code (“001”) is detected in the receive data

for longer than 5 seconds.

This bit stays high as long as the Receive E1 LIU Block detects the

presence of the Loop-Down code in the receive data and it is reset

to “0” as soon as it stops receiving the Loop-Down Code.

If the NLCD interrupt is enabled, the XRT86VX38 will initiate an

interrupt on eve r y tra n s it i on of the NLCD status bit.

Automatic Loop-code detection mode

(i.e., If NLCDE1 = “1” and NLCDE0 =”1”), the state of the NLCD sta-

tus bit is reset to “0” and the XRT86VX38 is programmed to monitor

the receive input data for the Loop-Up code.

This bit is set to a “1” to indicate that the Network Loop Code is

detected for more than 5 seconds. Simultaneously the Remote

Loop-Back condition is automatically activated and the XRT86VX38

is programmed to monitor the receive data for the Network Loop

Down code. The NLCD bit stays ‘high’ as long as the Remote Loop-

Back condition is in effect even if the chip stops receiving the Loop-

Up code. Remote Loop-Back is removed only if the XRT86VX38

detects the Loop-Down Code “001” pattern for longer than 5 sec-

onds in the receive data. Upon detecting the Loop-Down Code “001”

pattern, the XRT86VX38 will reset the NLCD status bit and an inter-

rupt will be generated if the NLCD interrupt enable bit is enabled.

Users can monitor the state of this bit to determine if the Remote

Loop-Back is activated.

2 AISD_n RO 0 Alarm Indicatio n Signal detect : This bit is set to "1" to indicate All

Ones Siganl is detected by the receiver of channel n. If the AISDIE

bit is enabled any transition on this bit will generate an interrupt.

NOTE: Only use for Framer Bypass operation. When framer is in

path, use Framer RxAIS State in register 0xNB02.

TABLE 140: LIU CHANNEL CONTROL STATUS REGISTER (LIUCCSR) HEX ADDRESS: 0X0FN5

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

168

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

NOTE: Register 0xNf04, 0xNf05 and 0xNf06 only work if the LIU is placed in Single Rail mode. If done so, the Framer block

must also be placed in Single Rail mode in Register 0xN101.

1RLOS_nRO0Receive Loss of Signal Defect Condition Status:

This READ-ONL Y bit indicates whether or not the Receive LIU Block

is currently declaring the LOS defect condition.

0 = Indicates that the Receive Section is NOT currently declaring

the LOS Defect Condition.

1 = Indicates that the Receive Section is currently declaring the LOS

Defect condition.

NOTE: If the RLOSIE bit (bit D1 of Register 0xNf04) is enabled, any

transition on this bit will generate an Interrupt.

0 QRPD_n RO 0 Quasi-random Pattern Detection Status:

This READ-ONL Y bit indicates whether or not the Receive LIU Block

is currently declaring the QRSS Pattern LOCK status.

0 = Indicates that the XRT86VX38 is NOT currently declaring the

QRSS Pattern LOCK.

1 = Indicates that the XRT86VX38 is currently declaring the QRSS

Pattern LOCK.

NOTE: If the QRPDIE bit (bit D0 of register 0xNf04) is enabled, any

transition on this bit will generate an Interrupt.

TABLE 140: LIU CHANNEL CONTROL STATUS REGISTER (LIUCCSR) HEX ADDRESS: 0X0FN5

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

169

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 141: LIU CHANNEL CONTROL INTERRUPT STATUS REGISTER (LIUCCISR) HEX ADDRESS: 0X0FN6

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved RO 0

6 DMOIS_n RUR/

WC 0Change of Transmit DMO (Drive Monitor Output) Condition

Interrupt Status:

This RESET -upon-READ bit indicates whether or not the “Change of

the Transmit DMO Condition” Interrupt has occurred since the last

read of this register.

0 = Indicates that the “Change of the Transmit DMO Condition”

Interrupt has NOT occurred since the last read of this register.

1 = Indicates that the “Change of the Transmit DMO Condition”

Interrupt has occurred since the last read of this register.

This bit is set to a “1” every time when DMO_n status bit (bit 6

of Register 0xNf05) has changed since the last read of this

NOTE: Users can determine th e current state of the “Transmit DMO

Condition” by reading out the content of bit 6 within Register

0xNf05

5 FLSIS_n RUR/

WC 0FIFO Limit Interrupt Status:

This RESET-upon-READ bit indicates whether or not the “FIFO

Limit” Interrupt has occurred since the last read of th is register.

0 = Indicates that the “FIFO Limit Status” Interrupt has NOT

occurred since the last read of this register.

1 = Indicates that the “FIFO Limit Status” Interrupt has occurred

since the last rea d of thi s reg i ste r.

This bit is set to a “1” every time when FIFO Limit Status bit

(bit 5 of Registe r 0xNf05) has change d since the last read of

this register.

NOTE: Users can determine the current state of the “FIFO Limit” by

reading out the content of bi t 5 wi t hi n Register 0xNf05

4 LCVIS_n RUR 0 Line Code Violation Interrupt Status: This bit is set to a "1" every

time the LCV_n status has changed since the last read.

NOTE: Only use for Framer Bypass operation. When framer is in

path, use Framer LCV Int Status in register 0xNB02.

3 NLCDIS_n RUR/

WC 0Change in Network Loop-Code Detection Interrupt Status:

This RESET -upon-READ bit indicates whether or not the “Change in

Network Loop-Code Detection” Interrupt has occurred since the last

read of this register.

0 = Indicates that the “Change in Network Loop-Code Detection”

Interrupt has NOT occurred since the last read of this register.

1 = Indicates that the “Change in Network Loop-Code Detection”

Interrupt has occurred since the last read of this register.

This bit is set to a “1” every time when NLCD status bit (bit 3 of Reg-

ister 0xNf05) has changed since the last read of this register.

NOTE: Users can determine the current state of the “Network Loop-

Code Detection” by reading out the content of bit 3 within

XRT86VX38

170

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

NOTE: Register 0xNf04, 0xNf05 and 0xNf06 only work if the LIU is placed in Single Rail mode. If done so, the Framer block

must also be placed in Single Rail mode in Register 0xN101.

2 AISDIS_n RUR 0 AIS Detection Interrupt Status: Thi s bit is s et to a "1" every ti me th e

AISD_n status has changed since the last read.

NOTE: Only use for Framer Bypass operation. When framer is in

path, use Framer RxAIS State Change in register 0xNB02.

1 RLOSIS_n RUR/

WC 0Change of Receive LOS (Loss of Signal) Defect Condition Inter-

rupt Status:

This RESET -upon-READ bit indicates whether or not the “Change of

the Receive LOS Defect Condition” Interrupt has occurred since the

last read of this register.

0 = Indicates that the “Change of the Receive LOS Defect Condi-

tion” Interrupt has NOT occurred since the last read of this register.

1 - Indicates that the “Change of the Receive LOS Defect Condition”

Interrupt has occurred since the last read of this register.

NOTE: The user can determine the current state of the “Receive

LOS Defect condition” by reading out the contents of Bit 1

(Receive LOS Defect Condition Status) within Register

0xNf05.

0 QRPDIS_n RUR/

WC 0Change in Quasi-Random Pattern Detection Interrupt Status:

This RESET -upon-READ bit indicates whether or not the “Change in

QRSS Pattern Detection” Interrupt has occurred since the last read

of this register.

0 = Indicates that the “Change in QRSS Pattern Detection” Interrupt

has NOT occurred since the last read of this register.

1 = Indicates that the “Change in QRSS Pattern Detection” Interrupt

has occurred since the last read of this register.

This bit is set to a “1” every time when QRPD st atus bit (bit 0 of Reg-

ister 0xNf05) has changed since the last read of this register.

NOTE: Users can determine the current state of the “QRSS Pattern

Detection” by reading out the content of bit 0 within Register

0xNf05

TABLE 141: LIU CHANNEL CONTROL INTERRUPT STATUS REGISTER (LIUCCISR) HEX ADDRESS: 0X0FN6

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

171

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 142: LIU CHANNEL CONTROL CABLE LOSS REGISTER (LIUCCCCR) HEX ADDRESS: 0X0FN7

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved RO 0

6 Reserved RO 0

5-0 CLOS[5:0] RO 0 Cable Loss [5:0]:

These bits represent the six bit receive selective equalizer setting

which is also a binary word that represents the cable attenuation

indication within ±1dB.

CLOS5_n is the most significant bit (MSB) and CLOS0_n is th e

least significant bit (LSB).

NOTE: In RxSYNC (Sect 13) mode, ExLOS must be configured (this

will set the DLOS to 4,096 bits which does not meet G.775).

However, the CLOS bits can be used to meet the DLOS

requirements of G.775 with a simple so ftware procedure. To

meet G.775, simply choose a desired value of attenuation

(For example: between 9dB and 35dB) to monitor in this

Clock Cycles (UI). The internal RLOS alarm should be

masked unless ExLOS is being used. For more details,

please contact the factory.

TABLE 143: LIU CHANNEL CONTROL ARBITRARY REGISTER 1 (LIUCCAR1) HEX ADDRESS: 0X0FN8

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved R/W 0

6-0 Arb_Seg1 R/W 0 Arbitrary Transmit Pulse Shape, Segment 1:

These seven bits form the first of the eight segments of the transmit

shape pulse when the XRT86VX38 is configured in “Arbitrary

Mode”.

These seven bits represent the amplitude of the nth channel' s arbi-

trary pulse in signed magnitude format with Bit 6 as the sign bit and

Bit 0 as the least significant bit (LSB).

NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in

XRT86VX38

172

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 144: LIU CHANNEL CONTROL ARBITRARY REGISTER 2 (LIUCCAR2) HEX ADDRESS: 0X0FN9

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved R/W 0

6-0 Arb_Seg2 R/W 0 Arbitrary Transmit Pulse Shape, Segment 2

These seven bits form the second of the eight segments of the

transmit shape pulse when the XRT86VX38 is configured in “Arbi-

trary Mode”.

These seven bits represent the amplitude of the nth channel' s arb i-

trary pulse in signed magnitude format with Bit 6 as the sign bit and

Bit 0 as the least significant bit (LSB).

NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in

TABLE 145: LIU CHANNEL CONTROL ARBITRARY REGISTER 3 (LIUCCAR3) HEX ADDRESS: 0X0FNA

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved R/W 0

6-0 Arb_seg3 R/W 0 Arbitrary T ransmit Pulse Shape, Segment 3

These seven bits form the third of the eight segments of the transmit

shape pulse when the XRT86VX38 is configured in “Arbitrary

Mode”.

These seven bits represent the amplitude of the nth channel' s arb i-

trary pulse in signed magnitude format with Bit 6 as the sign bit and

Bit 0 as the least significant bit (LSB).

NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in

TABLE 146: LIU CHANNEL CONTROL ARBITRARY REGISTER 4 (LIUCCAR4) HEX ADDRESS:0X0FNB

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved R/W 0

6-0 Arb_seg4 R/W 0 Arbitrary T ransmit Pulse Shape, Segment 4

These seven bits form the forth of the eight segments of the transmit

shape pulse when the XRT86VX38 is configured in “Arbitrary

Mode”.

These seven bits represent the amplitude of the nth channel' s arb i-

trary pulse in signed magnitude format with Bit 6 as the sign bit and

Bit 0 as the least significant bit (LSB).

Arbitrary mode is enabled by writing to the EQC[4:0] bits in register

0xNf00.

XRT86VX38

173

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 147: LIU CHANNEL CONTROL ARBITRARY REGISTER 5 (LIUCCAR5) HEX ADDRESS: 0X0FNC

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved R/W 0

6-0 Arb_seg5 R/W 0 Arbitrary T ransmit Pulse Shape, Segment 5

These seven bits form the fifth of the eight segments of the transmit

shape pulse when the XRT86VX38 is configured in “Arbitrary

Mode”.

These seven bits represent the amplitude of the nth channel' s arbi-

trary pulse in signed magnitude format with Bit 6 as the sign bit and

Bit 0 as the least significant bit (LSB).

Arbitrary mode is enabled by writing to the EQC[4:0] bits in register

0xNf00.

TABLE 148: LIU CHANNEL CONTROL ARBITRARY REGISTER 6 (LIUCCAR6) HEX ADDRESS: 0X0FND

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved R/W 0

6-0 Arb_seg6 R/W 0 Arbitrary T ransmit Pulse Shape, Segment 6

These seven bits form the sixth of the eight segments of the transmit

shape pulse when the XRT86VX38 is configured in “Arbitrary

Mode”.

These seven bits represent the amplitude of the nth channel' s arbi-

trary pulse in signed magnitude format with Bit 6 as the sign bit and

Bit 0 as the least significant bit (LSB).

Arbitrary mode is enabled by writing to the EQC[4:0] bits in register

0xNf00.

TABLE 149: LIU CHANNEL CONTROL ARBITRARY REGISTER 7 (LIUCCAR7) HEX ADDRESS: 0X0FNE

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved R/W 0

6 Arb_seg7 R/W 0 Arbitrary Transmit Pulse Shape, Segment 7

These seven bits form the seventh of the eight segments of the

transmit shape pulse when the XRT86VX38 is configured in “Arbi-

trary Mode”.

These seven bits represent the amplitude of the nth channel' s arbi-

trary pulse in signed magnitude format with Bit 6 as the sign bit and

Bit 0 as the least significant bit (LSB).

Arbitrary mode is enabled by writing to the EQC[4:0] bits in register

0xNf00.

XRT86VX38

174

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 150: LIU CHANNEL CONTROL ARBITRARY REGISTER 8 (LIUCCAR8) HEX ADDRESS:0X0FNF

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Reserved R/W 0

6 Arb_seg8 R/W 0 Arbitrary Transmit Pulse Shape, Segment 8

These seven bits form the eight of the eight segments of the trans-

mit shape pulse when the XRT86VX38 is configured in “Arbitrary

Mode”.

These seven bits represent the amplitude of the nth channel' s arb i-

trary pulse in signed magnitude format with Bit 6 as the sign bit and

Bit 0 as the least significant bit (LSB).

Arbitrary mode is enabled by writing to the EQC[4:0] bits in register

0xNf00.

TABLE 151: LIU GLOBAL CONTROL REGISTER 0 (LIUGCR0) HEX ADDRESS: 0X0FE0

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7SRR/W0Single Rail mode

This bit must set to "1" for Single Rail mode to use LIU diagnotic fea-

tures. The Framer section must be programmed as well in Register

0xN101.

0 - Dual Rail

1 - Single Rail

6ATAOSR/W0

Automatic Transmit All Ones Upon RLOS:

This bit enables automatic transmission of All Ones Pattern upon

detecting the Receive Loss of Signal (RLOS) condition.

Once this bit is enabled, the Transmit E1 Framer Block will automat-

ically transmit an All “Ones” data to the line for the channel that

detects an RLOS condition.

0 = Disables the “Automatic Transmit All Ones” feature upon detect-

ing RLOS

1 = Enables the “Automatic Transmit All Ones” feature upon detect-

ing RLOS

5 RCLKE R/W 0 Receive Clock Data (Framer Bypass mode)

0 = RPOS/RNEG data is updated on the rising edge of RCLK

1 = RPOS/RNEG data is updated on the fallin g edge of RCLK

4 TCLKE R/W 0 Transmit Clock Data (Framer Bypass mode)

0 = TPOS/TNEG data is sampled on the falling edge of TCLK

1 = TPOS/TNEG data is sampled on the rising edge of TCLK

3DATAPR/W0Data Polarity

0 = Transmit input and receive output data is active “High”

1 = Transmit input and receive output data is active “Low”

2 Reserved This Bit Is Not Used

XRT86VX38

175

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

1GIER/W0Global Interrupt Enable:

This bit allows users to enable or disable the global inte rrupt gener-

ation for all channels within the E1 LIU Block. Once this global inter-

rupt is disabled, no interrupt will be generated to the Microprocessor

Interrupt Pin even when the individual “source” interrupt status bit

pulses ‘high’.

If this global interrupt is enabled, users still need to enable the indi-

vidual “source” interrupt in order for the E1 LIU Block to generate an

interrupt to the Microprocessor pin.

0 - Disables the global interrupt generation for all channels within

the E1 LIU Block.

1 - Enables the global interrupt generation for all channels within the

E1 LIU Block.

0 SRESET R/W 0 Software Reset P Registers:

This bit allows users to reset the XRT86VX38 device. Writing a “1”

to this bit and keeping it at ’1’ for longer than 10µs initiates a device

reset through the microprocessor interface. Once the XRT86VX38 is

reset, all intern al circu i ts are plac e d in th e re set state except the

microprocessor register bits.

0 = Disables software reset to the XRT86VX38 device.

1 = Enables software reset to the XRT86VX38 device.

TABLE 151: LIU GLOBAL CONTROL REGISTER 0 (LIUGCR0) HEX ADDRESS: 0X0FE0

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

176

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 152: LIU GLOBAL CONTROL REGISTER 1 (LIUGCR1) HEX ADDRESS: 0X0FE1

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 TxSYNC(Sect 13) R/W 0 G.703 Section 13 Transmit Pulse

When this bit is set to ’1’, the LIU transmitter will send the E1 syn-

chrnonous waveform as described in Section 13 of ITU-T G.703.

This register bit takes priority over every other LIU setting on the

transmit path.

0 = Normal E1 puls e

1 = Section 13 Synchronous Pulse

6 RxSYNC(Sect 13) R/W 0 G.703 Section 13 Receiver

When this bit is set to ’1’, the CDR block of the receiver is configured

to accept a waveform as described in Section 13 of ITU-T G.703.

0 = Normal E1 (Equalizer Bit Settings - EQC[4:0])

1 = Section 13 Synchronous Pulse

NOTE: 1. For the RxSync(Sect 13) mode, bit 1 in this register

(0xFE1) must be set to ’1’ to enable ExLOS. This only

applies to the receiver.

NOTE: 2. If RLOS is required to meet G.775 in this mode (and not

ExLOS), then the CLOS[5:0] bits in Register 0x0FN7 can be

used. See Register 0x0FN7 for more details.

5-4 Gauge [1:0] R/W 00 Wire Gauge Selector [1:0]:

This bit together with Guage0 bit (bit 4 within this register) are used

to select the wire gauge size as shown in the table below.

3 E1 Arbitrary Enable E1 Arbitrary Mode Enable

This bit is used to enable the Arbitrary Pulse Generators for shaping

the transmit pulse shape for E1 mode. If this bit is set to “1”, all 2

channels will be configured for the Arbitrary Mode. However, the

pulse shape is individually controlled by programming the 8 transmit

pulse shape segments (channel registers 0xNf08 through 0xNf0F)

“0” = Disabled (Normal E1 Pulse Shape ITU G.703)

“1” = Arbitrary Pulse Enabled

GAUGE1

GAUGE0

Wire Size

22 and 24 Gauge

26 Gauge

24 Gauge

22 Gauge

XRT86VX38

177

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

2RXMUTER/W0Receive Output Mute:

This bit permits the user to configure the Receive E1 Block to auto-

matically pull its Recovered Data Output pins to GND anytime (and

for the duration that) the Receive E1 LIU Block declares the LOS

defect condition.

In other words, if this feature is enabled, the Receive E1 LIU Block

will automatically “mute” the Recovered data that is being routed to

the Receive E1 Framer block anytime (and for the duration that) the

Receive E1 LIU Block declares the LOS defect condition.

0 – Disables the “Muting upon LOS” feature.

1 – Enables the “Muting upo n LOS” feature.

NOTE: The receive clock is not muted when this feature is enabled.

1 EXLOS Extended LOS Enable:

This bit allows users to extend the number of zeros at the receive

input of each channel before RLOS is declared.

When Extended LOS is enabled, the Receive E1 LIU Block will

declare RLOS condition when it receives 4096 number of consecu-

tive zeros at the receive input.

When Extended LOS is disabled , the Receive E1 LIU Block will

declare RLOS condition when it receives 175 number of consecu-

tive zeros at the receive input.

0 = Disables the Extended LOS Feature.

1 = Enables the Extended LOS Feature.

0ICTR/W 0 In-Circuit-Testing Enable:

This bit allows users to tristate the output pins of all channels for in-

circuit testing purposes.

When In-Circuit-Testing is enabled, all output pins of the

XRT86VX38 are “Tri-st ated”. When In-Circuit-Testing is disabled, all

output pins will resume to normal condition.

0 = Disables the In-Circuit-Testing Feature.

1 = Enables the In-Circuit-Testing Feature.

TABLE 153: LIU GLOBAL CONTROL REGISTER 2 (LIUGCR2) HEX ADDRESS: 0X0FE2

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7 Force to "0" R/W 0 Set to "0"

6-0 Reserved R/W 0 These Bits Are Not Used

TABLE 152: LIU GLOBAL CONTROL REGISTER 1 (LIUGCR1) HEX ADDRESS: 0X0FE1

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

XRT86VX38

178

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 154: LIU GLOBAL CONTROL REGISTER 3 (LIUGCR3) HEX ADDRESS: 0X0FE4

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-0 Reserved R/W 0 These Bits are Not Used.

TABLE 155: LIU GLOBAL CONTROL REGISTER 4 (LIUGCR4) HEX ADDRESS: 0X0FE9

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-4 Reserved R/W 0

3-0 CLKSEL[3:0] R/W 0001 Clock Select Input [3:0]

These four bits allow users to select the programmable input clock

rates for the MCLKIN input pin, according to the table below.

NOTE: User must provide any one of the above clock frequencies to

the MCLKIN input pin for the device to be functional.

CLKSEL[3:0] CLOCK RATE OF THE MCLKIN

INPUT PIN

0000 2.048MHz

0001 1.544MHz

0010 - 0111 Reserved

1000 4.096MHz

1001 3.088MHz

1010 8.192MHz

1011 6.176MHz

1100 16.384MHz

1101 12.352MH

1110 2.048MHz

1111 1.544MHz

XRT86VX38

179

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

TABLE 156: LIU GLOBAL CONTROL REGISTER 5 (LIUGCR5) HEX ADDRESS: 0X0FEA

BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION

7-1 Reserved - 0 These bits are reserved

0 GCHIS0 RUR/

WC 0Global Channel 0 In terrupt Status Indicator

This Reset-Upon-Read bit field indicates whether or not an interrupt

has occurred on Channel 0 within the XRT86VX38 device since the

last read of this register.

0 = Indicates that No interrupt has occurred on Channel 0 within the

XRT8 6VX38 device since th e la st read of this register.

1 = Indicates that an interrupt has occurred on Channel 0 within the

XRT8 6VX38 device since th e la st read of this register.

XRT86VX38

180

REV. 1.0.4 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

ORDERING INFORMATION

PRODUCT NUMBER PACKAGE OPERATING TEMPERATURE RANGE

XRT86VX38IB256 256 PIn Fine Pitch Ball Grid Array -40C to +85C

XRT86VX38IB329 329 PIn Fine Pitch Ball Grid Array -40C to +85C

PACKAGE DIMENSIONS FOR 256 PIN FINE PITCH BALL GRID ARRAY

256 Fine Pitch Ball Grid Array

(17.0 mm x 17.0 mm, fpBGA)

Re v. 1.0 0

SYMBOL MIN MAX MIN MAX

A 0.058 0.070 1.48 1.78

A1 0.013 0.017 0.33 0.43

A2 0.045 0.053 1.15 1.35

D 0.661 0.677 16.80 17.20

D1 0.591 BSC 15.00 BSC

b 0.020 0.024 0.50 0.60

e 0.039 BSC 1.00 BSC

INCHES MILLIMETERS

Not e: T he c ontrol dim ension i s in m i ll i m et er.

A1 corner

13245

789

10 6

1314

AA2

(A1 corner feature is mfger option)

Plane

Seating

1516

XRT86VX38

181

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

PACKAGE DIMENSIONS FOR 329 PIN FINE PITCH BALL GRID ARRAY

329 Fine Pitch Ball Grid Array

(17.0 mm x 17.0 mm, fpBGA)

Re v. 1.00

SYMBOL MIN MAX MIN MAX

A 0.056 0.067 1.43 1.71

A1 0.010 0.014 0.26 0.36

A2 0.046 0.053 1.17 1.35

D 0.663 0.675 16.85 17.15

D1 0.567 BSC 14.40 BSC

b 0.014 0.018 0.36 0.46

e 0.031 BSC 0.80 BSC

INCHES MILLIMETERS

Not e: The cont rol di m ension i s i n m i l l i m eter.

A1 corner

13245

78910 6

121314

D1D

A1AA2

(A1 corner feature is mfger option)

Plane

Seating

18 17 1516 15151519

182

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuits descr ibed herein , conveys no license unde r any p atent or other r ight, and makes no repre sentatio n that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

purposes and may vary depending upon a user’s specific application. While the information in this publication

has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the

failure or malfunction of the product can reasonably be expected to cause failure of the life support system or

to significantly affect it s safety or effectiveness. Products ar e not authorized for use in such applications unless

EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has

been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately

protected un de r the circumstances.

Datasheet November 2013.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4

P4.

REVISION HISTORY

REVISION #DATE DESCRIPTION

1.0.0 M ay 2009 Release of the XRT86VX38 E1 Register Description Datasheet.

1.0.1 Jun e 15, 2009 Update the package name to fpBGA, update applications and features lists

1.0.2 January 29, 2010 Clarified the RxSYNC (Sect13) operation for the RLOS feature, added GPIO Reg-

isters 0x0102 and 0x4102, and general edits.

1.0.3 June 24, 20 11 Modified EQC table (removed "N" channel reference), added LCV and AIS inter-

upt bits to registers 0xFN4, 0xFN5 & 0xFN6.

1.0.4 October 29, 2013 Changed to new Exar logo, updated Rev ID, modified RDS0MR, TDS0MR, TICR,

RICR and PRBSCSR0 register descriptions.

ECN 1348-03