DL6000TM Family Fast Field Programmable Gate ArrayTM Features * System Clock Rates Up To 200 MHz * 9,000 to 105,000 Usable Gates * Synchronous Dual-port RAM with 8 ns Access Time * 2 Analog PLLs For Clock Multiplication, Division and Locking * LV-TTL and GTL Interface Levels * Up to 10 LVDS Compatible Inputs * Up to 10 Differential or Single-Ended LV-PECL Inputs * 1.3 ns Input Register Setup Time * 33/66 MHz PCI Compatible * Partial Reconfiguration * 10 Clock Trees with 150 ps Skew * 3.3 Volt Operation * 5 Volt Tolerant I/O * Patented Active Repeater Architecture * In-System Reprogrammability (ISP) * JTAG Support * Output Slew Rate Control * Fully Automatic Implementation With DynaToolTM Applications Examples * * * * * Introduction The DL6000 is DynaChip's second generation Fast Field Programmable Gate Array family. Built on a deep sub-micron CMOS process, this family supports applications with system clock rates up to 200 MHz. The DL6000 family features DynaChip's patented Active Repeater Architecture. This results in extremely short routing delays allowing these devices to run at system frequencies well above conventional FPGAs. To support the fast data rates of high-speed applications, every I/O pin can be programmed to LV-TTL or GTL interface levels. DL6000 family devices contain synchronous RAM with 8 ns access time. These flexible RAM structures operate in true dual and single port modes and are ideal for applications that require fast access to memory. Telecommunication Datacommunication High Speed Graphics DSP ASIC Emulation High operating frequencies, on-chip RAM, fast I/O and PCI compatibility make these devices ideal for high-speed telecommunications, datacommunications, graphics and emulation applications. The DL6000 features SRAM-based programming allowing the devices to be configured in-circuit and reprogrammed on-the-fly. They support dynamic single-block reconfiguration enabling a portion of the device to be reprogrammed without affecting operation of the remaining logic. Device Gates DL6009 DL6020 DL6035 DL6055 DL6080 DL6105 9,000 20,000 35,000 55,000 80,000 105,000 Logic Blocks 256 576 1,024 1,600 2,304 3,136 Max User RAM Bits 8,192 18,432 32,768 51,200 73,728 100,352 Flip Flops Clock Trees I/O Blocks 768 1,536 2,560 3,840 5,376 7,168 10 10 10 10 10 10 128 192 254 320 384 448 Table 1: DL6000 Family Datasheet September 1998 DL6000 - Fast Field Programmable Gate Array Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Performance Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 High Performance Active Repeater Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Top-Level Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Routing Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Input/Output Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Phase Lock Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Microprocessor Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Dynamic Reconfiguration Using Full Chip Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Partial Reprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Configuration Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Mode Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Flip Flop Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Configuration Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Serial PROM Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Microprocessor Configuration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Programming Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bitstream Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Product Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Clock and Set/Reset Buffer Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Input and Output Block Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Three-state Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Logic Block Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 RAM Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Programmable Interconnect Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 352-pin SBGA - DL6035 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 208-pin QFP - DL6035. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 352-pin SBGA - DL6020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 352-pin SBGA - DL6009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 352-pin SBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 208-pin Thermal Enhanced PQFP (PQ208) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Page 2 DynaChip DL6000 - Fast Field Programmable Gate Array Performance Examples The DL6000 family with DynaChip's patented Active Repeater Architecture supports high-speed applications with clock rates up to 200 MHz. The following table shows the performance of various size functions implemented in the DL6035*. DL6035 - G Logic Block Count 8-bit Fully Synchronous, Loadable Up Counter Circuit 145 MHz 9 16-bit Fully Synchronous, Loadable Up Counter 140 MHz 20 32-bit Fully Synchronous, Loadable Up Counter 125 MHz 42 64-bit Fully Synchronous, Loadable Up Counter 100 MHz 86 32x32 RAM-based FIFO 100 MHz 49 128x32 RAM-based FIFO 80 MHz 145 64-bit Shift Register 160 MHz 64 250 MHz - Maximum chip-to-chip performance** Table 2: Performance of Various Applications * Based on -G speed grade over commercial voltage and temperature range. ** With 10 pF load and fast slew rate. High Performance Active Repeater Technology The enabling technology behind DynaChip's Fast Field Programmable Gate Arrays is the Active Repeater. Conventional FPGA devices use pass gates to create programmable interconnections. These pass gates act like a series of resistors with distributed capacitance to ground. Nets formed out of these pass gates slow down dramatically as the number of programmable connections increases. This results in long, unpredictable delays, especially for nets that have to travel a long distance or drive a large number of loads. In contrast, DynaChip uses Active Repeaters to create programmable interconnections. As shown in figure 1, these repeaters buffer the signal at every interconnection point and isolate the capacitance of the rest of the net. The result is fast, predictable performance even for long, high fanout nets. Logic Block C C C Figure 1: DynaChip's Active Interconnect DynaChip Page 3 DL6000 - Fast Field Programmable Gate Array In FPGA devices that use pass-gate based interconnect, net delays increase quadratically with the number of programmable interconnect points, as shown in figure 2. This results in a performance bottleneck that is especially troublesome for nets that have to travel a long distance or drive a large number of loads. Interconnect Delay In devices that use Active Repeaters for interconnect, net delays are linear and are not affected by fanout. The result is much higher performance and greater predictability. # of Connections Pass-gate Interconnect Active Repeater Figure 2: Active RepeaterTM vs. Pass Gate Delays Page 4 DynaChip DL6000 - Fast Field Programmable Gate Array Top-Level Architecture At the very top level, DynaChip devices look a lot like conventional FPGA devices. As shown in figure 3, input/output blocks surround the edges of the device, an array of logic blocks fill the interior and routing tracks are distributed between the rows and columns of logic blocks. The difference in DynaChip's architecture lies in the routing resources. Input and Output Blocks Logic Blocks Routing Tracks Figure 3: High Level View of Architecture Routing Architecture DynaChip's architecture is optimized for Active Repeater technology. As shown in figure 4, interconnect resources consist of a series of vertical and horizontal wires that make up a routing region. Buffers that drive these wires can be turned on and off to create the required connections. Since every buffer drives a fixed load, it has been carefully optimized to provide maximum performance. The fixed load nature of the interconnect results in completely predictable performance since the delay through the buffer is fixed. Routing regions are connected with Active Repeaters. After passing through an Active Repeater, signals are available throughout the next routing region. In the DL6000 family, each routing region is 3 columns wide by 3 rows tall. The location of the Active Repeaters are staggered so that each logic block has its own 3 x 3 region. DynaChip Page 5 DL6000 - Fast Field Programmable Gate Array Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Active Repeater Connection Buffer Input Connection Each vertical line shown represents 9 actual vertical lines Each horizontal line shown represents 15 actual horizontal lines Figure 4: Routing Architecture This architecture results in completely deterministic performance within a routing region. The logic block delays specified in this datasheet include the delay of the connection buffers and all the routing within a region (refer to table 24 for logic block delays). As shown in figure 5, this architecture allows a logic block to drive all 9 blocks in the 3 column by 3 row routing region with no additional routing delays. This allows even high fanout nets to have extremely high performance. Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Figure 5: Routing Region With No Interconnect Delay For signals that drive blocks in the next region, the fixed delay through an Active Repeater is added to the logic block delay. These Active Repeater delays are the only routing delays in the device and their performance is completely specified in this datasheet (refer to table 27 for Active Repeater delays). Page 6 DynaChip DL6000 - Fast Field Programmable Gate Array As shown in figure 6, a logic block output can drive 33 logic blocks with just 1 Active Repeater delay. This allows structures with up to 660 gates of logic or 1,056 bits of RAM to be implemented with just 800 ps routing delay. With 2 Active Repeater delays, a logic block output can drive 73 logic blocks. This allows up to 1,460 gates of logic or 2,336 bits of RAM with just 1.6 ns routing delay. All routing delays in the device are fixed and are not affected by the fanout on the net. LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK Source block Access with no repeaters Access with 1 repeater Access with 2 repeaters Figure 6: Logic Block Reached With 2 Repeaters DynaChip Page 7 DL6000 - Fast Field Programmable Gate Array Input/Output Blocks Every input/output block in the DL6000 can be independently set to TTL and GTL interface levels. The 10 clock inputs can also be set to single-ended or differential LVPECL levels. When set to differential LV-PECL, the inputs are compatible with LVDS. If any of these 10 inputs are not used for clock signals, they can be used as general purpose inputs. When set to TTL mode, input/output blocks are 100% compliant with 33Mhz and 66 MHz PCI busses. Each input/output block can be configured for input, output or bi-directional signals. Each block has 2 flip flops that can be used to register input and output signals. Each flip flop has a clock enable input. Clock signals for flip flops in the input/output blocks are sourced from either of the 2 global clock pins and either of the 2 quadrant clock pins for that region. Each output has individual slew rate control and 3-state capability. The 3-state enable for each output can be controlled individually. Each input/output block contains dedicated JTAG Boundary Scan logic compatible with IEEE specifications. From Global Set/Reset Line Input/ Output Pad 202 R Bidirectional Boundary Scan Circuit D To Vertical or Horizontal Routing Channels (Input Data) Q 201 CLK From Global Clock Array 1 From Global Clock Array 2 204 203 From Quadrant Clock Array 1 205 From Quadrant Clock Array 2 S0 S1 From Horizontal or Vertical Routing Channels (Output Enable) 206 From Global Set/Reset Line 208 209 Output Slew Rate Control From Horizontal or Vertical Routing Channels (Output Data) 211 R Q S0 S1 From Horizontal or Vertical Routing Channels (Clock Enable) D 212 210 CLK From Global Clock Array 1 Bidirectional Boundary Scan Circuit 214 From Global Clock Array 2 215 216 From Quadrant Clock Array 1 From Quadrant Clock Array 2 S0 S1 Figure 7: Input/Output Block Page 8 DynaChip DL6000 - Fast Field Programmable Gate Array LVDS When set to differential LV-PECL levels, the 10 clock inputs can interface to LVDS levels using a 100 ohm shunt resistor as shown in the following figure. If these inputs are not used for clock signals, they can be used as general purpose inputs. 3.3V 3.3V Z = 50 LVDS Z = 50 LV-PECL 100 Figure 8: Interfacing LVDS to LV-PECL Logic Block The logic block in the DL6000 is extremely flexible and can implement a wide variety of functions. Each block has 18 inputs. One of the inputs is dedicated for clocking and one is for a set or reset signal. The remaining 16 are general purpose inputs to the logic block. Each logic block contains combinatorial logic, RAM and two flip flops. The combinatorial section contains flexible building blocks optimized for high utilization. Structures like multiplexers, AND/OR gates, comparators and arithmetic functions are automatically mapped to these resources by the DynaChip Development System. A multiplexer allows the outputs of the combinatorial logic to exit the block directly or to serve as inputs to the two flip flops. Local, Global or Quadrant Clock Local or Global Set/Rst I N P U T S AND/OR MUX ARITHMETIC 32-bit RAM F-F M U X F-F COMB M U X O U T P U T S Figure 9: Logic Block Figure 10 shows a detailed diagram of the logic block in the DL6000. The logic block contains sections that are optimized for AND/OR logic, multiplexers, arithmetic logic and RAM. All logic block inputs have polarity control allowing signals to be inverted as they enter the block. Each logic block contains two storage elements that can be configured as D-type or T (toggle) flip flops. The flip flops share a common clock that can be driven by the DynaChip Page 9 DL6000 - Fast Field Programmable Gate Array device's global or quadrant clocks or by local interconnect. The clock input to each logic block has polarity control allowing the flip flops to be triggered from either clock edge. The flip flops also share a common set/reset signal that is driven by the device's global set/reset or by local interconnect. Each flip flop can be configured to have either a set or reset capability. The set/reset input to each logic block has polarity control allowing active high or active low operation. Each logic block has 3 outputs that are driven by the combinatorial logic, RAM or flip flops. Page 10 DynaChip DL6000 - Fast Field Programmable Gate Array Global SR LCLK 1 PC PC GCLK 1 GCLK 2 GCLK 1 GCLK 2 PC FB PC 2 Clock Enable PC OR4 MUX5 AND/OR Logic FA PC MUX3 LSR PC 63 F A6 G7 8 PC PC G10 Q D/ T PC 13 14 R PC G15 PC PC MUX17 FH FI FJ S MUX11 OR9 FD FE FF 16 R PC 18 RA PC RB PC 19 G20 21 PC PC PC OR23 G22 S MUX24 RD RE RF D/ T Q 26 RH PC RI PC RJ PC G27 R Multiplexer Logic MUX28 29 Arithmetic Logic A31 M 38 A30 A35 A34 A33 A32 36 A37 A39 A40 RAM Logic FJ RI RJ RA FD FB RB FF FE FA FH RH FI CLK WE D0 D1 A0(0) A0(1) A0(2) A0(3) A1(0) A1(1) A1(2) A1(3) A4/W A4R SRAM F (Rout1) R (Rout0) Polarity Control PC Programmable Point 64,65,66 GND Figure 10: Logic Block Resources DynaChip Page 11 DL6000 - Fast Field Programmable Gate Array RAM Each logic block in DL6000 family devices contain a 32-bit fully synchronous configurable RAM. The RAM can be configured as a 32x1 dual port RAM, a 32x1 single port RAM or two 16x1 RAMs with independent data and addresses. The RAM is "self-timed" which makes both read and write operations fully synchronous. The user only needs to be concerned with maintaining setup and hold times for all inputs with respect to the clock. This includes the WE, data and address inputs. There is no need for standard RAM timing parameters such as `WE pulse width', `write cycle' or `read cycle'. From a timing standpoint, the RAM can be treated just like a flip-flop. The RAM includes a clock generator cell and latches data on its inputs and outputs. Upon receipt of a LOW-to-HIGH transition on the clock input, the clock generator creates a set of internal signals for the RAM. During a write cycle, the clock generator creates a pulse to latch the write enable, data and address inputs. During a read cycle a pulse is generated to latch the addressed data in the output latches. Both read and write operations are completed upon a single low-to-high transition of the clock. This is true for both single and dual port modes. Timing diagrams for the 2 operations are shown in figure 11. Write Cycle CLK tWS tWH WE tAS tAH Addresses tDS tDH Data Read Cycle CLK tWS tWH WE tAS tAH Addresses tROS Output Figure 11: Read/Write Cycle Timing Page 12 DynaChip DL6000 - Fast Field Programmable Gate Array CLK CLOCK GENERATOR O0O WE WE D Q D ARW LE A4 RAM 1 O D Q LE O0O D D Q LE A[0:3] WE D D Q R O ARW LE RAM 0 D Q LE Figure 12: 32x1 Single Port RAM Figure 12 shows the configuration for the 32x1 Single Port RAM. There are 5 bits for address (A0 - A4), a data input (D), a write enable (WE) and a clock input. All 7 inputs are totally synchronous to the clock. Just like an edge triggered flip flop, the only timing requirement is that all setup and hold times must be obeyed. When WE is HIGH, the RAM is in the write mode. Data presented on the D input will be written to the location specified by addresses A0 - A4. During a write cycle, the output of the RAM is in an unknown state. When WE is LOW, the RAM is in the read mode. The data stored in the location specified by A0 - A4 appears on the output after the rising edge of the clock. This is a single clock operation. The WE and A0 - A4 are setup before the rising edge of the clock and the data stored in the RAM appears after the rising edge of the clock. DynaChip Page 13 DL6000 - Fast Field Programmable Gate Array CLK CLOCK GENERATOR RAM 1 WE D Q WE F D LE O ARW LE DP D1 D Q D Q LE A1[0:3] D Q LE D0 D Q LE A0[0:3] D Q WE D DP O ARW R D Q LE RAM 0 LE Figure 13: Dual 16X1 Single Port RAM Figure 13 shows the configuration for the dual 16X1 single port RAM. The cell contains 2 separate 16X1 RAMs where each has their own address and data pins. The dual RAM has 12 inputs. There are 4 bits of address (A00 - A03) and a data input (D0) for RAM 0 and 4 separate bits of address (A10 - A13) and a separate data input (D1) for RAM 1. Both RAMs share the same write enable (WE) and clock input. All 11 inputs are totally synchronous to the clock. Just like an edge triggered flip flop, the only timing requirement is that all setup and hold times are obeyed. Operation of the RAMs is identical to that of the 32X1 single port. When WE is HIGH, the RAMs are in the write mode. Data presented on the D0 input will be written to the location specified by addresses A00 - A03 while data presented on the D1 input will be written to the location specified by addresses A10 - A13. During a write cycle, the outputs of the RAMs are in an unknown state. When WE is LOW, the RAMs are in the read mode. After the rising edge of the clock, the data stored in the location specified by A00 - A03 appears on the output of RAM 0 and the data stored in the location specified by A10 - A13 appears on the output of RAM 1. This is a single clock operation. Page 14 DynaChip DL6000 - Fast Field Programmable Gate Array CLK CLOCK GENERATOR RAM 1 O0O WE D Q WE D LE AR O AW AW[0:3] D Q LE A4W D Q LE A4R D Q LE R WE O0O D D Q D Q D O AW LE AR LE AR[0:3] RAM 0 D Q LE Figure 14: 32x1 Dual Port RAM Figure 14 shows the configuration for the 32x1 Dual Port RAM. This is a true dual port RAM with separate read and write addresses. The RAM has 5 bits of read address (A0R - A4R), 5 bits of write address (A0W - A4W), a data input (D), a write enable (WE) and a clock input. All 12 inputs are totally synchronous to the clock. Just like an edge triggered flip flop, the only timing requirement is that all setup and hold times are obeyed. The operation of the dual port RAM is slightly different than that of the single port RAMs. When WE is HIGH, the RAM is in the write mode. Data presented on the D input will be written to the location specified by addresses A0W - A4W. The dual port RAM is always in read mode. The state of WE is unimportant thus WE can either be a "0" or a "1". The data stored in the location specified by A0R - A4R will appear on the output after the rising edge of the clock. This is a single clock operation. There is one exception to the rule that the RAM is always in read mode. If the read and write addresses are equal and WE is HIGH, the write function takes precedence over the read. As a result, when reading and writing to the same location, only the write function is enabled and the output will be at an unknown state. Note that if WE is LOW, the dual port RAM is in read mode and there will never be a conflict when the read and write addresses are identical. DynaChip Page 15 DL6000 - Fast Field Programmable Gate Array Clock Distribution DL6000 family devices have 10 low-skew clock distribution networks. These networks are driven by dedicated pins on the device, internal logic or by the internal PLLs. Two of the clock networks are global clocks that can drive every flip flop in the device. Eight of the networks are quadrant clocks. The quadrant clocks can drive all the logic block flip flops in one quarter of the device and the I/O flip flops adjacent to these logic blocks. When driven by input pins, each of the 10 clocks are programmable to LV-TTL, GTL or LV-PECL interface levels. When set to LV-PECL, clock inputs can be single-ended or differential. Any I/O pin can be used to drive a clock signal out of the device for use elsewhere in the system. Phase Lock Loops Devices in the DL6000 family contain 2 analog phase lock loop (PLL) circuits that are used for clock multiplication, division and phase locking. The output clock from the PLL has a duty cycle of 50% +/- 5% and a lock time of 1 ms. As shown in figure 15, the output of each PLL can drive 1 global clock and 4 quadrant clock trees. The multipliers and dividers for each quadrant can be set independently. This allows each PLL to generate up to 5 derivative frequencies from the incoming clock. FGCLK V co f in m Phase Detector ~ k1 k2 n k3 FQCLK1 FQCLK2 FQCLK3 FQCLK4 k4 Figure 15: PLL Frequencies for quadrant clock outputs can be divided or multiplied according to the following formula. fQCLKx = fin*n / kx*m Frequencies for global clock outputs can be multiplied according to the following formula. fGCLK = fin*n / m Page 16 DynaChip DL6000 - Fast Field Programmable Gate Array Values for k, m, and n can be programmed as shown in table 3. Variable Allowable Values k 2,3,4,6 or 8 m 1 or 2 n 2,3,4,6 or 8 Table 3: PLL Variables The following tables show the available multipliers and dividers for different frequencies. Fin Min 14.4 Fin Max 20.6 GCLK Multiplier 8 19.2 27.5 6 1 (Lock) 28.8 41.3 4 1 (Lock) 38.3 55.0 3 1 (Lock) 57.5 82.5 2 1 (Lock) 76.7 110.0 1 1/2 1 (Lock) 115.0 200.0 1 (Lock) QCLK Multiplier 4 2 2/3 2 1 1/3 1 (Lock) 3 2 1 1/2 1 (Lock) 2 1 1/3 1 (Lock) 1 1/2 1 (Lock) 1 (Lock) QCLK Dividers 3/4 2/3 1/2 3/4 1/2 3/8 2/3 1/2 1/3 1/4 1/2 3/4 3/8 1/4 3/16 1/2 1/3 1/4 1/6 1/8 Table 4: Multipliers and Dividers for PLL1 Notes: (1) PLL1 is located in the top left corner and drives GCLK1, QCLK1TL, QCLK1TR, QCLK1BL, and QCLK1BR. (3) Some frequencies require an external resistor connected to the PLL1REST pin. DynaChip Page 17 DL6000 - Fast Field Programmable Gate Array Fin Min 10.3 Fin Max 14.4 GCLK Multiplier 8 13.8 19.2 6 20.6 28.8 4 1 (Lock) 27.5 38.3 3 1 (Lock) 41.3 57.5 2 1 (Lock) 55.0 76.7 1.5 1 (Lock) 82.5 115.0 1 (Lock) QCLK Multiplier 4 2 2/3 2 1 1/3 1 (Lock) 3 2 1 1/2 1 (Lock) 2 1 1/3 1 (Lock) 1 1/2 1 (Lock) 1 (Lock) QCLK Dividers 3/4 2/3 1/2 3/4 1/2 3/8 2/3 1/2 1/3 1/4 3/4 1/2 3/8 1/4 3/16 1/2 1/3 1/4 1/6 1/8 Table 5: Multipliers and Dividers for PLL2 Notes: (1) PLL2 is located in the top right corner and drives GCLK2, QCLK2TL, QCLK2TR, QCLK2BL, and QCLK2BR. (3) Some frequencies require an external resistor connected to the PLL2REST pin. GCLK Frequency Jitter 14 to 80 MHz 3% of clock period 81 to 165 MHz 350 ps (1) Table 6: PLL Jitter Note: (1) Requires input clock jitter 100 ps. Page 18 DynaChip DL6000 - Fast Field Programmable Gate Array Power Consumption Power consumption for a specific design implemented in a DL6000 family device depends on the following factors. * Number of logic blocks used * Operating frequency * Number of outputs used * I/O interface level setting (TTL or GTL) * Output slew rate selection * Number of global and quadrant clocks used * Operating supply voltage The following table shows typical power consumption for various components of a DL6035 operating at 100 MHz. DL6035 Component Typical Power Consumption at 100 MHz Logic Block (including interconnect) 4.6 mW I/O Block set to TTL mode (excluding off-chip current) 910 W I/O Block set to GTL mode (excluding off-chip current) 7.5 mW Each Global Clock 600 mW Each Quadrant Clock 150 mW Table 7: Typical Power Consumption DynaChip Page 19 DL6000 - Fast Field Programmable Gate Array Configuration Memory cells in DynaChip FPGAs store configuration bits that control all the programmable elements in the device. These configuration bits are called a bitstream and they are loaded automatically from a PROM at power-up or under user control through a microprocessor. Systems that contain more than one DynaChip device can be set up in a programming chain to simplify connections. Configuration Modes The DL6000 supports 6 configuration modes. Five are for loading a bitstream into the device and one is for reading a bitstream out of a programmed device. The state of three special pins called mode pins sets the configuration mode of the DL6000 device. Serial Configuration Modes There are 3 serial configuration modes as described in table 8. Serial Configuration Mode Serial Internal Last Description This mode is used in 2 situations. 1) To program a single device from a serial PROM. In this mode, the DL6000 generates a clock signal to drive the serial PROM. 2) For the last device in a programming chain that uses a serial PROM. In this mode, the DL6000 generates a clock signal to drive the serial PROM and the other DynaChip devices in the chain. Serial External Not Last This mode is used for each device except the last device in a programming chain that uses a serial PROM. Serial External Last This mode is used to program a single device using a serial bitstream and a user supplied clock. It is also used for the last device in a programming chain that is programmed using a serial bitstream and a user supplied clock. Table 8: Serial Configuration Modes Page 20 DynaChip DL6000 - Fast Field Programmable Gate Array Microprocessor Configuration Modes There are 2 microprocessor configuration modes as described in table 9. Microprocessor Configuration Mode Microprocessor Last Description This mode is used in 2 situations. 1) To program a single device from a microprocessor. 2) For the last device in a programming chain that uses a microprocessor. Microprocessor Not Last This mode is used for each device except the last device in a programming chain that uses a microprocessor. Table 9: Microprocessor Configuration Modes Dynamic Reconfiguration Using Full Chip Reset Full Chip Reset enables the user to completely reset the device without turning off the power. It is typically used to prepare a device for a complete reconfiguration after initial configuration. When full chip reset is asserted, all the configuration bits and flip flops in the device are reset. This is similar to the internal reset that occurs when the device is first powered-up. Full chip reset is activated by setting the mode pins to `111' and then asserting the RESET pin (active low) for a minimum of 10 ms. The mode pins must be set before the reset is asserted. To reprogram the device after a full chip reset, set the mode pins to their appropriate values (refer to table 10, page 22) and apply another RESET pulse of at least 10 ms. As an alternative to using full chip reset, the device can be reprogrammed using a complete bitstream that programs every element. Contact the factory for availability of a complete bitstream. Partial Reprogramming After the device has been powered-up and programmed, the user can reprogram a portion of the device on the fly without affecting the existing application. To dynamically reprogram a portion of the device, set the mode pins to their appropriate value (refer to table10, page20), and then assert RESET (active low). The mode pins must be set before the RESET is asserted. The portion of the device that is not affected by the partial reprogramming operates normally during reconfiguration. Special bitstreams must be used for partial reconfiguration to insure that unused logic and interconnect from the previous function are deleted. Contact the factory for more information on availability of these special bitstreams. DynaChip Page 21 DL6000 - Fast Field Programmable Gate Array Some of the non-dedicated configuration I/O do not function as user I/O during dynamic reprogramming as indicated below: In Serial Mode: * Pins M0, M1, M2 and D0, become dedicated for programming. * The DONE pin becomes dedicated for programming when the device is used in a programming chain. * The DOUT pin becomes dedicated for programming if readback is required. * The rest of the I/O's remain operational. In Processor Mode: * Pins M0, M1, M2, D0, D1-D7, WE and RDY become dedicated for programming. * The DONE pin becomes dedicated for programming when the device is used in a programming chain. * The DOUT pin becomes dedicated for programming if readback is required. * The rest of the I/O's remain operational. Readback Once the device has been programmed, a configuration mode called readback can be used to read the program bitstream out of the device to determine if it was loaded properly. Configuration Clock Frequencies In Serial Internal Last mode, the DL6000 generates a 2.5 MHz clock that is used to drive the serial PROM. In Serial External Last mode, an external clock up to 25 MHz can be supplied to the DL6000. Mode Pin Settings The state of three pins on the DL6000 device named M0, M1 and M2 determine the loading mode. The settings for each mode are shown in table 10. Configuration Mode M2 M1 M0 Serial Internal Last 0 0 0 Serial External Not Last 1 0 0 Serial External Last 0 0 1 Microprocessor Last 1 0 1 Microprocessor Not Last 1 1 0 Readback 0 1 1 Full Chip Reset 1 1 1 Table 10: Mode Pin Settings Note: If the mode pins are not connected, they are pulled down to a logic '0'. Page 22 DynaChip DL6000 - Fast Field Programmable Gate Array Flip Flop Initialization After configuration, flip flops are in an unknown state. All flip flops can be initialized by applying a global reset signal to the device. Upon assertion of the global reset, I/O and logic block flip flops are either set or reset depending on their definition in the design. Configuration Schematics The following schematics show typical connections to the DL6000 for each loading mode. Serial PROM Configuration Mode In the serial PROM configuration mode, the device automatically loads itself from a serial PROM when the system is powered up. The PROM provides serial data and responds to a clock signal generated by the DL6000 device. Systems using this loading mode should be connected as shown in figure 16. Serial Data Memory CLK D0 PCLK SYSDONE CE Reset/OE DL6000 0 0 0 1 M0 M1 M2 STRPGM Reset Reset Figure 16: Serial PROM Configuration Schematic Microprocessor Configuration Mode In the microprocessor configuration mode, the device is loaded under user control from a microprocessor interface. Data is loaded into the DL6000 device byte-wide in response to the rising edge of a write enable signal. The DL6000 device generates a ready signal that indicates it is ready for the next byte of data. Systems using the microprocessor configuration mode should be connected as shown in figure 17. DynaChip Page 23 DL6000 - Fast Field Programmable Gate Array Data 8 D0, D[7:1] DL6000 P RDY WE STRTPGM SYSDONE 1 M0 0 M1 1 M2 Reset Figure 17: Microprocessor Configuration A microprocessor can also be used to load the DL6000 family device in serial external mode. In this configuration, the microprocessor supplies a clock and serial data to the DL6000 family device. Programming Chains Programming chains simplify connections for systems that use more than one DL6000 family device. Using programming chains, one DL6000, called the last device, connects to the source of the configuration data. The remaining DL6000 devices connect in a chain using their serial configuration pins. Systems using programming chains with a serial PROM should be connected as shown in figure 18. Systems using programming chains with a microprocessor should be connected as shown in figure 19. Page 24 DynaChip DL6000 - Fast Field Programmable Gate Array Most Positive Voltage VCC VCC VCC DL6000 DL6000 DL6000 Done Done PCLK PCLK Reset Reset VCC Reset 0 M0 0 M0 0 M0 0 M1 0 M1 0 M1 1 M2 1 M2 0 M2 1 STPGM SYS Done SYS Done STPGM D0 D0 GND Serial Memory Reset/OE STPGM PCLK CLK SYS Done CE D0 GND GND Data Reset GND Most Negaitive Voltage Figure 18: Programming Chain Using Serial Memory DynaChip Page 25 DL6000 - Fast Field Programmable Gate Array Most Positive Voltage VCC VCC VCC DL6000 DL6000 DL6000 Done Done Reset Reset VCC Reset Processor 0 M0 0 M0 1 M0 1 M1 1 M1 0 M1 1 M2 1 M2 1 M2 STPGM SYS Done SYS Done STPGM STPGM D0, D[7:1] D0, D[7:1] D0, D[7:1] RDY RDY RDY WE WE GND WE GND SYS Done GND D[7:0] GND Most Negaitive Voltage Figure 19: Programming Chain Using Microprocessor Bitstream Size The size of the programming bitstream for a DL6000 family device depends on the number of logic blocks that are used in the design. The following table shows the maximum number of programming bits for each device in the DL6000 family. Device Maximum Number of Programming Bits DL6009 140,000 DL6020 270,000 DL6035 450,000 DL6055 670,000 DL6080 940,000 DL6105 1,300,000 Table 11: Maximum Number of Programming Bits Page 26 DynaChip DL6000 - Fast Field Programmable Gate Array Configuration Pins Two types of pins are used in the configuration process. Permanently dedicated pins are always dedicated to configuration functions. User pins that can have special functions become user I/O pins after device configuration Pin PCKI/ PCKO Dedicated Yes Function This pin has 3 different functions depending on the programming mode. 1) If the device is the only device to be programmed or is last in a programming chain and an external clock is not being used, this pin is an output that sends the master clock to all other devices and the serial PROM. 2) If the device is in a programming chain and is not the last device, this is an input pin that receives the master clock from the last device. 3) If an external, user supplied clock controls the configuration process, this pin is the input for that clock. When not in programming, this pin defaults to an input. STRPGM Yes This pin should be connected as shown in the configuration schematics. RESET Yes This reset is used for dynamic reprogramming. It is asserted by setting the mode pins to any value except `111' and asserting the RESET pin (active low) for a minimum of 10 ms. Note that the mode pins must be set before the RESET is asserted. All non-dedicated configuration I/O's assume states based on the function defined by the programming mode. If dynamic reprogramming is not required, the RESET pin should be connected as shown in the configuration schematics. DynaChip SYS DONE Yes This output pin is dedicated for programming. Once configuration has been completed, this pin goes from low to high and stays high until either the power is turned off or a reset signal is applied. If the device is the last or only device to be programmed, this pin signals the device that configuration has been completed and to start normal operation. Also, if the device is the last in a programming chain, this pin signals all other devices that programming has been completed and to return to normal operation. This signal also controls the enabling and disabling of a serial PROM(s). M0 - M2 No These pins are inputs during programming. They are used to tell the device(s) which mode will be used for configuration. The list of settings for each configuration mode is shown in table 10. These pins become I/O's during normal operation. If the mode pins are not connected, they are pulled down to a logic `0'. Page 27 DL6000 - Fast Field Programmable Gate Array Pin Page 28 Dedicated Function DONE No This is an input pin during programming that is only used in a multiple device configuration mode. If the device is not last, the DONE pin is tied to the SYSDONE pin of the last device. A low to high on this pin signals that programming has been completed and the device begins normal operation. This pin can be used as an I/O during normal operation. D0 No This is an input pin during programming. It accepts serial data from a memory source or another device. It can also accept the LSB from a byte wide memory source for microprocessor configuration mode. This pin can be used as an I/O during normal operation. D1 - D7 No These are data input pins for the microprocessor configuration mode. They are only activated after the reset signal has been applied. They accepts bits 1 - 7 of data loaded from a parallel source. Can be used as I/Os during normal operation. WE No This is a input pin during microprocessor configuration mode. It is only activated after the reset signal has been applied. This pin is used by the processor to signal the DL6000 that 8-bits have been placed on the D[7:0] pins for loading. This pin becomes an I/O during normal operation. RDY No This is an output pin for microprocessor configuration mode. It signals an external processor that 8 bits have been loaded and the device is ready to receive the next 8 bits. This pin can be used as an I/O during normal operation. DOUT No This outputs pin supplies the bitstream during readback mode. This pin can be used as an I/O during normal operation. DynaChip DL6000 - Fast Field Programmable Gate Array JTAG All devices in the DL60000 family provide JTAG Boundary Scan. Completely compatible with IEEE specifications, this feature simplifies testing of boards with surface mount packages or closely spaced pins. Four JTAG instructions are supported as shown in table 12. JTAG Instructions Register Opcode SAMPL/PRE BSC 1000 EXTEST BSC 0000 BYPASS BYPASS 1111 IDCODE ID 1101 Table 12: JTAG Instructions The JTAG ID register is read when the DL6000 is reset and when Opcode 1101 is loaded. On power-up, the opcode defaults to 1101. Internal pull-up resistors are provided on the TDI and TMS pins. The DL6000 JEDEC ID number is 331-300-6100-0. DynaChip Page 29 DL6000 - Fast Field Programmable Gate Array Product Specifications Maximum Ratings Symbol Description Value Unit -0.5 to +5.0 V VCC VCC Pin Potential to GND Pin VIN Input Voltage -0.5 to VCC + 0.5 V VTS Voltage applied to 3-state output -0.5 to VCC + 0.5 V TSTORE Storage temperature -65 to +150 C TJ Junction Temperature +150 C Table 13: Absolute Maximum Rating Note: Permanent damage to the device may occur if the Absolute Maximum ratings are exceeded. This is a stress rating only. Functional operation of the device at these or any other conditions other than those listed under the Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC(1) VTT Description Min Max Unit Commercial 0 C to 85 C junction 3.14 3.47 V Industrial -40 C to 100 C junction 3.0 3.6 V Supply voltage relative to GND GTL terminating voltage relative to GND Commercial 0 C to 85 C junction 1.14 1.26 V Industrial -40 C to 100 C junction 1.08 1.32 V Table 14: Recommended Operating Conditions Notes: (1) 0.25 devices require a core supply voltage of 2.5V +/- 5% and an I/O supply voltage of 3.3V +/- 5%. (2) All junction temperatures above those listed as Operating conditions are illegal. Page 30 DynaChip DL6000 - Fast Field Programmable Gate Array DC Characteristics Over Operating Conditions Symbol Parameter Min Max Units Max. voltage applied to input - 5.5 V VCMAX(6) Max. voltage applied to clock inputs - 3.63 V VIH(TTL) High-level Input Voltage 2.0 VCC + 0.3 V VIL(TTL) Low-level input voltage 0.0 0.8 V VIH(CMOS) High-level Input Voltage 0.7VCC VCC V VIL(CMOS) Low-level input voltage 0.0 0.3VCC V VIH(GTL) High-level Input Voltage VREF + 0.2 VTT V VIL(GTL) Low-level input voltage 0.0 VREF 0.2 V VIH(LVPECL) High-level input voltage 2.135 2.420 V When VCC = 3.3V VIL(LVPECL) Low-level input voltage 1.490 1.825 V When VCC = 3.3V VOH (TTL) High level output voltage V VCC min, See note 2 for IOH VOL(TTL) Low level output voltage (1,2) - 0.4 V VCC min, See note 2 for IOL VOH(GTL) High level output voltage (3,4) - VTT V VOL(GTL) Low level output voltage (3) - 0.4 V ICC Quiescent current - 10 mA IIL Leakage Current -10 +10 A CIN Input capacitance - 8.5 pF VIMAX (5) 2.4 Test Conditions IOL = 20 mA, VTT max VCC = MAX; All I/O's open Table 15: DC Electrical Characteristics Notes: (1) With 50% of the outputs simultaneously sinking 16 mA each. (2) Sink/Source current in TTL mode varies with slew rate setting: Fast slew rate: sink/source current = 16 mA (at VCC min) Medium slew rate: sink/source current = 11 mA (at VCC min) Slow slew rate: sink/source current = 5 mA (at VCC min) (3) Sink current in GTL mode = 24 mA. Source current is provided by external pull-up resistor. (4) VREF = 2/3 VTT (5) All I/O pins except clock inputs are 5 volt tolerant. (6) The maximum voltage applied to the following clock input pins should not exceed this value, even if they are used as non-clock I/O. QCLK1TL, QCLK1TLN, QCLK2TL, QCKL2TLN, QCLK1BL, QCKL1BLN, QCLK2BL, QCKL2BLN, QCLK1BR, QCLK1BRN, QCLK2BR, QCKL2BRN, QCLK1TR, QCKL1TRN, QCLK2TR, QCKL2TRN, GCLK1, GCLK1N, GCLK2, GCLK2N, PLLIREST, PLL2REST DynaChip Page 31 DL6000 - Fast Field Programmable Gate Array Clock and Set/Reset Buffer Switching Characteristics Speed Grade Description Symbol -E -F -G Max Max Max Units Clock buffer delay with PLL TCPLL 1.1 1.0 0.9 ns Global clock delay without PLL (1) TGCKD 6.7 5.6 5.0 ns Global clock skew TGCKS .15 .15 .15 ns Quadrant clock delay without PLL(1) TQCKD 5.5 5.0 4.5 ns Quadrant clock skew TQCKS .15 .15 .15 ns Clock min pulse width high TMPH 2.4 2.2 2.0 ns Clock min pulse width low TMPL 2.4 2.2 2.0 ns Global Set/Reset delay TGSR 33 30 27 ns Table 16: Clock Buffer AC Characteristics (Input Set to TTL) Notes: (1) Global and quadrant clock delays are measured from the input pin on the device to the flip flop clock input. (2) All delays are specified over commercial voltage and temperature range. (3) Clock delays are also referred to as latency. Speed Grade Description Symbol -E -F -G Max Max Max Units Clock buffer delay with PLL TCPLL 1.9 1.7 1.6 ns Global clock delay without PLL (1) TGCKD 7.6 6.1 5.5 ns Global clock skew TGCKS .15 .15 .15 ns Quadrant clock delay without PLL(1) TQCKD 6.4 5.9 5.4 ns Quadrant clock skew TQCKS .15 .15 .15 ns Clock min pulse width high TMPH 2.4 2.2 2.0 ns Clock min pulse width low TMPL 2.4 2.2 2.0 ns Global Set/Reset delay TGSR 34 31 28 ns Table 17: Clock Buffer AC Characteristics (Input Set to GTL) Notes: (1) Global and quadrant clock delays are measured from the input pin on the device to the flip flop clock input. (2) All delays are specified over commercial voltage and temperature range. (3) Clock delays are also referred to as latency. Page 32 DynaChip DL6000 - Fast Field Programmable Gate Array Speed Grade Description Symbol -E -F -G Max Max Max Units Clock buffer delay with PLL TCPLL 1.9 1.7 1.6 ns Global clock delay without PLL (1) TGCKD 7.6 6.1 5.5 ns Global clock skew TGCKS .15 .15 .15 ns Quadrant clock delay without PLL(1) TQCKD 6.4 5.9 5.4 ns Quadrant clock skew TQCKS .15 .15 .15 ns Clock min pulse width high TMPH 2.4 2.2 2.0 ns Clock min pulse width low TMPL 2.4 2.2 2.0 ns Global Set/Reset delay TGSR 34 31 28 ns Table 18: Clock Buffer AC Characteristics (Input Set to LV-PECL) Notes: (1) Global and quadrant clock delays are measured from the input pin on the device to the flip flop clock input. (2) All delays are specified over commercial voltage and temperature range. (3) Clock delays are also referred to as latency. Speed Grade Description Symbol -E -F -G Max Max Max Units Clock buffer delay with PLL TCPLL 1.9 1.7 1.6 ns Global clock delay without PLL (1) TGCKD 7.6 6.1 5.5 ns Global clock skew TGCKS .15 .15 .15 ns Quadrant clock delay without PLL(1) TQCKD 6.4 5.9 5.4 ns Quadrant clock skew TQCKS .15 .15 .15 ns Clock min pulse width high (4) TMPH 2.4 2.2 2.0 ns Clock min pulse width low TMPL 2.4 2.2 2.0 ns Global Set/Reset delay TGSR 34 31 28 ns Table 19: Clock Buffer AC Characteristics (Input Set to Differential LV-PECL) Notes: (1) Global and quadrant clock delays are measured from the input pin on the device to the flip flop clock input. (2) All delays are specified over commercial voltage and temperature range. (3) Clock delays are also referred to as latency. (4) For RAM operation, see clock min pulse width high in table 25. DynaChip Page 33 DL6000 - Fast Field Programmable Gate Array Input and Output Block Switching Characteristics Speed Grade Description Symbol -E -F -G Max Max Max Units Input buffer combinatorial delay TINPD 4.3 3.2 2.6 ns Input Register Set-up Time (global clock) TINIS1 2.1 1.6 1.3 ns Input Register Hold Time (global clock) TINIH1 0 0 0 ns Input Register Clock to Output (global clock) TINCO1 3.5 2.6 2.1 ns TOUTIS1 6.0 4.6 3.5 ns Output Register Set-up Time (global clock) TOUTIS2 3.5 2.6 1.9 ns Output Register Hold Time (global clock) TOUTIH1 0 0 0 ns Output Register Clock to Output (global clock, TOUTCO1 3.6 2.9 2.3 ns I/O Register Clock Enable Setup Time TCES1 2.7 2.0 1.4 ns I/O Register Clock Enable Hold Time TCEH1 0 0 0 ns Input Register GSR set/reset delays TGSRI 3.4 2.6 2.1 ns Output Register GSR set/reset delays TGSRO 3.7 3.0 2.4 ns Input Register GSR set/reset setup time TGSRIS1 0.5 0.4 0.3 ns Output Register GSR set/reset setup time TGSROS1 0.5 0.4 0.3 ns Output buffer combinatorial delay (no load)(2,3) no load) (2,3) Table 20: Input and Output Buffer Parameters (I/O Set to TTL) Notes: (1) All delays are specified over commercial voltage and temperature range. (2) Output delays are specified with no load. Add the following delays to adjust for loading. Fast Slew Rate: 40 ps/pf Medium Slew Rate: 60 ps/pf Slow Slew Rate: 95 ps/pf (3) The maximum loading for outputs switching at the same time in the same direction is shown below. Significant ground bounce may occur if these guidelines are violated. Fast Slew Rate: 200 pf between each power/ground pair Medium Slew Rate: 300 pf between each power/ground pair Slow Slew Rate: 400 pf between each power/ground pair (4) Each output pin has individual slew rate control. Three-state Buffer Characteristics Speed Grade Description Symbol -E -F -G Max Max Max Units 3-state to Pad Active (no load)(2,3) T3SOE 4.5 3.7 3.3 ns 3-state to Pad Hi-Z (no load) (2,3) TINIS1 4.5 3.7 3.3 ns Table 21: Three-state Buffer Delays Notes: (1) All delays are specified over commercial voltage and temperature range. (2) Output delays are specified with no load. Add the following delays to adjust for loading. Fast Slew Rate: 40 ps/pf Medium Slew Rate: 60 ps/pf Slow Slew Rate: 95 ps/pf (3) Each output pin has individual slew rate control. Page 34 DynaChip DL6000 - Fast Field Programmable Gate Array Speed Grade Description Symbol -E -F -G Units Max Max Max Output buffer combinatorial delay (no load)(2) TOUTIS1 5.2 3.9 2.9 ns Output Register Set-up Time (global clock) TOUTIS2 3.4 2.6 2.0 ns Output Register Hold Time (global clock) TOUTIH1 0 0 0 ns Output Register Clock to Output (global TOUTCO1 2.8 2.2 1.8 ns I/O Register Clock Enable Setup Time TCES1 2.8 2.0 1.6 ns I/O Register Clock Enable Hold Time TCEH1 0 0 0 ns Input Register GSR set/reset delays TGSRI 3.5 2.6 2.1 ns Output Register GSR set/reset delays TGSRO 2.9 2.3 1.9 ns Input Register GSR set/reset setup time TGSRIS1 0.5 0.4 0.3 ns Output Register GSR set/reset setup time TGSROS1 0.5 0.4 0.3 ns clock, no load) (2) Table 22: Input and Output Buffer Parameters (I/O Set to GTL) Notes: (1) All delays are specified over commercial voltage and temperature range. (2) Output delays are specified with no load. Add the following delays to adjust for loading. GTL: 27 ps/pf Speed Grade Description Symbol -E -F -G Units Max Max Max Input buffer combinatorial delay TINPD 5.3 4.0 3.2 ns Input Register Set-up Time (global clock) TINIS1 3.2 2.4 1.9 ns Input Register Hold Time (global clock) TINIH1 0 0 0 ns Input Register Clock to Output (global clock) TINCO1 4.5 3.4 2.7 ns Table 23: Input and Output Buffer Parameters (I/O Set to LV-PECL/LVDS) DynaChip Page 35 DL6000 - Fast Field Programmable Gate Array Logic Block Switching Characteristics Speed Grade Description Symbol -E -F -G Max Max Max Units 3-input AND/OR to flip-flop delay TANDR3 3.6 3.3 3.0 ns 6-input AND/OR to flip-flop delay TANDR6 4.2 3.8 3.4 ns 9-input AND/OR to flip-flop delay TANDR9 5.1 4.6 4.1 ns 4:1 Multiplexer data to flip-flop TMUXR 3.5 3.2 2.9 ns 4:1 Multiplexer select to flip-flop TMUXSR 3.5 3.2 2.9 ns Adder/multiplier to flip-flop (sum) TADDCR 4.6 3.6 3.2 ns 3-input AND/OR combinatorial delay TANDC3 4.0 3.8 3.6 ns 6-input AND/OR combinatorial delay TANDC6 4.7 4.3 3.9 ns 9-input AND/OR combinatorial delay TANDC9 5.6 5.1 4.6 ns Adder/Multiplier delay (sum) TADDC 4.5 4.1 3.7 ns 4:1 Multiplexer data delay TMUXC 4.1 3.7 3.4 ns 4:1 Multiplexer select delay TMUXS 4.1 3.7 3.4 ns D Flip-flop setup time TSU 0.7 0.6 0.5 ns T Flip-flop setup time TSUT 0.9 0.8 0.7 ns Flip-flop clock to out (GCLK or QCLK) TCOG 2.0 1.8 1.6 ns Flip-flop clock to out (LCK2) TCOL 5.5 5.0 4.5 ns GSR set/reset to flip-flop out TGSRFF 2.2 2.0 1.8 ns LSR set/reset delay TLSR 5.9 5.4 4.9 ns Logic Block Pass Through TLBPT 4.0 3.6 3.2 ns Table 24: Logic Block Switching Parameters (Includes All Routing Delays Within Routing Region(6)) Notes: (1) All delays are specified over commercial voltage and temperature range. (2) Industrial speed grade delays are 5% higher. (3) Refer to figure 10 for a picture of the logic paths described in the above table. (4) The AND/OR combinatorial delay, adder/multiplier delay and 4:1 multiplexer delay include the complete path through the logic block from inputs through outputs, connection buffers and routing to the next logic block or active repeater. (5) The AND/OR to flip flop, 4:1 multiplexer data to flip-flop, 4:1 multiplexer select to flipflop and adder/multiplier to flip flop delay includes all elements from inputs to the D/T input of either flip flop. (6) Logic block delays shown in table 24 include all connection buffer and routing delays within a 9 block routing region. Additional delays are incurred only when a net must go through an active repeater to reach a block in another routing region. See table 27 for active repeater delays. Page 36 DynaChip DL6000 - Fast Field Programmable Gate Array Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Connection Buffer Input Connection Routing The delay through all these elements are included in the logic block delays in table 23. Figure 20: Logic Block Delays Includes Routing Within a Region RAM Switching Characteristics Speed Grade Description Symbol Read/Write Operation -E -F -G Units Max Max Max Address setup time before clock TAS 4.0 3.5 3.0 ns Address hold time after clock TAH 0 0 0 ns WE setup time before clock TWS 4.0 3.5 3.0 ns WE hold time after clock TWH 0 0 0 ns DIN setup time before clock TDS 4.0 3.5 3.0 ns DIN hold time after clock TDH 0 0 0 ns Clock min pulse width high (2) TMPH 5.0 5.0 5.0 ns Min Min Min 10.0 9.0 8.0 Read Cycle Output data valid after clock TROS ns Table 25: RAM Switching Parameters - Dual Port Mode Notes: (1) All delays are specified over commercial voltage and temperature range. (2) Applies to RAM operation only. See table 19 for clock min pulse width high in all other operating modes. DynaChip Page 37 DL6000 - Fast Field Programmable Gate Array Speed Grade Description Symbol Read/Write Operation -E -F -G Max Max Max Units Address setup time before clock TAS 4.0 3.5 3.0 ns Address hold time after clock TAH 0 0 0 ns WE setup time before clock TWS 4.0 3.5 3.0 ns WE hold time after clock TWH 0 0 0 ns DIN setup time before clock TDS 4.0 3.5 3.0 ns DIN hold time after clock TDH 0 0 0 ns Min Min Min 11.0 10.0 9.0 ns Units Read Cycle Output data valid after clock TROS Table 26: RAM Switching Parameters - Single Port Mode Note: All delays are specified over commercial voltage and temperature range. Programmable Interconnect Characteristics Speed Grade Description Symbol -E -F -G Max Max Max Horizontal Active Repeater Delay THRPT 1.2 0.9 0.8 ns Vertical Active Repeater Delay TVRPT 0.9 0.7 0.6 ns Vertical to Horizontal Active Repeater Delay TVHRPT 1.2 0.9 0.8 ns Horizontal to Vertical Active Repeater Delay THVRPT 1.2 0.9 0.8 ns Table 27: Active Repeater Switching Parameters Note: All delays are specified over commercial voltage and temperature range. Page 38 DynaChip DL6000 - Fast Field Programmable Gate Array Pin Description 352-pin SBGA - DL6035 Pin Description RESET STRPGM PCKI/PCKO SYSDONE PLL1REST PLL2REST IO_2 (1) IO_3 IO_4 IO_5 IO_6 IO_7 IO_8 IO_9 IO_10 IO_11 IO_12 IO_13 IO_14/QCLK1TLN IO_15/QCLK1TL IO_16 IO_17 IO_18/QCLK2TLN IO_19/QCLK2TL IO_20 IO_21 IO_22 IO_23 IO_24 IO_25 IO_26 IO_27 IO_28 IO_29 IO_30/GCLK1N IO_31/GCLK1 IO_32 IO_33 IO_34 IO_35 IO_36 IO_37/WE IO_38 IO_39/RDY IO_40 IO_41/DI(7) IO_42 IO_43/DI(6) IO_44 IO_45 352 SBGA Ball No. Pin Description 352 SBGA Ball No. AE25 AE24 AD22 AE3 B25 C3 C24 IO_46/QCLK1BLN IO_47/QCLK1BL IO_48 IO_49/DI(5) IO_50/QCLK2BLN IO_51/QCLK2BL IO_52 V25 V23 W26 W24 W25 Y24 Y25 C25 E24 F23 D25 F24 B26 D26 G24 E25 H23 H24 F25 J24 G25 K23 G26 K24 H25 L23 J25 L24 K25 L25 M23 L26 M24 N23 M25 N24 N25 P24 N26 R24 P25 R25 R23 T25 T24 T23 U26 U24 U25 V24 IO_53/DI(4) IO_54 IO_55/DI(3) IO_56 IO_57/DI(2) IO_58 IO_59/DI(1) IO_60 IO_61/DI(0) IO_62/TDO IO_63 IO_64 IO_65 IO_66 IO_67/M0 IO_68 IO_69 IO_70/M1 IO_71 IO_72/M2 IO_73 IO_74/DONE IO_75 IO_76/DOUT IO_77 IO_78 IO_79 IO_80 IO_81 IO_82 IO_83 IO_84 IO_85 IO_86 IO_87 IO_88 IO_89 IO_90 IO_91 IO_92 IO_93 IO_94 IO_95 AA25 Y23 AB25 AA24 AA23 AC26 AB24 AC25 AD25 AB23 AD24 AC24 AD23 AF25 AC22 AE23 AE22 AC21 AF22 AD21 AC20 AE21 AD20 AE20 AE19 AD19 AE18 AC18 AD18 AF18 AC17 AE17 AE16 AD17 AF16 AC16 AD16 AE15 AC15 AE14 AF13 AD15 AE13 Table 28: DL6035/352 Pin Description DynaChip Page 39 DL6000 - Fast Field Programmable Gate Array Pin Description IO_96 IO_97 IO_98 IO_99 IO_100 IO_101 IO_102 IO_103 IO_104 IO_105 IO_106 IO_107 IO_108 IO_109 IO_110 IO_111 IO_112 IO_113 IO_114 IO_115 IO_116 IO_117 IO_118 IO_119 IO_120 IO_121 IO_122 IO_123 IO_124 IO_125 IO_126 IO_127/TMS IO_128/TCK IO_129/TDI IO_130 IO_131 IO_132 IO_133 IO_134 IO_135 IO_136 IO_137 IO_138 IO_139 IO_140 IO_141 IO_142 IO_143 IO_144/QCLK2BR IO_145/QCKL2BRN IO_146 IO_147 IO_148/QCLK1BR 352 SBGA Ball No. AD14 AE12 AD13 AD12 AC13 AC12 AF11 AD11 AE11 AE10 AC11 AE9 AD10 AD9 AE8 AC9 AE7 AF6 AD8 AE6 AD7 AC7 AE5 AD6 AF4 AF2 AC6 AE4 AD5 AC5 AD3 AD4 AE2 AD2 AC3 AC2 AB4 AB3 AE1 AA3 AB2 AB1 Y4 AA2 Y3 W4 Y2 W3 W2 V3 V2 U4 V1 Pin Description IO_149/QCLK1BRN IO_150 IO_151 IO_152 IO_153 IO_154 IO_155 IO_156 IO_157 IO_158 IO_159 IO_160/GSR IO_161 IO_162 IO_163 IO_164/GCLK2 IO_165/GCLK2N IO_166 IO_167 IO_168 IO_169 IO_170 IO_171 IO_172 IO_173 IO_174 IO_175 IO_176/QCLK2TR IO_177/QCLK2TRN IO_178 IO_179 IO_180/QCLK1TR IO_181/QCLK1TRN IO_182 IO_183 IO_184 IO_185 IO_186 IO_187 IO_188 IO_189 IO_190 IO_191 IO_193 (2) IO_194 IO_195 IO_196 IO_197 IO_198 IO_199 IO_200 IO_201 IO_202 352 SBGA Ball No. U3 U2 T4 T2 R2 T3 P2 R3 P4 P1 P3 N2 N3 M2 M3 L2 K1 M4 K2 L3 L4 J2 K3 H1 K4 H2 J3 G2 F1 J4 F2 H3 G3 E2 G4 D1 D2 F3 C2 F4 E3 D3 B2 C4 B3 C5 B4 A3 D6 B5 C7 D8 A5 Table 28: DL6035/352 Pin Description Page 40 DynaChip DL6000 - Fast Field Programmable Gate Array Pin Description IO_203 IO_204 IO_205 IO_206 IO_207 IO_208 IO_209 IO_210 IO_211 IO_212 IO_213 IO_214 IO_215 IO_216 IO_217 IO_218 IO_219 IO_220 IO_221 IO_222 IO_223 IO_224 IO_225 IO_226 IO_227 IO_228 IO_229 IO_230 IO_231 IO_232 IO_233 IO_234 IO_235 IO_236 IO_237 IO_238 IO_239 IO_240 IO_241 IO_242 IO_243 IO_244 IO_245 IO_246 IO_247 IO_248 IO_249 IO_250 IO_251 IO_252 IO_253 IO_254 IO_255 352 SBGA Ball No. C8 C6 B6 D9 B7 C9 C10 B8 D11 A8 B9 C11 B10 D12 C12 A10 C13 B11 B12 C14 B13 D14 A14 C15 B14 D15 C16 A15 D16 B15 B16 C17 B17 D17 C18 B18 C19 A19 B19 D19 B20 C20 C21 A21 D21 B21 A22 C22 B22 B24 C23 A25 D24 Pin Description IO_256 VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_PLL VCC_PLL GND_IO GND_IO GND_IO GND_IO 352 SBGA Ball No. B23 B1 E1 L1 R1 W1 AC1 AF5 AF9 AF12 AF17 AF20 AF23 AD26 Y26 T26 K26 H26 C26 A23 A18 A16 A12 A9 A4 C1 J1 M1 T1 AA1 AD1 AF3 AF8 AF15 AF21 AF24 AE26 AB26 R26 M26 J26 E26 A24 A17 A11 A6 A2 E4 E23 D4 H4 N4 R4 Table 28: DL6035/352 Pin Description DynaChip Page 41 DL6000 - Fast Field Programmable Gate Array Pin Description GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_CORE/CLK 352 SBGA Ball No. V4 AA4 AC4 AC8 AC10 AC14 AC19 AC23 W23 U23 P23 J23 G23 D23 D20 D18 D13 D10 D7 A1 Pin Description GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_PLL GND_PLL 352 SBGA Ball No. G1 N1 U1 Y1 AF1 AF7 AF10 AF14 AF19 AF26 AA26 V26 P26 F26 A26 A20 A13 A7 D5 D22 Table 28: DL6035/352 Pin Description Notes: (1) IO_1 is not available due to the PLL1REST. (2) IO_192 is not available due to the PLL2REST. Page 42 DynaChip DL6000 - Fast Field Programmable Gate Array 208-pin QFP - DL6035 Pin Description 208 QFP Pin No. VCC_PLL GND_CK VCC_CK GND_INT PLL2REST IO_190 VCC_INT IO_187 GND_IO IO_184 VCC_IO IO_181 QCLK1TRN IO_180 QCLK1TR IO_177 QCLK2TRN SUBN-GND IO_176 QCLK2TR IO_172 IO_171 GND_IO GND_INT VCC_IO IO_166 IO_165 GCLK2N IO_164 GCLK2 IO_163 GND_IO IO_161 VCC_CK GND_CK IO_160 GSR IO_159 VCC_IO IO_157 IO_156 IO_155 GND_IO IO_153 IO_152 VCC_IO IO_149 QCLK1BRN IO_148 QCLK1BR IO_145 QCKL2BRN IO_144 QCLK2BR GND_INT GND_IO VCC_INT IO_136 VCC_IO 6035 IO_131 6035X GTL_REF_EXT IO_129 TDI Blank Pin on the 35K 208 QFP GND_CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 VCC_CK IO_128 TCK IO_127 TMS SYSDONE IO_124 IO_123 GND_IO GND_INT IO_120 IO_119 VCC_IO VCC_INT IO_116 IO_115 IO_112 IO_111 IO_108 IO_107 GND_IO GND_INT IO_104 VCC_IO VCC_INT IO_99 IO_96 IO_93 IO_92 IO_91 GND_IO IO_89 VCC_INT IO_88 IO_87 VCC_IO GND_INT IO_84 IO_83 IO_80 IO_79 IO_76 DOUT GND_IO IO_74 DONE VCC_INT IO_72 M2 VCC_IO IO_70 M1 PCKI/PCKO IO_68 IO_67 M0 Pin Description 208 QFP Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 50 51 STRPGM VCC_CK 102 103 52 GND_INT 104 Table 29: DL6035/208 Pin Description DynaChip Page 43 DL6000 - Fast Field Programmable Gate Array Pin Description GND_CK RESET IO_62 TDO IO_61 DI(0) VCC_INT IO_59 DI(1) GND_IO IO_57 DI(2) GND_INT IO_55 DI(3) VCC_IO IO_53 DI(4) IO_51 QCLK2BL IO_50 QCLK2BLN IO_49 DI(5) IO_47 QCLK1BL IO_46 QCLK1BLN IO_43 DI(6) GND_IO IO_42 IO_41 DI(7) IO_39 RDY VCC_IO IO_37 WE IO_35 IO_34 GND_CK VCC_CK IO_31 GCLK1 IO_30 GCLK1N IO_28 GND_IO IO_23 VCC_IO IO_19 QCLK2TL IO_18 QCLK2TLN IO_15 QCLK1TL IO_14 QCLK1TN IO_11 GND_IO IO_8 IO_7 VCC_IO IO_5 GND_INT IO_4 IO_3 PLL1REST VCC_INT VCC_CK GND_CK VCC_PLL 208 QFP Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Pin Description GND_PLL IO_256 IO_255 VCC_IO IO_254 IO_253 VCC_INT GND_IO IO_250 GND_INT IO_246 IO_245 IO_242 IO_241 VCC_IO IO_238 VCC_INT GND_IO IO_234 GND_INT IO_231 IO_230 IO_227 GND_IO IO_226 IO_224 IO_223 VCC_IO IO_222 IO_221 IO_220 IO_219 GND_IO IO_218 IO_217 VCC_IO IO_214 IO_213 IO_210 IO_209 IO_206 IO_205 GND_INT GND_IO IO_202 IO_201 VCC_INT VCC_IO IO_198 IO_194 IO_193 GND_PLL 208 QFP Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Table 29: DL6035/208 Pin Description Page 44 DynaChip DL6000 - Fast Field Programmable Gate Array 352-pin SBGA - DL6020 Pin Description RESET STRPGM PCKI/PCKO SYSDONE PLL1REST PLL2REST IO_2 IO_3 IO_4 IO_5 IO_6 IO_7 IO_8 IO_9 IO_10 IO_11 IO_12 IO_13 IO_14/QCLK1TLN IO_15/QCLK1TL IO_17 IO_18/QCLK2TLN IO_19/QCLK2TL IO_20 IO_22 IO_24 IO_25 IO_26 IO_28 IO_30/GCLK1N IO_31/GCLK1 IO_32 IO_33 IO_34 IO_35 IO_36 IO_37/WE IO_39/RDY IO_41/DI(7) IO_43/DI(6) IO_44 IO_46/QCLK1BLN IO_47/QCLK1BL IO_49/DI(5) IO_50/QCLK2BLN IO_51/QCLK2BL IO_53/DI(4) IO_55/DI(3) IO_57/DI(2) IO_58 352 SBGA Ball No. AE25 AE24 AD22 AE3 B25 C3 C24 C25 E24 F23 D25 F24 B26 D26 G24 E25 H23 H24 F25 J24 K23 G26 K24 H25 J25 K25 L25 M23 M24 M25 N24 N25 P24 N26 R24 P25 R25 T25 T23 U24 U25 V25 V23 W24 W25 Y24 AA25 AB25 AA23 AC26 Pin Description IO_59/DI(1) IO_61/DI(0) IO_62/TDO IO_63 IO_64 IO_65 IO_66 IO_67/M0 IO_68 IO_69 IO_70/M1 IO_72/M2 IO_74/DONE IO_76/DOUT IO_77 IO_78 IO_79 IO_81 IO_82 IO_83 IO_85 IO_87 IO_88 IO_89 IO_91 IO_93 IO_94 IO_95 IO_96 IO_98 IO_99 IO_100 IO_101 IO_102 IO_103 IO_105 IO_106 IO_108 IO_110 IO_112 IO_113 IO_115 IO_117 IO_118 IO_119 IO_120 IO_122 IO_123 IO_124 IO_125 352 SBGA Ball No. AB24 AD25 AB23 AD24 AC24 AD23 AF25 AC22 AE23 AE22 AC21 AD21 AE21 AE20 AE19 AD19 AE18 AD18 AF18 AC17 AE16 AF16 AC16 AD16 AC15 AF13 AD15 AE13 AD14 AD13 AD12 AC13 AC12 AF11 AD11 AE10 AC11 AD10 AE8 AE7 AF6 AE6 AC7 AE5 AD6 AF4 AC6 AE4 AD5 AC5 Table 30: DL6020 Pin Description DynaChip Page 45 DL6000 - Fast Field Programmable Gate Array Pin Description IO_126 IO_127/TMS IO_128/TCK IO_129/TDI IO_130 IO_131 IO_132 IO_133 IO_134 IO_135 IO_137 IO_138 IO_139 IO_140 IO_142 IO_143 IO_144/QCLK2BR IO_145/QCKL2BRN IO_146 IO_148/QCLK1BR IO_149/QCLK1BRN IO_151 IO_152 IO_154 IO_156 IO_158 IO_159 IO_160/GSR IO_162 IO_164/GCLK2 IO_165/GCLK2N IO_167 IO_168 IO_170 IO_171 IO_173 IO_174 IO_176/QCLK2TR IO_177/QCLK2TRN IO_178 IO_180/QCLK1TR IO_181/QCLK1TRN IO_183 IO_185 IO_186 IO_187 IO_188 IO_189 IO_190 IO_191 IO_193 IO_194 IO_195 352 SBGA Ball No. AD3 AD4 AE2 AD2 AC3 AC2 AB4 AB3 AE1 AA3 AB1 Y4 AA2 Y3 Y2 W3 W2 V3 V2 V1 U3 T4 T2 T3 R3 P1 P3 N2 M2 L2 K1 K2 L3 J2 K3 K4 H2 G2 F1 J4 H3 G3 G4 D2 F3 C2 F4 E3 D3 B2 C4 B3 C5 Pin Description IO_196 IO_197 IO_198 IO_199 IO_201 IO_202 IO_204 IO_205 IO_207 IO_208 IO_210 IO_212 IO_213 IO_215 IO_216 IO_217 IO_219 IO_221 IO_222 IO_223 IO_224 IO_225 IO_226 IO_227 IO_229 IO_230 IO_232 IO_233 IO_235 IO_237 IO_238 IO_240 IO_242 IO_243 IO_245 IO_247 IO_248 IO_249 IO_250 IO_251 IO_252 IO_253 IO_254 IO_255 IO_256 VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO 352 SBGA Ball No. B4 A3 D6 B5 D8 A5 C6 B6 B7 C9 B8 A8 B9 B10 D12 C12 C13 B12 C14 B13 D14 A14 C15 B14 C16 A15 B15 B16 B17 C18 B18 A19 D19 B20 C21 D21 B21 A22 C22 B22 B24 C23 A25 D24 B23 B1 E1 L1 R1 W1 AC1 AF5 AF9 Table 30: DL6020 Pin Description Page 46 DynaChip DL6000 - Fast Field Programmable Gate Array Pin Description VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_PLL VCC_PLL GND_IO GND_IO 352 SBGA Ball No. AF12 AF17 AF20 AF23 AD26 Y26 T26 K26 H26 C26 A23 A18 A16 A12 A9 A4 C1 J1 M1 T1 AA1 AD1 AF3 AF8 AF15 AF21 AF24 AE26 AB26 R26 M26 J26 E26 A24 A17 A11 A6 A2 E4 E23 D4 H4 Pin Description GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_PLL GND_PLL 352 SBGA Ball No. N4 R4 V4 AA4 AC4 AC8 AC10 AC14 AC19 AC23 W23 U23 P23 J23 G23 D23 D20 D18 D13 D10 D7 A1 G1 N1 U1 Y1 AF1 AF7 AF10 AF14 AF19 AF26 AA26 V26 P26 F26 A26 A20 A13 A7 D5 D22 Table 30: DL6020 Pin Description Note: Pins that are not shown should be left disconnected on the board. DynaChip Page 47 DL6000 - Fast Field Programmable Gate Array 352-pin SBGA - DL6009 Pin Description RESET STRPGM PCKI/PCKO SYSDONE PLL1REST PLL2REST IO_3 IO_5 IO_7 IO_9 IO_11 IO_14/QCLK1TLN IO_15/QCLK1TL IO_18/QCLK2TLN IO_19/QCLK2TL IO_22 IO_26 IO_30/GCLK1N IO_31/GCLK1 IO_33 IO_35 IO_37/WE IO_39/RDY IO_41/DI(7) IO_43/DI(6) IO_46/QCLK1BLN IO_47/QCLK1BL IO_49/DI(5) IO_50/QCLK2BLN IO_51/QCLK2BL IO_53/DI(4) IO_55/DI(3) IO_57/DI(2) IO_59/DI(1) IO_61/DI(0) IO_62/TDO IO_64 IO_65 IO_67/M0 IO_68 IO_70/M1 IO_72/M2 IO_74/DONE IO_76/DOUT IO_79 IO_82 IO_85 IO_88 IO_89 IO_91 352 SBGA Ball No. AE25 AE24 AD22 AE3 B26 C3 C25 F23 F24 D26 E25 F25 J24 G26 K24 J25 M23 M25 N24 P24 R24 R25 T25 T23 U24 V25 V23 W24 W25 Y24 AA25 AB25 AA23 AB24 AD25 AB23 AC24 AD23 AC22 AE23 AC21 AD21 AE21 AE20 AE18 AF18 AE16 AC16 AD16 AC15 Pin Description IO_93 IO_94 IO_96 IO_98 IO_101 IO_103 IO_105 IO_106 IO_108 IO_110 IO_112 IO_115 IO_117 IO_120 IO_122 IO_123 IO_125 IO_127/TMS IO_128/TCK IO_129/TDI IO_132 IO_135 IO_137 IO_138 IO_140 IO_142 IO_144/QCLK2BR IO_145/QCKL2BRN IO_148/QCLK1BR IO_149/QCLK1BRN IO_151 IO_154 IO_156 IO_158 IO_159 IO_160/GSR IO_162 IO_164/GCLK2 IO_165/GCLK2N IO_167 IO_170 IO_173 IO_176/QCLK2TR IO_177/QCLK2TRN IO_180/QCLK1TR IO_181/QCLK1TRN IO_183 IO_185 IO_188 IO_189 352 SBGA Ball No. AF13 AD15 AD14 AD13 AC12 AD11 AE10 AC11 AD10 AE8 AE7 AE6 AC7 AF4 AC6 AE4 AC5 AD4 AE2 AD2 AB4 AA3 AB1 Y4 Y3 Y2 W2 V3 V1 U3 T4 T3 R3 P1 P3 N2 M2 L2 K1 K2 J2 K4 G2 F1 H3 G3 G4 D2 F4 E3 Table 31: DL6009 Pin Description Page 48 DynaChip DL6000 - Fast Field Programmable Gate Array Pin Description IO_194 IO_196 IO_198 IO_199 IO_201 IO_202 IO_204 IO_205 IO_207 IO_210 IO_212 IO_213 IO_216 IO_219 IO_222 IO_223 IO_226 IO_229 IO_232 IO_233 IO_235 IO_237 IO_240 IO_242 IO_245 IO_247 IO_249 IO_251 IO_252 IO_253 IO_255 IO_256 VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO 352 SBGA Ball No. B3 B4 D6 B5 D8 A5 C6 B6 B7 B8 A8 B9 D12 C13 C14 B13 C15 C16 B15 B16 B17 C18 A19 D19 C21 D21 A22 B22 B24 C23 D24 B23 B1 E1 L1 R1 W1 AC1 AF5 AF9 AF12 AF17 AF20 AF23 AD26 Y26 T26 K26 H26 C26 A23 A18 A16 Pin Description VCC_IO VCC_IO VCC_IO VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_PLL VCC_PLL GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK 352 SBGA Ball No. A12 A9 A4 C1 J1 M1 T1 AA1 AD1 AF3 AF8 AF15 AF21 AF24 AE26 AB26 R26 M26 J26 E26 A24 A17 A11 A6 A2 E4 E23 D4 H4 N4 R4 V4 AA4 AC4 AC8 AC10 AC14 AC19 AC23 W23 U23 P23 J23 G23 D23 D20 D18 D13 D10 D7 A1 G1 N1 Table 31: DL6009 Pin Description DynaChip Page 49 DL6000 - Fast Field Programmable Gate Array Pin Description GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK 352 SBGA Ball No. U1 Y1 AF1 AF7 AF10 AF14 AF19 AF26 AA26 Pin Description 352 SBGA Ball No. GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_PLL GND_PLL V26 P26 F26 A26 A20 A13 A7 D5 D22 Table 31: DL6009 Pin Description Note: Pins that are not shown should be left disconnected on the board. Page 50 DynaChip DL6000 - Fast Field Programmable Gate Array Package Drawings 352-pin SBGA A1 BALL PAD CORNER 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1.625 REF 35 mm 1.27 TYP. REF 1.625 REF 35 mm UNIT SHOWN FROM BALL ARRAY SIDE (Dimensions in mm) 0.91 1.54 0.63 SIDE VIEW Figure 21: Package Drawing of 352-pin SBGA DynaChip Page 51 DL6000 - Fast Field Programmable Gate Array 208-pin Thermal Enhanced PQFP (PQ208) 208 157 Pin 1 ID 156 52 105 53 30.4 - 31.2 Sq 28.00 Sq +/- 0.1 1 104 Top View Dimension in Millimeters Lead Pitch 0.50 12 - 15 Metal Heat Sink 3.2 - 3.6 Stand-Off 0.25 Min 4.1 Max Side View 0.13 - 0.27 Figure 22: Package Drawing of 208-pin PQFP Page 52 DynaChip DL6000 - Fast Field Programmable Gate Array Ordering Information Order codes are shown below. DL6009BG352FC Prefix DL - Prefix Device 6009 6020 6035 6055 6080 6105 - 9,000 Gate Device 20,000 Gate Device 35,000 Gate Device 55,000 Gate Device 80,000 Gate Device 105,000 Gate Device Package Type BG - Ball Grid Array QP - Quad Flat Pack PG - Pin Grid Array Pin Count Speed Grade E F See Product Specifications G Temperature Range C - Commercial I - Industrial DynaChip, DL6000, DL5000, FFPGA and DynaTool are registered trademarks of DynaChip. These products may be covered by the following U.S. patents: 5355035, 5397943, 5504440, 4497108, 5614844, 5570059, 5406133, 5654665. DynaChip 1255 Oakmead Pkwy. Sunnyvale, CA 94086 Phone: 408-481-3100 Fax: 408-481-3136 Email: support@dyna.com http://www.dyna.com The information contained in this document is subject to change without notice. DynaChip Page 53 Sales Representatives 37 40 39 41 38 36 International 36 Actron Technology (China/Hong Kong) 26/F., Lever Centre 69-71 King Yip Street Kwun Tong, Kowloon, Hong Kong 852-2727-3978 FAX: 852-2727-4330 37 Ambar Components, Ltd. (U.K. & Eire) Rabans Close Aylesbury Bucks. HP19 3RS, England, U.K. 44 1296 397396 FAX: 44 1296 397439 38 CMR Design Automation Pvt. Ltd. (India) E 534 Greater Kailash II New Delhi 110 048 India 91 11 6477085 FAX: 91 11 6213498 39 Dasko, Co. Ltd. (Korea) #3808, KWTC 159-1, Samsung-dong, Kangnam-ku Seoul 135-729 Korea 82-2-551-3143 FAX: 82-2-551-6411 http://www.dyna.com 40 El-Gev Electronics Ltd. (Israel) 11 Ha'Avoda Street Rosh Ha'Ayin 48101 Israel Shipping office 183 Donna Court Lynbrook, NY 11563 (516) 599-4399 FAX (516) 599-4920 41 JEPICO Corp. (Japan) Shinjuku Dai-ichi Seimei Building Nishi-Shinjuku 2-7-1 Shinjuku-ku, Tokyo 163-0729, Japan (03) 3348-0611 FAX: (03) 3348-0623 Sales Representatives North America (cont.) 10 InTelaTech Inc. (Vancouver) 3665 Kingsway Suite 300 Vancouver, B.C. V5R 5W2 (604) 434-5699, ext. 252 FAX: (604) 434-5655 19 Mission Technology (Orange County) 24422 Avenida de la Carlotta Suite 315 Laguna Hills, CA 92653 (714) 951-3696 FAX: (714) 951-3874 11 InTelaTech Inc. (Calgary) 140, 6815 8th Street N.E. Calgary, AB T2E 7H7 (403) 686-2268 FAX: (403) 686-6926 20 Mission Technology (San Diego) 16466 Bernardo Center Drive Suite 188 San Diego, CA 92128 (619) 674-6191 FAX: (619) 674-6196 12 J-Square Marketing Inc. (CT, NY, No. NJ) P. O. Box 103 Jericho, NY 11753-0103 (516) 935-3200 FAX: (516) 935-0029 Ship to: 161C Levittown Parkway Hicksville, NY 11801 13 James E. Zimmerman Sales (W. NY) 111 Marsh Road Pittsford, NY 14534 (716) 381-3186 FAX: (716) 385-2103 14 KMA Sales Company (IL) 1040 S. Arlington Heights Arlington Heights, IL 60005 (847) 398-5300 FAX: (847) 398-5708 15 KMA Sales Company (WI) 2433 North Mayfair Road Suite 202 Milwaukee, WI 53226-1406 (414) 259-1771 FAX: (414) 259-0246 16 Millennium Sales, Inc. (No. TX, OK, LA, AR) 1701 North Greenville #1107 Richardson, TX 75081 (972) 235-5990 FAX: (972) 618-4163 17 Millennium Sales, Inc. (Austin and San Antonio, Texas) 12343 Hymeadow Drive Suite 2A Austin, TX 78750 (512) 335-2375 FAX: (512) 335-2376 18 Millennium Sales, Inc. (Houston and South Texas) 14714 Oak Bluff Court Houston, TX 77070 (281) 655-9688 FAX: (281) 655-9703 21 Mission Technology (Los Angeles) 6345 Balboa Boulevard Suite 240 Encino, CA 91316 (818) 342-3141 FAX: (818) 342-9564 22 NELCO Electronics (Denver, Utah, New Mexico) 9725 E. Hampden Avenue Suite 100 Denver, CO 80231 (303) 671-7677 FAX: (303) 671-7994 23 Oasis Sales (Minnesota, Western Wisconsin, N. Dakota, and S. Dakota) 4620 West 77th Street Suite 100 Edina, MN 55435 (612) 841-1088 FAX: (612) 841-1103 24 Premier Technical Sales, Inc. (Bay Area) 3235 Kifer Road Suite 110 Santa Clara, CA 95051 (408) 736-2260 FAX: (408) 736-2826 25 ProComp Assoc., Inc. (MA, VT, NH, ME, RI) 1049 East Street Tewksbury, MA 01876 (978) 858-0100 FAX: (978) 858-0110 26 SierraTek Marketing (Sacramento, NV) 11531 Sun Valley Road Truckee, CA 96161 (916) 587-8360 FAX: (916) 587-8361 27 Thompson Associates, Inc. (Southern Ohio) 1025 Centerville-Station Road Centerville, OH 45459 (937) 435-7733 FAX: (937) 435-1898 http://www.dyna.com 28 Thompson Associates, Inc. (Northern Ohio) 23240 Chagrin Boulevard Suite 150 Beachwood, OH 44122 (216) 831-6277 FAX: (216) 831-2553 29 Thompson Assoc., Inc. (Columbus, OH) 5321 Grosbeak Glen Orient, OH 43146 (614) 877-4304 FAX: (614) 877-0872 30 Thompson Associates Inc. (West PA) 1311 Laclair Street Pittsburgh, PA 15218 (412) 244-0317 FAX: (412) 244-0318 31 Thompson Associates, Inc. (Eastern Michigan) 26105 Orchard Lake Road Suite 212 Farmington Hills, MI 48334 (248) 476-0505 FAX: (248) 476-0156 32 Thompson Associates, Inc. (Western Michigan) 3116 Chamberlain SE Grand Rapids, MI 49508 (616) 247-6574 FAX: (616) 247-1211 33 Trinity Technologies, Inc. (Northwest) 6443 SW Beaverton-Hillsdale Highway Suite 320 Portland, OR 97221 (503) 291-1333 FAX: (503) 291-2529 34 Trinity Technologies, Inc. (Northwest) 10710 3rd Avenue NW Seattle, WA 98177 (206) 440-3059 FAX: (206) 364-6739 35 Tusar (Southwest) P. O. Box 12460 Scottsdale, AZ 85267-2460 (602) 998-3688 FAX: (602) 991-0468 Ship to: 6016 E. Larkspur Scottsdale, AZ 85254 Sales Representatives 10 11 07 34 08 33 23 25 13 12 09 15 32 31 28 14 30 06 29 27 22 40 05 26 35 24 16 17 18 02 04 21 01 19 03 20 North America 01 Apollo Technical Sales (East Coast) 1275 S. Patrick Drive Suite M2 Satellite Beach, FL 32937 (407) 777-7511 Fax (407) 777-5251 04 Apollo Technical Sales (West Coast Florida) 43 Leeward Island Clearwater, FL 33767 (813) 445-1640 FAX: (813) 468-9496 07 InTelaTech Inc. (Montreal) 1755 St. Regis Street Suite 220 DDO, Quebec H9B 2M9 (514) 421-5833 FAX: (514) 421-4105 02 Apollo Technical Sales (Central Florida) 1703 Magnolia Avenue #C13 South Daytona, FL 32119 (904) 304-3225 Fax: (904) 304-3221 05 BGR-WYCK (Chesapeake) 11350 Random Hills Road Suite 800 Fairfax, VA 22030 (703) 934-6053 FAX: (703) 648-0231 08 InTelaTech Inc. (Ottawa) 260 Hearst Way Suite 248 Kanata, ON K2L 3H1 (613) 599-7330 FAX: (613) 599-7329 03 Apollo Technical Sales (So. Florida) 1251 S. Federal Highway Suite E-120 Boca Raton, FL 33432-7352 (561) 347-1500 Fax: (561) 750-9127 06 BGR-WYCK (So. NJ to Virginia) 3701 Church Road Mt. Laurel, NJ 08054 (609) 727-1070 FAX: (609) 727-9633 09 InTelaTech Inc. (Toronto) 5225 Orbitor Drive Suite 2 Mississauga, ON L4W 4Y8 (905) 629-0082 FAX: (905) 629-1795 http://www.dyna.com