1
Data sheet acquired from Harris Semiconductor
SCHS218C
Features
• Center Frequency of 18MHz (Typ) at VCC = 5V,
Minimum Center Frequency of 12MHz at VCC = 4.5V
• Choice of Two Phase Comparators
- Exclusive-OR
- Edge-Triggered JK Flip-Flop
• Excellent VCO Frequency Linearity
• VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption
• Minimal Frequency Drift
• Zero Voltage Offset Due to Op-Amp Buffer
• Operating Power-Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Applications
• FM Modulation and Demodulation
• Frequency Synthesis and Multiplication
• Frequency Discrimination
• Tone Decoding
• Data Synchronization and Conditioning
• Voltage-to-Frequency Conversion
• Motor-Speed Control
• Related Literature
- AN8823, CMOS Phase-Locked-Loop Application
Using the CD74HC/HCT7046A and
CD74HC/HCT7046A
Description
The CD74HC7046A and CD74HCT7046A high-speed
silicon-gate CMOS devices, specified in compliance with
JEDEC Standard No. 7A, are phase-locked-loop (PLL)
circuits that contain a linear voltage-controlled oscillator
(VCO), two-phase comparators (PC1, PC2), and a lock
detector. A signal input and a comparator input are common
to each comparator. The lock detector gives a HIGH level at
pin 1 (LD) when the PLL is locked. The lock detector
capacitor must be connected between pin 15 (CLD) and pin
8 (Gnd). For a frequency range of 100kHz to 10MHz, the
lock detector capacitor should be 1000pF to 10pF,
respectively.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input amplifiers.
With a passive low-pass filter, the 7046A forms a second-
order loop PLL. The excellent VCO linearity is achieved by
the use of linear op-amp techniques.
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD74HC7046AE -55 to 125 16 Ld PDIP
CD74HC7046AM -55 to 125 16 Ld SOIC
CD74HC7046AMT -55 to 125 16 Ld SOIC
CD74HC7046AM96 -55 to 125 16 Ld SOIC
CD74HCT7046AE -55 to 125 16 Ld PDIP
CD74HCT7046AM -55 to 125 16 Ld SOIC
CD74HCT7046AMT -55 to 125 16 Ld SOIC
CD74HCT7046AM96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
0.1
CD74HC7046A,
CD74HCT7046A
Phase-Locked Loop
with VCO and Lock Detector
[ /Title
(CD74
HC704
6A,
CD74
HCT70
46A)
/Sub-
ject
(Phase-
Locked
Loop
2
Pinout
CD74HC7046A, CD74HCT7046A
(PDIP, SOIC)
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
PC1OUT
COMPIN
VCOOUT
INH
C1A
GND
C1B
VCC
SIGIN
PC2OUT
R2
R1
DEMOUT
VCOIN
CLD
LD
10
4VCOOUT
DEMOUT
5
6
7
12
C1A
R1
VCOIN
INH
9
11
C1B
R2
15
1
13
2PC1OUT
CLD
PC2OUT
LD
14
3
COMPIN
SIGIN
φ
VCO
FIGURE 1. LOGIC DIAGRAM
DEMOUT
R2
12
R1
R5
11
10
C1
R3
C2
PC2OUT 13
p
n
GND
VCC
2
PC1OUT
DOWN
RD
Q
Q
D
CP
RD
Q
Q
D
CP
UP
VCC
VCC
INH
59
VCOIN
VCO
-+
VCOOUT
COMPIN
-+
SIGIN
C1B
C1A
VREF
R2
R1
674314
-
+
1
15
150Ω
1.5K LOCK
DETECTOR
OUTPUT
LOCK
DETECTOR
CAPACITOR
CLD
LOCK DETECTOR
CD74HC7046A, CD74HCT7046A
3
General Description
VCO
The VCO requires one external capacitor C1 (between C1A
and C1B) and one external resistor R1 (between R1 and
Gnd) or two external resistors R1 and R2 (between R1 and
Gnd, and R2 and Gnd). Resistor R1 and capacitor C1 deter-
mine the frequency range of the VCO. Resistor R2 enables
the VCO to have a frequency offset if required. See logic dia-
gram, Figure 1.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is pro-
vided at pin 10 (DEMOUT). In contrast to conventional tech-
niques where the DEMOUT voltage is one threshold voltage
lower than the VCO input voltage, here the DEMOUT voltage
equals that of the VCO input. If DEMOUT is used, a load
resistor (RS) should be connected from DEMOUT to Gnd; if
unused, DEMOUT should be left open. The VCO output
(VCOOUT) can be connected directly to the comparator
input (COMPIN), or connected via a frequency-divider. The
VCO output signal has a specified duty factor of 50%. A
LOW level at the inhibit input (INH) enables the VCO, while a
HIGH level disables the VCO to minimize standby power
consumption.
Phase Comparators
The signal input (SIGIN) can be directly coupled to the self-
biasing amplifier at pin 14, provided that the signal swing is
between the standard HC family input logic levels, Capaci-
tive coupling is required for signals with smaller swings.
Phase Comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator
input frequencies (fi) must have a 50% duty factor to obtain
the maximum locking range. The transfer characteristic of
PC1, assuming ripple (fr = 2fi) is suppressed, is:
VDEMOUT =(V
CC/π)(φSIGIN -φCOMPIN) where VDEMOUT
is the demodulator output at pin 10; VDEMOUT =V
PC1OUT
(via low-pass filter).
The average output voltage from PC1, fed to the VCO input
via the low-pass filter and seen at the demodulator output at
pin 10 (VDEMOUT), is the resultant of the phase differences
of signals (SIGIN) and the comparator input (COMPIN)as
shown in Figure 2. The average of VDEM is equal to 1/2 VCC
when there is no signal or noise at SIGIN, and with this input
the VCO oscillates at the center frequency (fo). Typical wave-
forms for the PC1 loop locked at fo shown in Figure 3.
The frequency capture range (2fc) is defined as the fre-
quency range of input signals on which the PLL will lock if it
was initially out-of-lock. The frequency lock range (2fL)is
defined as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass filter
characteristics and can be made as large as the lock range.
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
Phase Comparator 2 (PC2)
This is a positive edge-triggered phase and frequency detec-
tor. When the PLL is using this comparator, the loop is con-
trolled by positive signal transitions and the duty factors of
SIGIN and COMPIN are not important. PC2 comprises two
D-type flip-flops, control-gating and a three-state output
stage. The circuit functions as an up-down counter (Figure
1) where SIGIN causes an up-count and COMPIN a down-
count. The transfer function of PC2, assuming ripple (fr=f
i)
is suppressed, is:
VDEMOUT =(V
CC/4π)(φSIGN -φCOMPIN) where VDEMOUT
is the demodulator output at pin 10; VDEMOUT =V
PC2OUT
(via low-pass filter).
The average output voltage from PC2, fed to the VCO via the
low-pass filter and seen at the demodulator output at pin 10
(VDEMOUT), is the resultant of the phase differences of
SIGIN and COMPIN as shown in Figure 4. Typical waveforms
for the PC2 loop locked at fo are shown in Figure 5.
When the frequencies of SIGIN and COMPIN are equal but
the phase of SIGIN leads that of COMPIN, the p-type output
driver at PC2OUT is held “ON” for a time corresponding to
the phase differences (φDEMOUT). When the phase of SIGIN
lags that of COMPIN, the n-type driver is held “ON”.
When the frequency of SIGIN is higher than that of COMPIN,
the p-type output driver is held “ON” for most of the input sig-
nal cycle time, and for the remainder of the cycle both n-type
and p-type drivers are “OFF” (three-state). If the SIGIN fre-
Pin Descriptions
PIN NO. SYMBOL NAME AND FUNCTION
1 LD Lock Detector Output (Active High)
2 PC1OUT Phase Comparator 1 Output
3 COMPIN Comparator Input
4 VCOOUT VCO Output
5 INH Inhibit Input
6C1
ACapacitor C1 Connection A
7C1
BCapacitor C1 Connection B
8 Gnd Ground (0V)
9 VCOIN VCO Input
10 DEMOUT Demodulator Output
11 R1Resistor R1 Connection
12 R2Resistor R2 Connection
13 PC2OUT Phase Comparator 2 Output
14 SIGIN Signal Input
15 CLD Lock Detector Capacitor Input
16 VCC Positive Supply Voltage
CD74HC7046A, CD74HCT7046A
4
quency is lower than the COMPIN frequency, then it is the n-
type driver that is held “ON” for most of the cycle. Subse-
quently, the voltage at the capacitor (C2) of the low-pass filter
connected to PC2OUT varies until the signal and comparator
inputs are equal in both phase and frequency. At this stable
point the voltage on C2 remains constant as the PC2 output is
in three-state and the VCO input at pin 9 is a high impedance.
Thus, for PC2, no phase difference exists between SIGIN
and COMPIN over the full frequency range of the VCO.
Moreover, the power dissipation due to the low-pass filter is
reduced because both p-type and n-type drivers are “OFF”
for most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range and is independent of the low-pass filter.
With no signal present at SIGIN, the VCO adjusts, via PC2,
to its lowest frequency.
Lock Detector Theory of Operation
Detection of a locked condition is accomplished by a NOR
gate and an envelope detector as shown in Figure 6. When
the PLL is in Lock, the output of the NOR gate is High and
the lock detector output (Pin 1) is at a constant high level. As
the loop tracks the signal on Pin 14 (signal in), the NOR gate
outputs pulses whose widths represent the phase differ-
ences between the VCO and the input signal. The time
between pulses will be approximately equal to the time con-
stant of the VCO center frequency. During the rise time of
the pulse, the diode across the 1.5kΩresistor is forward
biased and the time constant in the path that charges the
lock detector capacitor is T = (150Ω x CLD).
During the fall time of the pulse the capacitor discharges
through the 1.5kΩand the 150Ωresistors and the channel
resistance of the n-device of the NOR gate to ground
(T = (1.5kΩ + 150Ω + Rn-channel) x CLD).
The waveform preset at the capacitor resembles a sawtooth
as shown in Figure 7. The lock detector capacitor value is
determined by the VCO center frequency. The typical range
of capacitor for a frequency of 10MHz is about 10pF and for
a frequency of 100kHz is about 1000pF. The chart in Figure
8 can be used to select the proper lock detector capacitor
value. As long as the loop remains locked and tracking, the
level of the sawtooth will not go below the switching thresh-
old of the Schmitt-trigger inverter. If the loop breaks lock, the
width of the error pulse will be wide enough to allow the saw-
tooth waveform to go below threshold and a level change at
the output of the Schmitt trigger will indicate a loss of lock,
as shown in Figure 9. The lock detector capacitor also acts
to filter out small glitches that can occur when the loop is
either seeking or losing lock.
Note: When using phase comparator 1, the detector will only
indicate a lock condition on the fundamental frequency and
not on the harmonics, which PC1 will also lock on. If a detec-
tion of lock is needed over the harmonic locking range of
PC1, then the lock detector output must be OR-ed with the
output of PC1.
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
VDEMOUT = VPC1OUT = (VCC/π) (φSIGIN - φCOM-
PIN); φDEMOUT = (φSIGIN - φCOMPIN)
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 1, LOOP LOCKED AT fo
VCC
VDEMOUT (AV)
1/2 VCC
0
0o90oφDEMOUT 180o
SIGIN
COMPIN
VCOOUT
PC1OUT
VCOIN
VCC
GND
CD74HC7046A, CD74HCT7046A
5
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
VDEMOUT = VPC2OUT = (VCC/π) (φSIGIN - φCOM-
PIN); φDEMOUT = (φSIGIN - φCOMPIN)
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 2, LOOP LOCKED AT fo
FIGURE 6. CD74HC/HCT7046A LOCK DETECTOR CIRCUIT
FIGURE 7. WAVEFORM PRESENT AT LOCK DETECTOR CAPACITOR WHEN IN LOCK
VCC
VDEMOUT (AV)
1/2 VCC
0
-360o0oφDEMOUT 360o
SIGIN
COMPIN
VCOOUT
PC2OUT
VCOIN
VCC
GND
PCPOUT
HIGH IMPEDANCE OFF - STATE
UP
FF
DN
FF
COMPIN
SIGIN
PHASE DIFFERENCE
7046 LOCK DETECTOR CIRCUITRY
1.5kΩ150ΩPIN 1
LOCK DETECTOR
OUTPUT
PIN 15 CLD
LOCK DETECTOR
CAPACITOR
VCAP VTH
LOCK
DETECTOR
OUTPUT
PIN 1
CLD
PIN 15
LOCK
DETECTOR
CAPACITOR
1.5kΩ150Ω
CD74HC7046A, CD74HCT7046A
6
FIGURE 8. LOCK DETECTOR CAPACITOR SELECTION CHART
FIGURE 9. WAVEFORM PRESENT AT LOCK DETECTOR CAPACITOR WHEN UNLOCKED
10M
1M
100K
10K
1K
100
10
10 100 1K 10K 100K 1M 10M 100M
f, VCO CENTER FREQUENCY (HZ)
LOCK DETECTOR CAPACITOR VALUE (pF)
VCAP VTH
LOCK
DETECTOR
OUTPUT
PIN 1
CLD
PIN 15
LOCK
DETECTOR
CAPACITOR
1.5kΩ150Ω
LOSS OF LOCK
CD74HC7046A, CD74HCT7046A
7
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1) θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
VCO SECTION
INH High Level Input
Voltage VIH - - 3 2.1 - - 2.1 - 2.1 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
INH Low Level Input
Voltage VIL - - 3 - - 0.9 - 0.9 - 0.9 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VCOOUT High Level
Output Voltage
CMOS Loads
VOH VIH or VIL -0.02 3 2.9 - - 2.9 - 2.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
VCOOUT High Level
Output Voltage
TTL Loads
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VCOOUT Low Level
Output Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
VCOOUT Low Level
Output Voltage
TTL Loads
- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
C1A, C1B Low Level
Output Voltage
(Test Purposes Only)
VOL VIL or
VOL 4 4.5 - - 0.40 - 0.47 - 0.54 V
5.2 6 - - 0.40 - 0.47 - 0.54 V
CD74HC7046A, CD74HCT7046A
8
INH VCOIN Input
Leakage Current IIVCC or
GND -6--±0.1 - ±1-±1µA
R1 Range (Note 2) - - - 4.5 3 - - - - - - kΩ
R2 Range (Note 2) - - - 4.5 3 - - - - - - kΩ
C1 Capacitance
Range ---3--No
Limit ----pF
4.5 40 - - - - - pF
6-- ----pF
VCOIN Operating
Voltage Range - Over the range
specified for R1 for
LinearitySeeFigure
8, and 35 - 38
(Note 3)
3 1.1 - 1.9 - - - - V
4.5 1.1 - 3.2 - - - - V
6 1.1 - 4.6 - - - - V
PHASE COMPARATOR SECTION
SIGIN, COMPIN
DC Coupled
High-Level Input
Voltage
VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
SIGIN, COMPIN
DC Coupled
Low-Level Input
Voltage
VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
LD, PCnOUT High-
Level Output Voltage
CMOS Loads
VOH VIL or VIH -0.02 2 1.9 - - 1.9 - 1.9 - V
4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V
LD, PCnOUT High-
Level Output Voltage
TTL Loads
VOH VIL or VIH -4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
LD, PCnOUT Low-
Level Output Voltage
CMOS Loads
VOL VIL or VIH 0.02 2 - - 0.1 - 0.1 - 0.1 V
4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V
LD, PCnOUT Low-
Level Output Voltage
TTL Loads
VOL VIL or VIH 4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
SIGIN, COMPIN Input
Leakage Current IIVCC or
GND -2--±3-±4-±5µA
3--±7-±9-±11 µA
4.5 - - ±18 - ±23 - ±29 µA
6--±30 - ±38 - ±45 µA
PC2OUT Three-State
Off-State Current IOZ VIL or VIH -6--±0.5 - ±5-±10 µA
SIGIN, COMPIN Input
Resistance RIVI at Self-Bias
Operation Point:
∆VI = 0.5V,
See Figure 8
3 - 800 - - - - - kΩ
4.5 - 250 - - - - - kΩ
6 - 150 - - - - - kΩ
DEMODULATOR SECTION
Resistor Range RSat RS > 300kΩ
Leakage Current
Can Influence
VDEMOUT
3 10 - 300 - - - - kΩ
4.5 10 - 300 - - - - kΩ
6 10 - 300 - - - - kΩ
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
CD74HC7046A, CD74HCT7046A
9
OffsetVoltageVCOIN
to VDEM VOFF VI = VVCOIN =
Values taken over
RS Range
See Figure 15
3-±30 - - - - - mV
4.5 - ±20 - - - - - mV
6-±10 - - - - - mV
Dynamic Output
Resistance at
DEMOUT
ROVDEMOUT =3-25-----Ω
4.5 - 25 - - - - - Ω
6 - 25 - - - - - Ω
Quiescent Device
Current ICC Pins 3, 5 and 14
at VCC Pin 9 at
GND, II at Pins 3
and 14 to be
excluded
6 - - 8 - 80 - 160 µA
HCT TYPES
VCO SECTION
INH High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
INH Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
VCOOUT High Level
Output Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
VCOOUT High Level
Output Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
VCOOUT Low Level
Output Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
VCOOUT Low Level
Output Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
C1A, C1B Low Level
Output Voltage
(Test Purposes Only)
VOL VIH or VIL 4 4.5 - - 0.40 - 0.47 - 0.54 V
INH VCOIN Input
Leakage Current IIAny Voltage
Between VCC and
GND
5.5 - ±0.1 - ±1-±1µA
R1 Range (Note 2) - - - 4.5 3 - - - - - - kΩ
R2 Range (Note 2) - - - 4.5 3 - - - - - - kΩ
C1 Capacitance
Range - - - 4.5 40 - No
Limit ----pF
VCOIN Operating
Voltage Range - Over the range
specified for R1 for
LinearitySeeFigure
8, and 35 - 38
(Note 3)
4.5 1.1 - 3.2 - - - - V
PHASE COMPARATOR SECTION
SIGIN, COMPIN
DC Coupled
High-Level Input
Voltage
VIH - - 4.5 to
5.5 3.15 - - 3.15 - 3.15 - V
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
V
C
C
2
V
C
C
2
CD74HC7046A, CD74HCT7046A
10
SIGIN, COMPIN
DC Coupled
Low-Level Input
Voltage
VIL - - 4.5 to
5.5 - - 1.35 - 1.35 - 1.35 V
LD, PCnOUT High-
Level Output Voltage
CMOS Loads
VOH VIL or VIH - 4.5 4.4 - - 4.4 - 4.4 - V
LD, PCnOUT High-
Level Output Voltage
TTL Loads
VOH VIL or VIH - 4.5 3.98 - - 3.84 - 3.7 - V
LD, PCnOUT Low-
Level Output Voltage
CMOS Loads
VOL VIL or VIH - 4.5 - - 0.1 - 0.1 - 0.1 V
LD, PCnOUT Low-
Level Output Voltage
TTL Loads
VOL VIL or VIH - 4.5 - - 0.26 - 0.33 - 0.4 V
SIGIN, COMPIN Input
Leakage Current IIAny
Voltage
Between
VCC and
GND
- 5.5 - - ±30 ±38 ±45 µA
PC2OUT Three-State
Off-State Current IOZ VIL or VIH - 5.5 - - ±0.5 ±5- -±10 µA
SIGIN, COMPIN Input
Resistance RIVI at Self-Bias
Operation Point:
∆V, 0.5V,
See Figure 8
4.5 - 250 - - - - - kΩ
DEMODULATOR SECTION
Resistor Range RSat RS > 300kΩ
Leakage Current
Can Influence
VDEMOUT
4.5 10 - 300 - - - - kΩ
OffsetVoltageVCOIN
to VDEM VOFF VI = VVCOIN =
Values taken over
RS Range
See Figure 15
4.5 - ±20 - - - - - mV
Dynamic Output
Resistance at
DEMOUT
ROVDEMOUT = 4.5 - 25 - - - - - Ω
Quiescent Device
Current ICC VCC or
GND - 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 4) VCC
-2.1
(Exclud-
ing Pin 5)
- 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTES:
2. ThevalueforR1and R2inparallelshouldexceed 2.7kΩ;R1andR2values above300kΩmaycontributetofrequency shiftduetoleakage
currents.
3. The maximum operating voltage can be as high as VCC -0.9V, however, this may result in an increased offset voltage.
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
V
C
C
2
V
C
C
2
CD74HC7046A, CD74HCT7046A
11
HCT Input Loading Table
INPUT UNIT LOADS
INH 1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Switching Specifications CL = 50pF, Input tr, tf= 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
PHASE COMPARATOR SECTION
Propagation Delay tPLH, tPHL
SIGIN, COMPIN to PC1OUT 2 - - 200 - 250 - 300 ns
4.5 - - 40 - 50 - 60 ns
6 - - 34 - 43 - 51 ns
Output Transition Time tTHL, tTLH 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Output Enable Time, SIGIN,
COMPIN to PC2OUT tPZH, tPZL 2 - - 280 - 350 - 420 ns
4.5 - - 56 - 70 - 84 ns
6 - - 48 - 60 - 71 ns
Output Disable Time, SIGIN,
COMPIN to PC2OUT tPHZ, tPLZ 2 - - 325 - 405 - 490 ns
4.5 - - 65 - 81 - 98 ns
6 - - 55 - 69 - 83 ns
AC Coupled Input Sensitivity (P-
P) at SIGIN or COMPIN VI(P-P) 3 - 11 - - - - - mV
4.5 - 15 - - - - - mV
6 - 33 - - - - - mV
VCO SECTION
Frequency Stability with
Temperature Change ∆f
∆TR1 = 100kΩ,
R2 = ∞3 - - - Typ 0.11 - - %/oC
4.5 - - - - - %/oC
6--- --%/
oC
Maximum Frequency fMAX C1 = 50pF
R1 = 3.5kΩ
R2 = ∞
3 - - - - - - - MHz
4.5 - 24 - - - - - MHz
6 - - - - - - - MHz
C1 = 0pF
R1 = 9.1kΩ
R2 = ∞
3 - - - - - - - MHz
4.5 - 38 - - - - - MHz
6 - - - - - - - MHz
Center Frequency foC1 = 40pF
R1 = 3kΩ
R2 = ∞
VCOIN =V
CC/2
3 7 10 - - - - - MHz
4.5 12 17 - - - - - MHz
6 14 21 - - - - - MHz
Frequency Linearity ∆fVCO R1 = 100kΩ
R2 = ∞
C1 = 100pF
3-------%
4.5 - 0.4 - - - - - %
6-------%
CD74HC7046A, CD74HCT7046A
12
Offset Frequency R2 = 220kΩ
C1 = 1nF 3 - - - - - - - kHz
4.5 - 400 - - - - - kHz
6 - - - - - - - kHz
DEMODULATOR SECTION
VOUT vs fIN R1 = 100kΩ
R2 = ∞
C1 = 100pF
R5 = 10kΩ
R3 = 100kΩ
C2 = 100pF
3 - - - - - - - mV/kHz
4.5 - 330 - - - - - mV/kHz
6 - - - - - - - mV/kHz
HCT TYPES
PHASE COMPARATOR SECTION
Propagation Delay tPLH, tPHL
SIGIN, COMPIN to PC1OUT 4.5 - - 45 - 56 - 68 ns
Output Transition Time tTHL, tTLH 4.5 - - 15 - 19 - 22 ns
Output Enable Time, SIGIN,
COMPIN to PC2OUT tPZH, tPZL 4.5 - - 60 - 75 - 90 ns
Output Disable Time, SIGIN,
COMPIN to PCZOUT tPHZ, tPLZ 4.5 - - 70 - 86 - 105 ns
AC Coupled Input Sensitivity
(P-P) at SIGIN or COMPIN VI(P-P) 3 - 11 - - - - - mV
4.5 - 15 - - - - - mV
6 - 33 - - - - - mV
VCO SECTION
Frequency Stability with
Temperature Change ∆f
∆TR1 = 100kΩ,
R2 = ∞4.5 - - - Typ 0.11 - - %/oC
Maximum Frequency fMAX C1 = 50pF
R1 = 3.5kΩ
R2 = ∞
4.5 - 24 - - - - - MHz
C1 = 0pF
R1 = 9.1kΩ
R2 = ∞
4.5 - 38 - - - - - MHz
Center Frequency foC1 = 40pF
R1 = 3kΩ
R2 = ∞
VCOIN =V
CC/2
4.5 12 17 - - - - - MHz
Frequency Linearity ∆fVCO R1 = 100kΩ
R2 = ∞
C1 = 100pF
4.5 - 0.4 - - - - - %
Offset Frequency R2 = 220kΩ
C1 = 1nF 4.5 - 400 - - - - - kHz
DEMODULATOR SECTION
VOUT vs fIN R1 = 100kΩ
R2 = ∞
C1 = 100pF
R5 = 10kΩ
R3 = 100kΩ
C2 = 100pF
4.5 - 330 - - - - - mV/kHz
Switching Specifications CL = 50pF, Input tr, tf= 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD74HC7046A, CD74HCT7046A
13
Test Circuits and Waveforms
FIGURE 10. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC FIGURE 11. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
Typical Performance Curves
FIGURE 12. TYPICAL INPUT RESISTANCE CURVE AT
SIGIN, COMPIN
FIGURE 13. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1
FIGURE 14. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1 FIGURE 15. HC7046A TYPICAL CENTER FREQUENCY vs R1, C1
II
VI
∆VI
SELF-BIAS OPERATING POINT
108
107
106
105
104
103
102
10
1110102103104105106
CAPACITANCE, C1 (pF)
CENTER FREQUENCY (Hz)
VCOIN = 0.5 VCC
VCC = 4.5V
R1 = 2.2K
R1 = 22K
R1 = 220K
R1 = 2.2M
R1 = 11M
R2 = ∞
108
107
106
105
104
103
102
10
1110102103104105106
CAPACITANCE, C1 (pF)
CENTER FREQUENCY (Hz)
VCOIN = 0.5 VCC
VCC = 6.0V
R1 = 3K
R1 = 30K
R1 = 330K
R1 = 3M
R1 = 15M
R2 = ∞
108
107
106
105
104
103
102
10
1110102103104105106
CAPACITANCE, C1 (pF)
CENTER FREQUENCY (Hz)
VCOIN = 0.5 VCC
VCC = 3.0V
R2 = ∞
R1 = 1.5K
R1 = 15K
R1 = 150K
R1 = 1.5M
R1 = 7.5M
CD74HC7046A, CD74HCT7046A
14
FIGURE 16. HCT7046A TYPICAL CENTER FREQUENCY vs R1, C1 FIGURE 17. HCT7046A TYPICALCENTER FREQUENCYvs R1,C1
FIGURE 18. HC7046A TYPICAL VCO FREQUENCY vs VCOIN FIGURE 19. HC7046A TYPICAL VCO FREQUENCY vs VCOIN
(R1 = 1.5MΩ, C1 = 0.1µF)
FIGURE 20. HC7046A TYPICAL VCO FREQUENCY vs VCOIN
(R1 = 150kΩ, C1 = 0.1µF) FIGURE 21. HC7046A TYPICAL VCO FREQUENCY vs VCOIN
(R1 = 5.6kΩ, C1 = 0.1µF)
Typical Performance Curves (Continued)
108
107
106
105
104
103
102
10
1110102103104105106
CAPACITANCE, C1 (pF)
CENTER FREQUENCY (Hz)
VCOIN = 0.5 VCC
VCC = 4.5V
R1 = 2.2K
R1 = 22K
R1 = 220K
R1 = 2.2M
R1 = 11M
R2 = ∞
108
107
106
105
104
103
102
10
1110102103104105106
CAPACITANCE, C1 (pF)
CENTER FREQUENCY (Hz)
VCOIN = 0.5 VCC
VCC = 5.5V
R1 = 3K
R1 = 30K
R1 = 300K
R1 = 3M
R1 = 15M
R2 = ∞
140
120
100
80
60
40
20 01 2 3 456
VCOIN (V)
VCO FREQUENCY (kHz)
C1 = 50pF
R1 = 1.5M
VCC = 3V
VCC = 4.5V
VCC = 6V
R2 = ∞
90
70
60
50
40
30
20
10 01 2 3 45 6
VCOIN (V)
VCO FREQUENCY (Hz)
C1 = 0.1µF
R1 = 1.5M
VCC = 3V
VCC = 4.5V
VCC = 6V
80 R2 = ∞
C1 = 0.1µF
R1 = 150K
R2 = ∞
800
600
500
400
300
200
100 01 2 3 4 5 6
VCOIN (V)
VCO FREQUENCY (Hz)
VCC = 3V
VCC = 4.5V
VCC = 6V
700
18
14
12
10
8
6
4
201 2 3 4 5 6
VCOIN (V)
VCO FREQUENCY (kHz)
C1 = 0.1µF
R1 = 5.6k
VCC = 3V
VCC = 4.5V
VCC = 6V
16 R2 = ∞
CD74HC7046A, CD74HCT7046A
15
FIGURE 22. HC7046A TYPICAL VCO FREQUENCY vs VCOIN
(R1 = 150kΩ, C1 = 0.1µF) FIGURE 23. HC7046A TYPICAL VCO FREQUENCY vs VCOIN
(R1 = 5.6kΩ, C1 = 50pF)
FIGURE 24. HC7046A TYPICAL CHANGE IN VCO FREQUENCY
vs AMBIENT TEMPERATURE AS A FUNCTION OF
R1 (VCC = 3V)
FIGURE25. HC7046A TYPICALCHANGE INVCOFREQUENCY vs
AMBIENT TEMPERATURE AS A FUNCTION OF R1
Typical Performance Curves (Continued)
1400
1000
800
600
400
200 01 2 3 4 5 6
VCOIN (V)
VCO FREQUENCY (kHz)
VCC = 3V
VCC = 4.5V
VCC = 6V
1200 C1 = 50pF
R1 = 150K
R2 = ∞20
16
12
8
401 2 3 45 6
VCOIN (V)
VCO FREQUENCY (MHz)
C1 = 50pF
R1 = 5.6K
VCC = 3V
VCC = 4.5V
VCC = 6V
24
R2 = ∞
R1 = 1.5M
R1 = 150K
R1 = 3K
VCOIN = 0.5 VCC
C1 = 50pF, VCC = 3V
R2 = ∞
24
16
12
8
4
0
-4
VCO FREQUENCY CHANGE, ∆f (%)
20
-75 -50 -25 0 25 50 75
AMBIENT TEMPERATURE, TA (oC)
100 125 150
-8
-12
-16
R1 = 2.2M
R1 = 220K
R1 = 2.2K
VCOIN = 0.5 VCC
C1 = 50pF, VCC = 4.5V
R2 = ∞
16
12
8
4
0
VCO FREQUENCY CHANGE, ∆f (%)
20
-75 -50 -25 0 25 50 75
AMBIENT TEMPERATURE, TA (oC)
100 125 150
-4
-8
-12
CD74HC7046A, CD74HCT7046A
16
FIGURE26. HC7046A TYPICALCHANGE INVCOFREQUENCY vs
AMBIENT TEMPERATURE AS A FUNCTION OF R1 FIGURE 27. HCT7046A TYPICAL CHANGE IN VCO
FREQUENCY vs AMBIENT TEMPERATURE AS A
FUNCTION OF R1
FIGURE28. HC7046A TYPICALCHANGE INVCOFREQUENCY vs
AMBIENT TEMPERATURE AS A FUNCTION OF R1 FIGURE 29. HC7046A OFFSET FREQUENCY vs R2, C1
FIGURE 30. HC7046A OFFSET FREQUENCY vs R2, C1 FIGURE 31. HCT7046A OFFSET FREQUENCY vs R2, C1
Typical Performance Curves (Continued)
R1 = 3M
R1 = 300K
R1 = 3K
VCOIN = 0.5 VCC
C1 = 50pF, VCC = 6.0V
R2 = ∞
16
12
8
4
0
VCO FREQUENCY CHANGE, ∆f (%)
-75 -50 -25 0 25 50 75
AMBIENT TEMPERATURE, TA (oC)
100 125 150
-4
-8
-12
R1 = 3M
R1 = 300K
R1 = 3K
VCOIN = 0.5 VCC
C1 = 50pF, VCC = 5.5V
R2 = ∞
16
12
8
4
0
VCO FREQUENCY CHANGE, ∆f (%)
20
-75 -50 -25 0 25 50 75
AMBIENT TEMPERATURE, TA (oC)
100 125 150
-4
-8
-12
R1 = 2.2M
R1 = 220K
R1 = 2.2K
VCOIN = 0.5 VCC
C1 = 50pF, VCC = 4.5V
R2 = ∞
16
12
8
4
0
VCO FREQUENCY CHANGE, ∆f (%)
20
-75 -50 -25 0 25 50 75
AMBIENT TEMPERATURE, TA (oC)
100 125 150
-4
-8
-12
R2 = 2.2K
R2 = 22K
R2 = 220K
VCOIN = 0.5 VCC
VCC = 4.5V
110
102103104105106
CAPACITANCE, C1 (pF)
108
107
106
105
104
103
102
10
1
OFFSET FREQUENCY (Hz)
R2 = 2.2M
R2 = 11M
VCOIN = GND
VCC = 3V
110
102103104105106
CAPACITANCE, C1 (pF)
108
107
106
105
104
103
102
10
1
OFFSET FREQUENCY (Hz)
R2 = 1.5K
R2 = 15K
R2 = 150K
R2 = 1.5M
R2 = 7.5M VCOIN = GND
VCC = 4.5V
110
102103104105106
CAPACITANCE, C1 (pF)
108
107
106
105
104
103
102
10
1
OFFSET FREQUENCY (Hz)
R2 = 2.2K
R2 = 22K
R2 = 220K
R2 = 2.2M
R2 = 11M
CD74HC7046A, CD74HCT7046A
17
FIGURE 32. HC7046A AND HCT7046A OFFSET FREQUENCY
vs R2, C1 FIGURE 33. HC7046A fMIN/fMAX vs R2/R1
FIGURE 34. HCT7046A fMAX/fMIN vs R2/R1 FIGURE 35. DEFINITION OF VCO FREQUENCY LINEARITY
FIGURE 36. HC7046A VCO LINEARITY vs R1 FIGURE 37. HC7046A VCO LINEARITY vs R1
Typical Performance Curves (Continued)
110
102103104105106
CAPACITANCE, C1 (pF)
108
107
106
105
104
103
102
10
1
OFFSET FREQUENCY (Hz)
R2 = 3K
R2 = 30K
R2 = 300K
R2 = 3M
R2 = 15M
VCOIN = GND
HC - VCC = 6V
HCT - VCC = 5.5V
VCOIN = VCC - 0.9V FOR fMAX
VCOIN = 0V FOR fMIN
VCC = 3V, 4.5V, 6V
102
10
fMAX/fMIN
110-2 10-1 1
R2/R1 102
10
VCOIN = VCC - 0.9V FOR fMAX
VCOIN = 0V FOR fMIN
VCC = 4.5V TO 5.5V
102
10
fMAX/fMIN
110-2 10-1 1
R2/R1 102
10
f
f2
f0
f0’
f1
∆V
1/2VCC VVCOIN
MIN MAX
∆V
∆V = 0.5V OVER THE VCC RANGE
:
FOR VCO LINEARITY
f’o = f1 + f2
2
LINEARITY = f’o - fo
f’ox 100%
1K 10K 100K 1M 10M
R1 (OHMS)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY (%)
VCOIN = 2.25V ±1V
C1 = 50pF
VCC = 4.5V
R2 = ∞
VCOIN = 2.25V ±0.45V
1K 10K 100K 1M 10M
R1 (OHMS)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY (%)
VCOIN = 1.50V ±0.4V
C1 = 50pF
VCC = 3V
R2 = ∞
VCOIN = 1.50V ±0.3V
CD74HC7046A, CD74HCT7046A
18
FIGURE 38. HC7046A VCO LINEARITY vs R1 FIGURE 39. HCT7046A VCO LINEARITY vs R1
FIGURE 40. HC7046A DEMODULATOR POWER DISSIPATION
vs RS (TYP) FIGURE 41. HCT7046A DEMODULATOR POWER DISSIPATION
vs RS (TYP) (VCC = 3V, 4.5V, 6V)
FIGURE 42. HC7046A VCO POWER DISSIPATION vs R1
(C1 = 50pF, 1µF) FIGURE 43. HCT7046A VCO POWER DISSIPATION vs R2
(C1 = 50pF, 1µF)
Typical Performance Curves (Continued)
1K 10K 100K 1M 10M
R1 (OHMS)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY (%)
VCOIN = 3V ±1.5V
C1 = 50pF
VCC = 6V
R2 = ∞
VCOIN = 3V ±0.6V
1K 10K 100K 1M 10M
R1 (OHMS)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY (%)
VCC = 5.5V,
C1 = 50pF
R2 = OPEN
VCC = 4.5V,
VCOIN = 2.75V ±1.3V
VCOIN = 2.25V ±1.0V
VCC = 5.5V,
VCC = 4.5V,
VCOIN = 2.75V ±0.55V
VCOIN = 2.25V ±0.45V
VCOIN = 0.5 VCC
1K 10K 100K 1M
RS (OHMS)
104
103
102
10
1
VCC = 3V VCC = 4.5V
VCC = 6V
DEMODULATOR POWER DISSIPATION, PD (µW)
VCOIN = 0.5 VCC
1K 10K 100K 1M
RS (OHMS)
104
103
102
10
1
VCC = 3V VCC = 4.5V
VCC = 6V
R1 = R2 = OPEN
DEMODULATOR POWER DISSIPATION, PD (µW)
VCOIN = 0.5VCC
1K 10K 100K 1M
R1 (OHMS)
106
105
104
103
102
R2 = RS = OPEN
CL = 50pF VCC = 6V
C1 = 50pF
VCC = 3V
C1 = 1µF
VCO POWER DISSIPATION, PD (µW)
VCC = 6V
C1 = 1µF
VCC = 3V
C1 = 50pF VCC = 4.5V
C1 = 1µF
VCC = 4.5V
C1 = 50pF
VCOIN = 0V (AT fMIN)
1K 10K 100K 1M
R2 (OHMS)
106
105
104
103
102
R1 = RS = ∞
CL = 50pF
VCC = 6V
C1 = 50pF
VCC = 4.5V
C1 = 1µF
VCO POWER DISSIPATION, PD (µW)
VCC = 4.5V
C1 = 50pF
VCC = 6V
C1 = 1µF
CD74HC7046A, CD74HCT7046A
19
FIGURE 44. HCT7046A VCO POWER DISSIPATION vs R1
(C1 = 50pF, 1µF) FIGURE 45. HC7046A VCO POWER DISSIPATION vs R2 (C1 =
50pF, 1µF)
Typical Performance Curves (Continued)
VCOIN = 0.5V
1K 10K 100K 1M
R1 (OHMS)
106
105
104
103
102
R2 = RS = ∞
VCC = 5.5V
C1 = 50pF
VCC = 5.5V
C1 = 1µF
VCO POWER DISSIPATION, PD (µW)
VCC = 4.5V
C1 = 50pF
VCC = 4.5V
C1 = 1µF
VCOIN = 0V (AT fMIN)
1K 10K 100K 1M
R2 (OHMS)
106
105
104
103
102
R1 = RS = ∞
CL = 50pF
VCC = 6V
C1 = 50pF
VCC = 3V
C1 = 1µF
VCO POWER DISSIPATION, PD (µW)
VCC = 4.5V
C1 = 1µF
VCC = 4.5V
C1 = 50pF
VCC = 6V
C1 = 1µF
VCC = 3V
C1 = 50pF
CD74HC7046A, CD74HCT7046A
20
Application Information
This information is a guide for the approximation of values of
external components to be used with the CD74HC7046A
and CD74HCT7046A in a phase-lock-loop system.
References should be made to Figures 13 through 23 and
Figures 36 through 41 as indicated in the table.
Values of the selected components should be within the fol-
lowing ranges:
HC/HCT7046A CPD
CHIP SECTION HC HCT UNIT
Comparator 1 48 50 pF
Comparator 2 39 48 pF
VCO 61 53 pF R1 > 3kΩ;
R2 > 3kΩ;
R1 || R2 parallel value > 2.7kΩ;
C1 greater than 40pF
SUBJECT PHASE
COMPARATOR DESIGN CONSIDERATIONS
VCO Frequency
Without Extra Offset
(R2 = ∞)
PC1 or PC2 VCO Frequency Characteristic
The characteristics of the VCO operation are shown in Figures 13 - 23.
PC1 Selection of R1 and C1
Given fo, determine the values of R1 and C1 using Figures 13 - 17.
PC2 Given fMAX calculate foas fMAX/2 and determine the values of R1 and C1 using Figures 13 - 17.
To obtain 2fL: 2fL≈ where 0.9V < VCOIN < VCC - 0.9V is the range of ∆VCOIN
VCO Frequency with
Extra Offset
(R2 > 3kΩ)
PC1 or PC2 VCO Frequency Characteristic
The characteristics of the VCO operation are shown in Figures 29 - 32.
PC1 or PC2 Selection of R1, R2 and C1
Given fo and fL, offset frequency, fMIN, may be calculated from fMIN ≈ fo - 1.6 fL.
Obtain the values of C1 and R2 by using Figures 29 - 32.
Calculate the values of R1 from Figures 33 - 34.
FIGURE 46. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITHOUT
OFFSET: fo = CENTER FREQUENCY: 2fL = FREQUENCY LOCK RANGE
fMAX
fVCO
fo
fMIN MIN 1/2 VCC VVCOIN MAX
2fL
2(∆VCOIN
)
R1C1
FIGURE 47. FREQUENCY CHARACTERISTIC OF VCO OPERATING WITH OFFSET:
fo = CENTER FREQUENCY: 2fL = FREQUENCY LOCK RANGE
fMAX
fVCO
fo
fMIN
MIN 1/2 VCC VVCOIN MAX
2fL
CD74HC7046A, CD74HCT7046A
21
Lock Detector Circuit
The lock detector feature is very useful in data synchroniza-
tion, motor speed control, and demodulation. By adjusting
the value of the lock detector capacitor so that the lock out-
put will change slightly before actually losing lock, the
designer can create an “early warning” indication allowing
corrective measures to be implemented. The reverse is also
true, especially with motor speed controls, generators, and
clutches that must be set up before actual lock occurs or dis-
connected during loss of lock.
When using phase comparator 1, the detector will only indi-
cate a lock condition on the fundamental frequency and not
on the harmonics, which PC1 will lock on.
PLL Conditions with
No Signal at the
SIGIN Input
PC1 VCO adjusts to fo with φDEMOUT = 90o and VVCOIN = 1/2 VCC (see Figure 2)
PC2 VCO adjusts to fMIN with φDEMOUT = -360o and VVCOIN = 0V (see Figure 4)
PLL Frequency
Capture Range PC1 or PC2 Loop Filter Component Selection
PLL Locks on
Harmonics at Center
Frequency
PC1 Yes
PC2 No
Noise Rejection at
Signal Input PC1 High
PC2 Low
AC Ripple Content
when PLL is Locked PC1 fr = 2fi, large ripple content at φDEMOUT = 90o
PC2 fr = fi, small ripple content at φDEMOUT = 0o
SUBJECT PHASE
COMPARATOR DESIGN CONSIDERATIONS
A
small capture range (2fc) is obtained if τ > 2fc≈ (1/π) (2πfL/τ1.)1/2
FIGURE 48. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET
(A) τ1 = R3 x C2 (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM
R3
C2
INPUT OUTPUT
|F(jω)|
ω
-1/τ
FIGURE 49. SIMPLE LOOP FILTER FOR PLL WITH OFFSET
(A) τ2 = R4 x C2; (B) AMPLITUDE CHARACTERISTIC (C) POLE-ZERO DIAGRAM
|F(jω)|
ω
-1/τ2
R3
C2
INPUT OUTPUT
τ3 = (R3 + R4) x C2
-1/τ3
m
1/τ31/τ2
R4 m = R4
R3 + R4
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD74HC7046AE ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC7046AEE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC7046AM ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC7046AM96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC7046AM96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC7046AM96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC7046AME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC7046AMG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC7046AMT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC7046AMTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC7046AMTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT7046AE ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT7046AEE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT7046AM ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT7046AM96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT7046AM96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT7046AM96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT7046AME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT7046AMG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT7046AMT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT7046AMTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT7046AMTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2007
Addendum-Page 1
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC7046AM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT7046AM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC7046AM96 SOIC D 16 2500 333.2 345.9 28.6
CD74HCT7046AM96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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