GS8160E18/32/36BT-250/200/150
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
250 MHz–150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.05a 1/2011 1/23 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• FT pin for user-configurable flow through or pipeline opera-
tion
• Dual Cycle Deselect (DCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
Applications
The GS8160E18/32/36BT is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8160E18/32/36BT is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8160E18/32/36BT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -200 -150 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
4.0
3.0
5.0
3.8
6.7
ns
ns
Curr (x18)
Curr (x32/x36)
295
345
245
285
200
225
mA
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
Curr (x18)
Curr (x32/x36)
225
255
200
220
185
205
mA
mA
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
VSS
VDDQ
VDDQ
VSS
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
VSS
VDDQ
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
A
E1
E2
NC
NC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A
A
A
1M x 18
Top View
DQPA
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC 10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 2/23 © 2004, GSI Technology
GS8160E18B 100-Pin TQFP Pinout
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC
DQC
VSS
VDDQ
DQC
DQC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
VSS
VDDQ
VDDQ
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
VSS
VDDQ
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
A
E1
E2
BD
BC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A
A
A
512K x 32
Top View
DQB
NC
DQB
DQB
DQB
DQA
DQA
DQA
DQA
NC
DQC
DQC
DQC
DQD
DQD
DQD
NC
DQC
NC 10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 3/23 © 2004, GSI Technology
GS8160E32B 100-Pin TQFP Pinout
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC
DQC
VSS
VDDQ
DQC
DQC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
VSS
VDDQ
VDDQ
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
VSS
VDDQ
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
A
E1
E2
BD
BC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A
A
A
512K x 36
Top View
DQB
DQPB
DQB
DQB
DQB
DQA
DQA
DQA
DQA
DQPA
DQC
DQC
DQC
DQD
DQD
DQD
DQPD
DQC
DQPC
10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 4/23 © 2004, GSI Technology
GS8160E36B 100-Pin TQFP Pinout
Note:
Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating.
TQFP Pin Description
Symbol Type Description
A0, A1IAddress field LSBs and Address Counter preset Inputs
A I Address Inputs
DQA
DQB
DQC
DQD
I/O Data Input and Output pins
NC No Connect
BW IByte Write—Writes all enabled bytes; active low
BA, BB, BC, BDIByte Write Enable for DQA, DQB Data I/Os; active low
CK IClock Input Signal; active high
GW IGlobal Write Enable—Writes all bytes; active low
E1IChip Enable; active low
E2IChip Enable; active high
G I Output Enable; active low
ADV IBurst address counter advance enable; active low
ADSP, ADSC IAddress Strobe (Processor, Cache Controller); active low
ZZ ISleep Mode control; active high
FT IFlow Through or Pipeline mode; active low
LBO ILinear Burst Order mode; active low
VDD ICore power supply
VSS II/O and Core Ground
VDDQ IOutput driver power supply
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 5/23 © 2004, GSI Technology
A1
A0 A0
A1
D0
D1 Q1
Q0
Counter
Load
DQ
DQ
Register
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
E1
G
ZZ Power Down
Control
Memory
Array
36 36
4
A
QD
E2
E3
DQx1–DQx9
Note: Only x36 version shown for simplicity.
0
BA
BB
BC
BD
FT
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 6/23 © 2004, GSI Technology
GS8160E18/32/36B Block Diagram
Mode Pin Functions
Mode Name Pin Name State Function
Burst Order Control LBO LLinear Burst
HInterleaved Burst
Output Register Control FT LFlow Through
H or NC Pipeline
Power Down Control ZZ L or NC Active
H Standby, IDD = ISB
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 7/23 © 2004, GSI Technology
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Burst Counter Sequences
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 8/23 © 2004, GSI Technology
Byte Write Truth Table
Function GW BW BABBBCBDNotes
Read H H X X X X 1
Write No Bytes H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4
Write all bytes H L L L L L 2, 3, 4
Write all bytes L X X X X X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 9/23 © 2004, GSI Technology
Synchronous Truth Table
Operation Address
Used
State
Diagram
Key
E1E2E3ADSP ADSC ADV WDQ3
Deselect Cycle, Power Down None X L X H X L X X High-Z
Deselect Cycle, Power Down None X L L X X L X X High-Z
Deselect Cycle, Power Down None X L X H L X X X High-Z
Deselect Cycle, Power Down None X L L X L X X X High-Z
Deselect Cycle, Power Down None X H X X X L X X High-Z
Read Cycle, Begin Burst External R L H L L X X X Q
Read Cycle, Begin Burst External R L H L H L X F Q
Write Cycle, Begin Burst External W L H L H L X T D
Read Cycle, Continue Burst Next CR X X X H H L F Q
Read Cycle, Continue Burst Next CR H X X X H L F Q
Write Cycle, Continue Burst Next CW X X X H H L T D
Write Cycle, Continue Burst Next CW H X X X H L T D
Read Cycle, Suspend Burst Current X X X H H H F Q
Read Cycle, Suspend Burst Current H X X X H H F Q
Write Cycle, Suspend Burst Current X X X H H H T D
Write Cycle, Suspend Burst Current H X X X H H T D
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
First Write First Read
Burst Write Burst Read
Deselect
R
W
CRCW
X
X
WR
R
WR
XX
X
Simple Synchronous OperationSimple Burst Synchronous Operation
CR
R
CW CR
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)
control inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 10/23 © 2004, GSI Technology
Simplified State Diagram
First Write First Read
Burst Write Burst Read
Deselect
R
W
CRCW
X
X
WR
R
WR
X
X
X
CR
R
CW CR
CR
W
CW
W
CW
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 11/23 © 2004, GSI Technology
Simplified State Diagram with G
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 4.6 V
VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V
IIN Input Current on Any Pin +/–20 mA
IOUT Output Current on Any I/O Pin +/–20 mA
PDPackage Power Dissipation 1.5 W
TSTG Storage Temperature –55 to 125 oC
TBIAS Temperature Under Bias –55 to 125 oC
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 12/23 © 2004, GSI Technology
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter Symbol Min. Typ. Max. Unit
3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V
2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V
3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V
2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V
VDD3 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit
Input High Voltage VIH 2.0 —VDD + 0.3 V
Input Low Voltage VIL –0.3 —0.8 V
Note:
VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 13/23 © 2004, GSI Technology
VDD2 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit
Input High Voltage VIH 0.6*VDD —VDD + 0.3 V
Input Low Voltage VIL –0.3 —0.3*VDD V
Note:
VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Recommended Operating Temperatures
Parameter Symbol Min. Typ. Max. Unit
Ambient Temperature (Commercial Range Versions) TA025 70 °C
Ambient Temperature (Industrial Range Versions)* TA–40 25 85 °C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
20% tKC
VSS – 2.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKC
VDD + 2.0 V
50%
VDD
VIL
Note:
Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Capacitance
oC, f = 1 MHZ, VDD = 2.5 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 4 5 pF
Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF
Note:
These parameters are sample tested.
(TA = 25
AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDD/2
Output reference level VDDQ/2
Output load Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 14/23 © 2004, GSI Technology
DQ
VDDQ/2
50Ω30pF*
Output Load 1
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA
ZZ Input Current IIN1
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
100 uA
FT Input Current IIN2
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–1 uA
1 uA
1 uA
Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA
Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V —
Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V —
Output Low Voltage VOL IOL = 8 mA —0.4 V
Operating Currents
Parameter Test Conditions Mode Symbol
-250 -200 -150
Unit
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Operating
Current
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
(x32/
x36)
Pipeline IDD
IDDQ
305
40
315
40
255
30
265
30
205
20
215
20 mA
Flow Through IDD
IDDQ
235
20
245
20
205
15
215
15
190
15
200
15 mA
(x18)
Pipeline IDD
IDDQ
275
20
285
20
230
15
240
15
185
15
195
15 mA
Flow Through IDD
IDDQ
215
10
225
10
190
10
200
10
175
10
185
10 mA
Standby
Current ZZ ≥ VDD – 0.2 V —
Pipeline ISB 40 50 40 50 40 50 mA
Flow Through ISB 40 50 40 50 40 50 mA
Deselect
Current
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
—
Pipeline IDD 85 90 75 80 60 65 mA
Flow Through IDD 60 65 50 55 50 55 mA
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 15/23 © 2004, GSI Technology
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
AC Electrical Characteristics
Parameter Symbol -250 -200 -150 Unit
Min Max Min Max Min Max
Pipeline
Clock Cycle Time tKC 4.0 —5.0 —6.7 —ns
Clock to Output Valid tKQ —2.5 —3.0 —3.8 ns
Clock to Output Invalid tKQX 1.5 —1.5 —1.5 —ns
Clock to Output in Low-Z tLZ11.5 —1.5 —1.5 —ns
Setup time tS 1.2 —1.4 —1.5 —ns
Hold time tH 0.2 —0.4 —0.5 —ns
Flow Through
Clock Cycle Time tKC 5.5 —6.5 —7.5 —ns
Clock to Output Valid tKQ —5.5 —6.5 —7.5 ns
Clock to Output Invalid tKQX 2.0 —2.0 —2.0 —ns
Clock to Output in Low-Z tLZ12.0 —2.0 —2.0 —ns
Setup time tS 1.5 —1.5 —1.5 —ns
Hold time tH 0.5 —0.5 —0.5 —ns
Clock HIGH Time tKH 1.3 —1.3 —1.5 —ns
Clock LOW Time tKL 1.5 —1.5 —1.7 —ns
Clock to Output in
High-Z tHZ11.5 2.5 1.5 3.0 1.5 3.0 ns
G to Output Valid tOE —2.5 —3.0 —3.8 ns
G to output in Low-Z tOLZ10—0—0—ns
G to output in High-Z tOHZ1—2.5 —3.0 —3.8 ns
ZZ setup time tZZS25—5—5—ns
ZZ hold time tZZH21—1—1—ns
ZZ recovery tZZR 20 —20 —20 —ns
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 16/23 © 2004, GSI Technology
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 17/23 © 2004, GSI Technology
Pipeline Mode Timing (DCD)
Begin Read A Cont Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect Deselect
tHZ
tKQX
tKQ
tLZtH
tS
tOHZtOE
tH
tS
tH
tS
tH
tS
tH
tS
tHtS
tS
tH
tS
tHtS
tH
tS
tKCtKC
tKLtKL
tKHtKH
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)
ABC
Hi-Z
Deselected with E1
E2 and E3 only sampled with ADSC
ADSC initiated read
CK
ADSP
ADSC
ADV
Ao–An
GW
BW
Ba–Bd
E1
E2
E3
G
DQa–DQd
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 18/23 © 2004, GSI Technology
Flow Through Mode Timing (DCD)
Begin Read A Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C Deselect
tHZ
tKQX
tLZ
tH
tS
tOHZ
tOE
tKQ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tHtS
tH
tS
tH
tS
tH
tS
tKCtKC
tKLtKL
tKHtKH
ABC
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
E2 and E3 only sampled with ADSP and ADSC
E1 masks ADSP
ADSC initiated read
Deselected with E1
E1 masks ADSP
Fixed High
CK
ADSP
ADSC
ADV
Ao–An
GW
BW
Ba–Bd
E1
E2
E3
G
DQa–DQd
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 19/23 © 2004, GSI Technology
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs (like this one) do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 20/23 © 2004, GSI Technology
TQFP Package Drawing (Package T)
D1
D
E1
E
Pin 1
b
e
c
L
L1
A2
A1
Y
θ
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
b Lead Width 0.20 0.30 0.40
c Lead Thickness 0.09 —0.20
D Terminal Dimension 21.9 22.0 22.1
D1 Package Body 19.9 20.0 20.1
E Terminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
e Lead Pitch —0.65 —
L Foot Length 0.45 0.60 0.75
L1 Lead Length —1.00 —
Y Coplanarity 0.10
θLead Angle 0°—7°
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 21/23 © 2004, GSI Technology
Ordering Information for GSI Synchronous Burst RAMs
Org Part Number1Type Package Speed2
(MHz/ns) TA3
1M x 18 GS8160E18BT-250 DCD Pipeline/Flow Through TQFP 250/5.5 C
1M x 18 GS8160E18BT-200 DCD Pipeline/Flow Through TQFP 200/6.5 C
1M x 18 GS8160E18BT-150 DCD Pipeline/Flow Through TQFP 150/7.5 C
512K x 32 GS8160E32BT-250 DCD Pipeline/Flow Through TQFP 250/5.5 C
512K x 32 GS8160E32BT-200 DCD Pipeline/Flow Through TQFP 200/6.5 C
512K x 32 GS8160E32BT-150 DCD Pipeline/Flow Through TQFP 150/7.5 C
512K x 36 GS8160E36BT-250 DCD Pipeline/Flow Through TQFP 250/5.5 C
512K x 36 GS8160E36BT-200 DCD Pipeline/Flow Through TQFP 200/6.5 C
512K x 36 GS8160E36BT-150 DCD Pipeline/Flow Through TQFP 150/7.5 C
1M x 18 GS8160E18BT-250I DCD Pipeline/Flow Through TQFP 250/5.5 I
1M x 18 GS8160E18BT-200I DCD Pipeline/Flow Through TQFP 200/6.5 I
1M x 18 GS8160E18BT-150I DCD Pipeline/Flow Through TQFP 150/7.5 I
512K x 32 GS8160E32BT-250I DCD Pipeline/Flow Through TQFP 250/5.5 I
512K x 32 GS8160E32BT-200I DCD Pipeline/Flow Through TQFP 200/6.5 I
512K x 32 GS8160E32BT-150I DCD Pipeline/Flow Through TQFP 150/7.5 I
512K x 36 GS8160E36BT-250I DCD Pipeline/Flow Through TQFP 250/5.5 I
512K x 36 GS8160E36BT-200I DCD Pipeline/Flow Through TQFP 200/6.5 I
512K x 36 GS8160E36BT-150I DCD Pipeline/Flow Through TQFP 150/7.5 I
1M x 18 GS8160E18BGT-250 DCD Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C
1M x 18 GS8160E18BGT-200 DCD Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C
1M x 18 GS8160E18BGT-150 DCD Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C
512K x 32 GS8160E32BGT-250 DCD Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C
512K x 32 GS8160E32BGT-200 DCD Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C
512K x 32 GS8160E32BGT-150 DCD Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C
512K x 36 GS8160E36BGT-250 DCD Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C
512K x 36 GS8160E36BGT-200 DCD Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C
512K x 36 GS8160E36BGT-150 DCD Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C
1M x 18 GS8160E18BGT-250I DCD Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I
1M x 18 GS8160E18BGT-200I DCD Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I
1M x 18 GS8160E18BGT-150I DCD Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160E18B-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 22/23 © 2004, GSI Technology
512K x 32 GS8160E32BGT-250I DCD Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I
512K x 32 GS8160E32BGT-200I DCD Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I
512K x 32 GS8160E32BGT-150I DCD Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I
512K x 36 GS8160E36BGT-250I DCD Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I
512K x 36 GS8160E36BGT-200I DCD Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I
512K x 36 GS8160E36BGT-150I DCD Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I
Ordering Information for GSI Synchronous Burst RAMs (Continued)
Org Part Number1Type Package Speed2
(MHz/ns) TA3
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160E18B-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content Page;Revisions;Reason
GS8160ExxB_r1 • Creation of new datasheet
8160ExxB_r1;
8160ExxB_r1_01 Content • Updated overshoot/undershoot information
8160ExxB_r1_01;
8160ExxB_r1_02 Content • Added 300 MHz speed bin
8160ExxB_r1_02;
8160ExxB_r1_03 Content
• Removed 300 MHz speed bin
• Added Status column to Ordering Information table
• Changed Pb-free to RoHS-compliant
8160ExxB_r1_03;
8160ExxB_r1_04 Content • Updated Truth Tables (pg. 7, 8)
8160ExxB_r1_04;
8160ExxB_r1_05 Content • Updated for MP status
• \(Rev1.05a: added missing mode pins table)
GS8160E18/32/36BT-250/200/150
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05a 1/2011 23/23 © 2004, GSI Technology