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CY7C1049GN
4-Mbit (512K words × 8-bit) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-10613 Rev. *C Revised November 14, 2017
4-Mbit (512K wo rds × 8-bit) Static RAM
Features
■High speed
❐tAA = 10 ns
■Low active and standby currents
❐Active current: ICC = 38 mA typical
❐Standby current: ISB2 = 6 mA typical
■Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
■1.0 V data retention
■TTL-compatible inputs and outputs
■Pb-free 36-pin SOJ and 44-pin TSOP II packages
Functional Description
CY7C1049GN is a high-performance CMOS fast static RAM
device organized as 512K words by 8-bits.
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O0
through I/O7 and address on A0 through A18 pins.
Data reads are performed by asserting the Chip Enable (CE) and
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O0 through I/O7).
All I/Os (I/O0 through I/O7) are placed in a high-impedance state
during the following events:
■The device is deselected (CE HIGH)
■The control signal OE is de-asserted
The logic block diagram is on page 2.
Product Portfolio
Product Range VCC Range (V)
Speed
(ns)
10/15
Power Dissipation
Operating ICC, (mA) Standby, ISB2 (mA)
f = fmax
Typ[1] Max Typ[1] Max
CY7C1049GN18 Industrial 1.65 V–2.2 V 15 – 40 6 8
CY7C1049GN30 2.2 V–3.6 V 10 38 45
CY7C1049GN 4.5 V–5.5 V 10 38 45
Note
1. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
Document Number: 002-10613 Rev. *C Page 2 of 17
CY7C1049GN
Logic Block Diagram – CY7C1049GN
512Kx8
RAMARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMN
DECODER
A10
SENSE
AMPLIFIERS
A11
A12
A13
A14
A15
A16
A17
A18
INPUTBUFFER
I/O0‐I/O7
WE
OE
CE
Document Number: 002-10613 Rev. *C Page 3 of 17
CY7C1049GN
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
DC Electrical Characteristics .......................................... 5
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
AC Switching Characteristics ......................................... 8
Switching Waveforms ...................................................... 9
Truth Table ...................................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 002-10613 Rev. *C Page 4 of 17
CY7C1049GN
Pin Configurations
Figure 1. 36-pin SOJ pinout [2]
Figure 2. 44-pin TSOP II pinout, Single Chip Enable [2]
SOJ
A18A1235
A17A2334
A16A3433
I/O7I/O0730
OE
631
CE
GNDVCC 928
VCCGND 10 27
I/O5I/O211 26
I/O4I/O312 25
A14
WE 13 24
A13
A514 23
A12
A615 22
A11
A716 21
A10
A817 20
NCA918 19
NCA0136
I/O6I/O1829
A15A4532
NCNC 243
NCA0 342
A18A1 441
A15A4 738
A16
639
A3
I/O7I/O0 936
I/O6I/O1 10 35
VSSVCC 11 34
VCCVSS 12 33
I/O5
I/O2 13 32
I/O4
I/O3 14 31
A14
/WE 15 30
A13
A5 16 29
A12A6 17 28
A11A7 18 27
A10A8 19 26
NCA9 20 25
NC
NC 21 24
NC 22 23
NCNC 144
/OE/CE 837
A17A2 540
NC
44-pin TSOP II
Note
2. NC pins are not connected internally to the die.
Document Number: 002-10613 Rev. *C Page 5 of 17
CY7C1049GN
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage
on VCC relative to GND [3] ..................... –0.5 to VCC + 0.5 V
DC voltage applied to outputs
in HI-Z State [3] ................................... –0.5 V to VCC + 0.5 V
DC input voltage [3].............................. –0.5 V to VCC + 0.5 V
Current into outputs (in LOW state) ............................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Grade Ambient Temperature VCC
Industrial –40 C to +85 C 1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter Description Test Conditions 10 ns/15 ns Unit
Min Typ [4] Max
VOH Output HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – V
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2 – –
2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA 2.2 – –
3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –0.1mA VCC – 0.5[5] ––
VOL Output LOW
voltage
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 V
2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4
2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4
4.5 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4
VIH
Input HIGH
voltage
1.65 V to 2.2 V – 1.4 – VCC + 0.2[3] V
2.2 V to 2.7 V – 2 – VCC + 0.3[3]
2.7 V to 3.6 V – 2 – VCC + 0.3[3]
4.5 V to 5.5 V – 2 – VCC + 0.5[3]
VIL
Input LOW
voltage
1.65 V to 2.2 V – –0.2[3] –0.4V
2.2 V to 2.7 V – –0.3[3] –0.6
2.7 V to 3.6 V – –0.3[3] –0.8
4.5 V to 5.5 V – –0.5[3] –0.8
IIX Input leakage current GND < VIN < VCC –1 – +1 A
IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A
ICC Operating supply current Max VCC, IOUT = 0 mA,
CMOS levels
f = 100 MHz – 38 45 mA
f = 66.7 MHz – – 40
ISB1 Automatic CE power-down
current – TTL inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
––15mA
ISB2 Automatic CE power-down
current – CMOS inputs
Max VCC, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–68mA
Notes
3. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V),
VCC =3V (for V
CC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C.
5. This parameter is guaranteed by design and not tested.
Document Number: 002-10613 Rev. *C Page 6 of 17
CY7C1049GN
Capacitance
Parameter [6] Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit
CIN Input capacitance TA = 25 C, f = 1 MHz,
VCC = VCC(typ)
10 10 pF
COUT I/O capacitance 10 10 pF
Thermal Resistance
Parameter [6] Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52 68.85 C/W
JC Thermal resistance
(junction to case)
31.48 15.97 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [7]
90%
10%
VHIGH
GND
90%
10%
All Input Pulses
VCC
Output
5 pF*
* Including
jig and
scope (b)
R1
R2
Rise Time: Fall Time:
> 1 V/ns
(c)
Output
50
Z
0
= 50
V
TH
30 pF*
* Capacitive load consists
of all components of the
test environment
High-Z Characteristics:
(a)
> 1 V/ns
Parameters 1.8 V 3.0 V 5.0 V Unit
R1 1667 317 317
R2 1538 351 351
VTH 0.9 1.5 1.5 V
VHIGH 1.8 3 3 V
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization.
Document Number: 002-10613 Rev. *C Page 7 of 17
CY7C1049GN
Data Retention Characteristics
Over the operating range of –40 C to 85 C
Parameter Description Conditions Min Max Unit
VDR VCC for data retention 1 – V
ICCDR Data retention current VCC = 1.2 V, CE > VCC – 0.2 V[8],
VIN > VCC – 0.2 V, or VIN < 0.2 V
–8mA
tCDR[9] Chip deselect to data retention
time
0–ns
tR[8, 9] Operation recovery time VCC > 2.2 V 10 – ns
VCC < 2.2 V 15 – ns
Data Retention Waveform
Figure 4. Data Retention Waveform [8]
tCDR tR
VDR = 1.0 V
DATA RETENTION MODE
VCC(min) VCC(min)
VCC
CE
Notes
8. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC (min) > 100 s.
9. These parameters are guaranteed by design.
Document Number: 002-10613 Rev. *C Page 8 of 17
CY7C1049GN
AC Switching Characteristics
Over the operating range of –40 C to 85 C
Parameter [10] Description 10 ns 15 ns Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 10 – 15 – ns
tAA Address to data – 10 – 15 ns
tOHA Data hold from address change 3 – 3 – ns
tACE CE LOW to data – 10 – 15 ns
tDOE OE LOW to data – 4.5 – 8 ns
tLZOE OE LOW to low impedance [11] 0–0–ns
tHZOE OE HIGH to High-Z [11] –5–8ns
tLZCE CE LOW to low impedance [11] 3–3–ns
tHZCE CE HIGH to High-Z [11] –5–8ns
tPU CE LOW to power-up [12, 13] 0–0–ns
tPD CE HIGH to power-down [12, 13] –10–15ns
Write Cycle [13, 14]
tWC Write cycle time 10 – 15 – ns
tSCE CE LOW to write end 7 – 12 – ns
tAW Address setup to write end 7 – 12 – ns
tHA Address hold from write end 0–0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 7 – 12 – ns
tSD Data setup to write end 5 – 8 – ns
tHD Data hold from write end 0 – 0 – ns
tLZWE WE HIGH to low impedance [11] 3–3–ns
tHZWE WE LOW to High-Z [11] –5–8ns
Notes
10. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
le ve ls of 0 to 3 V (for VCC > 3 V) and 0 to VCC (f or VCC < 3 V). Test conditions for the read cycle use output loading, as shown in part (a) of Figure 3 on page 6, unless specified otherwise.
11. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 3 on page 6. Transition is measured 200 mV from steady state
voltage.
12. These parameters are guaranteed by design and are not tested.
13. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
14. The minimum write cycle pulse width in Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of tDS and tHZWE.
Document Number: 002-10613 Rev. *C Page 9 of 17
CY7C1049GN
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [15, 16]
Figure 6. Read Cycle No. 2 (OE Controlled) [15, 16]
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
tRC
tHZCE
tPD
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE DATAOUT VALID HIGH
IMPEDANCE
ADDRESS
CE
OE
DATA I /O
tHZOE
SUPPLY
CURRENT
VCC
ISB
Notes
15. WE is HIGH for the read cycle.
16. Address valid prior to or coincident with CE LOW transition.
Document Number: 002-10613 Rev. *C Page 10 of 17
CY7C1049GN
Figure 7. Write Cycle No. 1 (CE Controlled) [17, 18]
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [17, 18, 19]
Switching Waveforms (continued)
ADDRESS
CE
WE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPW E
tHA
tHD
tHZOE tSD
DATA
IN V A LID
ADDRESS
CE
DATA I/O
tWC
tSCE
tHD
tSD
tAW tHA
tSA tPWE
tLZW E
tHZWE
WE
DATA IN VALID
Notes
17. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
18. Data I/O is in HI-Z state if CE = VIH, or OE = VIH.
19. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE.
Document Number: 002-10613 Rev. *C Page 11 of 17
CY7C1049GN
Figure 9. Write Cycle No. 3 (WE Controlled) [20, 21, 22]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATA IN VALID
NOTE 23
CE1
ADDRESS
CE2
WE
DATA I/O
OE
Notes
20. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
21. Data I/O is in HI-Z state if CE = VIH, or OE = VIH.
22. Data I/O is high impedance if OE = VIH.
23. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 002-10613 Rev. *C Page 12 of 17
CY7C1049GN
Truth Table
CE OE WE I/O0–I/O7Mode Power
HX
[24] X[24] HI-Z Power down Standby (ISB)
L L H Data out Read all bits Active (ICC)
L X L Data in Write all bits Active (ICC)
L H H HI-Z Selected, outputs disabled Active (ICC)
Note
24. The input voltage levels on these pins should be either at VIH or VIL.
Document Number: 002-10613 Rev. *C Page 13 of 17
CY7C1049GN
Ordering Code Definitions
Ordering Information
Speed
(ns)
Voltage
Range Ordering Code Package
Diagram Package Type (all Pb-free) Operating
Range
10 2.2 V–3.6 V CY7C1049GN30-10ZSXI 51-85087 44-pin TSOP II Industrial
CY7C1049GN30-10ZSXIT 51-85087 44-pin TSOP II, Tape and Reel
CY7C1049GN30-10VXI 51-85090 36-pin Molded SOJ
CY7C1049GN30-10VXIT 51-85090 36-pin Molded SOJ, Tape and Reel
4.5 V–5.5 V CY7C1049GN-10VXI 51-85090 36-pin Molded SOJ
CY7C1049GN-10VXIT 51-85090 36-pin Molded SOJ, Tape and Reel
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = ZS or V
ZS = 44-pin TSOP II; V= 36-pin Molded SOJ
Speed: XX = 10 ns
Voltage Range: XX = 30 or blank
30 = 2.2 V–3.6 V; no character = 4.5 V–5.5 V
Process Technology: GN = 65 nm
Data Width: 9 = × 8-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 -XX I704 GN9XX
XX XX
Document Number: 002-10613 Rev. *C Page 14 of 17
CY7C1049GN
Package Diagrams
Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087
Figure 11. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090
51-85087 *E
51-85090 *G
Document Number: 002-10613 Rev. *C Page 15 of 17
CY7C1049GN
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE byte high enable
BLE byte low enable
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
TTL transistor-transistor logic
VFBGA very fine-pitch ball grid array
WE write enable
Symbol Unit of Measure
°C Degrees Celsius
MHz megahertz
Amicroamperes
smicroseconds
mA milliamperes
mm millimeter
ns nanoseconds
ohms
%percent
pF picofarads
Vvolts
Wwatts
Document Number: 002-10613 Rev. *C Page 16 of 17
CY7C1049GN
Document History Page
Document Title: CY7C1049GN, 4-Mbit (512K words × 8-bit) Static RAM
Document Number: 002-10613
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 5074703 NILE 01/06/2016 New data sheet.
*A 5082587 NILE 01/12/2016 Updated Logic Block Diagram – CY7C1049GN.
Updated Ordering Information:
Updated part numbers.
*B 5437570 NILE 09/15/2016 Updated DC Electrical Characteristics:
Removed details of VOH parameter corresponding to “2.7 V to 3.6 V” and
Test Condition “VCC = Min, IOH = –4.0 mA”.
Added details of VOH parameter corresponding to “2.7 V to 3.0 V” and
Test Condition “VCC = Min, IOH = –4.0 mA”.
Added details of VOH parameter corresponding to “3.0 V to 3.6 V” and
Test Condition “VCC = Min, IOH = –4.0 mA”.
Changed minimum value of VIH parameter corresponding to “4.5 V to 5.5 V”
from 2.2 V to 2 V.
Updated Note 3 (Replaced “2 ns” with “20 ns”).
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*C 5966829 NILE 11/14/2017 Updated Switching Waveforms:
Updated Figure 6.
Updated Figure 7.
Updated Figure 8.
Updated Figure 9.
Updated to new template.
Completing Sunset Review.
Document Number: 002-10613 Rev. *C Revised November 14, 2017 Page 17 of 17
CY7C1049GN
© Cypress Semiconductor Corporation, 2016-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
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