Semiconductor Components Industries, LLC, 2004
October, 2004 − Rev. 4 1Publication Order Number:
NTHS2101P/D
NTHS2101P
Power MOSFET
−8.0 V, −7.5 A P−Channel ChipFET
Features
•Offers an Ultra Low RDS(on) Solution in the ChipFET Package
•Miniature ChipFET Package 40% Smaller Footprint than TSOP−6
making it an Ideal Device for Applications where Board Space is at a
Premium
•Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin
Environments such as Portable Electronics
•Designed to Provide Low RDS(on) at Gate Voltage as Low as 1.8 V, the
Operating Voltage used in many Logic ICs in Portable Electronics
•Simplifies Circuit Design since Additional Boost Circuits for Gate
Voltages are not Required
•Operated at Standard Logic Level Gate Drive, Facilitating Future
Migration to Lower Levels using the same Basic Topology
•Pb−Free Package is Available
Applications
•Optimized for Battery and Load Management Applications in
Portable Equipment such as MP3 Players, Cell Phones, Digital
Cameras, Personal Digital Assistant and other Portable Applications
•Charge Control in Battery Chargers
•Buck and Boost Converters
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain−to−Source Voltage VDSS −8.0 Vdc
Gate−to−Source Voltage − Continuous VGS 8.0 Vdc
Drain Current − Continuous
− 5 seconds ID−5.4
−7.5 A
Total Power Dissipation
Continuous @ TA = 25°C
(5 sec) @ TA = 25°C
Continuous @ 85°C
(5 sec) @ 85°C
PD1.3
2.5
0.7
1.3
W
Continuous Source Current Is −1.1 A
Thermal Resistance (Note 1)
Junction−to−Ambient, 5 sec
Junction−to−Ambient, Continuous
RJA 50
95
°C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds TL260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
G
S
D
P−Channel MOSFET
S
D
G
D
D
D
D
D
1
2
3
45
6
7
8
Device Package Shipping†
ORDERING INFORMATION
NTHS2101PT1 ChipFET 3000/Tape & Reel
PIN
CONNECTIONS
ChipFET
CASE 1206A
STYLE 1
MARKING
DIAGRAM
D4 M
D4 = Specific Device Code
M = Month Code
1
2
3
4
8
7
6
5
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†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
25 m @ −2.5 VGS
Ultra Low RDS(on) TYP ID MAXV(BR)DSS
−8.0 V
19 m @ −4.5 VGS
−7.5 A
34 m @ −1.8 VGS
NTHS2101PT1G ChipFET
(Pb−Free) 3000/Tape & Reel
NTHS2101P
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
Temperature Coefficient (Positive) V(Br)DSS VGS = 0 Vdc, ID = −250 Adc −8.0 Vdc
Gate−Body Leakage Current Zero IGSS VDS = 0 Vdc, VGS = 8.0 Vdc 100 nAdc
Zero Gate Voltage Drain Current IDSS VDS = −6.4 Vdc, VGS = 0 Vdc
VDS = −6.4 Vdc, VGS = 0 Vdc,
TJ = 85°C
−1.0
−5.0 Adc
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage VGS(th) VDS = VGS, ID = −250 Adc −0.45 −1.5 Vdc
Static Drain−to−Source On−Resistance RDS(on) VGS = −4.5 Vdc, ID = −5.4 Adc
VGS = −2.5 Vdc, ID = −4.5 Adc
VGS = −1.8 Vdc, ID = −2.0 Adc
19
25
34
25
36
48
m
Forward Transconductance gFS VDS = −5.0 Vdc, ID = −5.2 Adc 20 S
Diode Forward Voltage VSD IS = −1.1 Adc, VGS = 0 Vdc −0.62 −1.2 V
DYNAMIC CHARACTERISTIC
Input Capacitance Ciss VDS = −6.4 Vdc
V V
2400 pF
Output Capacitance Coss VGS = 0 V
f=10MHz
550
Transfer Capacitance Crss
f
=
1
.
0
MH
z420
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time td(on) VDD = −6.4 Vdc
V V
7.0 ns
Rise Time trVGS = −4.5 Vdc
ID=
−
54A
dc
28
Turn−Off Delay Time td(off)
I
D = −
5
.
4
A
dc
RG = 2.0 (Note 2) 73
Fall Time tf
RG
=
2
.
0
(Note
2)
60
Gate Charge QGV
GS
= −4.5 V
dc
15 30 nC
QGS
VGS
=
−
4
.
5
Vd
c
ID = −5.4 Adc 4.0
QGD
Ddc
VDS = −6.4 Vdc 8.0
Source−Drain Reverse Recovery Time Trr IF = −1.1 A, di/dt = 100 A/s 90 ns
2. Pulse Test: Pulse Width = 250 s, Duty Cycle = 2%.
3. Switching characteristics are independent of operating junction temperatures.
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3
TYPICAL ELECTRICAL CHARACTERISTICS
16
12
8
4
00123456
−2 V 16
12
8
4
00 0.5 1.0 1.5 2.0 2.5
TJ = −55°C
−VDS, DRAIN−TO−SOURCE VOLTAGE (V) −VGS, GATE−TO−SOURCE VOLTAGE (V)
VGS = −8 thru −2.4 V
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
−1.8 V
−1.6 V
−1.4 V
TJ = 25°C
−ID, DRAIN CURRENT (AMPS)
−ID, DRAIN CURRENT (AMPS)
3.0
TJ = 100°C TJ = 25°C
0.08
0.06
0.04
0.02
02 4 6 8 10 12 20
1.6
1.4
1.2
0.8
0.6
−50 −25 0 25 50 125
VGS = −4.5 V
−ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE (°C)
VGS = −1.8 V
Figure 3. On−Resistance versus Drain Current
and Gate Voltage Figure 4. On−Resistance Variation with
Temperature
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
150
10,000
1000
100
10
102468
3500
3000
1000
500
086 4 2 0 2
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
VGS = 0 V
Figure 5. Drain−to−Source Leakage Current
vs. Voltage Figure 6. Capacitance Variation
−IDSS, LEAKAGE (nA)
C, CAPACITANCE (pF)
4
TJ = 25°C
14 16 18
0.10
VGS = −2.5 V
VGS = −4.5 V
1.0
75 100
TJ = 125°C
TJ = 100°C
68
1500
2000
2500
5000
4500
4000
Ciss
Crss
Coss
Ciss
Crss
−VGS −VDS
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4
TYPICAL ELECTRICAL CHARACTERISTICS
4
3
2
1
00369
1000
100
1110
VDD = −6.4 V
ID = −5.4 A
VGS = −4.5 V
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE ()
Figure 7. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge Figure 8. Resistive Switching Time Variation
vs. Gate Resistance
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
100
5
3
2
1
00.4 0.5 0.6 0.7 0.8
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
VGS = 0 V
TJ = 25°C
Figure 9. Diode Forward Voltage vs. Current
−IS, SOURCE CURRENT (AMPS)
12 15
5
ID = 5.4 A
TJ = 25°C
10
QT
td(off)
td(on)
tf
tr
4
8
7
5
3
1
0
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−VGS
2
4
Q1 Q2
6
2
1
0.1
0.0110 1010
−4 −3 −2 −1
10 1 10 100 600
SQUARE WAVE PULSE DURATION (sec)
Duty Cycle = 0.5
0.2
Single Pulse
0.1
0.05
0.02
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 80°C/W
3. TJM − TA = PDMZthJA(t)
4. Surface Mounted
t1
t2
PDM
Notes:
t1t2
Figure 10. Normalized Thermal Transient Impedance, Junction−to−Ambient
NORMALIZED EFFECTIVE TRANSIENT
THERMAL IMPEDANCE
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5
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE E
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
BS
C
D
G
L
A
1234
8765
M
J
K
1234
8765
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.95 3.10 0.116 0.122
B1.55 1.70 0.061 0.067
C1.00 1.10 0.039 0.043
D0.25 0.35 0.010 0.014
G0.65 BSC 0.025 BSC
J0.10 0.20 0.004 0.008
K0.28 0.42 0.011 0.017
L0.55 BSC 0.022 BSC
M°5 NOM
S1.80
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.
0.05 (0.002)
°5 NOM
2.00 0.072 0.080
Basic Style 1 mm
inches
0.178
0.007
2.032
0.08
1.727
0.068
0.66
0.026
0.711
0.028
0.457
0.018
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.711
0.028 mm
inches
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINTS*
NTHS2101P
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to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5773−3850
NTHS2101P/D
ChipFET is a trademark of Vishay Siliconix.
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