2009-2016 Microchip Technology Inc. DS60001156J-page 1
PIC32MX5XX/6XX/7XX
Operating Conditions
• 2.3V to 3.6V, -40ºC to +105ºC, DC to 80 MHz
Core: 80 MHz/105 DMIPS MIPS32
®
M4K
®
• MIPS16e
®
mode for up to 40% smaller code size
• Code-effici ent (C and Assembly) architecture
• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply
Clock Management
• 0.9% internal oscillator (on some variants)
• Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent W at chdog Timer
• Fast wake-up and start-up
Power Management
• Low-power management modes (Sleep and Idle)
• Integrated Power-on Reset, Brown-out Reset
• 0.5 mA/MHz dynamic current (typical)
• 41 µA IPD current (typical)
Graphics Features
• External graphics interface with up to 34 Parallel Master
Port (PMP ) p ins :
- Int er fa ce t o external graphics controller
- Capable of driving LCD directly with DMA and
internal or external memory
Analog Features
• ADC Module:
- 10-b it 1 M sps rate with one Sampl e and Hold (S&H )
- 16 analog inputs
- Can operate during Sleep mode
• Flexible and independent ADC trigger sources
•Comparators:
- Two dual-i nput Com parator m odules
- Pr ogr am m able ref er enc es w i t h 32 voltage points
T imers/Output Compare/Input Captur e
• Five General Purpose T imers:
- Five 16-bit and up to two 32-bit Timers /C ounters
• Five Output Compare (OC) modules
• Five Input Capture (IC) modules
• Real-T ime Clock and Calendar (RTCC) module
Communication Interf aces
• USB 2.0-compliant Full-Speed OTG controller
• 10/100 Mbps Ethernet MAC with MII and RMII interface
• CAN module:
- 2.0B Active with DeviceNet™ addressing support
• Six UART modules (20 Mbps):
- Sup ports LIN 2.1 prot ocols and I rDA
®
support
• Up to four 4-wire SPI modules (25 Mbps)
• Up to five I
2
C modules (up to 1 Mbaud) with SMBus
support
• Parallel Master Port (PMP)
Direct Memory Access (DMA)
• Up to eight channels of hardware DMA with automatic
data size detection
• 32-bit Programmable Cyclic Redundancy Check (CRC)
• Six additional channel s dedicated to USB, Ethernet and
CAN modules
Input/Output
• 15 mA or 10 mA source/sink for standard V
OH
/V
OL
and
up to 22 mA for non-standard V
OH
1
• 5V-t olerant pins
• Selectable open drain and pull-ups
• External interrupts
Qualification and Class B Support
• AEC-Q100 REVH (Grade 2 -40ºC to +105ºC)
• Class B Safety Library, IEC 60730
Debugger Development Support
• In-circuit and in-application programming
•4-wire MIPS
®
Enhanced JTA G interface
• Unlimited program and six complex data breakpoints
• IEEE 1149.2-compatible (JTAG) boundary scan
Packages
Type QFN TQFP TFBGA VTLA
Pin Count 64 64 100 100 121 124
I/O Pins (up to) 51 51 83 83 83 83
Contact/Lead Pitch 0.50 0.50 0.40 0.50 0.80 0.50
Dimensions 9x9x0.9 10x10x1 12x12x1 14x14x1 10x10x1.1 9x9x0.9
Note: All dimensions are in millimeters (mm) unless specified.
32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM)
with
Graphics Interface, USB, CAN, and Ethernet
PIC32MX5XX/6XX/7XX
DS60001156J-page 2 2009-2016 Mic rochip Technology Inc.
TABLE 1: PIC32MX5XX USB AND CAN FEATURES
USB and CAN
Device
Pins
Progra m Memory (K B)
Data Memory (KB)
USB
CAN
Timers/Capture/Compare
DMA Channels
(Programmable/Dedicated)
UART
(2,3)
SPI
(3)
I
2
C
(3)
10-bit 1 Msps A D C ( C ha nne ls)
Comparators
PMP/PSP
JTAG
Trace
Packages
(4)
PIC32MX534F064H 64 64 + 12
(1)
16 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX564F064H 64 64 + 12
(1)
32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX564F128H 64 128 + 12
(1)
32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX575F256H 64 256 + 12
(1)
64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX575F512H 64 512 + 12
(1)
64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX534F064L 100 64 + 12
(1)
16 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT,
PF,
BG
PIC32MX564F064L 100 64 + 12
(1)
32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT,
PF,
BG
PIC32MX564F128L 100 128 + 12
(1)
32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT,
PF,
BG
PIC32MX575F256L 100 256 + 12
(1)
64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT,
PF,
BG
PIC32MX575F512L 100 512 + 12
(1)
64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT,
PF,
BG
Legend: PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA
(5)
Note 1: This device features 12 KB boot Flash memory.
2: CTS and RTS pins may not be available for all UART modules. Refer to the “Device Pin Tables” section for more
information.
3: Some pins between the UART, SPI and I
2
C modules may be shared. Refer to the “Device Pin T ables” section for more
information.
4: Refer to 34.0 “Packaging Information” for more inform ation.
5: 100-pin devices in the VTLA package are available upon request. Please contact your local Microchip Sales Office for
details.
2009-2016 Microchip Technology Inc. DS60001156J-page 3
PIC32MX5XX/6XX/7XX
TABLE 2: PIC32MX6XX USB AND ETHERNET FEATURES
USB and Ethernet
Device
Pins
Program Memory (KB)
Data Memory (KB)
USB
Ethernet
Timers/Capture/Compare
DMA Channels
(Programmable/Dedicated)
UART
(2,3)
SPI
(3)
I
2
C
(3)
10-bit 1 Msps ADC (Channels)
Comparators
PMP/PSP
JTAG
Trace
Packages
(4)
PIC32MX664F064H 64 64 + 12
(1)
32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX664F128H 64 128 + 12
(1)
32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX675F256H 64 256 + 12
(1)
64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX675F512H 64 512 + 12
(1)
64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX695F512H 64 512 + 12
(1)
128 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX664F064L 100 64 + 12
(1)
32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT , PF,
BG
PIC32MX664F128L 100 128 + 12
(1)
32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PT , PF,
BG
PIC32MX675F256L 100 256 + 12
(1)
64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT , PF,
BG
PIC32MX675F512L 100 512 + 12
(1)
64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT , PF,
BG, TL
PIC32MX695F512L 100 512 + 12
(1)
128 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PT , PF,
BG, TL
Legend: PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA
(5)
Note 1: This device features 12 KB boot Flash memory.
2: CTS and RTS pins may not be available for all UART modules. Refer to the “Device Pin Tables” section for more
information.
3: Some pins between the UART, SPI and I
2
C modules may be shared. Refer to the “Device Pin Tables” se cti on fo r
more information.
4: Refer to 34.0 “Packaging Information” for more information.
5: 100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local
Microchip Sales Office for details.
PIC32MX5XX/6XX/7XX
DS60001156J-page 4 2009-2016 Mic rochip Technology Inc.
TABLE 3: PIC32MX7XX USB, ETHERNET, AND CAN FEATURES
USB, Ethernet, and CAN
Device
Pins
Progra m Memory (K B)
Data Memory (KB)
USB
Ethernet
CAN
Timers/Capture/Compare
DMA Channels
(Programmable/Dedicated)
UART
(2,3)
SPI
(3)
I
2
C
(3)
10-bit 1 Msps A D C ( C ha nne ls)
Comparators
PMP/PSP
JTAG
Trace
Packages
(4)
PIC32MX764F128H 64 128 + 12
(1)
32 1 1 1 5/5/5 4/8 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX775F256H 64 256 + 12
(1)
64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX775F512H 64 512 + 12
(1)
64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX795F512H 64 512 + 12
(1)
128 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT,
MR
PIC32MX764F128L 100 128 + 12
(1)
32 1 1 1 5/5/5 4/6 6 4 5 16 2 Yes Yes Yes PT, PF,
BG
PIC32MX775F256L 100 256 + 12
(1)
64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PT, PF,
BG
PIC32MX775F512L 100 512 + 12
(1)
64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PT, PF,
BG
PIC32MX795F512L 100 512 + 12
(1)
128 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PT, PF,
BG, TL
Legend: PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA
(5)
Note 1: This device features 12 KB boot Flash memory.
2: CTS and RTS pins may not be available for all UART modules. Refer to the “Device Pin Tables” section for more
information.
3: Some pins between the UART, SPI and I
2
C modules may be shared. Refer to the “Device Pin Tables” se cti on fo r
more information.
4: Refer to Section 34.0 “Packaging Informatio n” for more information.
5: 100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local
Microchip Sales Office for details.
2009-2016 Microchip Technology Inc. DS60001156J-page 5
PIC32MX5XX/6XX/7XX
Device Pin Tables
TABLE 4: PIN NAMES FOR 64-PIN USB AND CAN DEVICES
Pin # Full Pin Name Pin # Full Pin Name
1PMD5/RE5 33 USBID/RF3
2PMD6/RE6 34 V
BUS
3PMD7/RE7 35 V
USB
3
V
3
4 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 36 D-/RG3
5SDA4/SDI2/U3RX/PMA4/CN9/RG7 37 D+/RG2
6 SCL4/SDO2/U3TX/PMA3/CN10/RG8 38 V
DD
7MCLR 39 OSC1/CLKI/RC12
8SS2/U6RX/U3CTS/PMA2/CN11/RG9 40 OSC2/CLKO/RC15
9V
SS
41 Vss
10 V
DD
42 RTCC/IC1/INT1/RD8
11 AN5/C1IN+/V
BUSON
/CN7/RB5 43 SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
12 AN4/C1IN-/CN6/RB4 44 SCL1/IC3/PMCS2/PMA15/INT3/RD10
13 AN3/C2IN+/CN5/RB3 45 IC4/PMCS1/PMA14/INT4/RD11
14 AN2/C2IN-/CN4/RB2 46 OC1/INT0/RD0
15 PGEC1/AN1/V
REF
-/CV
REF
-/CN3/RB1 47 SOSCI/CN1/RC13
16 PGED1/AN0/V
REF
+/CV
REF
+/PMA6/CN2/RB0 48 SOSCO/T1CK/CN0/RC14
17 PGEC2/AN6/OCFA/RB6 49 SCK3/U4TX/U1RTS/OC2/RD1
18 PGED2/AN7/RB7 50 SDA3/SDI3/U1RX/OC3/RD2
19 AV
DD
51 SCL3/SDO3/U1TX/OC4/RD3
20 AV
SS
52 OC5/IC5/PMWR/CN13/RD4
21 AN8/SS4/U5RX/U2CTS/C1OUT/RB8 53 PMRD/CN14/RD5
22 AN9/C2OUT/PMA7/RB9 54 CN15/RD6
23 TMS/AN10/CV
REFOUT
/PMA13/RB10 55 CN16/RD7
24 TDO/AN11/PMA12/RB11 56 V
CAP
25 V
SS
57 V
DD
26 V
DD
58 C1RX/RF0
27 TCK/AN12/PMA11/RB12 59 C1TX/RF1
28 TDI/AN13/PMA10/RB13 60 PMD0/RE0
29 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 61 PMD1/RE1
30 AN15/OCFB/PMALL/PMA0/CN12/RB15 62 PMD2/RE2
31 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 63 PMD3/RE3
32 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 64 PMD4/RE4
Note 1: Shaded pins are 5V tolerant.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V
SS
external ly.
64 1
QFN
(2)
64-PIN QF N
(2)
AND TQFP (TOP VIEW)
PIC32MX534F064H
PIC32MX564F064H
PIC32MX564F128H
PIC32MX575F256H
PIC32MX575F512H
1
64
TQFP
PIC32MX5XX/6XX/7XX
DS60001156J-page 6 2009-2016 Mic rochip Technology Inc.
TABLE 5: PIN NAMES FOR 64-PIN USB AND ETHERNET DEVICES
Pin # Full Pin Name Pin # Full Pin Name
1
ETXEN/PMD5/RE5 33 USBID/RF3
2 ETXD0/PMD6/RE6 34 V
BUS
3ETXD1/PMD7/RE7 35 V
USB
3
V
3
4 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 36 D-/RG3
5SDA4/SDI2/U3RX/PMA4/CN9/RG7 37 D+/RG2
6 SCL4/SDO2/U3TX/PMA3/CN10/RG8 38 V
DD
7MCLR 39 OSC1/CLKI/RC12
8 SS2/U6RX/U3CTS/PMA2/CN11/RG9 40 OSC2/CLKO/RC15
9V
SS
41 Vss
10 V
DD
42 RTCC/AERXD1/ETXD3/IC1/INT1/RD8
11 AN5/C1IN+/V
BUSON
/CN7/RB5 43 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
12 AN4/C1IN-/CN6/RB4 44 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
13 AN3/C2IN+/CN5/RB3 45 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
14 AN2/C2IN-/CN4/RB2 46 OC1/INT0/RD0
15 PGEC1/AN1/V
REF
-/CV
REF
-/CN3/RB1 47 SOSCI/CN1/RC13
16 PGED1/AN0/V
REF
+/CV
REF
+/PMA6/CN2/RB0 48 SOSCO/T1CK/CN0/RC14
17 PGEC2/AN6/OCFA/RB6 49 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
18 PGED2/AN7/RB7 50 SDA3/SDI3/U1RX/OC3/RD2
19 AV
DD
51 SCL3/SDO3/U1TX/OC4/RD3
20 AV
SS
52 OC5/IC5/PMWR/CN13/RD4
21 AN8/SS4/U5RX/U2CTS/C1OUT/RB8 53 PMRD/CN14/RD5
22 AN9/C2OUT/PMA7/RB9 54 AETXEN/ETXERR/CN15/RD6
23 TMS/AN10/CV
REFOUT
/PMA13/RB10 55 ETXCLK/AERXERR/CN16/RD7
24 TDO/AN11/PMA12/RB11 56 V
CAP
25 V
SS
57 V
DD
26 V
DD
58 AETXD1/ERXD3/RF0
27 TCK/AN12/PMA11/RB12 59 AETXD0/ERXD2/RF1
28 TDI/AN13/PMA10/RB13 60 ERXD1/PMD0/RE0
29 AN14/SCK4/U5TX/U2RTSU2RTS/PMALH/PMA1/RB14 61 ERXD0/PMD1/RE1
30 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 62 ERXDV/ECRSDV/PMD2/RE2
31 SDA5/SDI4/U2RX/PMA9/CN17/RF4 63 ERXCLK/EREFCLK/PMD3/RE3
32 SCL5/SDO4/U2TX/PMA8/CN18/RF5 64 ERXERR/PMD4/RE4
Note 1:
Shaded pins are 5V tolerant.
2:
The metal plane at the bottom of the QFN device is not connected to any pins and is recommended to be connected to V
SS
externally.
64 1
QFN
(2)
1
64
TQFP
64-PIN QF N
(2)
AND TQFP (TOP VIEW)
PIC32MX664F128H
PIC32MX675F256H
PIC32MX695F512H
PIC32MX675F512H
PIC32MX664F064H
2009-2016 Microchip Technology Inc. DS60001156J-page 7
PIC32MX5XX/6XX/7XX
TABLE 6: PIN NAMES FOR 64-PIN USB, ETHERNET, AND CAN DEVICES
Pin # Full Pin Name Pin # Full Pin Name
1ETXEN/PMD5/RE5 33 USBID/RF3
2 ETXD0/PMD6/RE6 34 V
BUS
3ETXD1/PMD7/RE7 35 V
USB
3
V
3
4 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 36 D-/RG3
5SDA4/SDI2/U3RX/PMA4/CN9/RG7 37 D+/RG2
6 SCL4/SDO2/U3TX/PMA3/CN10/RG8 38 V
DD
7MCLR 39 OSC1/CLKI/RC12
8 SS2/U6RX/U3CTS/PMA2/CN11/RG9 40 OSC2/CLKO/RC15
9V
SS
41 Vss
10 V
DD
42 RTCC/AERXD1/ETXD3/IC1/INT1/RD8
11 AN5/C1IN+/V
BUSON
/CN7/RB5 43 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
12 AN4/C1IN-/CN6/RB4 44 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
13 AN3/C2IN+/CN5/RB3 45 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
14 AN2/C2IN-/CN4/RB2 46 OC1/INT0/RD0
15 PGEC1/AN1/V
REF
-/CV
REF
-/CN3/RB1 47 SOSCI/CN1/RC13
16 PGED1/AN0/V
REF
+/CV
REF
+/PMA6/CN2/RB0 48 SOSCO/T1CK/CN0/RC14
17 PGEC2/AN6/OCFA/RB6 49 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
18 PGED2/AN7/RB7 50 SDA3/SDI3/U1RX/OC3/RD2
19 AV
DD
51 SCL3/SDO3/U1TX/OC4/RD3
20 AV
SS
52 OC5/IC5/PMWR/CN13/RD4
21 AN8/C2TX
(2)
/SS4/U5RX/U2CTS/C1OUT/RB8 53 PMRD/CN14/RD5
22 AN9/C2OUT/PMA7/RB9 54 AETXEN/ETXERR/CN15/RD6
23 TMS/AN10/CV
REFOUT
/PMA13/RB10 55 ETXCLK/AERXERR/CN16/RD7
24 TDO/AN11/PMA12/RB11 56 V
CAP
25 V
SS
57 V
DD
26 V
DD
58 C1RX/AETXD1/ERXD3/RF0
27 TCK/AN12/PMA11/RB12 59 C1TX/AETXD0/ERXD2/RF1
28 TDI/AN13/PMA10/RB13 60 ERXD1/PMD0/RE0
29 AN14/C2RX
(2)
/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 61 ERXD0/PMD1/RE1
30 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 62 ERXDV/ECRSDV/PMD2/RE2
31 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 63 ERXCLK/EREFCLKPMD3/RE3
32 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 64 ERXERR/PMD4/RE4
Note 1:
Shaded pins are 5V tolerant.
2:
This pin is not available on PIC32MX765F128H devices.
3:
The metal plane at the bottom of the QFN device is not connected to any pins and is recommended to be connected to V
SS
externally.
64 1
QFN
(3)
1
64
TQFP
64-PIN QF N
(3)
AND TQFP (TOP VIEW)
PIC32MX775F256H
PIC32MX775F512H
PIC32MX795F512H
PIC32MX764F128H
PIC32MX5XX/6XX/7XX
DS60001156J-page 8 2009-2016 Mic rochip Technology Inc.
TABLE 7: PIN NAMES FOR 100-PIN USB AND CAN DEVICES
Pin # Full Pin Name Pin # Full Pin Name
1RG15 36V
SS
2V
DD
37 V
DD
3PMD5/RE5 38 TCK/RA1
4PMD6/RE6 39 AC1TX/SCK4/U5TX/U2RTS/RF13
5PMD7/RE7 40 AC1RX/SS4/U5RX/U2CTS/RF12
6 T2CK/RC1 41 AN12/PMA11/RB12
7 T3CK/RC2 42 AN13/PMA10/RB13
8 T4CK/RC3 43 AN14/PMALH/PMA1/RB14
9 T5CK/SDI1/RC4 44 AN15/OCFB/PMALL/PMA0/CN12/RB15
10 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 45 V
SS
11 SDA4/SDI2/U3RX/PMA4/CN9/RG7 46 V
DD
12 SCL4/SDO2/U3TX/PMA3/CN10/RG8 47 SS3/U4RX/U1CTS/CN20/RD14
13 MCLR 48 SCK3/U4TX/U1RTS/CN21/RD15
14 SS2/U6RX/U3CTS/PMA2/CN11/RG9 49 SDA5/SDI4/U2RX/PMA9/CN17/RF4
15 V
SS
50 SCL5/SDO4/U2TX/PMA8/CN18/RF5
16 V
DD
51 USBID/RF3
17 TMS/RA0 52 SDA3/SDI3/U1RX/RF2
18 INT1/RE8 53 SCL3/SDO3/U1TX/RF8
19 INT2/RE9 54 V
BUS
20 AN5/C1IN+/V
BUSON
/CN7/RB5 55 V
USB
3
V
3
21 AN4/C1IN-/CN6/RB4 56 D-/RG3
22 AN3/C2IN+/CN5/RB3 57 D+/RG2
23 AN2/C2IN-/CN4/RB2 58 SCL2/RA2
24 PGEC1/AN1/CN3/RB1 59 SDA2/RA3
25 PGED1/AN0/CN2/RB0 60 TDI/RA4
26 PGEC2/AN6/OCFA/RB6 61 TDO/RA5
27 PGED2/AN7/RB7 62 V
DD
28 V
REF
-/CV
REF
-/PMA7/RA9 63 OSC1/CLKI/RC12
29 V
REF
+/CV
REF
+/PMA6/RA10 64 OSC2/CLKO/RC15
30 AV
DD
65 V
SS
31 AV
SS
66 SCL1/INT3/RA14
32 AN8/C1OUT/RB8 67 SDA1/INT4/RA15
33 AN9/C2OUT/RB9 68 RTCC/IC1/RD8
34 AN10/CV
REFOUT
/PMA13/RB10 69 SS1/IC2/RD9
35 AN11/PMA12/RB11 70 SCK1/IC3/PMCS2/PMA15/RD10
Note 1:
Shaded pins are 5V tolerant.
100-PIN TQFP (TOP VIEW)
PIC32MX534F064L
PIC32MX564F128L
PIC32MX564F064L
PIC32MX575F512L
PIC32MX575F256L
1
100
2009-2016 Microchip Technology Inc. DS60001156J-page 9
PIC32MX5XX/6XX/7XX
71 IC4/PMCS1/PMA14/RD11 86 V
DD
72 SDO1/OC1/INT0/RD0 87 C1RX/PMD11/RF0
73 SOSCI/CN1/RC13 88 C1TX/PMD10/RF1
74 SOSCO/T1CK/CN0/RC14 89 PMD9/RG1
75 V
SS
90 PMD8/RG0
76 OC2/RD1 91 TRCLK/RA6
77 OC3/RD2 92 TRD3/RA7
78 OC4/RD3 93 PMD0/RE0
79 IC5/PMD12/RD12 94 PMD1/RE1
80 PMD13/CN19/RD13 95 TRD2/RG14
81 OC5/PMWR/CN13/RD4 96 TRD1/RG12
82 PMRD/CN14/RD5 97 TRD0/RG13
83 PMD14/CN15/RD6 98 PMD2/RE2
84 PMD15/CN16/RD7 99 PMD3/RE3
85 V
CAP
100 PMD4/RE4
TABLE 7: PIN NAMES FOR 100-PIN USB AND CAN DEVICES (CONTINUED)
Pin # Full Pin Name Pin # Full Pin Name
Note 1:
Shaded pins are 5V tolerant.
100-PIN TQFP (TOP VIEW)
PIC32MX534F064L
PIC32MX564F128L
PIC32MX564F064L
PIC32MX575F512L
PIC32MX575F256L
1
100
PIC32MX5XX/6XX/7XX
DS60001156J-page 10 2009-2016 Microchip Technology Inc.
TABLE 8: PIN NAMES FOR 100-PIN USB AND ETHERNET DEVICES
Pin # Full P in Name Pin # Full Pin Name
1 AERXERR/RG15 36 V
SS
2V
DD
37 V
DD
3PMD5/RE5 38 TCK/RA1
4PMD6/RE6 39 SCK4/U5TX/U2RTS/RF13
5PMD7/RE7 40 SS4/U5RX/U2CTS/RF12
6 T2CK/RC1 41 AN12/ERXD0/AECRS/PMA11/RB12
7 T3CK/RC2 42 AN13/ERXD1/AECOL/PMA10/RB13
8 T4CK/RC3 43 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
9 T5CK/SDI1/RC4 44 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
10 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 45 V
SS
11 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 46 V
DD
12
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8
47 AETXD0/SS3/U4RX/U1CTS/CN20/RD14
13 MCLR 48 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
14 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 49 SDA5/SDI4/U2RX/PMA9/CN17/RF4
15 V
SS
50 SCL5/SDO4/U2TX/PMA8/CN18/RF5
16 V
DD
51 USBID/RF3
17 TMS/RA0 52 SDA3/SDI3/U1RX/RF2
18 AERXD0/INT1/RE8 53 SCL3/SDO3/U1TX/RF8
19 AERXD1/INT2/RE9 54 V
BUS
20 AN5/C1IN+/V
BUSON
/CN7/RB5 55 V
USB
3
V
3
21 AN4/C1IN-/CN6/RB4 56 D-/RG3
22 AN3/C2IN+/CN5/RB3 57 D+/RG2
23 AN2/C2IN-/CN4/RB2 58 SCL2/RA2
24 PGEC1/AN1/CN3/RB1 59 SDA2/RA3
25 PGED1/AN0/CN2/RB0 60 TDI/RA4
26 PGEC2/AN6/OCFA/RB6 61 TDO/RA5
27 PGED2/AN7/RB7 62 V
DD
28 V
REF
-/CV
REF
-/AERXD2/PMA7/RA9 63 OSC1/CLKI/RC12
29 V
REF
+/CV
REF
+/AERXD3/PMA6/RA10 64 OSC2/CLKO/RC15
30 AV
DD
65 V
SS
31 AV
SS
66 AETXCLK/SCL1/INT3/RA14
32 AN8/C1OUT/RB8 67 AETXEN/SDA1/INT4/RA15
33 AN9/C2OUT/RB9 68 RTCC/EMDIO/AEMDIO/IC1/RD8
34 AN10/CV
REFOUT
/PMA13/RB10 69
SS1/
IC2/RD9
35 AN11/ERXERR/AETXERR/PMA12/RB11 70
SCK1/IC3/PMCS2/PMA15/RD10
Note 1:
Shaded pins are 5V tolerant.
100-PIN TQFP (TOP VIEW)
PIC32MX664F128L
PIC32MX675F256L
PIC32MX695F512L
PIC32MX675F512L
PIC32MX664F064L
1
100
2009-2016 Microchip Technology Inc. DS60001156J- page 11
PIC32MX5XX/6XX/7XX
71
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
86 V
DD
72 SDO1/OC1/INT0/RD0 87 ETXD1/PMD11/RF0
73 SOSCI/CN1/RC13 88 ETXD0/PMD10/RF1
74 SOSCO/T1CK/CN0/RC14 89 ETXERR/PMD9/RG1
75 V
SS
90 PMD8/RG0
76 OC2/RD1 91 TRCLK/RA6
77 OC3/RD2 92 TRD3/RA7
78 OC4/RD3 93 PMD0/RE0
79 ETXD2/IC5/PMD12/RD12 94 PMD1/RE1
80 ETXD3/PMD13/CN19/RD13 95 TRD2/RG14
81 OC5/PMWR/CN13/RD4 96 TRD1/RG12
82 PMRD/CN14/RD5 97 TRD0/RG13
83 ETXEN/PMD14/CN15/RD6 98 PMD2/RE2
84 ETXCLK/PMD15/CN16/RD7 99 PMD3/RE3
85 V
CAP
/V
DDCORE
100 PMD4/RE4
TABLE 8: PIN NAMES FOR 100-PIN USB AND ETHERNET DEVICES (CONTINUED)
Pin # Full P in Name Pin # Full Pin Name
Note 1:
Shaded pins are 5V tolerant.
100-PIN TQFP (TOP VIEW)
PIC32MX664F128L
PIC32MX675F256L
PIC32MX695F512L
PIC32MX675F512L
PIC32MX664F064L
1
100
PIC32MX5XX/6XX/7XX
DS60001156J-page 12 2009-2016 Microchip Technology Inc.
TABLE 9: PIN NAMES FOR 100-PIN USB, ETHERNET, AND CAN DEVICES
Pin # Full P in Name Pin # Full Pin Name
1 AERXERR/RG15 36 V
SS
2V
DD
37 V
DD
3PMD5/RE5 38 TCK/RA1
4PMD6/RE6 39 AC1TX/SCK4/U5TX/U2RTS/RF13
5PMD7/RE7 40 AC1RX/SS4/U5RX/U2CTS/RF12
6 T2CK/RC1 41 AN12/ERXD0/AECRS/PMA11/RB12
7 T3CK/AC2TX
(1)
/RC2 42 AN13/ERXD1/AECOL/PMA10/RB13
8 T4CK/AC2RX
(1)
/RC3 43 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
9 T5CK/SDI1/RC4 44 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
10 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 45 V
SS
11 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 46 V
DD
12
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8
47 AETXD0/SS3/U4RX/U1CTS/CN20/RD14
13 MCLR 48 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
14 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 49 SDA5/SDI4/U2RX/PMA9/CN17/RF4
15 V
SS
50 SCL5/SDO4/U2TX/PMA8/CN18/RF5
16 V
DD
51 USBID/RF3
17 TMS/RA0 52 SDA3/SDI3/U1RX/RF2
18 AERXD0/INT1/RE8 53 SCL3/SDO3/U1TX/RF8
19 AERXD1/INT2/RE9 54 V
BUS
20 AN5/C1IN+/V
BUSON
/CN7/RB5 55 V
USB
3
V
3
21 AN4/C1IN-/CN6/RB4 56 D-/RG3
22 AN3/C2IN+/CN5/RB3 57 D+/RG2
23 AN2/C2IN-/CN4/RB2 58 SCL2/RA2
24 PGEC1/AN1/CN3/RB1 59 SDA2/RA3
25 PGED1/AN0/CN2/RB0 60 TDI/RA4
26 PGEC2/AN6/OCFA/RB6 61 TDO/RA5
27 PGED2/AN7/RB7 62 V
DD
28 V
REF
-/CV
REF
-/AERXD2/PMA7/RA9 63 OSC1/CLKI/RC12
29 V
REF
+/CV
REF
+/AERXD3/PMA6/RA10 64 OSC2/CLKO/RC15
30 AV
DD
65 V
SS
31 AV
SS
66 AETXCLK/SCL1/INT3/RA14
32 AN8/C1OUT/RB8 67 AETXEN/SDA1/INT4/RA15
33 AN9/C2OUT/RB9 68 RTCC/EMDIO/AEMDIO/IC1/RD8
34 AN10/CV
REFOUT
/PMA13/RB10 69
SS1/
IC2
/
RD9
35 AN11/ERXERR/AETXERR/PMA12/RB11 70 SCK1/IC3/PMCS2/PMA15/RD10
Note 1:
This pin is not available on PIC32MX764F128L devices.
2:
Shaded pins are 5V tolerant.
100-PIN TQFP (TOP VIEW)
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
PIC32MX764F128L
1
100
2009-2016 Microchip Technology Inc. DS60001156J- page 13
PIC32MX5XX/6XX/7XX
71
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
86 V
DD
72 SDO1/OC1/INT0/RD0 87 C1RX/ETXD1/PMD11/RF0
73 SOSCI/CN1/RC13 88 C1TX/ETXD0/PMD10/RF1
74 SOSCO/T1CK/CN0/RC14 89 C2TX
(1)
/ETXERR/PMD9/RG1
75 V
SS
90 C2RX
(1)
/PMD8/RG0
76 OC2/RD1 91 TRCLK/RA6
77 OC3/RD2 92 TRD3/RA7
78 OC4/RD3 93 PMD0/RE0
79 ETXD2/IC5/PMD12/RD12 94 PMD1/RE1
80 ETXD3/PMD13/CN19/RD13 95 TRD2/RG14
81 OC5/PMWR/CN13/RD4 96 TRD1/RG12
82 PMRD/CN14/RD5 97 TRD0/RG13
83 ETXEN/PMD14/CN15/RD6 98 PMD2/RE2
84 ETXCLK/PMD15/CN16/RD7 99 PMD3/RE3
85 V
CAP
/V
DDCORE
100 PMD4/RE4
TABLE 9: PIN NAMES FOR 100-PIN USB, ETHERNET, AND CAN DEVICES (CONTINUED)
Pin # Full P in Name Pin # Full Pin Name
Note 1:
This pin is not available on PIC32MX764F128L devices.
2:
Shaded pins are 5V tolerant.
100-PIN TQFP (TOP VIEW)
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
PIC32MX764F128L
1
100
PIC32MX5XX/6XX/7XX
DS60001156J-page 14 2009-2016 Microchip Technology Inc.
TABLE 10: PIN NAMES FOR USB AND CAN DEVICES
Pin # Full Pin Name Pin # Full Pin Name
A1 PMD4/RE4 E2 T4CK/RC3
A2 PMD3/RE3 E3 SCK2/U6TXU6TX/U3RTS/PMA5/CN8/RG6
A3 TRD0/RG13 E4 T3CK/RC2
A4 PMD0/RE0 E5 V
DD
A5 PMD8/RG0 E6 PMD9/RG1
A6 C1TX/PMD10/RF1 E7 V
SS
A7 V
DD
E8 SDA1/INT4/RA15
A8 V
SS
E9 RTCC/IC1/RD8
A9 IC5/PMD12/RD12 E10 SS1/IC2/RD9
A10 OC3/RD2 E11 SCL1/INT3/RA14
A11 OC2/RD1 F1 MCLR
B1 No Connect (NC) F2 SCL4/SDO2/U3TX/PMA3/CN10/RG8
B2 RG15 F3 SS2/U6RX/U3CTS/PMA2/CN11/RG9
B3 PMD2/RE2 F4 SDA4/SDI2/U3RX/PMA4/CN9/RG7
B4 PMD1/RE1 F5 V
SS
B5 TRD3/RA7 F6 No Connect (NC)
B6 C1RX/PMD11/RF0 F7 No Connect (NC)
B7 V
CAP
F8 V
DD
B8 PMRD/CN14/RD5 F9 OSC1/CLKI/RC12
B9 OC4/RD3 F10 V
SS
B10 V
SS
F11 OSC2/CLKO/RC15
B11 SOSCO/T1CK/CN0/RC14 G1 INT1/RE8
C1 PMD6/RE6 G2 INT2/RE9
C2 V
DD
G3 TMS/RA0
C3 TRD1/RG12 G4 No Connect (NC)
C4 TRD2/RG14 G5 V
DD
C5 TRCLK/RA6 G6 V
SS
C6 No Connect (NC) G7 V
SS
C7 PMD15/CN16/RD7 G8 No Connect (NC)
C8 OC5/PMWR/CN13/RD4 G9 TDO/RA5
C9 V
DD
G10 SDA2/RA3
C10 SOSCI/CN1/RC13 G11 TDI/RA4
C11 IC4/PMCS1/PMA14/RD11 H1 AN5/C1IN+/V
BUSON
/CN7/RB5
D1 T2CK/RC1 H2 AN4/C1IN-/CN6/RB4
D2 PMD7/RE7 H3 V
SS
D3 PMD5/RE5 H4 V
DD
D4 V
SS
H5 No Connect (NC)
D5 V
SS
H6 V
DD
D6 No Connect (NC) H7 No Connect (NC)
D7 PMD14/CN15/RD6 H8 V
BUS
D8 PMD13/CN19/RD13 H9 V
USB
3
V
3
D9 SDO1/OC1/INT0/RD0 H10 D+/RG2
D10 No Connect (NC) H11 SCL2/RA2
D11 SCK1/IC3/PMCS2/PMA15/RD10 J1 AN3/C2IN+/CN5/RB3
E1 T5CK/SDI1/RC4 J2 AN2/C2IN-/CN4/RB2
Note 1:
Shaded pins are 5V tolerant.
121-PIN TFBGA (BOTTOM VI EW)
PIC32MX534F064L
PIC32MX564F064L
PIC32MX564F128L
PIC32MX575F256L
PIC32MX575F512L
A1
L1
L11
A11
Note: The T FBG A package skips from row “H” to row “J” and has no “I” row.
2009-2016 Microchip Technology Inc. DS60001156J- page 15
PIC32MX5XX/6XX/7XX
J3 PGED2/AN7/RB7 K8 V
DD
J4 AV
DD
K9 SCK3/U4TX/U1RTS/CN21/RD15
J5 AN11/PMA12/RB11 K10 USBID/RF3
J6 TCK/RA1 K11 SDA3/SDI3/U1RX/RF2
J7 AN12/PMA11/RB12 L1 PGEC2/AN6/OCFA/RB6
J8 No Connect (NC) L2 V
REF
-/CV
REF
-/PMA7/RA9
J9 No Connect (NC) L3 AV
SS
J10 SCL3/SDO3/U1TX/RF8 L4 AN9/C2OUT/RB9
J11 D-/RG3 L5 AN10/CV
REFOUT
/PMA13/RB10
K1 PGEC1/AN1/CN3/RB1 L6 AC1TX/SCK4/U5TX/U2RTS/RF13
K2 PGED1/AN0/CN2/RB0 L7 AN13/PMA10/RB13
K3 V
REF
+/CV
REF
+/PMA6/RA10 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15
K4 AN8/C1OUT/RB8 L9 SS3/U4RX/U1CTS/CN20/RD14
K5 No Connect (NC) L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4
K6 AC1RX/SS4/U5RX/U2CTS/RF12 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5
K7 AN14/PMALH/PMA1/RB14
TABLE 10: PIN NAMES (CONTINUED)FOR USB AND CAN DEVICES
Pin # Full Pin Name Pin # Full Pin Name
Note 1:
Shaded pins are 5V tolerant.
121-PIN TFBGA (BOTTOM VI EW)
PIC32MX534F064L
PIC32MX564F064L
PIC32MX564F128L
PIC32MX575F256L
PIC32MX575F512L
A1
L1
L11
A11
Note: The T FBG A package skips from row “H” to row “J” and has no “I” row.
PIC32MX5XX/6XX/7XX
DS60001156J-page 16 2009-2016 Microchip Technology Inc.
TABLE 11: PIN NAMES FOR USB AND ETHERNET DEVICES
Pin # Ful l Pin Name Pin # Full Pin Name
A1 PMD4/RE4 E2 T4CK/RC3
A2 PMD3/RE3 E3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
A3 TRD0/RG13 E4 T3CK/RC2
A4 PMD0/RE0 E5 V
DD
A5 PMD8/RG0 E6 ETXERR/PMD9/RG1
A6 ETXD0/PMD10/RF1 E7 V
SS
A7 V
DD
E8 AETXEN/SDA1/INT4/RA15
A8 V
SS
E9 RTCC/EMDIO/AEMDIO/IC1/RD8
A9 ETXD2/IC5/PMD12/RD12 E10 SS1/IC2/RD9
A10 OC3/RD2 E11 AETXCLK/SCL1/INT3/RA14
A11 OC2/RD1 F1 MCLR
B1 No Connect (NC) F2 ERXDV/AERXDV/ECRSDV/AECRSDV//SCL4/SDO2/U3TX/PMA3/CN10/RG8
B2 AERXERR/RG15 F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
B3 PMD2/RE2 F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
B4 PMD1/RE1 F5 V
SS
B5 TRD3/RA7 F6 No Connect (NC)
B6 ETXD1/PMD11/RF0 F7 No Connect (NC)
B7 V
CAP
F8 V
DD
B8 PMRD/CN14/RD5 F9 OSC1/CLKI/RC12
B9 OC4/RD3 F10 V
SS
B10 V
SS
F11 OSC2/CLKO/RC15
B11 SOSCO/T1CK/CN0/RC14 G1 AERXD0/INT1/RE8
C1 PMD6/RE6 G2 AERXD1/INT2/RE9
C2 V
DD
G3 TMS/RA0
C3 TRD1/RG12 G4 No Connect (NC)
C4 TRD2/RG14 G5 V
DD
C5 TRCLK/RA6 G6 V
SS
C6 No Connect (NC) G7 V
SS
C7 ETXCLK/PMD15/CN16/RD7 G8 No Connect (NC)
C8 OC5/PMWR/CN13/RD4 G9 TDO/RA5
C9 V
DD
G10 SDA2/RA3
C10 SOSCI/CN1/RC13 G11 TDI/RA4
C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H1 AN5/C1IN+/V
BUSON
/CN7/RB5
D1 T2CK/RC1 H2 AN4/C1IN-/CN6/RB4
D2 PMD7/RE7 H3 V
SS
D3 PMD5/RE5 H4 V
DD
D4 V
SS
H5 No Connect (NC)
D5 V
SS
H6 V
DD
D6 No Connect (NC) H7 No Connect (NC)
D7 ETXEN/PMD14/CN15/RD6 H8 V
BUS
D8 ETXD3/PMD13/CN19/RD13 H9 V
USB
3
V
3
D9 SDO1/OC1/INT0/RD0 H10 D+/RG2
D10 No Connect (NC) H11 SCL2/RA2
D11 SCK1/IC3/PMCS2/PMA15/RD10 J1 AN3/C2IN+/CN5/RB3
E1 T5CK/SDI1/RC4 J2 AN2/C2IN-/CN4/RB2
Note 1:
Shaded pins are 5V tolerant.
121-PIN TFBGA (BOTTOM VI EW)
PIC32MX664F064L
PIC32MX664F128L
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L
A1
L1
L11
A11
Note: The TFBGA package skips from row “H” to row “J” and has no “I” row.
2009-2016 Microchip Technology Inc. DS60001156J- page 17
PIC32MX5XX/6XX/7XX
J3 PGED2/AN7/RB7 K8 V
DD
J4 AV
DD
K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
J5 AN11/ERXERR/AETXERR/PMA12/RB11 K10 USBID/RF3
J6 TCK/RA1 K11 SDA3/SDI3/U1RX/RF2
J7 AN12/ERXD0/AECRS/PMA11/RB12 L1 PGEC2/AN6/OCFA/RB6
J8 No Connect (NC) L2 V
REF
-/CV
REF
-/AERXD2/PMA7/RA9
J9 No Connect (NC) L3 AV
SS
J10 SCL3/SDO3/U1TX/RF8 L4 AN9/C2OUT/RB9
J11 D-/RG3 L5 AN10/CV
REFOUT
/PMA13/RB10
K1 PGEC1/AN1/CN3/RB1 L6 SCK4/U5TX/U2RTS/RF13
K2 PGED1/AN0/CN2/RB0 L7 AN13/ERXD1/AECOL/PMA10/RB13
K3 V
REF
+/CV
REF
+/AERXD3/PMA6/RA10 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
K4 AN8/C1OUT/RB8 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14
K5 No Connect (NC) L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4
K6 SS4/U5RX/U2CTS/RF12 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5
K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
TABLE 11: PIN NAMES FOR USB AND ETHERNET DEVICES (CONTINUED)
Pin # Ful l Pin Name Pin # Full Pin Name
Note 1:
Shaded pins are 5V tolerant.
121-PIN TFBGA (BOTTOM VI EW)
PIC32MX664F064L
PIC32MX664F128L
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L
A1
L1
L11
A11
Note: The TFBGA package skips from row “H” to row “J” and has no “I” row.
PIC32MX5XX/6XX/7XX
DS60001156J-page 18 2009-2016 Microchip Technology Inc.
TABLE 12: PIN NAMES FOR USB, ETHERNET, AND CAN DEVICES
Pin # Full Pin Name Pin # Full Pin Name
A1 PMD4/RE4 E2 T4CK/AC2RX
(1)
/RC3
A2 PMD3/RE3 E3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
A3 TRD0/RG13 E4 T3CK/AC2TX
(1)
/RC2
A4 PMD0/RE0 E5 V
DD
A5 C2RX
(1)
/PMD8/RG0 E6 C2TX
(1)
/ETXERR/PMD9/RG1
A6 C1TX/ETXD0/PMD10/RF1 E7 V
SS
A7 V
DD
E8 AETXEN/SDA1/INT4/RA15
A8 V
SS
E9 RTCC/EMDIO/AEMDIO/IC1/RD8
A9 ETXD2/IC5/PMD12/RD12 E10 SS1/IC2/RD9
A10 OC3/RD2 E11 AETXCLK/SCL1/INT3/RA14
A11 OC2/RD1 F1 MCLR
B1 No Connect (NC) F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8
B2 AERXERR/RG15 F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
B3 PMD2/RE2 F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
B4 PMD1/RE1 F5 V
SS
B5 TRD3/RA7 F6 No Connect (NC)
B6 C1RX/ETXD1/PMD11/RF0 F7 No Connect (NC)
B7 V
CAP
F8 V
DD
B8 PMRD/CN14/RD5 F9 OSC1/CLKI/RC12
B9 OC4/RD3 F10 V
SS
B10 V
SS
F11 OSC2/CLKO/RC15
B11 SOSCO/T1CK/CN0/RC14 G1 AERXD0/INT1/RE8
C1 PMD6/RE6 G2 AERXD1/INT2/RE9
C2 V
DD
G3 TMS/RA0
C3 TRD1/RG12 G4 No Conn ect (NC)
C4 TRD2/RG14 G5 V
DD
C5 TRCLK/RA6 G6 V
SS
C6 No Connect (NC) G7 V
SS
C7 ETXCLK/PMD15/CN16/RD7 G8 No Connect (NC)
C8 OC5/PMWR/CN13/RD4 G9 TDO/RA5
C9 V
DD
G10 SDA2/RA3
C10 SOSCI/CN1/RC13 G11 TDI/RA4
C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H1 AN5/C1IN+/V
BUSON
/CN7/RB5
D1 T2CK/RC1 H2 AN4/C1IN-/CN6/RB4
D2 PMD7/RE7 H3 V
SS
D3 PMD5/RE5 H4 V
DD
D4 V
SS
H5 No Connect (NC)
D5 V
SS
H6 V
DD
D6 No Connect (NC) H7 No Connect (NC)
D7 ETXEN/PMD14/CN15/RD6 H8 V
BUS
D8 ETXD3/PMD13/CN19/RD13 H9 V
USB
3
V
3
D9 SDO1/OC1/INT0/RD0 H10 D+/RG2
D10 No Connect (NC) H11 SCL2/RA2
D11 SCK1/IC3/PMCS2/PMA15/RD10 J1 AN3/C2IN+/CN5/RB3
E1 T5CK/SDI1/RC4 J2 AN2/C2IN-/CN4/RB2
Note 1:
This pin is not available on PIC32MX764F128L devices.
2:
Shaded pins are 5V tolerant.
121-PIN TFBGA (BOTTOM VI EW)
PIC32MX764F128L
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
A1
L1
L11
A11
Note: The TFBGA package skips from row “H” to row “J” and has no “I” row.
2009-2016 Microchip Technology Inc. DS60001156J- page 19
PIC32MX5XX/6XX/7XX
J3 PGED2/AN7/RB7 K8 V
DD
J4 AV
DD
K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
J5 AN11/ERXERR/AETXERR/PMA12/RB11 K10 USBID/RF3
J6 TCK/RA1 K11 SDA3/SDI3/U1RX/RF2
J7 AN12/ERXD0/AECRS/PMA11/RB12 L1 PGEC2/AN6/OCFA/RB6
J8 No Connect (NC) L2 V
REF
-/CV
REF
-/AERXD2/PMA7/RA9
J9 No Connect (NC) L3 AV
SS
J10 SCL3/SDO3/U1TX/RF8 L4 AN9/C2OUT/RB9
J11 D-/RG3 L5 AN10/CV
REFOUT
/PMA13/RB10
K1 PGEC1/AN1/CN3/RB1 L6 AC1TX/SCK4/U5TX/U2RTS/RF13
K2 PGED1/AN0/CN2/RB0 L7 AN13/ERXD1/AECOL/PMA10/RB13
K3 V
REF
+/CV
REF
+/AERXD3/PMA6/RA10 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
K4 AN8/C1OUT/RB8 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14
K5 No Connect (NC) L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4
K6 AC1RX/SS4/U5RX/U2CTS/RF12 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5
K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
TABLE 12: PIN NAMES FOR USB, ETHERNET, AND CAN DEVICES (CONTINUED)
Pin # Full Pin Name Pin # Full Pin Name
Note 1:
This pin is not available on PIC32MX764F128L devices.
2:
Shaded pins are 5V tolerant.
121-PIN TFBGA (BOTTOM VI EW)
PIC32MX764F128L
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
A1
L1
L11
A11
Note: The TFBGA package skips from row “H” to row “J” and has no “I” row.
PIC32MX5XX/6XX/7XX
DS60001156J-page 20 2009-2016 Microchip Technology Inc.
TABLE 13: PIN NAMES FOR 124-PIN USB, ETHERNET, AND CAN DEVICES
Package
Bump # Full Pin Name Package
Bump # Full Pin Name
A1 No Connect (NC) A38 D-/RG3
A2 AERXERR/RG15 A39 SCL2/RA2
A3 V
SS
A40 TDI/RA4
A4 PMD6/RE6 A41 V
DD
A5 T2CK/RC1 A42 OSC2/CLKO/RC15
A6 T4CK/AC2RX
(1)
/RC3 A43 V
SS
A7 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 A44 AETXEN/SDA1/INT4/RA15
A8 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 A45 SS1/IC2/RD9
A9 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 A46 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
A10 V
DD
A47 SOSCI/CN1/RC13
A11 AERXD0/INT1/RE8 A48 V
DD
A12 AN5/C1IN+/VBUSON/CN7/RB5 A49 No Connect (NC)
A13 AN3/C2IN+/CN5/RB3 A50 No Connect (NC)
A14 V
DD
A51 No Connect (NC)
A15 PGEC1/AN1/CN3/RB1 A52 OC2/RD1
A16 No Connect (NC) A53 OC4/RD3
A17 No Connect (NC) A54 ETXD3/PMD13/CN19/RD13
A18 No Connect (NC) A55 PMRD/CN14/RD5
A19 No Connect (NC) A56 ETXCLK/PMD15/CN16/RD7
A20 PGEC2/AN6/OCFA/RB6 A57 No Connect (NC)
A21 V
REF
-/CV
REF
-/AERXD2/PMA7/RA9 A58 No Connect (NC)
A22 AV
DD
A59 V
DD
A23 AN8/C1OUT/RB8 A60 C1TX/ETXD0/PMD10/RF1
A24 AN10/CV
REFOUT
/PMA13/RB10 A61 C2RX
(1)
/PMD8/RG0
A25 V
SS
A62 TRD3/RA7
A26 TCK/RA1 A63 V
SS
A27 AC1RX
(1)
/SS4/U5RX/U2CTS/RF12 A64 PMD1/RE1
A28 AN13/ERXD1/AECOL/PMA10/RB13 A65 TRD1/RG12
A29 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 A66 PMD2/RE2
A30 V
DD
A67 PMD4/RE4
A31 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 A68 No Connect (NC)
A32 SCL5/SDO4/U2TX/PMA8/CN18/RF5 B1 V
DD
A33 No Connect (NC) B2 PMD5/RE5
A34 No Connect (NC) B3 PMD7/RE7
A35 USBID/RF3 B4 T3CK/AC2TX
(1)
/RC2
A36 SDA3/SDI3/U1RX/RF2 B5 T5CK/SDI1/RC4
A37 V
BUS
B6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
B7 MCLR B32 SDA2/RA3
Note 1:
This pin is only available on PIC32MX795F512L devices.
2:
Shaded package bumps are 5V tolerant.
3:
It is recommended that the user connect the printed circuit board (PCB) ground to the conductive thermal pad on the bottom of the
package. And to not run non-Vss PCB traces under the conductive thermal pad on the same side of the PCB layout.
A1
A68
A17 B29
B13
B41
B1
A34
A51
B56
124-PIN VTLA (BOTTOM VIEW)
(2,3)
Pola rit y In dicato r
PIC32MX675F512L
PIC32MX695F512L
PIC32MX795F512L
Conductive
Thermal Pad
2009-2016 Microchip Technology Inc. DS60001156J- page 21
PIC32MX5XX/6XX/7XX
B8 V
SS
B33 TDO/RA5
B9 TMS/RA0 B34 OSC1/CLKI/RC12
B10 AERXD1/INT2/RE9 B35 No Connect (NC)
B11 AN4/C1IN-/CN6/RB4 B36 AETXCLK/SCL1/INT3/RA14
B12 V
SS
B37 RTCC/EMDIO/AEMDIO/IC1/RD8
B13 AN2/C2IN-/CN4/RB2 B38 SCK1/IC3/PMCS2/PMA15/RD10
B14 PGED1/AN0/CN2/RB0 B39 SDO1/OC1/INT0/RD0
B15 No Connect (NC) B40 SOSCO/T1CK/CN0/RC14
B16 PGED2/AN7/RB7 B41 V
SS
B17 V
REF
+/CV
REF
+/AERXD3/PMA6/RA10 B42 OC3/RD2
B18 AV
SS
B43 ETXD2/IC5/PMD12/RD12
B19 AN9/C2OUT/RB9 B44 OC5/PMWR/CN13/RD4
B20 AN11/ERXERR/AETXERR/PMA12/RB11 B45 ETXEN/PMD14/CN15/RD6
B21 V
DD
B46 V
SS
B22 AC1TX/SCK4/U5TX/U2RTS/RF13 B47 No Connect (NC)
B23 AN12/ERXD0/AECRS/PMA11/RB12 B48 V
CAP
B24 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 B49 C1RX
(1)
/ETXD1/PMD11/RF0
B25 V
SS
B50 C2TX
(1)
/ETXERR/PMD9/RG1
B26 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 B51 TRCLK/RA6
B27 SDA5/SDI4/U2RX/PMA9/CN17/RF4 B52 PMD0/RE0
B28 No Connect (NC) B53 V
DD
B29 SCL3/SDO3/U1TX/RF8 B54 TRD2/RG14
B30 V
USB
3
V
3
B55 TRD0/RG13
B31 D+/RG2 B56 PMD3/RE3
TABLE 13: PIN NAMES FOR 124-PIN USB, ETHERNET, AND CAN DEVICES (CONTINUED)
Package
Bump # Full Pin Name Package
Bump # Full Pin Name
Note 1:
This pin is only available on PIC32MX795F512L devices.
2:
Shaded package bumps are 5V tolerant.
3:
It is recommended that the user connect the printed circuit board (PCB) ground to the conductive thermal pad on the bottom of the
package. And to not run non-Vss PCB traces under the conductive thermal pad on the same side of the PCB layout.
A1
A68
A17 B29
B13
B41
B1
A34
A51
B56
124-PIN VTLA (BOTTOM VIEW)
(2,3)
Pola rit y In dicato r
PIC32MX675F512L
PIC32MX695F512L
PIC32MX795F512L
Conductive
Thermal Pad
PIC32MX5XX/6XX/7XX
DS60001156J-page 22 2009-2016 Microchip Technology Inc.
Table of C ontents
1.0 Device Overview ........................................................................................................................................................................ 25
2.0 Gui delines for Getting Started with 32-bi t MCU s......... ................... .......... ................... ........... .................................................... 37
3.0 CPU............................................................................................................................................................................................ 41
4.0 Memory Organizati on................................................................................................................................................................. 47
5.0 Flash Program Memory........... ................... ........... .................. ................... ........... ..................................................................... 63
6.0 Resets ........................................................................................................................................................................................ 69
7.0 Inte rrupt Controller ............................................. ........... ................... .......... ................................................................................ 73
8.0 Oscillator Configuration.............................................................................................................................................................. 95
9.0 Pre fe tch Cache........................ ........... ................... ..................................... .............................................................................. 101
10.0 Direct Memory Access (DMA) Cont roller ............................................. ........... .................. ........... ............................................ 111
11.0 USB On-The-Go (OTG)....... .......... ................... ........... ................... .......................................................................................... 133
12.0 I/O Ports ... ................... .......... ................... ................... ...................................... ....................................................................... 157
13.0 Timer1 ...................................................................................................................................................................................... 167
14.0 Tim er2/3, Timer4/5................................................................................................................................................................... 171
15.0 Watchdog Timer (WDT) ............................... ...... ......... ...... .... ........... .... .... ............. .... .... .... ....................................................... 177
16.0 Input Capture....................... .... .... .. ......... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......... .... .. ............................................................... 181
17.0 Output Compare....................................... ...................................... .......................................................................................... 185
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 189
19.0 Inter-Integrated Circuit (I
2
C)..................................................................................................................................................... 195
20.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 203
21.0 P a rallel Maste r Port (PM P).............................................. ........... .............................................................................................. 211
22.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 221
23.0 10-bit Analog- to-Digital Converter (A DC)................................................................................................................................. 231
24.0 Co n troller Area Ne tw o rk (CAN)........ .................. ........... ................... ................... .......... ........................................................... 241
25.0 E th e rnet Controller................ ................... .......... ................... ........... ................... ..................................................................... 279
26.0 Comparator .............................................................................................................................................................................. 323
27.0 Comparator Voltage Reference (CV
REF
).................................................................................................................................. 327
28.0 P o w e r- Saving Features .... ................... .......... ................... ........... ................... ......................................................................... 331
29.0 Special Features ...................................................................................................................................................................... 333
30.0 Instruction Set .......................................................................................................................................................................... 345
31.0 Development Support............................................................................................................................................................... 347
32.0 Electrical Characteristics.......................................................................................................................................................... 351
33.0 DC and AC Device Characteristics Graphs............................. ................. ................. ........ ....................................................... 399
34.0 P a ck a g i n g In fo rmation..... ...................................... .......... ................... .......... ................... ......................................................... 401
The Microchip Web Site..... ................... ................... ................... ................... ........... ......................................................................... 437
Customer Change Notification Service .............................................................................................................................................. 437
Customer Support.............................................................................................................................................................................. 437
Product Ide ntification System............................................................................................................................................................. 438
2009-2016 Microchip Technology Inc. DS60001156J- page 23
PIC32MX5XX/6XX/7XX
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of
your Mic rochi p produ cts . To this e nd, we will co ntinue to impro ve our p ublic ations to bette r suit y our nee ds. Ou r pub-
lications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications
Depart ment vi a E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data
sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
To obtain the most up -to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determ ine th e ver sion of a d at a sh eet by exa mining i t s litera ture nu mb er foun d on the bo ttom o uts ide c orner
of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of
docu me nt DS3 00 000 00).
Errata
An errata sheet, des c ribi ng mi nor operational differences from th e d ata sheet an d re com m end ed w ork arou nds , m ay
exist f or c urren t devices. As d ev ice /do cu me nt a tion issues becom e k no w n to us , w e wi ll publish an errat a sh eet. The
errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please chec k with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature
number) you are using.
Customer No tific atio n Syst em
Register on our web site at www.microchip.com to receive the most current information on all of our products.
PIC32MX5XX/6XX/7XX
DS60001156J-page 24 2009-2016 Microchip Technology Inc.
Referenced Sources
This device data sheet is based on the following
individual chapters of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
•Section 1. “Introduction” (DS60001127)
•Section 2. “CPU” (DS60001113)
•Section 4. “Prefetch C ach e” (DS60001119)
•Section 3. “Memory Organization” (DS60001115)
•Section 5. “Flash Program Memory” (DS60001121)
•Section 6. “Oscillator Configuration” (DS60001112)
•Section 7. “Resets” (DS60001118)
•Section 8. “Interrupt Controller” (DS60001108)
•Section 9. “Watchdog Timer and Power-up Timer (DS60001114)
•Section 10. “Power-Saving Features” (DS60001130)
•Section 12. “I/O Ports” (DS60001120)
•Section 13. “Parallel Master Port (PMP)” (DS60001128)
•Section 14. “Tim ers” (DS60001105)
•Section 15. “Input Capture” (DS60001122)
•Section 16. “Output Capture” (DS60001111)
•Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104)
•Section 19. “Comparator” (DS60001110)
•Section 20. “Comparator Voltage Reference (CV
REF
)” (DS60001109)
•Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107)
•Section 23. “Serial Peripheral Interface (SPI)” (DS600 01106)
•Section 24. “Inter-Integrated Circuit (I2C)” (DS60001116)
•Section 27. “USB On-The-Go (OTG)” (DS60001126)
•Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
•Section 31. “Direct Memory Access (DMA) Controller” (DS60001117)
•Section 32. “Configuration” (DS60001124)
•Section 33. “Programming and Diagnostics” (DS60001129)
•Section 34. “Controller Area Network (CAN)” (DS60001154)
•Section 35. “Ethernet Controller” (DS60001155)
Note 1: To access the documents listed below,
browse to the documentation section of
the PIC32MX795F512L product page on
the Microchip web site
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
2009-2016 Microchip Technology Inc. DS60001156J- page 25
PIC32MX5XX/6XX/7XX
1.0 DEVICE OVERVIEW
This document contains device-specific information for
PIC32MX5XX/6 XX/7XX dev ices .
Figure 1-1 illustrates a general block diagram of the
core an d peripher al modul es in th e PIC32M X5XX/6XX/
7XX family of devices.
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
FIGURE 1-1: BLOCK DIAGRAM
(1,2)
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the documents listed in the
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
Note 1:
Some features are not available on all devices.
2:
BOR functionality is provided when the on-board voltage regulator is enabled.
UART1-6
Comparators
PORTA
PORTD
PORTE
PORTF
PORTG
PORTB
CN1-22
JTAG Priority
DMAC
ICD
MIPS32
®
M4K
®
IS DS
EJTAG INT
Bus Matrix
Prefetch Data RAM Peripheral Bridge
128
128-bit Wide
Flash
32
32 32 32 32
Peripheral Bus Clocked by PBCLK
Program Flash Memory
Controller
32
Module
32 32
Interrupt
Controller
BSCAN
PORTC
PMP
I2C1-5
SPI1-4
IC1-5
PWM
OC1-5
OSC1/CLKI
OSC2/CLKO V
DD
, V
SS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Precision
Reference
Band Gap
FRC/LPRC
Oscillators Regulator
Voltage
V
CAP
OSC/S
OSC
Oscillators
PLL
Dividers
SYSCLK
PBCLK
Peripheral Bus Clocked by SYSCLK
USB
PLL-USB USBCLK
32
RTCC
10-bit ADC
Timer1-5
32
32
CAN1, CAN2
ETHERNET
32 32
CPU Core
PIC32MX5XX/6XX/7XX
DS60001156J-page 26 2009-2016 Microchip Technology Inc.
TABLE 1-1: PINOU T I/O DESCRI PTIONS
Pin Name Pin Number
(1)
Pin
Type Buffer
Type Description
64-Pin
QFN/TQFP 100-Pin
TQFP 121-Pin
TFBGA 124-pin
VTLA
AN0 16 25 K2 B14 I Analog Analog input channels
AN1 15 24 K1 A15 I Analog
AN2 14 23 J2 B13 I Analog
AN3 13 22 J1 A13 I Analog
AN4 12 21 H2 B11 I Analog
AN5 11 20 H1 A12 I Analog
AN6 17 26 L1 A20 I Analog
AN7 18 27 J3 B16 I Analog
AN8 21 32 K4 A23 I Analog
AN9 22 33 L4 B19 I Analog
AN10 23 34 L5 A24 I Analog
AN11 24 35 J5 B20 I Analog
AN12 27 41 J7 B23 I Analog
AN13 28 42 L7 A28 I Analog
AN14 29 43 K7 B24 I Analog
AN15 30 44 L8 A29 I Analog
CLKI 39 63 F9 B34 I ST/
CMOS External clock source input. Always
assoc ia ted with OSC 1 pin func tion .
CLKO 40 64 F11 A42 O —
Osci lla tor cry st a l outp ut. Co nn ects to
cryst a l or re sonato r i n Cry st al Os cill ator
mode. Optionally functions as CLKO in
RC and EC modes. Always associated
with OSC2 pin function.
OSC1 39 63 F9 B34 I ST/
CMOS
Oscillator crystal input. ST buffer when
configured in RC mode; CMOS
otherwise.
OSC2 40 64 F11 A42 I/O —
Osci lla tor cry st a l outp ut. Co nn ects to
cryst a l or re sonato r i n Cry st al Os cill ator
mode. Optionally functions as CLKO in
RC and EC modes.
SOSCI 47 73 C10 A47 I ST/
CMOS 32.768 kHz low -power oscilla tor cr y stal
input; CMOS otherwise
SOSCO 48 74 B11 B40 O — 32.7 68 kHz low -power oscilla tor cr y stal
output
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin nu mbers are only provide d for refer ence. Se e the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
2009-2016 Microchip Technology Inc. DS60001156J- page 27
PIC32MX5XX/6XX/7XX
CN0 48 74 B11 B40 I ST Change notification inputs. Can be
sof tware programm ed for interna l weak
pull-ups on all inpu ts.
CN1 47 73 C10 A47 I ST
CN2 16 25 K2 B14 I ST
CN3 15 24 K1 A15 I ST
CN4 14 23 J2 B13 I ST
CN5 13 22 J1 A13 I ST
CN6 12 21 H2 B11 I ST
CN7 11 20 H1 A12 I ST
CN8 4 10 E3 A7 I ST
CN9 5 11 F4 B6 I ST
CN10 6 12 F2 A8 I ST
CN11 8 14 F3 A9 I ST
CN12 30 44 L8 A29 I ST
CN13 52 81 C8 B44 I ST
CN14 53 82 B8 A55 I ST
CN15 54 83 D7 B45 I ST
CN16 55 84 C7 A56 I ST
CN17 31 49 L10 B27 I ST
CN18 32 50 L11 A32 I ST
CN19 — 80 D8 A54 I ST
CN20 — 47 L9 B26 I ST
CN21 — 48 K9 A31 I ST
IC1 42 68 E9 B37 I ST Capture Inputs 1-5
IC2 43 69 E10 A45 I ST
IC3 44 70 D11 B38 I ST
IC4 45 71 C11 A46 I ST
IC5 52 79 A9 A60 I ST
OCFA 17 26 L1 A20 I ST Output Compare Fault A Inpu t
OC1 46 72 D9 B39 O — Output Compare Output 1
OC2 49 76 A11 A52 O — Output Compare Output 2
OC3 50 77 A10 B42 O — Output Compare Output 3
OC4 51 78 B9 A53 O — Output Compare Output 4
OC5 52 81 C8 B44 O — Output Compare Output 5
OCFB 30 44 L8 A29 I ST Output Compare Fault B Input
INT0 46 72 D9 B39 I ST External Interrupt 0
INT1 42 18 G1 A11 I ST External Interrupt 1
INT2 43 19 G2 B10 I ST External Inte rrupt 2
INT3 44 66 E11 B 36 I ST Exter nal Interrupt 3
INT4 45 67 E8 A44 I ST External Interrupt 4
TABLE 1-1: PINOU T I/O DESCRI PTIONS (CONTINUED)
Pin Name Pin Number
(1)
Pin
Type Buffer
Type Description
64-Pin
QFN/TQFP 100-Pin
TQFP 121-Pin
TFBGA 124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin nu mbers are only provided for reference. See th e “Device Pin Tables ” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 28 2009-2016 Microchip Technology Inc.
RA0 — 17 G3 B9 I/O ST PORTA is a bidirectional I/O port
RA1 — 38 J6 A26 I/O ST
RA2 — 58 H11 A39 I/O ST
RA3 — 59 G10 B32 I/O ST
RA4 — 60 G11 A40 I/O ST
RA5 — 61 G9 B33 I/O ST
RA6 — 91 C5 B51 I/O ST
RA7 — 92 B5 A62 I/O ST
RA9 — 28 L2 A21 I/O ST
RA10 — 29 K3 B17 I/O ST
RA14 — 66 E11 B36 I/O ST
RA15 — 67 E8 A44 I/O ST
RB0 16 25 K2 B14 I/O ST PORTB is a bidi rectional I/O port
RB1 15 24 K1 A15 I/O ST
RB2 14 23 J2 B13 I/O ST
RB3 13 22 J1 A13 I/O ST
RB4 12 21 H2 B11 I/O ST
RB5 11 20 H1 A12 I/O ST
RB6 17 26 L1 A20 I/O ST
RB7 18 27 J3 B16 I/O ST
RB8 21 32 K4 A23 I/O ST
RB9 22 33 L4 B19 I/O ST
RB10 23 34 L5 A24 I/O ST
RB11 24 35 J5 B20 I/O ST
RB12 27 41 J7 B23 I/O ST
RB13 28 42 L7 A28 I/O ST
RB14 29 43 K7 B24 I/O ST
RB15 30 44 L8 A29 I/O ST
RC1 — 6 D1 A5 I/O ST PORTC is a bidirectional I/O port
RC2 — 7 E4 B4 I/O ST
RC3 — 8 E2 A6 I/O ST
RC4 — 9 E1 B5 I/O ST
RC12 39 63 F9 B34 I/O ST
RC13 47 73 C10 A47 I/O ST
RC14 48 74 B11 B40 I/O ST
RC15 40 64 F11 A42 I/O ST
TABLE 1-1: PINOU T I/O DESCRI PTIONS (CONTINUED )
Pin Name Pin Number
(1)
Pin
Type Buffer
Type Description
64-Pin
QFN/TQFP 100-Pin
TQFP 121-Pin
TFBGA 124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin nu mbers are only provide d for refer ence. Se e the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
2009-2016 Microchip Technology Inc. DS60001156J- page 29
PIC32MX5XX/6XX/7XX
RD0 46 72 D9 B39 I/O ST PORTD is a bidirectional I/O port
RD1 49 76 A11 A52 I/O ST
RD2 50 77 A10 B42 I/O ST
RD3 51 78 B9 A53 I/O ST
RD4 52 81 C8 B44 I/O ST
RD5 53 82 B8 A55 I/O ST
RD6 54 83 D7 B45 I/O ST
RD7 55 84 C7 A56 I/O ST
RD8 42 68 E9 B37 I/O ST
RD9 43 69 E10 A45 I/O ST
RD10 44 70 D11 B38 I/O ST
RD11 45 71 C11 A46 I/O ST
RD12 — 79 A9 B43 I/O ST
RD13 — 80 D8 A54 I/O ST
RD14 — 47 L9 B26 I/O ST
RD15 — 48 K9 A31 I/O ST
RE0 60 93 A4 B52 I/O ST PORTE is a bidirectional I/O port
RE1 61 94 B4 A64 I/O ST
RE2 62 98 B3 A66 I/O ST
RE3 63 99 A2 B56 I/O ST
RE4 64 100 A1 A67 I/O ST
RE5 1 3 D3 B2 I/O ST
RE6 2 4 C1 A4 I/O ST
RE7 3 5 D2 B3 I/O ST
RE8 — 18 G1 A11 I/O ST
RE9 — 19 G2 B10 I/O ST
RF0 58 87 B6 B49 I/O ST PORTF is a bidirectional I/O port
RF1 59 88 A6 A60 I/O ST
RF2 — 52 K11 A36 I/O ST
RF3 33 51 K10 A35 I/O ST
RF4 31 49 L10 B27 I/O ST
RF5 32 50 L11 A32 I/O ST
RF8 — 53 J10 B29 I/O ST
RF12 — 40 K6 A27 I/O ST
RF13 — 39 L6 B22 I/O ST
TABLE 1-1: PINOU T I/O DESCRI PTIONS (CONTINUED)
Pin Name Pin Number
(1)
Pin
Type Buffer
Type Description
64-Pin
QFN/TQFP 100-Pin
TQFP 121-Pin
TFBGA 124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin nu mbers are only provided for reference. See th e “Device Pin Tables ” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 30 2009-2016 Microchip Technology Inc.
RG0 — 90 A5 A61 I/O ST PORTG is a bidirectional I/O port
RG1 — 89 E6 B50 I/O ST
RG6 4 10 E3 A7 I/O ST
RG7 5 11 F4 B6 I/O ST
RG8 6 12 F2 A8 I/O ST
RG9 8 14 F3 A9 I/O ST
RG12 — 96 C3 A65 I/O ST
RG13 — 97 A3 B55 I/O ST
RG14 — 95 C4 B54 I/O ST
RG15 — 1 B2 A2 I/O ST
RG2 37 57 H10 B31 I ST PORTG input pins
RG3 36 56 J11 A38 I ST
T1CK 48 74 B11 B40 I ST Timer1 external clock input
T2CK — 6 D1 A5 I ST Timer2 external clock in put
T3CK — 7 E4 B4 I S T Timer3 external clock input
T4CK — 8 E2 A6 I S T Timer4 external clock input
T5CK — 9 E1 B5 I S T Timer5 external clock input
U1CTS 43 47 L9 B26 I S T UART1 clear to send
U1RTS 49 48 K9 A31 O — UART1 ready to send
U1RX 50 52 K11 A36 ISTUART1 receive
U1TX 51 53 J10 B29 O — UART1 transmit
U3CTS 814F3
A9 I ST UA RT3 clear to send
U3RTS 410E3
A7 O — UART3 ready to send
U3RX 511F4B6
ISTUART3 receive
U3TX 612F2A8
O — UART3 transmit
U2CTS 21 40 K6 A27 I ST UART2 clea r to send
U2RTS 29 39 L6 B22 O — UART2 ready to send
U2RX 31 49 L10 B27 ISTUART2 receive
U2TX 32 50 L11 A32 O — UART2 transmit
U4RX 43 47 L9 B26 ISTUART4 receive
U4TX 49 48 K9 A31 O — UART4 transmit
U6RX 814F3A9
ISTUART6 receive
U6TX 410E3A7
O — UART6 transmit
U5RX 21 40 K6 A27 ISTUART5 receive
U5TX 29 39 L6 B22 O — UART5 transmit
SCK1 — 70 D11 B38 I/O ST Synchronous serial clock input/output
for SPI1
TABLE 1-1: PINOU T I/O DESCRI PTIONS (CONTINUED )
Pin Name Pin Number
(1)
Pin
Type Buffer
Type Description
64-Pin
QFN/TQFP 100-Pin
TQFP 121-Pin
TFBGA 124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin nu mbers are only provide d for refer ence. Se e the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
2009-2016 Microchip Technology Inc. DS60001156J- page 31
PIC32MX5XX/6XX/7XX
SDI1 — 9 E1 B5 I ST SPI1 data in
SDO1 — 72 D9 B39 O — SPI1 data out
SS1 —69E10
A45 I/O ST SPI1 slav e synchronization or frame
pulse I/O
SCK3 49 48 K9 A31 I/O ST Synchronous serial clock input/output
for SPI3
SDI3 50 52 K11 A36 I ST SPI3 data in
SDO3 51 53 J10 B29 O — SPI3 data o ut
SS3 43 47 L9 B26 I/O ST SPI3 slave synchronization or frame
pulse I/O
SCK2 4 10 E3 A7 I/O ST Synchronous serial clock input/output
for SPI2
SDI2 5 11 F4 B6 I ST SPI2 data in
SDO2 6 12 F2 A8 O — SPI2 data out
SS2 814F3
A9 I/O ST SPI2 slav e synchronization or frame
pulse I/O
SCK4 29 39 L6 B22 I/O ST Sy nchronous serial clock input/output
for SPI4
SDI4 31 49 L10 B27 I ST SPI4 data in
SDO4 32 50 L11 A32 O — SPI4 data out
SS4 21 40 K6 A27 I/O ST SPI4 slave synchronization or frame
pulse I/O
SCL1 44 66 E11 B36 I/O ST Synchronous serial clock input/output
for I2C1
SDA1 43 67 E8 A44 I/O ST Synchronous serial data input/output
for I2C1
SCL3 51 53 J10 B29 I/O ST Synchronous serial clock input/output
for I2C3
SDA3 50 52 K11 A36 I/O ST Synchronous serial data input/output
for I2C3
SCL2 — 58 H11 A39 I/O ST Synchronous seri al clock input/output
for I2C2
SDA2 — 59 G10 B32 I/O ST Synchronous serial data input/output
for I2C2
SCL4 6 12 F2 A8 I/O ST Synchronous serial clock input/output
for I2C4
SDA4 5 11 F4 B6 I/O ST Synchronous serial data input/output
for I2C4
SCL5 32 50 L11 A32 I/O ST Synchronous serial clock input/output
for I2C5
SDA5 31 49 L10 B27 I/O ST Synchronous serial data input/output
for I2C5
TABLE 1-1: PINOU T I/O DESCRI PTIONS (CONTINUED)
Pin Name Pin Number
(1)
Pin
Type Buffer
Type Description
64-Pin
QFN/TQFP 100-Pin
TQFP 121-Pin
TFBGA 124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin nu mbers are only provided for reference. See th e “Device Pin Tables ” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 32 2009-2016 Microchip Technology Inc.
TMS 23 17 G3 B9 I ST JTAG Test mod e select pin
TCK 27 38 J6 A26 I ST JTAG test clock input pin
TDI 28 60 G11 A40 I ST JTAG test data input pin
TDO 24 61 G9 B33 O — JTAG test data output pin
RTCC 42 68 E9 B37 O — Rea l-Time Clock ala rm output
CV
REF
-1528L2
A21 I Analog Comparator Voltage Reference (low)
CV
REF
+ 16 29 K3 B17 I Analog Comparator Voltage Reference (high)
CV
REFOUT
23 34 L5 A24 O Analog Comparator Voltage Reference output
C1IN- 12 21 H2 B11 I Analog Comparator 1 negative input
C1IN+ 11 20 H1 A12 I Analog Comparator 1 positive input
C1OUT 21 32 K4 A23 O — Comparator 1 output
C2IN- 14 23 J2 B13 I Analog Comparator 2 negative input
C2IN+ 13 22 J1 A13 I Analog Comparator 2 positive input
C2OUT 22 33 L4 B19 O — Comparator 2 outp ut
PMA0 30 44 L8 A29 I/O TTL/ST P aral lel M aster Port Address bi t 0 in pu t
(Buffered Slave modes) and output
(Master modes)
PMA1 29 43 K7 B24 I/O TTL/ST P aral lel M ast er Po rt Add res s bi t 1 input
(Buffered Slave modes) and output
(Master modes)
PMA2 8 14 F3 A9 O — Parallel Master Port address
(Demultiplexed Master modes)
PMA3 6 12 F2 A8 O —
PMA4 5 11 F4 B6 O —
PMA5 4 10 E3 A7 O —
PMA6 16 29 K3 B17 O —
PMA7 22 28 L2 A21 O —
PMA8 32 50 L11 A32 O —
PMA9 31 49 L10 B27 O —
PMA10 28 42 L7 A28 O —
PMA11 27 41 J7 B23 O —
PMA12 24 35 J5 B20 O —
PMA13 23 34 L5 A24 O —
PMA14 45 71 C11 A46 O —
PMA15 44 70 D11 B38 O —
PMCS1 45 71 C11 A46 O — Parallel Master Port Chip Select 1
strobe
PMCS2 44 70 D11 B38 O — Parallel Master Port Chip Select 2
strobe
TABLE 1-1: PINOU T I/O DESCRI PTIONS (CONTINUED )
Pin Name Pin Number
(1)
Pin
Type Buffer
Type Description
64-Pin
QFN/TQFP 100-Pin
TQFP 121-Pin
TFBGA 124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin nu mbers are only provide d for refer ence. Se e the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
2009-2016 Microchip Technology Inc. DS60001156J- page 33
PIC32MX5XX/6XX/7XX
PMD0 60 93 A4 B52 I/O TTL/ST Parallel Master Port data
(Demultipl exed Master mo de) or
address/data (Multiplexed Master
modes)
PMD1 61 94 B4 A64 I/O TTL/ST
PMD2 62 98 B3 A66 I/O TTL/ST
PMD3 63 99 A2 B56 I/O TTL/ST
PMD4 64 100 A1 A67 I/O TTL/ST
PMD5 1 3 D3 B2 I/O TTL/ST
PMD6 2 4 C1 A4 I/O TTL/ST
PMD7 3 5 D2 B3 I/O TTL/ST
PMD8 — 90 A5 A61 I/O TTL/ST
PMD9 — 89 E6 B50 I/O TTL/ST
PMD10 — 88 A6 A60 I/O TTL/ST
PMD11 — 87 B6 B49 I/O TTL/ST
PMD12 — 79 A9 B43 I/O TTL/ST
PMD13 — 80 D8 A54 I/O TTL/ST
PMD14 — 83 D7 B45 I/O TTL/ST
PMD15 — 84 C7 A56 I/O TTL/ST
PMALL 30 44 L8 A29 O — Parallel Master Port address latch
enable low byte (Multiplexed Master
modes)
PMALH 29 43 K7 B24 O — Parallel Master Port address latch
enable high byte (Multiplexed Master
modes)
PMRD 53 82 B8 A55 O — Parallel Master Port read strobe
PMWR 52 81 C8 B44 O — Parallel Master Port write strobe
V
BUS
34 54 H8 A37 I Analog USB bus power monitor
V
USB
3
V
3
35 55 H9 B30 P — USB internal transceive r supply. If the
USB modul e is not used, this pin must
be connected to V
DD
.
V
BUSON
11 20 H1 A12 O — USB Host and OTG bus power control
output
D+ 37 57 H10 B31 I/O Analog USB D+
D- 36 56 J11 A38 I/O Analog USB D-
USBID 33 51 K10 A35 I ST USB OTG ID detect
C1RX 58 87 B6 B49 I ST CAN1 bus receive pin
C1TX 59 88 A6 A60 O — CAN1 bus tran s mit pin
AC1RX 32 40 K6 A27 I ST Alternate CAN1 bus receive pin
AC1TX 31 39 L6 B22 O — Alternate CAN1 bus transmit pin
C2RX 29 90 A5 A61 I ST CAN2 bus receive pin
C2TX 21 89 E6 B50 O — CAN2 bus tran s mit pin
AC2RX — 8 E2 A6 1 ST Alternate CAN2 bus receive pin
TABLE 1-1: PINOU T I/O DESCRI PTIONS (CONTINUED)
Pin Name Pin Number
(1)
Pin
Type Buffer
Type Description
64-Pin
QFN/TQFP 100-Pin
TQFP 121-Pin
TFBGA 124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin nu mbers are only provided for reference. See th e “Device Pin Tables ” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 34 2009-2016 Microchip Technology Inc.
AC2TX — 7 E4 B4 O — Alternate CAN2 bus transmit pin
ERXD0 61 41 J7 B23 I ST Ethernet Receive Data 0
(2)
ERXD1 60 42 L7 A28 I ST Ethernet Receive Data 1
(2)
ERXD2 59 43 K7 B24 I ST Ethernet Receive Data 2
(2)
ERXD3 58 44 L8 A29 I ST Ethernet Receive Data 3
(2)
ERXERR 64 35 J5 B20 I ST Ethernet receive error input
(2)
ERXDV 62 12 F2 A8 I ST Ethernet receive data valid
(2)
ECRSDV 62 12 F2 A8 I ST Ethernet carrier sense data valid
(2)
ERXCLK 63 14 F3 A9 I ST Ethernet receive clock
(2)
EREFCLK 63 14 F3 A9 I ST Ethernet refer enc e clock
(2)
ETXD0 2 88 A6 A60 O — Ethernet Transmit Data 0
(2)
ETXD1 3 87 B6 B49 O — Ethernet Transmit Data 1
(2)
ETXD2 43 79 A9 B43 O — Ethernet Transmit Data 2
(2)
ETXD3 42 80 D8 A54 O — Ethernet Transmit Data 3
(2)
ETXERR 54 89 E6 B50 O — Ethernet transmit error
(2)
ETXEN 1 83 D7 B45 O — Ethernet transmit enable
(2)
ETXCLK 55 84 C7 A56 I ST Ethernet transmit clock
(2)
ECOL 44 10 E3 A7 I ST Ethernet collision detect
(2)
ECRS 45 11 F4 B6 I ST Ethernet carrier sense
(2)
EMDC 3 0 7 1 C11 A46 O — Ethernet manag em ent data clock
(2)
EMDIO 49 68 E9 B37 I/O — Ethernet manag em ent data
(2)
AERXD0 43 18 G1 A11 I ST Alternate Ethernet Receive Data 0
(2)
AERXD1 42 19 G2 B10 I ST Alternate Ethernet Receive Data 1
(2)
AERXD2 — 28 L2 A21 I ST Alternate Ethernet Receive Data 2
(2)
AERXD3 — 29 K3 B17 I ST Alternate Ethernet Receive Data 3
(2)
AERXERR 55 1 B2 A2 I ST Alternate Ethernet receive error input
(2)
AERXDV — 12 F2 A8 I ST Alternate Ethernet receive data valid
(2)
AECRSDV 44 12 F2 A8 I ST Alternate Ethernet carrier sense data
valid
(2)
AERXCLK — 14 F3 A9 I ST Alternate Ethernet receive clock
(2)
AEREFCLK 45 14 F3 A9 I ST Alternate Ethernet reference clock
(2)
AETXD0 59 47 L9 B26 O — Alternate Ethernet Transmit Data 0
(2)
AETXD1 58 48 K9 A31 O — Alternate Ethernet Transmit Data 1
(2)
AETXD2 — 44 L8 A29 O — Alternate Ethernet Transmit Data 2
(2)
AETXD3 — 43 K7 B24 O — Alternate Ethernet Transmit Data 3
(2)
AETXERR — 35 J5 B20 O — Alternate Ethernet transmit error
(2)
AETXEN 54 67 E8 A44 O — Alternate Ethernet transmit enable
(2)
AETXCLK — 66 E11 B36 I ST Alternate Ethernet transmit clock
(2)
AECOL — 42 L7 A28 I ST Alternate Ethernet collision detect
(2)
TABLE 1-1: PINOU T I/O DESCRI PTIONS (CONTINUED )
Pin Name Pin Number
(1)
Pin
Type Buffer
Type Description
64-Pin
QFN/TQFP 100-Pin
TQFP 121-Pin
TFBGA 124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin nu mbers are only provide d for refer ence. Se e the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
2009-2016 Microchip Technology Inc. DS60001156J- page 35
PIC32MX5XX/6XX/7XX
AECRS — 41 J7 B23 I ST Alternate Ethernet carrier sense
(2)
AEMDC 30 71 C11 A46 O — Alternate Ethernet Management Data
clock
(2)
AEMDIO 49 68 E9 B37 I/O — Alternate Ethernet Management Data
(2)
TRCLK — 91 C5 B51 O — Trace clock
TRD0 — 97 A3 B55 O — Trace Data bits 0-3
TRD1 — 96 C3 A65 O —
TRD2 — 95 C4 B54 O —
TRD3 — 92 B5 A62 O —
PGED1 16 25 K2 B14 I/O ST Data I/O pin for Programming/
Debugging Communication Channel 1
PGEC1 15 24 K1 A15 I ST Clock input pin for Programming/
Debugging Communication Channel 1
PGED2 18 27 J3 B16 I/O ST Data I/O pin for Programming/
Debugging Communication Channel 2
PGEC2 17 26 L1 A20 I ST Clock input pin for Programming/
Debugging Communication Channel 2
MCLR 713F1
B7 I/P ST Master Clear (Reset) input. This pin is
an active-low Reset to the device.
AV
DD
19 30 J4 A22 P P Positive su pply for analog modules.
This pin must be co nnected at all times .
AV
SS
20 31 L3 B18 P P Ground reference for anal og modules
V
DD
10, 26, 38,
57 2, 16, 37,
46, 62, 86
A7, C2,
C9, E5,
K8, F8,
G5, H4,
H6
A10, A14,
A30, A41,
A48, A59,
B1, B21,
B53
P—
Positive supply for peripheral logic and
I/O pins
V
CAP
56 85 B7 B48 P — Capac itor for Internal Voltage Regulator
V
SS
9, 25, 41 15, 36, 45,
65, 75
A8, B10,
D4, D5,
E7, F5,
F10, G6,
G7, H3
A3, A25,
A43, A63,
B8, B12,
B25, B41,
B46
P—
Ground referenc e for log ic and I/O pins.
This pin must be co nnected at all times .
V
REF
+ 16 29 K3 B17 I Analog Analog voltage reference (high) input
V
REF
- 15 28 L2 A21 I Analog Analog voltage reference (low) input
TABLE 1-1: PINOU T I/O DESCRI PTIONS (CONTINUED)
Pin Name Pin Number
(1)
Pin
Type Buffer
Type Description
64-Pin
QFN/TQFP 100-Pin
TQFP 121-Pin
TFBGA 124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin nu mbers are only provided for reference. See th e “Device Pin Tables ” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 36 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 37
PIC32MX5XX/6XX/7XX
2.0 GUIDELINES FOR GETTING
STARTE D WITH 32-BIT MCUS
2.1 Basic Connection Requirements
Getting started with the PIC32MX5XX/6XX/7XX family
of 32-bit Microcontrollers (MCUs) requires attention to
a minimal set of device pin connections before pro-
ceeding with development. The following is a list of pin
names, which must always be connected:
•All V
DD
and V
SS
pins (see 2.2 “Decoupling
Capacitors”)
•All AV
DD
and AV
SS
pins even if the ADC module is
not used (see 2.2 “Decoupling Capacitors”)
•V
CAP
pin (see 2.3 “Capacitor on Internal Voltage
Regulator (V
CAP
)”)
•MCLR
pin (see 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source i s use d (see 2.8 “External Oscilla tor Pins”)
The following pin may be required, as well: V
REF
+/
V
REF
- pins used when external voltage reference for
ADC module is implemented.
2.2 Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as V
DD
, V
SS
, AV
DD
and AV
SS
is required.
See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
•Value and type of cap a cito r: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance fre-
quency in the range of 20 MHz and higher. It is
further recommended to use ceramic capacitors.
•Placement on the printed circuit board: The
decoupling capacitors should be placed as cl ose
to the pins as possible. It is recommended that
the capacitors be placed on the same side of
the board as the device. If space is constricted,
the capacitor can be placed on another layer on
the PCB using a via; however, ensure that the
trace length from the pin to the capacitor i s
within one-quarter inch (6 mm) in length.
•Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, ad d a second c eramic-type capac itor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacito r next to the primary dec oupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
•Maximiz ing perform anc e: On the board layout
from the power supply circuit, run the power and
return traces to the decou pli ng ca p ac ito rs first,
and then to the device pins. This en sures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
inductance.
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“PI C32 Fa mily R efere nce Ma nual” , which
is available from the Microchip web site
(www.microchip.com/PIC32).
Note: The AV
DD
and AV
SS
pins must be
connected, regardless of the ADC use
and the ADC voltage reference source.
PIC32MX5XX/6XX/7XX
DS60001156J-page 38 2009-2016 Microchip Technology Inc.
FIGURE 2-1: RECOMMENDE D
MINIMUM CONNECTION
2.2.1 BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability . T ypical values range fro m 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
2.3 Capacitor on Internal Voltage
Regulator (V
CAP
)
2.3.1 INTERNAL REGULATOR MODE
A low -ESR (1 ohm ) capacito r is r equir ed on t he V
CAP
pin, whi ch is used to stab ilize the in ternal vo lta ge regu-
lator output. The V
CAP
pin must not be connected to
V
DD
, and must have a C
EFC
capaci tor, with at least a
6V rating, connected to ground. The type can be
cerami c or t ant alum . Refer to Sectio n 32.0 “Electrical
Characteristics” for additional information on C
EFC
specifications.
2.4 Mast er Clear (MCLR) Pin
The MCLR pin provides two specific device
functions:
• Device Reset
• Device Programming and Debugging
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (V
IH
and V
IL
) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
PIC32
V
DD
V
SS
V
DD
V
SS
V
SS
V
DD
AV
DD
AV
SS
V
DD
V
SS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
C
R
V
DD
MCLR
0.1 µF
Ceramic
L1
(2)
R1
Note 1:
If the USB module is not used, this pin must be
connected to V
DD
.
2:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between V
DD
and
AV
DD
to improve ADC nois e reje cti on. The in duct or
impedance should be less than 3
and the inductor
capacity greater than 10 mA.
Where:
fF
CNV
2
--------------=
f1
2LC
-----------------------=
L1
2fC
----------------------
2
=
(i.e., ADC conversion rate/2)
Connect
(2)
V
USB
3
V
3
(1)
V
CAP
Tantalum or
ceramic 10 µF
ESR 3
(3)
3:
Aluminum or electrolytic capacitors should not be
used. ESR
3
from -40ºC to 125ºC @ SYSCLK
frequency (i.e., MIPS).
Note 1:
470
R1
1k
will limit any current flowing into
MCLR from the externa l capaci tor C, i n the e vent of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin V
IH
and V
IL
speci ficati ons are met wi thout
interfering with the Debug/Programmer tools.
2:
The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
3:
No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
R1
(1)
10k
V
DD
MCLR
PIC32
1 k
0.1 µF
(2)
PGECx
(3)
PGEDx
(3)
ICSP™
1
5
4
2
3
6
V
DD
V
SS
NC
R
C
2009-2016 Microchip Technology Inc. DS60001156J- page 39
PIC32MX5XX/6XX/7XX
2.5 ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging. It is
recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is
recomm ended, with the value in th e range of a fe w tens
of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(V
IH
) and input low (V
IL
) requiremen t s .
Ensure that the “Communi cation Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB
®
ICD 3 or MPLAB
®
REAL ICE™.
For more in form at ion on IC D 3 a nd R EAL ICE connec-
tion requi rements, re fer to the following document s that
are available on the Microchip web site.
•“Using MPLAB
®
ICD 3” (poster) (DS50001765)
•“MPLAB
®
ICD 3 Design Advisory” (DS50001764)
•“MPLAB
®
REAL ICE™ In-Circui t Emula tor User’s
Guide” (DS50001616)
•“Using MPLAB
®
REAL ICE™ Emulator” (poster)
(DS50001749)
2.6 JTAG
The TMS, TDO , TD I an d TCK pi ns are us ed for tes tin g
and debugging according to the Joint Test Action
Group (J TAG) st andard. It is recomme nded to k eep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a se ries resistor is recomm ended, with the valu e
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
commu nic at ions to the device. If suc h dis cre te co mp o-
nents are an application requirement, they should be
removed from the circuit during programming and
debuggi ng. Altern atively, refer to the AC/DC charact er-
istics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (V
IH
) and input low (V
IL
) requirements.
2.7 Trace
The trace pins can be connected to a hardware-trace-
enabled programmer to provide a compress real time
instruction trace. When used for trace the TRD3,
TRD2, TRD1, TRD0 and TRCLK pins should be
dedicated for this use. The trace hardware requires
a22 series resistor between the trace pins and the
trace connector.
2.8 External Oscillator Pins
Many MCU s ha ve optio ns for at le as t two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator. Refer to Section 8.0 “Oscillator
Configuration” for details.
The osci llator circuit shou ld be placed on the same side
of the bo ard as the device. Al so, place the osci llator cir-
cuit close to the respective oscillator pins, not exceed-
ing one-ha lf inch (12 mm) distanc e between the m. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Us e a grounded
copper pour a round the oscill ator c ircui t to i solat e them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any si gnal traces or power traces inside the groun d
pour. Also, if usin g a two- sided board, av oid an y trace s
on the other side of the board where the crystal is
placed. A suggested layout is illustrated in Figure 2-3.
FIGURE 2-3: SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
Main Oscilla tor
Guard Ring
Guard Trace
Secondary
Oscillator
PIC32MX5XX/6XX/7XX
DS60001156J-page 40 2009-2016 Microchip Technology Inc.
2.9 Conf iguration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the Analog-
to-Digital input pins (ANx) as “digital” pins by setting
all bits in the AD1PCFG register.
The bits in this register that correspond to the Analog-
to-Digital pins that are initialized by MPLAB ICD 3 or
REAL ICE, mu st not be clea red by th e u se r a ppl ic atio n
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain ADC pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFG register during initialization of the ADC
module.
When MPLAB ICD 3 or REAL ICE is used as a pro-
grammer, the user application firmware must correctly
configure the AD1PCFG register. Automatic initializa-
tion of this register is only done during debugger oper-
ation. Failure to correctly configure the register(s) will
result in all ADC pins bei ng reco gni zed as analog input
pins, resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
2.10 Unused I/Os
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-lo w state.
Alternati vel y, inputs c an be res erv ed by connecting the
pin to V
SS
through a 1k to 10k resistor and configuring
the pin as an input.
2.11 EMI/EMC/EFT (IEC 61000-4-4 and
IEC 61000-4-2) Suppression
Considerations
The use of LDO regulators is preferred to reduce
overall system noise and provide a cleaner power
source. However, when utilizing switching Buck/
Boost regulators as the local power source for PIC32
devices, as well as in electrically noisy environ-
ments or test conditions required for IEC 61000-4-4
and IEC 61000-4-2, users should evaluate the use of
T-Filters (i.e., L-C-L) on the power pins, as shown in
Figure 2-4. In addition to a more stable power
source, use of this type of T-Filter can greatly reduce
susc eptibility to EMI s ources and events.
FIGURE 2-4: EMI/EMC/EFT
SUPPRESSION CIRCUIT
V
SS
V
DD
V
SS
V
USB3V3
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
AV
DD
AV
SS
Ferrite
Chips
0.01 μF
0.01 μF
V
DD
V
DD
0.1 μF
0.1 μF
0.1 μF
0.1 μF
0.1 μF
0.1 μF
0.1 μF
0.1 μF
Ferrite
Chips
Ferrite Chip SMD
DCR = 0.15ȍ(max)
600 ma ISAT
300ȍ@ 100 MHz
PN#: 1-1624117-3
0.1 μF
PIC32
2009-2016 Microchip Technology Inc. DS60001156J- page 41
PIC32MX5XX/6XX/7XX
3.0 CPU
The MIPS32
®
M4K
®
Processor co re is the heart of the
PIC32MX5XX/6XX/7XX family processor. The CPU
fetches instructions, decodes each instruction, fetches
source operands, ex ec ute s e ac h i ns truc tio n and writes
the results of instruction execution to the proper
destinations.
3.1 Features
• 5-stage pipeli ne
• 32-bit address and data paths
• MIPS32 En hanced Architecture (Release 2)
- Mul tipl y-a ccum ul ate and multi pl y-s ubt rac t
instructions
- Ta rgeted multiply instruction
- Zero/One detect instructions
-WAIT instructi on
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomi c interrupt enable/dis abl e
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit fiel d manipulation inst ruct ions
• MIPS16e
®
code compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
-SAVE and RESTORE macro instruct ions for
setting up and tearing down stack frames
within subrout ines
- Improved support for handling 8-bit and 16-bit
data types
• Simple Fixed Mapping Translation (FMT)
mechanism
• Simple dual bus interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt late nc y
• Autonomous multiply/divide unit
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maxim um 33 cloc k lat ency (divid end (rs) sign
extension-dependent)
• Power control
- Mini mu m freq uen cy : 0 MHz
- Low-Power mode (tri ggered by WAIT
instruction)
- Extensive use of local gated clocks
• EJTAG debug and instruction trace
- Support for single stepping
- Virtual instruction and data address/value
-Breakpoints
- PC tracing with trace compression
FIGURE 3-1: MIPS32
®
M4K
®
PROCESSOR CORE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS60001113) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site (www.micro-
chip.com/PIC32). Resources for the
MIPS32
®
M4K
®
Processor Core are
available at http://www.imgtec.com.
CPU MDU
Execution Core
(RF/ALU/Shift) FMT
TAP
EJTAG
Bus Interface
Power
Management
System
Co-processor
Off-chip Debug Interface
Bus Matrix
Dual Bus Interface
PIC32MX5XX/6XX/7XX
DS60001156J-page 42 2009-2016 Microchip Technology Inc.
3.2 Architecture Overview
The MIPS32 M4K processor core contains several
logic blocks working together in parallel, providing an
efficient high-performance computing engine. The
following blocks are included with the core:
• E x ecution Unit
• Multiply/Divide Unit (MDU)
• System Control Coprocessor (CP0)
• Fixed Mapping Transla tion (FMT)
• Dual Internal Bus inte rfaces
• Power Management
• MIPS16e
®
Support
• Enhanced JTAG (EJTAG) Controller
3.2.1 EXECUTION UNIT
The MIPS3 2 M4K processo r core ex ecutio n uni t imple-
ments a load/store architecture with single-cycle ALU
operations (logica l, sh if t, add, subtra ct ) a nd an autono-
mous multiply/divide unit. The core contains thirty-two
32-bit General Purpose Registers (GPRs) used for
integer operations and address calculation. One addi-
tional reg ister file shadow set (con taining thirty-t wo reg-
isters) is added to minimize context switching overhead
during interrupt/exception processing. The register file
consis ts of two read ports and o ne write port a nd is fully
byp assed to mi nimiz e opera tio n late ncy i n the pi pelin e.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
• Leading Zero/One detect unit for implementing
the CLZ and CLO instr uctions
• Arithmetic Logic U nit (ALU) for performing bit-wis e
logical operations
• Shifter and store aligner
3.2.2 MULTIPLY/DIVIDE UNIT (MDU)
MIPS32 M4K pr ocessor co re inclu des a Mu ltiply/D ivide
Unit (MDU ) th at co ntains a s eparat e pi pel ine fo r mu lti -
ply and divide operations. This pipeline operat es in par-
allel with the Integer Unit (IU) pipeli ne and does no t stall
when the IU pipeline stalls. This allows MDU opera-
tions to be partially masked by system stalls and/or
other integer unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32 core only checks the value of the latter (rt)
operand to determine how many times the operation
must p ass thro ugh the mul tiplier. The 16x1 6 and 32x1 6
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bit s w ide, 23 iterations are sk ipped. For a 16 bit
wide rs, 15 iterations are skipped and for a 24 bit wide rs,
7 iterations are skipped. Any attempt to issue a
subsequent MDU instruction while a divide is still active
causes an IU pipeline stall until the divide operation is
completed.
Table 3-1 list s the repeat rat e (peak issue rate of cycles
until the operation can be reissued) and latenc y (num-
ber of cycles until a result is available) for the PIC32
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
TABLE 3-1: MIPS32
®
M4K
®
CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT
LATENCIES AND REPEAT RATES
Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU 16 bits 1 1
32 bit s 2 2
MUL 16 bit s 2 1
32 bit s 3 2
DIV/DIVU 8 bits 12 11
16 bit s 19 18
24 bit s 26 25
32 bit s 33 32
2009-2016 Microchip Technology Inc. DS60001156J- page 43
PIC32MX5XX/6XX/7XX
The MIPS architecture defines that the result of a
multipl y or div id e ope ration be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, whic h places th e least signif icant result s in the p ri-
mary register file instead of the HI/LO register pair. By
avoiding the explicit MFLO instruction required when
using the LO regist er, and by supporti ng multi ple des ti-
nation registers, the throughput of multiply-intensive
operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are comm only used in DSP algorithms.
3.2.3 SYSTEM CONTR OL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor ’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configura-
tion information, such as presence of options like
MIPS16e, is also available by accessing the CP0
registers, listed in Table 3-2.
TABLE 3-2: COPROCESSOR 0 REGISTERS
Register
Number Register
Name Function
0-6 Reserved Reserved.
7 HWREna Enables access via the RDHWR instruction to selected hardware registers.
8 BadVAddr
(1)
Reports the address for the most recent address-related exception.
9 Count
(1)
Processor cy cl e coun t.
10 Reserved Reserved.
11 Compare
(1)
Timer interrupt control.
12 Status
(1)
Processor status and control.
12 IntCtl
(1)
Interrupt system status and control.
12 SRSCtl
(1)
Shadow register set status and control.
12 SRSMap
(1)
Provides mapping from vectored interrupt to a shadow set.
13 Cause
(1)
Cause of last general exception.
14 EPC
(1)
Program counte r at last except ion .
15 PRId Processor identifica tion and revision.
15 Ebase Exception vector base register.
16 Config Configuration register.
16 Config1 Configuration Register 1.
16 Config2 Configuration Register 2.
16 Config3 Configuration Register 3.
17-22 Reserved Reserved.
23 Debug
(2)
Debug control and exception status.
24 DEPC
(2)
Program counter at last debug exception.
25-29 Reserved Reserved.
30 ErrorEPC
(1)
Program counte r at last error.
31 DESAVE
(2)
Debug handler scratchpad register.
Note 1: Registers used in exception processing.
2: Registers used during debug.
PIC32MX5XX/6XX/7XX
DS60001156J-page 44 2009-2016 Microchip Technology Inc.
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors. Table 3-3 lists
the exception types in order of priority.
TABLE 3-3: PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES
Exception Description
Reset Assertion MCLR or a Power-on Reset (POR).
DSS EJTAG debug single step.
DINT EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
NMI Assertion of NMI signal.
Interrupt Assertion of unmasked hardware or software interrupt signal.
DIB EJTAG debug hardware instruction break matched.
AdEL Fetch address alignment error.
Fetch reference to protected address.
IBE Instruction fetch bus error.
DBp EJTAG breakpoi nt (execution of SDBBP instructi on).
Sys Execution of SYSCALL instruc tio n.
Bp Executi on of BREAK instruct ion.
RI Execution of a reserved inst ruct ion.
CpU Execution of a coprocessor instruction for a coprocessor that is not enabled.
CEU Execution of a CorExtend instruction when CorExtend is not enabled.
Ov Execution of an arithmetic in struction that overflowed.
Tr Execution of a trap (when trap condition is true).
DDBL/DDBS EJTAG Data Address Break (addres s only) or EJTAG data value break on store (address + value).
AdEL Load address alignment error.
Load reference to protected address.
AdES Store address alignment error.
Store to protected address.
DBE Load or store bus error.
DDBL EJTAG data hardware breakpoint matched in load data compare.
2009-2016 Microchip Technology Inc. DS60001156J- page 45
PIC32MX5XX/6XX/7XX
3.3 Power Management
The MIPS32 M4K Processor core offers a number of
power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or halting the clocks, which reduces
system power consump tion during idle periods.
3.3.1 INSTRUCTION-CONTROLLE D
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on pow er management, see Section 28.0
“Power-Saving Fea tures ”.
3.3. 2 LOCAL CLOCK GATING
The majority of the power consumed by the PIC32MX-
5XX/6XX/7XX fam ily core is in the clock tree an d clock-
ing registers. The PIC32 family uses extensive use of
local gated clocks to reduce this dynamic power con-
sumption.
3.4 EJTAG Debug Support
The MIPS32 M4K Processor core provides for an
Enhanced JTAG (EJTAG) interface for use in the
software debug of application and kernel code. In
addition to standard User mode and Kernel modes of
operatio n, the MIPS M4K core pro vides a Debug mod e
that is entered after a debug exc ep tio n (deri ved from a
hardware breakpoint, single-step exception, etc.) is
taken and continues until a Debug Exception Return
(DERET) instruction is executed. During this time, the
processor executes the debug exception handler rou-
tine.
The EJTAG interf ace operate s through the Test A ccess
Port (TAP), a serial communication port used for
transferring test data in and out of the MIPS32 M4K
processor core. In addition to the standard JTAG
instructions, special instructions defined in the EJTAG
specification define which registers are selected and
how they are use d.
PIC32MX5XX/6XX/7XX
DS60001156J-page 46 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 47
PIC32MX5XX/6XX/7XX
4.0 MEMORY ORGANIZATION
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB
of unified virtual memory address space. All memory
regions, including program, data memory, SFRs and
Config ura tion registers, reside in t his ad dres s s p a ce at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kern el memories. In a ddition, the da ta memory ca n
be made executable, allowing PIC32MX5XX/6XX/7XX
dev ices to execute from data memor y.
Key features include:
• 32-bit native data width
• Se p ara te User (KUSEG) and Kernel (KSEG0/
KSEG1) mode address spa ce
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
progra m space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Simple memory mapping with Fixed Mapping
Translation (FMT) u nit
• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions
4.1 Memory Layout
PIC32MX5XX/6XX/7XX microcontrollers implement
two address schemes: virtual and physical. All
hardware resources, such as program memory, data
memory and peripherals, are located at thei r respectiv e
physical addresses. Virtual addresses are exclusively
used by the CPU to fetch and execute instructions as
well as access peripherals. Physical addresses are
used by bus master peripherals, such as DMA and the
Flash controller, that access memory independently of
the CPU.
The memory maps for the PIC32MX5XX/6XX/7XX
devi ces are illu strated in Figure 4-1 through Figure 4-6.
Table 4-1 provides memory map information for the
Special Function Registers (SFRs).
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. For
detailed information, refer to Section 3.
“Memory Organization” (DS60001115)
in the “PIC32 Family R efere nce Manua l”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX
DS60001156J-page 48 2009-2016 Microchip Technology Inc.
FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L,
PIC32MX664F064H AND PIC32MX664F064L DEVICES
Virtual
Memory Map
(1)
Physical
Memory Map
(1)
0xFFFFFFFF Reserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Devic e
Configuration
Registers
0xBFC02FF0
0xBFC02FEF Boot Flash
0xBFC00000
Reserved
0xBF900000
0xBF8FFFFF SFRs
0xBF800000
Reserved
0xBD010000
0xBD00FFFF Program Flash
(2)
0xBD000000
Reserved
0xA0008000
0xA0007FFF RAM
(2)
0xA0000000 0x1FC03000
Reserved Device
Configuration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF Device
Configuration
Registers
0x1FC02FF0
Boot Flash 0x1FC02FEF
0x9FC02FF0
0x9FC02FEF Boot Flash 0x1FC00000
Reserved
0x9FC00000 0x1F900000
Reserved SFRs 0x1F8FFFFF
0x9D010000 0x1F800000
0x9D00FFFF Progr am Flas h
(2)
Reserved
0x9D000000 0x1D010000
Reserved Prog ram F lash
(2)
0x1D00FFFF
0x80008000
0x80007FFF RAM
(2)
0x1D000000
Reserved
0x80000000 0x00008000
Reserved RAM
(2)
0x00007FFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentat ion for information).
KSEG1KSEG0
2009-2016 Microchip Technology Inc. DS60001156J- page 49
PIC32MX5XX/6XX/7XX
FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L
DEVICES
Virtual
Memory Map
(1)
Physical
Memory Map
(1)
0xFFFFFFFF Reserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Devic e
Configuration
Registers
0xBFC02FF0
0xBFC02FEF Boot Flash
0xBFC00000
Reserved
0xBF900000
0xBF8FFFFF SFRs
0xBF800000
Reserved
0xBD010000
0xBD00FFFF Program Flash
(2)
0xBD000000
Reserved
0xA0004000
0xA0003FFF RAM
(2)
0xA0000000 0x1FC03000
Reserved Device
Configuration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF Device
Configuration
Registers
0x1FC02FF0
Boot Flash 0x1FC02FEF
0x9FC02FF0
0x9FC02FEF Boot Flash 0x1FC00000
Reserved
0x9FC00000 0x1F900000
Reserved SFRs 0x1F8FFFFF
0x9D010000 0x1F800000
0x9D00FFFF Progr am Flas h
(2)
Reserved
0x9D000000 0x1D010000
Reserved Prog ram F lash
(2)
0x1D00FFFF
0x80004000
0x80003FFF RAM
(2)
0x1D000000
Reserved
0x80000000 0x00004000
Reserved RAM
(2)
0x00003FFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentat ion for information).
KSEG1KSEG0
PIC32MX5XX/6XX/7XX
DS60001156J-page 50 2009-2016 Microchip Technology Inc.
FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L,
PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND
PIC32MX764F128L DEVICES
Virtual
Memory Map
(1)
Physical
Memory Map
(1)
0xFFFFFFFF Reserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Devic e
Configuration
Registers
0xBFC02FF0
0xBFC02FEF Boot Flash
0xBFC00000
Reserved
0xBF900000
0xBF8FFFFF SFRs
0xBF800000
Reserved
0xBD020000
0xBD01FFFF Program Flash
(2)
0xBD000000
Reserved
0xA0008000
0xA0007FFF RAM
(2)
0xA0000000 0x1FC03000
Reserved Device
Configuration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF Device
Configuration
Registers
0x1FC02FF0
Boot Flash 0x1FC02FEF
0x9FC02FF0
0x9FC02FEF Boot Flash 0x1FC00000
Reserved
0x9FC00000 0x1F900000
Reserved SFRs 0x1F8FFFFF
0x9D020000 0x1F800000
0x9D01FFFF Progr am Flas h
(2)
Reserved
0x9D000000 0x1D020000
Reserved Prog ram F lash
(2)
0x1D01FFFF
0x80008000
0x80007FFF RAM
(2)
0x1D000000
Reserved
0x80000000 0x00008000
Reserved RAM
(2)
0x00007FFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentat ion for information).
KSEG1KSEG0
2009-2016 Microchip Technology Inc. DS60001156J- page 51
PIC32MX5XX/6XX/7XX
FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32M X5 75F 25 6H, PIC3 2MX 57 5F256 L,
PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND
PIC32MX775F256L DEVICES
Virtual
Memory Map
(1)
Physical
Memory Map
(1)
0xFFFFFFFF Reserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Devic e
Configuration
Registers
0xBFC02FF0
0xBFC02FEF Boot Flash
0xBFC00000
Reserved
0xBF900000
0xBF8FFFFF SFRs
0xBF800000
Reserved
0xBD040000
0xBD03FFFF Program Flash
(2)
0xBD000000
Reserved
0xA0010000
0xA000FFFF RAM
(2)
0xA0000000 0x1FC03000
Reserved Device
Configuration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF Device
Configuration
Registers
0x1FC02FF0
Boot Flash 0x1FC02FEF
0x9FC02FF0
0x9FC02FEF Boot Flash 0x1FC00000
Reserved
0x9FC00000 0x1F900000
Reserved SFRs 0x1F8FFFFF
0x9D040000 0x1F800000
0x9D03FFFF Progr am Flas h
(2)
Reserved
0x9D000000 0x1D040000
Reserved Prog ram F lash
(2)
0x1D03FFFF
0x80008000
0x8000FFFF RAM
(2)
0x1D000000
Reserved
0x80000000 0x00010000
Reserved RAM
(2)
0x0000FFFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentat ion for information).
KSEG1KSEG0
PIC32MX5XX/6XX/7XX
DS60001156J-page 52 2009-2016 Microchip Technology Inc.
FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L,
PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND
PIC32MX775F512L DEVICES
Virtual
Memory Map
(1)
Physical
Memory Map
(1)
0xFFFFFFFF Reserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Devic e
Configuration
Registers
0xBFC02FF0
0xBFC02FEF Boot Flash
0xBFC00000
Reserved
0xBF900000
0xBF8FFFFF SFRs
0xBF800000
Reserved
0xBD080000
0xBD07FFFF Program Flash
(2)
0xBD000000
Reserved
0xA0010000
0xA000FFFF RAM
(2)
0xA0000000 0x1FC03000
Reserved Device
Configuration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF Device
Configuration
Registers
0x1FC02FF0
Boot Flash 0x1FC02FEF
0x9FC02FF0
0x9FC02FEF Boot Flash 0x1FC00000
Reserved
0x9FC00000 0x1F900000
Reserved SFRs 0x1F8FFFFF
0x9D080000 0x1F800000
0x9D07FFFF Prog ram Flas h
(2)
Reserved
0x9D000000 0x1D080000
Reserved Prog ram F lash
(2)
0x1D07FFFF
0x80010000
0x8000FFFF RAM
(2)
0x1D000000
Reserved
0x80000000 0x00010000
Reserved RAM
(2)
0x0000FFFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).
KSEG1KSEG0
2009-2016 Microchip Technology Inc. DS60001156J- page 53
PIC32MX5XX/6XX/7XX
FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L,
PIC32MX795F512H AND PIC32MX795F512L DEVICES
Virtual
Memory Map
(1)
Physical
Memory Map
(1)
0xFFFFFFFF Reserved
Reserved
0xFFFFFFFF
0xBFC03000
0xBFC02FFF Devic e
Configuration
Registers
0xBFC02FF0
0xBFC02FEF Boot Flash
0xBFC00000
Reserved
0xBF900000
0xBF8FFFFF SFRs
0xBF800000
Reserved
0xBD080000
0xBD07FFFF Program Flash
(2)
0xBD000000
Reserved
0xA0020000
0xA001FFFF RAM
(2)
0xA0000000 0x1FC03000
Reserved Device
Configuration
Registers
0x1FC02FFF
0x9FC03000
0x9FC02FFF Device
Configuration
Registers
0x1FC02FF0
Boot Flash 0x1FC02FEF
0x9FC02FF0
0x9FC02FEF Boot Flash 0x1FC00000
Reserved
0x9FC00000 0x1F900000
Reserved SFRs 0x1F8FFFFF
0x9D080000 0x1F800000
0x9D07FFFF Prog ram Flas h
(2)
Reserved
0x9D000000 0x1D080000
Reserved Prog ram F lash
(2)
0x1D07FFFF
0x80020000
0x8001FFFF RAM
(2)
0x1D000000
Reserved
0x80000000 0x00020000
Reserved RAM
(2)
0x0001FFFF
0x00000000 0x00000000
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).
KSEG1KSEG0
PIC32MX5XX/6XX/7XX
DS60001156J-page 54 2009-2016 Microchip Technology Inc.
TABLE 4-1: SFR MEMORY MAP
Peripheral
Virtual Address
Base Offset
Start
Watchdog Timer
0xBF80
0x0000
RTCC 0x0200
Timer1-Timer5 0x0600
Input Capture 1-5 0x2000
Output Co mpare 1-5 0x3000
I2C1-I2C5 0x5000
SPI1-SPI4 0x5800
UART1-UART6 0x6000
PMP 0x7000
ADC 0x9000
CV
REF
0x9800
Comparator 0xA000
Oscillator 0xF000
Device and Re vision ID 0xF200
Flash Controller 0xF400
Reset 0xF600
Interrupts
0xBF88
0x1000
Bus Matrix 0x 2000
DMA 0x3000
Prefetch 0x4000
USB 0x5040
PORTA-PORTG 0x6000
Ethernet 0x9000
Configuration 0xBFC0 0x2FF0
2009-2016 Microchip Technology Inc. DS60001156J-page 55
PIC32MX5XX/6XX/7XX
4.2 Control Registers
Register 4-1 through Register 4-8 are used for setting the RAM and Flash memory partitions for data and code.
TABLE 4-2: BUS MATRIX REGISTER MAP
Virtual Address
(BF88_#)
Register
Name
Bit Range
Bits
All
Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2000 BMXCON
(1)
31:16 — — — — — BMXCHEDMA — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F
15:0 — — — — — — — — —BMXWSDRM — — — BMXARB<2:0> 0041
2010 BMXDKPBA
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 BMXDKPBA<15:0> 0000
2020 BMXDUDBA
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 BMXDUDBA<15:0> 0000
2030 BMXDUPBA
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 BMXDUPBA<15:0> 0000
2040 BMXDRMSZ 31:16 BMXDRMSZ<31:0> xxxx
15:0 xxxx
2050 BMXPUPBA
(1)
31:16 — — — — — — — — — — — — BMXPUPBA<19:16> 0000
15:0 BMXPUPBA<15:0> 0000
2060 BMXPFMSZ 31:16 BMXPFMSZ<31:0> xxxx
15:0 xxxx
2070 BMXBOOTSZ 31:16 BMXBOOTSZ<31:0> 0000
15:0 3000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Rese t v alu es ar e s ho wn i n he x ade ci ma l.
Note 1: Thi s r eg ist er ha s cor re sp on di n g CLR , SE T an d INV re gis t er s at i ts virtua l add re s s, pl us a n offset of 0x4 , 0x8 an d 0x C , r esp ec t ively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 56 2009-2016 Microchip Technology Inc.
REGISTER 4-1: BMXCON: BUS MATRIX CONFIGURATION REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — BMX
ERRIXI BMX
ERRICD BMX
ERRDMA BMX
ERRDS BMX
ERRIS
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1
—BMX
WSDRM — — — BMXARB<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 31-21 Unimplemented: Read as ‘0’
bit 20 BMXERRIXI: Enable Bus Error from IXI bit
1= Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
0= Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit
1= Enable bus error exceptions for unmapped address accesses initiated from ICD
0= Disable bus error exceptions for unmapped address accesses initiated from ICD
bit 18 BMXERRDMA: Bus Error from DMA bit
1= Enable bus error exceptions for unmapped address accesses initiated from DMA
0= Disable bus error exceptions for unmapped address accesses initiated from DMA
bit 17 BMXERRDS: Bus Error from CPU Data Access bi t (disabled in Debug mode)
1= Enable bus error exceptions for unmapped address accesses initiated from CPU data access
0= Disable bus error exceptions for unmapped address accesses initiated from CPU data access
bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in D ebug mode)
1= Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
0= Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
bit 15-7 Unimplemented: Read as ‘0’
bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit
1= Data RAM accesses from CPU have one wait state for address setup
0= Data RAM accesses from CPU have zero wait states for address setup
bit 5-3 Unimplemented: Read as ‘ 0’
bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits
111 = Reserved (using these Configuration modes will produce undefined behavior)
•
•
•
011 = Reserved (using these Configuration modes will produce undefined behavior)
010 = Ar bitration Mode 2
001 = Arbitration Mode 1 (default)
000 = Ar bitration Mode 0
2009-2016 Microchip Technology Inc. DS60001156J- page 57
PIC32MX5XX/6XX/7XX
REGISTER 4-2: BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0
BMXDKPBA<15:8>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
BMXDKPBA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits
When non-zero, this value selects the rela tive base address for kernel program space in RAM
bit 9-0 BMXDKPBA<9:0>: DRM Kernel Program Base Address Read-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1: At Reset, the va lue in thi s reg ister is forc ed to z ero, which cau se s all of the RAM to be alloc ate d to Kern al
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
PIC32MX5XX/6XX/7XX
DS60001156J-page 58 2009-2016 Microchip Technology Inc.
REGISTER 4-3: BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0
BMXDUDBA<15:8>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
BMXDUDBA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUDBA<15:10>: DRM User Data Base Address bits
When non-ze ro, th e valu e sele cts the re lati ve base a ddres s for Use r mode data space i n RAM, the val ue
must be greater than BMXDKPBA.
bit 9-0 BMXDUDBA<9:0>: DRM User Data Base Address Re ad-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1: At Reset, the va lue in thi s reg ister is forc ed to z ero, which cau se s all of the RAM to be alloc ate d to Kern al
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
2009-2016 Microchip Technology Inc. DS60001156J- page 59
PIC32MX5XX/6XX/7XX
REGISTER 4-4: BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0
BMXDUPBA<15:8>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
BMXDUPBA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-10 BMXDUPBA<15:10>: DRM User Program Base Address bits
When non-zero, the value selects the relative base address for User mode program space in RAM,
BMXDUPBA must be greater than BMXDUDBA.
bit 9-0 BMXDUPBA<9:0>: DRM Us er Program Base Add ress Read-Only bits
Value is always ‘0’, which forces 1 KB increments
Note 1: At Reset, the va lue in thi s reg ister is forc ed to z ero, which cau se s all of the RAM to be alloc ate d to Kern al
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.
PIC32MX5XX/6XX/7XX
DS60001156J-page 60 2009-2016 Microchip Technology Inc.
REGISTER 4-5: BMXDRMSZ: DATA RAM SIZE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
RRRRR R R R
BMXDRMSZ<31:24>
23:16
RRRRR R R R
BMXDRMSZ<23:16>
15:8
RRRRR R R R
BMXDRMSZ<15:8>
7:0
RRRRR R R R
BMXDRMSZ<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits
Static value that indicates the size of the Data RAM in bytes:
0x00004000 = device has 16 KB RAM
0x00008000 = device has 32 KB RAM
0x00010000 = device has 64 KB RAM
REGISTER 4-6: BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS
REGISTER
(1,2)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
———— BMXPUPBA<19:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
BMXPUPBA<15:8>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
BMXPUPBA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-20 Unimplemented: Read as ‘0’
bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits
bit 10-0 BMXPUPBA<10:0>: Program Flash (PFM) User Program Base Address Read-Only bits
Value is always ‘0’, which forces 2 KB increments
Note 1: At Reset, the va lue in thi s reg ister is forc ed to z ero, which cau se s all of the RAM to be alloc ate d to Kern al
mode data usage.
2: The value in this register must be less than or equal to BMXPFMSZ.
2009-2016 Microchip Technology Inc. DS60001156J- page 61
PIC32MX5XX/6XX/7XX
REGISTER 4-7: BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
RRRRR R R R
BMXPFMSZ<31:24>
23:16
RRRRR R R R
BMXPFMSZ<23:16>
15:8
RRRRR R R R
BMXPFMSZ<15:8>
7:0
RRRRR R R R
BMXPFMSZ<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits
Static value that indicates the size of the PFM in bytes:
0x00010000 = device has 64 KB Flash
0x00020000 = device has 128 KB Flash
0x00040000 = device has 256 KB Flash
0x00080000 = device has 512 KB Flash
REGISTER 4-8: BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
RRRRR R R R
BMXBOOTSZ<31:24>
23:16
RRRRR R R R
BMXBOOTSZ<23:16>
15:8
RRRRR R R R
BMXBOOTSZ<15:8>
7:0
RRRRR R R R
BMXBOOTSZ<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits
Static value that indicates the size of the Boot PFM in bytes:
0x00003000 = device has 12 KB boot Flash
PIC32MX5XX/6XX/7XX
DS60001156J-page 62 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 63
PIC32MX5XX/6XX/7XX
5.0 FLASH PROGRAM MEMORY
PIC32MX5XX/6XX/7XX devices contain an internal
Flash prog ram me mory for ex ecuti ng user code. Ther e
are three methods by which the user can program this
memory:
• Run-Time Self-Programming (RTSP)
• EJTAG Programming
• In-Circuit Serial Programming™ (ICSP™)
RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP
techniques is available in Section 5. “Flash Program
Memory” (DS60001121) in the “PIC32 Family
Refere nce Manu al”.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is perfo rmed using a serial da ta connecti on to the
device and allows much faster programming times tha n
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32 Flash Programming Specification”
(DS60001145), which can be downloaded from the
Microchip web site.
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 5. “Flash
Program Memory” (DS60001121) in the
“PI C32 Fami ly Re ferenc e Manua l” , which
is available from the Microchip web site
(www.microchip.com/PIC32).
Note: For PIC32MX5XX/6XX/7XX devices, the
Flash page size is 4 KB and the row size
is 512 bytes (1024 IW and 128 IW,
respectively).
PIC32MX5XX/6XX/7XX
DS60001156J-page 64 2009-2016 Microchip Technology Inc.
5.1 Control Registers
TABLE 5-1: FLASH CONTROLLER REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
F400 NVMCON
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 WR WREN WRERR LVDERR LVDSTAT — — — — — — — NVMOP<3:0> 0000
F410 NVMKEY 31:16 NVMKEY<31:0> 0000
15:0 0000
F420
NVMADDR
(1)
31:16 NVMADDR<31:0> 0000
15:0 0000
F430 NVMDATA 31:16 NVMDATA<31:0> 0000
15:0 0000
F440 NVMSRC
ADDR 31:16 NVMSRCADDR<31:0> 0000
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
2009-2016 Microchip Technology Inc. DS60001156J- page 65
PIC32MX5XX/6XX/7XX
REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0, HC R/W-0 R-0, HS R-0, HS R-0, HSC U-0 U-0 U-0
WR WREN WRERR
(1)
LVDERR
(1)
LVDSTAT
(1)
— — —
7:0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
————NVMOP<3:0>
Legend: U = Unimplemented bit, read as ‘0’ HSC = Set and Cleared by hardware
R = Readable bit W = Writable bit HS = Set by hardware HC = Cleared by hardware
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 WR: Write Control bit
This bit is w ritable when WREN = 1 and the unlock sequence is followed.
1 = Initiate a Flash operation. Hardware clears this bit when the operation completes
0 = Flash operation complete or inactive
bit 14 WREN: Write Enable bit
1 = Enable writes to WR bit and enables LVD circuit
0 = Disabl e writes to WR bit and disable s LVD circuit
Note: This is the only bit in this register that is reset by a device Reset.
bit 13 WRERR: W rite Error bit
(1)
This bit is read-only and is automatically set by hardware.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)
(1)
This bit is read-only and is automatically set by hardware.
1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming
bit 11 LVDST AT: Low-Voltage Detect Status bit (LVD circuit must be enabled)
(1)
This bit is read-only and is automatically set, and cleared, by hardware.
1 = Low-voltage event is active
0 = Low-voltage event is not active
bit 10-4 Unimplemented: Read as ‘0’
bit 3-0 NVMOP<3:0>: NVM Operation bits
These bits are writable when WREN = 0.
1111 = Reserved
•
•
•
0111 = Reserved
0110 = No operation
0101 = Program Flash (PFM) erase operation: erases PFM if all pages are not write-protected
0100 = Page erase operation: erases page selected by NVMADDR if it is not write-protected
0011 = Row program operation: programs row selected by NVMADDR if it is not write-protected
0010 = No operation
0001 = Word program operation: programs word selected by NVMADDR if it is not write-protected
0000 = No operation
Note 1: This bit is cleared by setting NVMOP == 0000b, and initiating a Fl ash operation (i.e., WR).
PIC32MX5XX/6XX/7XX
DS60001156J-page 66 2009-2016 Microchip Technology Inc.
REGISTER 5-2: NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<31:24>
23:16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<23:16>
15:8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<15:8>
7:0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
NVMKEY<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMKEY<31:0>: Unlock Register bits
These bits are write-only, and read as ‘0’ on any read.
Note: This register is used as part of the unlock sequence to prevent inadverten t writes to the PFM.
REGISTER 5-3: NVMADDR: FLASH ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMADDR<31:0>: Flash Address bits
Bulk/C hip/PFM Erase: Addre s s is ignored.
Page Erase: Address identifies the page to erase.
Row Program: Address identifies the row to program.
Word Program: Address identifies the word to program.
2009-2016 Microchip Technology Inc. DS60001156J- page 67
PIC32MX5XX/6XX/7XX
REGISTER 5-4: NVMDATA: FLASH PROGRAM DATA REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATA<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATA<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATA<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMDATA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMDATA<31:0>: Flash Programming Data bits
Note: The bits in this register are only reset by a Power-on Reset (POR).
REGISTER 5-5: NVMSRCADDR: SOURCE DATA ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 NVMSRCADDR<31:0>: Source Data Addre ss bit s
The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits
(NVMCON<3:0>) are set to perform row programm ing.
PIC32MX5XX/6XX/7XX
DS60001156J-page 68 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 69
PIC32MX5XX/6XX/7XX
6.0 RESETS
The Reset module combines all Reset sources and
controls the device Ma ster Re se t s ignal , SYSRST. Th e
following is a list of device Reset sources:
• Power-on Reset (POR)
• Master Clear Reset pin (MCLR)
• Software Reset (SWR)
• Watchdog Timer Reset (WDTR)
• Brown-out Reset (BOR)
• Configuration Mismatch Reset (CMR)
A simplified block diagram of the Reset module is
illustrated in Figure 6-1.
FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 7. “Resets”
(DS60001118) in the “PIC32 Family Ref-
erence Manual”, which is available from
the Microchip web site
(www.microchip.com/PIC32).
MCLR
V
DD
V
DD
Rise
Detect
POR
Sleep or Idle
Brown-out
Reset
WDT
Time-out
Glitch Filter
BOR
Configuration
SYSRST
Software Reset
Power-up
Timer
Voltage
Enabled
Reset
WDTR
SWR
CMR
MCLR
Mismatch
Regulator
PIC32MX5XX/6XX/7XX
DS60001156J-page 70 2009-2016 Microchip Technology Inc.
6.1 Control Registers
TABLE 6-1: RESETS REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
(2)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
F600 RCON 31:16 ————————————————0000
15:0 —————— CMR VREGS EXTR SWR — WDTO SLEEP IDLE BOR POR 0000
F610 RSWRST 31:16 ————————————————0000
15:0 ———————————————SWRST0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
2009-2016 Microchip Technology Inc. DS60001156J- page 71
PIC32MX5XX/6XX/7XX
REGISTER 6-1: RCON: RESET CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0
— — — — — — CMR VREGS
7:0
R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W- 1, HS
EXTR SWR — WDTO SLEEP IDLE BOR
(1)
POR
(1)
Legend: HS = Set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-10 Unimplemented: Read as ‘0’
bit 9 CMR: Configuration Mismatch Reset Flag bit
1 = Configuration mism atch Reset has occurred
0 = Configuration mismatch Reset has not occurred
bit 8 VREGS: Voltage Regulator Standby Enable bit
1 = Regulator is enabled and is on during Sleep mode
0 = Regulator is set to Stand-by Tracking mode
bit 7 EXTR: External Reset (MCLR) Pin Flag bit
1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset Flag bit
1 = Soft ware Reset was executed
0 = Soft ware Reset was not executed
bit 5 Unimplemented: Read as ‘0’
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred
bit 3 SLEEP: Wake From Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
bit 2 IDLE: Wake From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1 BOR: Brown-out Reset Flag bit
(1)
1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
(1)
1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred
Note 1: User software must clear this bit to view the next detection.
PIC32MX5XX/6XX/7XX
DS60001156J-page 72 2009-2016 Microchip Technology Inc.
REGISTER 6-2: RSWRST: SOFTWARE RESET REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC
— — — — — — —SWRST
(1)
Legend: HC = Cle ared by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-1 Unimplemented: Read as ‘0’
bit 0 SWRST: Software Reset Trigger bit
(1)
1 = Enable software Reset event
0 = No effect
Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section
6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details.
2009-2016 Microchip Technology Inc. DS60001156J- page 73
PIC32MX5XX/6XX/7XX
7.0 INTERRUPT CONTROLLER
PIC32MX5XX/6XX/7XX devices generate interrupt
requests in response to interrupt events from peripheral
modules. The interrupt control module exists externally
to the CPU logic and prioritizes the interrupt events
before presenting them to the CPU.
The Interrupt Controller module includes the following
features:
• Up to 96 interrupt sources
• Up to 64 interrupt vectors
• Single and multi-vector mode operations
• Five extern al int errup t s w ith edg e pola rity contr ol
• Interrupt proximity timer
• Seven user-selectable priority levels for each vector
• Four user-selectable sub-p rior ity levels within each
priority
• Dedicated shadow set for user-selectable priority
level
• Software can generate any interrupt
• User-configurable interrupt vector table location
• User-configurable interrupt vector spacing
A simplified block diagram of the Interrupt Controller
module is illustrated in Figure 7-1.
FIGURE 7-1: INTERRUPT CONTROLLER MODULE
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupts”
(DS60001108) in the “PIC32 Family Ref-
erence Manual”, which is available from
the Microchip web site
(www.microchip.com/PIC32).
Interrupt Controller
Interrupt Requests
Vector Number
CPU Core
Priority Level
Shadow Set Number
PIC32MX5XX/6XX/7XX
DS60001156J-page 74 2009-2016 Microchip Technology Inc.
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION
Interrupt Source
(1)
IRQ
Number Vector
Number
Interrupt Bit Location
Flag Enable Priority Sub-Priority
Highest Natural Order Priority
CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0>
CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8>
CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16>
INT0 – External Interrupt 0 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24>
T1 – Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0>
IC1 – Input Capture 1 5 5 IFS0<5> IEC0<5 > IPC1< 12:10> IPC1<9:8>
OC1 – Output Compare 1 6 6 IFS0<6> IEC0<6> IPC1<20:18> IPC1<17:16>
INT1 – External Interrupt 1 7 7 IFS0<7> IEC0<7> IPC1<28:26> IPC1<25:24>
T2 – Timer2 8 8 IFS0<8> IEC0<8> IPC2<4:2> IPC2<1:0>
IC2 – Input Capture 2 9 9 IFS0<9> IEC0<9 > IPC2< 12:10> IPC2<9:8>
OC2 – Output Compare 2 10 10 IFS0<10> IEC0<10> IPC2<20:18> IPC2<17:16>
INT2 – External Interrupt 2 11 11 IFS0<11> IEC0<11> IPC2<28:26> IPC2<25:24>
T3 – Timer3 12 12 IFS0<12> IEC0<12> IPC3<4:2> IPC3<1:0>
IC3 – Input Capture 3 13 13 IFS0<13> IEC0<13> IPC3<12:10> IPC3<9:8>
OC3 – Output Compare 3 14 14 IFS0<14> IEC0<14> IPC3<20:18> IPC3<17:16>
INT3 – External Interrupt 3 15 15 IFS0<15> IEC0<15> IPC3<28:26> IPC3<25:24>
T4 – Timer4 16 16 IFS0<16> IEC0<16> IPC4<4:2> IPC4<1:0>
IC4 – Input Capture 4 17 17 IFS0<17> IEC0<17> IPC4<12:10> IPC4<9:8>
OC4 – Output Compare 4 18 18 IFS0<18> IEC0<18> IPC4<20:18> IPC4<17:16>
INT4 – External Interrupt 4 19 19 IFS0<19> IEC0<19> IPC4<28:26> IPC4<25:24>
T5 – Timer5 20 20 IFS0<20> IEC0<20> IPC5<4:2> IPC5<1:0>
IC5 – Input Capture 5 21 21 IFS0<21> IEC0<21> IPC5<12:10> IPC5<9:8>
OC5 – Output Compare 5 22 22 IFS0<22> IEC0<22> IPC5<20:18> IPC5<17:16>
SPI1E – SPI1 Fault 23 23 IFS0<23> IEC0<23> IPC5<28:26> IPC5<25:24>
SPI1RX – SPI1 Receive Done 24 23 IFS0<2 4> IEC0<24> IPC5<28 :26> IPC5<25: 24>
SPI1TX – SPI1 Transfer Done 25 23 IFS0<25> IEC0<25> IPC5<28:26> IPC5<25:24>
U1E – UART1 Error 26 24 IFS0<26> IEC0<26> IPC6<4:2> IPC6<1:0>SPI3E – SPI3 Fault
I2C3B – I2C3 Bus Collision Event
U1RX – UART1 Receiver 27 24 IFS0<27> IEC0<27> IPC6<4:2> IPC6<1:0>SPI3RX – SPI3 Receive Done
I2C3S – I2C3 Slave Event
U1TX – UAR T1 Transmitte r 28 24 IFS0<28> IEC0<28> IPC6<4:2> IPC6<1:0>SPI3TX – SPI3 Transfer Done
I2C3M – I2C3 Master Event
I2C1B – I2C1 Bus Collision Event 29 25 IFS0<29> IEC0<29> IPC6<12:10> IPC6<9:8>
I2C1S – I2C1 Slave Event 30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8>
I2C1M – I2C1 Master Event 31 25 IFS0<31> IEC0<31> IPC6<12:10> IPC6<9:8>
CN – Input Change Interrupt 32 26 IFS1<0> IEC1<0> IPC6<20:18> IPC6<17:16>
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX5XX USB and CAN
Features”, TABLE 2: “PIC32MX6XX USB an d Ethern et Features” and TABLE 3: “PIC32MX7XX USB,
Ethernet, and CAN Features” for the list of available peripherals.
2009-2016 Microchip Technology Inc. DS60001156J- page 75
PIC32MX5XX/6XX/7XX
AD1 – ADC1 Convert Done 33 27 IFS1<1> IEC1<1> IPC6<28:26> IPC6<25:24>
PMP – Parall el Master Port 34 28 IFS1<2> IEC1<2> IPC7<4:2> IPC7<1:0>
CMP1 – Co mparator Interrupt 35 29 IFS1<3> IEC1<3> IPC7<12:10> IPC7<9:8>
CMP2 – Co mparator Interrupt 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16>
U2E – UART2 Error
SPI2E – SPI2 Fault
I2C4B – I2C4 Bus Collision Event 37 31 IFS1<5> IEC1<5> IPC7<28:26> IPC7<25:24>
U2RX – UART2 Receiver
SPI2RX – SPI2 Receive Done
I2C4S – I2C4 Slave Event 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24>
U2TX – UART2 Transmitter
SPI2TX – SPI2 Transfer Done
IC4M – I2C4 Master Event 39 31 IFS1<7> IEC1<7> IPC7<28:26> IPC7<25:24>
U3E – UART3 Error
SPI4E – SPI4 Fault
I2C5B – I2C5 Bus Collision Event 40 32 IFS1<8> IEC1<8> IPC8<4:2> IPC8<1:0>
U3RX – UART3 Receiver
SPI4RX – SPI4 Receive Done
I2C5S – I2C5 Slave Event 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0>
U3TX – UART3 Transmitter
SPI4TX – SPI4 Transfer Done
IC5M – I2C5 Mast er Event 42 32 IFS1<10> IEC1<10> IPC8<4:2> IPC8<1:0>
I2C2B – I2C2 Bus Collision Event 43 33 IFS1<11> IEC1<11> IPC8<12:10> IPC8<9:8>
I2C2S – I2C2 Slave Event 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8>
I2C2M – I2C2 Master Event 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8>
FSCM – Fail-Safe Clock Monitor 46 34 IFS1<14> IEC1<14> IPC8<20:18> IPC8<17:16>
RTCC – Real-Time Clock and
Calendar 47 35 IFS1<15> IEC1<15> IPC8<28:26> IPC8<25:24>
DMA0 – DMA Channel 0 48 36 IFS1<16> IEC1<16> IPC9<4:2> IPC9<1:0>
DMA1 – DMA Channel 1 49 37 IFS1<17> IEC1<17> IPC9<12:10> IPC9<9:8>
DMA2 – DMA Channel 2 50 38 IFS1<18> IEC1<18> IPC9<20:18> IPC9<17:16>
DMA3 – DMA Channel 3 51 39 IFS1<19> IEC1<19> IPC9<28:26> IPC9<25:24>
DMA4 – DMA Channel 4 52 40 IFS1<20> IEC1<20> IPC10<4:2> IPC10<1:0>
DMA5 – DMA Channel 5 53 41 IFS1<21> IEC1<21> IPC10<12:10> IPC10<9:8>
DMA6 – DMA Channel 6 54 42 IFS1<22> IEC1<22> IPC10<20:18> IPC10<17:16>
DMA7 – DMA Channel 7 55 43 IFS1<23> IEC1<23> IPC10<28:26> IPC10<25:24>
FCE – Flash Control Event 56 44 IFS1<24> IEC1<24> IPC11<4:2> IPC11<1:0>
USB – USB Interrupt 57 45 IFS1<25> IEC1<25> IPC11<12:10> IPC11<9:8>
CAN1 – Control Area Network 1 58 46 IFS1<26> IEC1<26> IPC11<20:18> IPC11<17:16>
CAN2 – Control Area Network 2 59 47 IFS1<27> IEC1<27> IPC11<28:26> IPC11<25:24>
ETH – Ethernet Interrupt 60 48 IFS1<28> IEC1<28> IPC12<4:2> IPC12<1:0>
IC1E – Input Capture 1 Error 61 5 IFS1<29> IEC1<29> IPC1<12:10> IPC1<9:8>
IC2E – Input Capture 2 Error 62 9 IFS1<30> IEC1<30> IPC2<12:10> IPC2<9:8>
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source
(1)
IRQ
Number Vector
Number
Interrupt Bit Location
Flag Enable Priority Sub-Priority
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX5XX USB and CAN
Features”, TABLE 2: “PIC32MX6XX USB an d Ethern et Features” and TABLE 3: “PIC32MX7XX USB,
Ethernet, and CAN Features” for the list of available peripherals.
PIC32MX5XX/6XX/7XX
DS60001156J-page 76 2009-2016 Microchip Technology Inc.
IC3E – Input Capture 3 Error 63 13 IFS1<31> IEC1<31> IPC3<12:10> IPC3<9:8>
IC4E – Input Capture 4 Error 64 17 IFS2<0> IEC2<0> IPC4<12:10> IPC4<9:8>
IC5E – Input Capture 5 Error 65 21 IFS2<1> IEC2<1> IPC5<12:10> IPC5<9:8>
PMPE – Parallel Master Port Error 66 28 IFS2<2> IEC2<2> IPC7<4:2> IPC7<1:0>
U4E – UART4 Error 67 49 IFS2<3> IEC2<3> IPC12<12:10 > IPC12<9:8>
U4RX – UART4 Receiver 68 49 IFS2<4> IEC2<4> IPC12<12:10> IPC12<9:8>
U4TX – UAR T4 Transmitter 69 49 IFS2<5 > IEC2<5> IPC12<12:10> IPC12<9:8>
U6E – UART6 Error 70 50 IFS2<6> IEC2<6> IPC12<20:18> IPC12<17:16>
U6RX – UART6 Receiver 71 50 IFS2<7> IEC2<7> IPC12<20:18> IPC12<17:16>
U6TX – UAR T6 Transmitter 72 50 IFS2<8 > IEC2<8> IPC12<20:18> IPC12<17:16 >
U5E – UART5 Error 73 51 IFS2<9> IEC2<9> IPC12<28:26> IPC12<25:24>
U5RX – UART5 Receiver 74 51 IFS2<10> IEC2<10> IPC12<28:26> IPC12<25:24>
U5TX – UAR T5 Transmitter 75 51 IFS2<11> IEC2<11> IPC12<28:2 6> IPC12<25:24>
(Reserved) — — — — — —
Lowest Natural Order Priority
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Source
(1)
IRQ
Number Vector
Number
Interrupt Bit Location
Flag Enable Priority Sub-Priority
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX5XX USB and CAN
Features”, TABLE 2: “PIC32MX6XX USB an d Ethern et Features” and TABLE 3: “PIC32MX7XX USB,
Ethernet, and CAN Features” for the list of available peripherals.
2009-2016 Microchip Technology Inc. DS60001156J-page 77
PIC32MX5XX/6XX/7XX
7.1 Control Registers
TABLE 7-2: INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND
PIC32MX575F512H DEVICES
Virt ual Addre ss
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All
Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
1000 INTCON 31:16 — — — — — — — — — — — — — — — SS0 0000
15:0 — — — MVEC —TPC<2:0>— — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
1010 INTSTAT
(3)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — —SRIPL<2:0>—— VEC<5:0> 0000
1020 IPTMR 31:16 IPTMR<31:0> 0000
15:0 0000
1030 IFS0 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF — — — OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 000031:16 SPI3TXIF SPI3RXIF SPI3EIF
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
1040 IFS1
31:16 IC3EIF IC2EIF IC1EIF —— CAN1IF USBIF FCEIF DMA7IF
(2)
DMA6IF
(2)
DMA5IF
(2)
DMA4IF
(2)
DMA3IF DMA2IF DMA1IF DMA0IF 0000
RTCCIF FSCMIF — — — U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 000015:0 SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
1050 IFS2 31:16
15:0 — — — — — — — — — — — — — — — — 0000
— — — — U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000
1060 IEC0 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE — — — OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 000031:16 SPI3TXIE SPI3RXIE SPI3EIE
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
1070 IEC1
31:16 IC3EIE IC2EIE IC1EIE —— CAN1IE USBIE FCEIE DMA7IE
(2)
DMA6IE
(2)
DMA5IE
(2)
DMA4IE
(2)
DMA3IE DMA2IE DMA1IE DMA0IE 0000
RTCCIE FSCMIE — — — U2TXIE U2RXIE U2EIE U3TXIE U3RXIE U3EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 000015:0 SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
1080 IEC2 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
1090 IPC0 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Res e t v al u es ar e sh ow n in hexa de c i mal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET
and INV Registers” for more information.
2: These bits are not available on PIC32MX534/564/664/764 devices.
3: This register does not have associated CLR, SET, and INV registers.
PIC32MX5XX/6XX/7XX
DS60001156J-page 78 2009-2016 Microchip Technology Inc.
10A0 IPC1 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
10B0 IPC2 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
10D0 IPC4 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
10E0 IPC5 31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
10F0 IPC6
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
— — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0>
000015:0 SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
1100 IPC7 — — — U3IP<2:0> U3IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 000031:16 SPI2IP<2:0> SPI2IS<1:0>
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
1110 IPC8
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
— — — — — — — — — — — U2IP<2:0> U2IS<1:0>
000015:0 SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
1120 IPC9 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
1130 IPC10 31:16 — — — DMA7IP<2:0>
(2)
DMA7IS<1:0>
(2)
— — — DMA6IP<2:0>
(2)
DMA6IS<1:0>
(2)
0000
15:0 — — — DMA5IP<2:0>
(2)
DMA5IS<1:0>
(2)
— — — DMA4IP<2:0>
(2)
DMA4IS<1:0>
(2)
0000
1140 IPC11 31:16 — — — — — — — — — — — CAN1IP<2:0> CAN1IS<1:0> 0000
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
1150 IPC12 31:16 — — —U5IP<2:0> U5IS<1:0>— — — U6IP<2:0> U6IS<1:0> 0000
15:0 — — —U4IP<2:0> U4IS<1:0>— — — — — — — — 0000
TABLE 7-2: INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND
PIC32MX575F512H DEVICES (CONTINUED)
Virt ua l Addr es s
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All
Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Res e t v al u es ar e sh ow n in hexa de c i mal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET
and INV Registers” for more information.
2: These bits are not available on PIC32MX534/564/664/764 devices.
3: This register does not have associated CLR, SET, and INV registers.
2009-2016 Microchip Technology Inc. DS60001156J-page 79
PIC32MX5XX/6XX/7XX
TABLE 7-3: INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
1000 INTCON 31:16 ———————————————SS00000
15:0 — — — MVEC — TPC<2:0> ——— INT4EP INT3EP INT2EP INT1EP INT0EP 0000
1010 INTSTAT
(3)
31:16 ————————————————0000
15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000
1020 IPTMR 31:16 IPTMR<31:0> 0000
15:0 0000
1030 IFS0 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF ——— OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 000031:16 SPI3TXIF SPI3RXIF SPI3EIF
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
1040 IFS1
31:16 IC3EIF IC2EIF IC1EIF ETHIF —— USBIF FCEIF DMA7IF
(2)
DMA6IF
(2)
DMA5IF
(2)
DMA4IF
(2)
DMA3IF DMA2IF DMA1IF DMA0IF 0000
RTCCIF FSCMIF ———U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 000015:0 SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
1050 IFS2 31:16 —— ————————————0000
15:0 ———— U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000
1060 IEC0 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE ——— OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 000031:16 SPI3TXIE SPI3RXIE SPI3EIE
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
1070 IEC1
31:16 IC3EIE IC2EIE IC1EIE ETHIE —— USBIE FCEIE DMA7IE
(2)
DMA6IE
(2)
DMA5IE
(2)
DMA4IE
(2)
DMA3IE DMA2IE DMA1IE DMA0IE 0000
RTCCIE FSCMIE ———U2TXIE U2RXIE U2EIE U3TXIE U3RXIE U3EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 000015:0 SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
1080 IEC2 31:16 ————————————————0000
15:0 ———— U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
1090 IPC0 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
10A0 IPC1 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
10B0 IPC2 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX664 devices.
3: This register does not have associated CLR, SET, and INV registers.
PIC32MX5XX/6XX/7XX
DS60001156J-page 80 2009-2016 Microchip Technology Inc.
10D0 IPC4 31:16 —— — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
10E0 IPC5 31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
10F0 IPC6
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
— — — I2C1IP<2:0> I2C1IS<1:0> ——— U1IP<2:0> U1IS<1:0>
000015:0 SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
1100 IPC7 — — — U3IP<2:0> U3IS<1:0> ——— CMP2IP<2:0> CMP2IS<1:0> 000031:16 SPI2IP<2:0> SPI2IS<1:0>
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
1110 IPC8
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> ——— FSCMIP<2:0> FSCMIS<1:0> 0000
——————————— U2IP<2:0> U2IS<1:0>
000015:0 SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
1120 IPC9 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
1130 IPC10 31:16 — — — DMA7IP<2:0>
(2)
DMA7IS<1:0>
(2)
— — — DMA6IP<2:0>
(2)
DMA6IS<1:0>
(2)
0000
15:0 — — — DMA5IP<2:0>
(2)
DMA5IS<1:0>
(2)
— — — DMA4IP<2:0>
(2)
DMA4IS<1:0>
(2)
0000
1140 IPC11 31:16 ————————————————0000
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
1150 IPC12 31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000
15:0 — — — U4IP<2:0> U4IS<1:0> — — — ETHIP<2:0> ETHIS<1:0> 0000
TABLE 7-3: INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX664 devices.
3: This register does not have associated CLR, SET, and INV registers.
2009-2016 Microchip Technology Inc. DS60001156J-page 81
PIC32MX5XX/6XX/7XX
TABLE 7-4: INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
1000 INTCON 31:16 ——————————————— SS0 0000
15:0 — — —MVEC— TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
1010 INTSTAT
(3)
31:16 ————————————————0000
15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000
1020 IPTMR 31:16 IPTMR<31:0> 0000
15:0 0000
1030 IFS0 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF ——— OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 000031:16 SPI3TXIF SPI3RXIF SPI3EIF
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
1040 IFS1
31:16 IC3EIF IC2EIF IC1EIF ETHIF CAN2IF
(2)
CAN1IF USBIF FCEIF DMA7IF
(2)
DMA6IF
(2)
DMA5IF
(2)
DMA4IF
(2)
DMA3IF DMA2IF DMA1IF DMA0IF 0000
RTCCIF FSCMIF — — — U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 000015:0 SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
1050 IFS2 31:16 ————————————————0000
15:0 ———— U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000
1060 IEC0 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE ——— OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 000031:16 SPI3TXIE SPI3RXIE SPI3EIE
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
1070 IEC1
31:16 IC3EIE IC2EIE IC1EIE ETHIE CAN2IE
(2)
CAN1IE USBIE FCEIE DMA7IE
(2)
DMA6IE
(2)
DMA5IE
(2)
DMA4IE
(2)
DMA3IE DMA2IE DMA1IE DMA0IE 0000
RTCCIE FSCMIE — — — U2TXIE U2RXIE U2EIE U3TXIE U3RXIE U3EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 000015:0 SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
1080 IEC2 31:16 ————————————————0000
15:0 ———— U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
1090 IPC0 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
10A0 IPC1 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
10B0 IPC2 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: This bit is unimplemented on PIC32MX764F128H device.
3: This register does not have associated CLR, SET, and INV registers.
PIC32MX5XX/6XX/7XX
DS60001156J-page 82 2009-2016 Microchip Technology Inc.
10D0 IPC4 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
10E0 IPC5 31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
10F0 IPC6
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
— — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0>
000015:0 SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
1100 IPC7 — — — U3IP<2:0> U3IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 000031:16 SPI2IP<2:0> SPI2IS<1:0>
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
1110 IPC8
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
——————————— U2IP<2:0> U2IS<1:0>
000015:0 SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
1120 IPC9 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
1130 IPC10 31:16 — — — DMA7IP<2:0>
(2)
DMA7IS<1:0>
(2)
— — — DMA6IP<2:0>
(2)
DMA6IS<1:0>
(2)
0000
15:0 — — — DMA5IP<2:0>
(2)
DMA5IS<1:0>
(2)
— — — DMA4IP<2:0>
(2)
DMA4IS<1:0>
(2)
0000
1140 IPC11 31:16 — — — CAN2IP<2:0>
(2)
CAN2IS<1:0>
(2)
— — — CAN1IP<2:0> CAN1IS<1:0> 0000
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
1150 IPC12 31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000
15:0 — — — U4IP<2:0> U4IS<1:0> — — — ETHIP<2:0> ETHIS<1:0> 0000
TABLE 7-4: INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: This bit is unimplemented on PIC32MX764F128H device.
3: This register does not have associated CLR, SET, and INV registers.
2009-2016 Microchip Technology Inc. DS60001156J-page 83
PIC32MX5XX/6XX/7XX
TABLE 7-5: INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND
PIC32MX575F256L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
1000 INTCON 31:16 ——————————————— SS0 0000
15:0 — — —MVEC— TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
1010 INTSTAT
(3)
31:16 ————————————————0000
15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000
1020 IPTMR 31:16 IPTMR<31:0> 0000
15:0 0000
1030 IFS0 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1TXIF SPI1RXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 000031:16 SPI3TXIF SPI3RXIF SPI3EIF
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
1040 IFS1
31:16 IC3EIF IC2EIF IC1EIF —— CAN1IF USBIF FCEIF DMA7IF
(2)
DMA6IF
(2)
DMA5IF
(2)
DMA4IF
(2)
DMA3IF DMA2IF DMA1IF DMA0IF 0000
RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 000015:0 SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
1050 IFS2 31:16 ————————————————0000
15:0 ———— U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000
1060 IEC0 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1TXIE SPI1RXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 000031:16 SPI3TXIE SPI3RXIE SPI3EIE
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
1070 IEC1
31:16 IC3EIE IC2EIE IC1EIE —— CAN1IE USBIE FCEIE DMA7IE
(2)
DMA6IE
(2)
DMA5IE
(2)
DMA4IE
(2)
DMA3IE DMA2IE DMA1IE DMA0IE 0000
RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE U3TXIE U3RXIE U3EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 000015:0 SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
1080 IEC2 31:16 ————————————————0000
15:0 ———— U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
1090 IPC0 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
10A0 IPC1 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
10B0 IPC2 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX534/564 devices.
3: This register does not have associated CLR, SET, and INV registers.
PIC32MX5XX/6XX/7XX
DS60001156J-page 84 2009-2016 Microchip Technology Inc.
10D0 IPC4 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
10E0 IPC5 31:16 — — — SPI1IP<2:0> SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
10F0 IPC6
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
— — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0>
000015:0 SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
1100 IPC7 — — — U3IP<2:0> U3IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 000031:16 SPI2IP<2:0> SPI2IS<1:0>
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
1110 IPC8
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
— — — I2C2IP<2:0> I2C2IS<1:0> — — — U2IP<2:0> U2IS<1:0>
000015:0 SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
1120 IPC9 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
1130 IPC10 31:16 — — — DMA7IP<2:0>
(2)
DMA7IS<1:0>
(2)
— — — DMA6IP<2:0>
(2)
DMA6IS<1:0>
(2)
0000
15:0 — — — DMA5IP<2:0>
(2)
DMA5IS<1:0>
(2)
— — — DMA4IP<2:0>
(2)
DMA4IS<1:0>
(2)
0000
1140 IPC11 31:16 — — — — — — — — — — — CAN1IP<2:0> CAN1IS<1:0> 0000
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
1150 IPC12 31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000
15:0 — — — U4IP<2:0> U4IS<1:0> — — — — — — — — 0000
TABLE 7-5: INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND
PIC32MX575F256L DEVICES (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX534/564 devices.
3: This register does not have associated CLR, SET, and INV registers.
2009-2016 Microchip Technology Inc. DS60001156J-page 85
PIC32MX5XX/6XX/7XX
TABLE 7-6: INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
1000 INTCON 31:16 ——————————————— SS0 0000
15:0 — — — MVEC —TPC<2:0>— — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
1010 INTSTAT
(3)
31:16 ————————————————0000
15:0 —————SRIPL<2:0>—— VEC<5:0> 0000
1020 IPTMR 31:16 IPTMR<31:0> 0000
15:0 0000
1030 IFS0 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1TXIF SPI1RXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 000031:16 SPI3TXIF SPI3RXIF SPI3EIF
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
1040 IFS1
31:16 IC3EIF IC2EIF IC1EIF ETHIF —— USBIF FCEIF DMA7IF
(2)
DMA6IF
(2)
DMA5IF
(2)
DMA4IF
(2)
DMA3IF DMA2IF DMA1IF DMA0IF 0000
RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 000015:0 SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
1050 IFS2 31:16 ————————————————0000
15:0 ———— U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000
1060 IEC0 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1TXIE SPI1RXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 000031:16 SPI3TXIE SPI3RXIE SPI3EIE
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
1070 IEC1
31:16 IC3EIE IC2EIE IC1EIE ETHIE —— USBIE FCEIE DMA7IE
(2)
DMA6IE
(2)
DMA5IE
(2)
DMA4IE
(2)
DMA3IE DMA2IE DMA1IE DMA0IE 0000
RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE U3TXIE U3RXIE U3EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 000015:0 SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
1080 IEC2 31:16 ————————————————0000
15:0 ———— U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
1090 IPC0 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
10A0 IPC1 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
10B0 IPC2 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX664 devices.
3: This register does note have associated CLR, SET, and INV registers.
PIC32MX5XX/6XX/7XX
DS60001156J-page 86 2009-2016 Microchip Technology Inc.
10D0 IPC4 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
10E0 IPC5 31:16 — — — SPI1IP<2:0> SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
10F0 IPC6
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
— — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0>
000015:0 SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
1100 IPC7 — — — U3IP<2:0> U3IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 000031:16 SPI2IP<2:0> SPI2IS<1:0>
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
1110 IPC8
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
— — — I2C2IP<2:0> I2C2IS<1:0> — — — U2IP<2:0> U2IS<1:0>
000015:0 SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
1120 IPC9 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
1130 IPC10 31:16 — — — DMA7IP<2:0>
(2)
DMA7IS<1:0>
(2)
— — — DMA6IP<2:0>
(2)
DMA6IS<1:0>
(2)
0000
15:0 — — — DMA5IP<2:0>
(2)
DMA5IS<1:0>
(2)
— — — DMA4IP<2:0>
(2)
DMA4IS<1:0>
(2)
0000
1140 IPC11 31:16 ————————————————0000
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
1150 IPC12 31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000
15:0 — — — U4IP<2:0> U4IS<1:0> — — — ETHIP<2:0> ETHIS<1:0> 0000
TABLE 7-6: INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX664 devices.
3: This register does note have associated CLR, SET, and INV registers.
2009-2016 Microchip Technology Inc. DS60001156J-page 87
PIC32MX5XX/6XX/7XX
TABLE 7-7: INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
1000 INTCON 31:16 ———————————————SS00000
15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
1010 INTSTAT
(3)
31:16 ————————————————0000
15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000
1020 IPTMR 31:16 IPTMR<31:0> 0000
15:0 0000
1030 IFS0 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1TXIF SPI1RXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 000031:16 SPI3TXIF SPI3RXIF SPI3EIF
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
1040 IFS1
31:16 IC3EIF IC2EIF IC1EIF ETHIF CAN2IF
(2)
CAN1IF USBIF FCEIF DMA7IF
(2)
DMA6IF
(2)
DMA5IF
(2)
DMA4IF
(2)
DMA3IF DMA2IF DMA1IF DMA0IF 0000
RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF U3TXIF U3RXIF U3EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 000015:0 SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
1050 IFS2 31:16 ————————————————0000
15:0 — — — — U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000
1060 IEC0 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1TXIE SPI1RXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 000031:16 SPI3TXIE SPI3RXIE SPI3EIE
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
1070 IEC1
31:16 IC3EIE IC2EIE IC1EIE ETHIE CAN2IE
(2)
CAN1IE USBIE FCEIE DMA7IE
(2)
DMA6IE
(2)
DMA5IE
(2)
DMA4IE
(2)
DMA3IE DMA2IE DMA1IE DMA0IE 0000
RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE U3TXIE U3RXIE U3EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 000015:0 SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
1080 IEC2 31:16 ————————————————0000
15:0 — — — — U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
1090 IPC0 31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
10A0 IPC1 31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
10B0 IPC2 31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
10C0 IPC3 31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: This bit is unimplemented on PIC32MX764F128L device.
3: This register does not have associated CLR, SET, and INV registers.
PIC32MX5XX/6XX/7XX
DS60001156J-page 88 2009-2016 Microchip Technology Inc.
10D0 IPC4 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
10E0 IPC5 31:16 — — — SPI1IP<2:0> SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
10F0 IPC6
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
— — — I2C1IP<2:0> I2C1IS<1:0> — — — U1IP<2:0> U1IS<1:0>
000015:0 SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
1100 IPC7 — — — U3IP<2:0> U3IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 000031:16 SPI2IP<2:0> SPI2IS<1:0>
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
1110 IPC8
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
— — — I2C2IP<2:0> I2C2IS<1:0> — — — U2IP<2:0> U2IS<1:0>
000015:0 SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
1120 IPC9 31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
1130 IPC10 31:16 — — — DMA7IP<2:0>
(2)
DMA7IS<1:0>
(2)
— — — DMA6IP<2:0>
(2)
DMA6IS<1:0>
(2)
0000
15:0 — — — DMA5IP<2:0>
(2)
DMA5IS<1:0>
(2)
— — — DMA4IP<2:0>
(2)
DMA4IS<1:0>
(2)
0000
1140 IPC11 31:16 — — — CAN2IP<2:0>
(2)
CAN2IS<1:0>
(2)
— — — CAN1IP<2:0> CAN1IS<1:0> 0000
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
1150 IPC12 31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000
15:0 — — — U4IP<2:0> U4IS<1:0> — — — ETHIP<2:0> ETHIS<1:0> 0000
TABLE 7-7: INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: This bit is unimplemented on PIC32MX764F128L device.
3: This register does not have associated CLR, SET, and INV registers.
2009-2016 Microchip Technology Inc. DS60001156J- page 89
PIC32MX5XX/6XX/7XX
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — SS0
15:8
U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— — — MVEC —TPC<2:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — INT4EP INT3EP INT2EP INT1EP INT0EP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-17 Unimplemented: Read as ‘0’
bit 16 SS0: Single Vector Shadow Register Set bit
1 = Single vector is presen ted with a shadow regis ter se t
0 = Single vector is not presented with a shadow register set
bit 15-13 Unimplemented: Read as ‘0’
bit 12 MVEC: Multiple Vector Configuration bit
1 = Interrupt controller configured for Multi-vector mode
0 = Interrupt controller configured for Single-vector mode
bit 11 Unimplemented: Read as ‘0’
bit 10-8 TPC<2:0>: Interru pt Proxim ity Timer Control bits
111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer
bit 7-5 Unimplemented: Read as ‘0’
bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Ris ing edge
0 = Falling edge
bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
PIC32MX5XX/6XX/7XX
DS60001156J-page 90 2009-2016 Microchip Technology Inc.
REGISTER 7-2: INTSTAT: INTERRUPT STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — RIPL<2:0>
(1)
7:0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
——VEC<5:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-8 RIPL<2:0>: Requested Priority Level bits
(1)
111-000 = The priority level of the latest interrupt presented to the CPU
bit 7-6 Unimplemented: Read as ‘ 0’
bit 5-0 VEC<5:0>: Interrupt Vector bits
(1)
11111-00000 = The interrupt vector that is presented to the CPU
Note 1: This value should only be used when the interrupt controller is configured for Single-vector mode.
REGISTER 7-3: TPTMR: TEMPORAL PROXIMITY TIMER REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TPTMR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TPTMR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TPTMR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TPTMR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 TPTMR<31:0>: Temporal Proximity Timer Reload bits
Used by the Tempo ral Proxim ity Timer as a reload value when the Tempo ral Proxi mity tim er is triggere d by
an interrupt event.
2009-2016 Microchip Technology Inc. DS60001156J- page 91
PIC32MX5XX/6XX/7XX
REGISTER 7-4: IFSx: INTERRUPT FLAG STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS31 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS23 IFS22 IFS21 IFS20 IFS19 IFS18 IFS17 IFS16
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS15 IFS14 IFS13 IFS12 IFS11 IFS10 IFS09 IFS08
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IFS07 IFS06 IFS05 IFS04 IFS03 IFS02 IFS01 IFS00
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IFS31-IFS00: Interrupt Flag Status bits
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Note: This register represents a generic definition of the IFSx register. Refer to Table 7-1 for the exact bit
definitions.
REGISTER 7-5: IECx: INTERRUPT ENABLE CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC31 IEC30 IEC29 IEC28 IEC27 IEC26 IEC25 IEC24
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC23 IEC22 IEC21 IEC20 IEC19 IEC18 IEC17 IEC16
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC15 IEC14 IEC13 IEC12 IEC11 IEC10 IEC09 IEC08
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IEC07 IEC06 IEC05 IEC04 IEC03 IEC02 IEC01 IEC00
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 IEC31-IEC00: Interrupt Enable bits
1 = Interrupt is enabled
0 = Interrupt is disabled
Note: This register represents a generic definition of the IECx register. Refer to Table 7-1 for the exact bit
definitions.
PIC32MX5XX/6XX/7XX
DS60001156J-page 92 2009-2016 Microchip Technology Inc.
REGISTER 7-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP03<2:0> IS03<1:0>
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP02<2:0> IS02<1:0>
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP01<2:0> IS01<1:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — IP00<2:0> IS00<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP03<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disab led
bit 25-24 IS03<1:0>: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP02<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 17-16 IS02<1:0>: Interru pt Su b-pri ori ty bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
bit 15-13 Unimplemented: Read as ‘0’
Note: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.
2009-2016 Microchip Technology Inc. DS60001156J- page 93
PIC32MX5XX/6XX/7XX
bit 12-10 IP01<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 9-8 IS01<1:0>: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-2 IP00<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disab led
bit 1-0 IS00<1:0>: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
REGISTER 7-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)
Note: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.
PIC32MX5XX/6XX/7XX
DS60001156J-page 94 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 95
PIC32MX5XX/6XX/7XX
8.0 OSCILLATOR
CONFIGURATION
The Oscillator module has the following features:
• A total of four external and internal oscillator
options as clock sources
• On-chip PLL with user-selectable input divider,
multiplier and output divider to boost operating
frequency on select internal and external
oscillator sources
• On-chip user-selectable divisor postscaler on
select os cillator source s
• Software-controllable switching between
various clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and p ermits safe applic ation re covery
or shutdown
• Dedicated On-Chip PLL for USB peripheral
Figure 8-1shows the Oscillator module bloc k diagram.
FIGURE 8-1: OSCILLATOR BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 6. “Oscillator”
(DS60001112) in the “PIC32 Family Ref-
erence Manual”, which is available from
the Microchip web site (www.micro-
chip.com/PIC32).
Timer1, RTCC
Clock Control Logic
Fail-Safe
Clock
Monitor
FSCM INT
FSCM E vent
COSC<2:0>
NOSC<2:0>
OSWEN
FSCMEN<1:0>
PLL
Secondary Oscillator (S
OSC
)
SOSCEN and FSOSCEN
SOSCO
SOSCI
XTPLL, HSPLL,
XT, HS, EC
CPU and Select Peripherals
Peripherals
FRCDIV<2:0>
WDT, PWRT
8 MHz typi cal FRC
31.25 kHz typical
FRC
Oscillator
LPRC
Oscillator
S
OSC
LPRC
FRCDIV
ECPLL, FRCPLL
TUN<5:0> div 16
Postscaler
FPLLIDIV<2:0> PBDIV<1:0>
FRC/16
Postscaler
PLL Multiplier
COSC<2:0>
F
IN
div x di v y
PLL Output Div ider
PLLODIV<2:0>
PLL Input Divider
div x
32.768 kHz
PLLMULT<2:0>
PBCLK
UF
IN
4 MHz
PLL x24 USB Clock (48 MHz)
div 2
UPLLEN
UFRCEN
div x
UPLLIDIV<2:0>
UF
IN
4 MHz
F
IN
5 MHz
USB PLL
SYSCLK
Primary Oscillator
C1
(3)
C2
(3)
XTAL
R
S
(1)
Enable
OSC2
(4)
OSC1
R
F
(2)
To Internal
Logic
(P
OSC
)
R
P
(1)
Notes: 1.
A series resistor , R
S
, may be required for AT strip cut crystals or eliminate
clipping. Alternatel y, to increase oscillator circuit gain, add a parallel
resistor, R
P
, with a value of 1 M
2.
The internal feedback resistor, R
F
, is typically in the range of 2 to 10 M
3.
Refer to the “
PIC32 Family Reference Manual
”
Section 6. “Oscillator
Configuration”
(DS60001112) for help determining the best oscillator
components.
4.
PBCLK out is available on the OSC2 pin in certain clock modes.
(
001
= FRC,
011
= P
OSC
)
COSC<2:0>
PIC32MX5XX/6XX/7XX
DS60001156J-page 96 2009-2016 Microchip Technology Inc.
8.1 Control Registers
TABLE 8-1: OSCILLATOR REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
(2)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
F000 OSCCON 31:16 —— PLLODIV<2:0> FRCDIV<2:0> — SOSCRDY — PBDIV<1:0> PLLMULT<2:0> 0000
15:0 — COSC<2:0> — NOSC<2:0> CLKLOCK ULOCK SLOCK SLPEN CF UFRCEN SOSCEN OSWEN 0000
F010 OSCTUN 31:16 ————————————————0000
15:0 —————————— TUN<5:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
2009-2016 Microchip Technology Inc. DS60001156J- page 97
PIC32MX5XX/6XX/7XX
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 R/W-y R/W-y R/W-y R/W-0 R/W-0 R/W-1
—— PLLODIV<2:0> FRCDIV<2:0>
23:16
U-0 R-0 R-1 R/W-y R/W-y R/W-y R/W-y R/W-y
— SOSCRDY PBDIVRDY PBDIV<1:0> PLLMULT<2:0>
15:8
U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y
— COSC<2:0> —NOSC<2:0>
7:0
R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-y R/W-0
CLKLOCK ULOCK SLOCK SLPEN CF UFRCEN SOSCEN OSWEN
Legend: y = Value set from Configuration bits on POR
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-27 PLLODIV<2:0>: Output Divider for PLL
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2 (default setting)
000 = FRC divided by 1
bit 23 Unimplemented: Read as ‘0’
bit 22 SOSCRDY: Secondary Oscillator (S
OSC
) Ready Indicator bit
1 = Indicates that the Secondary Oscillator is running and is stable
0 = Secondary Oscillator is still warming up or is turned off
bit 21 PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit
1 = PBDIV<1:0> bits can be written
0 = PBDIV<1:0> bits cannot be written
bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits
11 = PBCLK is SYSCLK divided by 8 (default)
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
PIC32MX5XX/6XX/7XX
DS60001156J-page 98 2009-2016 Microchip Technology Inc.
bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Mu ltiplier bits
111 = Clock is multiplied by 24
110 = Clock is multiplied by 21
101 = Clock is multiplied by 20
100 = Clock is multiplied by 19
011 = Clock is multiplied by 18
010 = Clock is multiplied by 17
001 = Clock is multiplied by 16
000 = Clock is multiplied by 15
bit 15 Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Selection bits
111 = Internal Fast RC (FRC) Oscillator divided by OSCCON<FRCDIV> bits
110 = Internal Fast RC (FRC) Oscillator divided by 16
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (S
OSC
)
011 = Primary Oscillator (P
OSC
) with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (P
OSC
) (XT, HS or EC)
001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Internal Fast RC (FRC) Oscillator
bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Os cillator Selection bits
111 = Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits
110 = Internal Fast RC Oscillator (FRC) divided by 16
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (S
OSC
)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (XT, HS or EC)
001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Internal Fast Internal RC Oscillator (FRC)
On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>).
bit 7 CLKLOCK: Clock Selection Lock Enable bit
If clock switching and monitoring is disabled (FCKSM<1:0> = 1x):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
If clock switching and monitoring is enabled (FCKSM<1:0> = 0x):
Clock and PLL selections are nev er locked and may be modif ied.
bit 6 ULOCK: USB PLL Lock Status bit
1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied
0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or
USB PLL is disabled
bit 5 SLOCK: PLL Lock Status bit
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4 SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode w hen a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
2009-2016 Microchip Technology Inc. DS60001156J- page 99
PIC32MX5XX/6XX/7XX
bit 2 UFRCEN: USB FRC Clock Enable bit
1 = Enable FRC as the clock source for the USB clock source
0 = Use the Primary Oscillator or USB PLL as the USB clock source
bit 1 SOSCEN: Secondary Oscillator (S
OSC
) Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits
0 = Oscillator switch is complete
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
PIC32MX5XX/6XX/7XX
DS60001156J-page 100 2009-2016 Microchip Technology Inc.
REGISTER 8-2: OSCTUN: FRC TUNING REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
7:0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— TUN<5:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits
(1)
100000 = Center frequency -12.5% for PIC32MX575/595/675/695/775/795 devices
100000 = Center frequency -1.5% for PIC32MX534/564/664/764 devices
100001 =
•
•
•
111111 =
000000 = Center frequency; Oscillator runs at nominal frequency (8 MHz)
000001 =
•
•
•
011110 =
011111 = Center frequenc y +12 .5% for PIC32MX575/595/675/695 /77 5/7 95 dev ic es
011111 = Center frequency +1.5% for PIC32MX534/564/664/764 devices
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of tem peratures. The tuning step size is an approximation, and is neither
characterized nor tested.
Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.
2009-2016 Microchip Technology Inc. DS60001156J- page 101
PIC32MX5XX/6XX/7XX
9.0 PREFETCH CACHE
Prefetch ca ch e increa ses perfo rmanc e for applic ation s
execut ing out of the ca cheab le progra m Flas h memo ry
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.1 Features
• 16 fully-associative lockable cach e lines
• 16-byte cac he lines
• Up to four cache lines allocated to data
• Two cache lines with address mask to hold
repeated instructions
• Pseudo-L RU repl ac em ent polic y
• All cache lines are software writable
• 16-byte parallel memory fetch
• Predictiv e ins truc tion prefe tch
A simplified block diagram of the Prefetch Cache
module is illustrated in Figure 9-1.
FIGURE 9-1: PREFETCH CACHE MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS60001119) in the “PIC32
Family Refe rence Man ual”, which is avail-
able from the Microchip web site
(www.microchip.com/PIC32).
CTRL
RDATA
Prefetch
Prefetch
Hit Logic
Cache
Line
Address
Encode
Cache Line
FSM
CTRL RDATA
Tag Logic
Bus Control
Cache Control
Prefetch Control
Hit LRU
Miss LRU
BMX/CPU
BMX/CPU
CTRL
PFM
PIC32MX5XX/6XX/7XX
DS60001156J-page 102 2009-2016 Microchip Technology Inc.
9.2 Control Registers
TABLE 9-1: PREFETCH REGISTER MAP
Virtual Address
(BF88_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
4000 CHECON
(1,2)
31:16 — — — — — — — — — — — — — — — CHECOH 0000
15:0 — — — — — — DCSZ<1:0> —— PREFEN<1:0> —PFMWS<2:0>0007
4010 CHEACC
(1)
31:16 CHEWEN — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — — CHEIDX<3:0> 0000
4020 CHETAG
(1)
31:16 LTAGBOOT — — — — — — — LTAG<23:16> 00xx
15:0 LTAG<15:4> LVALID LLOCK LTYPE —xxx2
4030 CHEMSK
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 LMASK<15:5> — — — — — 0000
4040 CHEW0 31:16 CHEW0<31:0> xxxx
15:0 xxxx
4050 CHEW1 31:16 CHEW1<31:0> xxxx
15:0 xxxx
4060 CHEW2 31:16 CHEW2<31:0> xxxx
15:0 xxxx
4070 CHEW3 31:16 CHEW3<31:0> xxxx
15:0 xxxx
4080 CHELRU 31:16 — — — — — — — CHELRU<24:16> 0000
15:0 CHELRU<15:0> 0000
4090 CHEHIT 31:16 CHEHIT<31:0> xxxx
15:0 xxxx
40A0 CHEMIS 31:16 CHEMIS<31:0> xxxx
15:0 xxxx
40C0 CHEPFABT 31:16 CHEPFABT<31:0> xxxx
15:0 xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
2: Reset value is dependent on DEVCFGx configuration.
2009-2016 Microchip Technology Inc. DS60001156J- page 103
PIC32MX5XX/6XX/7XX
REGISTER 9-1: CHECON: CACHE CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CHECOH
15:8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — DCSZ<1:0>
7:0
U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
——PREFEN<1:0>— PFMWS<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-17 Unimplemented: Writ e ‘0’; ignore read
bit 16 CHECOH: Cache Coherency Setting on a PFM Program Cycle bit
1 = Invalidate all data and instruction lines
0 = Invalidate all data lnes and instruction lines that are not locked
bit 15-10 Unimplemented: Writ e ‘0’; ignore read
bit 9-8 DCSZ<1:0>: Data Cache Size in Lines bits
Changing these bits causes all lines to be reinitialized to the “invalid” state.
11 = Enable data caching with a size of 4 lines
10 = Enable data caching with a size of 2 lines
01 = Enable data caching with a size of 1 line
00 = Disable data caching
bit 7-6 Unimplemented: Write ‘0’; ignore read
bit 5-4 PREFEN<1:0>: Predictive Prefetch Enable bits
11 = Enable predictive prefetch for both cacheable and non-cacheable regions
10 = Enable predictive prefetch only for non-cacheable regions
01 = Enable predictive prefetch only for cacheable regions
00 = Disable predictive prefetch
bit 3 Unimplemented: Write ‘0’; i gnore read
bit 2-0 PFMWS<2:0>: PFM Access Time Defined in Terms of SYSLK Wait States bits
111 = Seven Wait states
110 = Six Wait states
101 = Five Wait states
100 = Four Wait states
011 = Three Wait states
010 = Two Wait states
001 = One Wait state
000 = Zero Wait state
PIC32MX5XX/6XX/7XX
DS60001156J-page 104 2009-2016 Microchip Technology Inc.
REGISTER 9-2: CHEACC: CACHE ACCESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
CHEWEN — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — CHEIDX<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 CHEWEN: Cache Access Enable bits
These bits apply to registers CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, and CHEW3.
1 = The cache line selected by CHEIDX<3:0> is writeable
0 = The cache line selected by CHEIDX<3:0> is not writeable
bit 30-4 Unimplemented: Write ‘0’; ignore read
bit 3-0 CHEIDX<3:0>: Cache Line Index bits
The value selects the cache line for reading or writing.
2009-2016 Microchip Technology Inc. DS60001156J- page 105
PIC32MX5XX/6XX/7XX
REGISTER 9-3: CHETAG: CACHE TAG REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
LTAGBOOT — — — — — — —
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
LTAG<19:12>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
LTAG<11:4>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-0 R/W-0 R/W-1 U-0
LTAG<3:0> LVALID LLOCK LTYPE —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 LTAGBOOT: Line Tag Address Boot bit
1 = The line is in the 0x1D000000 (physical) area of memory
0 = The line is in the 0x1FC00000 (physical) area of memory
bit 30-24 Unimplemented: Writ e ‘0’; ignore read
bit 23-4 LTAG<19:0>: Line Tag Address bits
LT AG <19:0> bi ts are comp ared agai nst physic al addres s to det ermine a hit. Becau se it s address range an d
position of PFM in kernel space and user space, the LTAG PFM address is identical for virtual addresses,
(system) physical addresses, and PFM physical addresses.
bit 3 LVALID: Line Valid bit
1 = The line is valid and is compared to the physical address for hit detection
0 = The line is not valid and is not compared to the physical address for hit detection
bit 2 LLOCK: Line Lock bit
1 = The line is locked and will not be replaced
0 = The line is not locked and can be replaced
bit 1 LTYPE: Line Type bit
1 = The line caches instruction words
0 = The line caches data words
bit 0 Unimplemented: Write ‘0’; i gnore read
PIC32MX5XX/6XX/7XX
DS60001156J-page 106 2009-2016 Microchip Technology Inc.
REGISTER 9-4: CHEMSK: CACHE TAG MASK REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LMASK<10:3>
7:0
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
LMASK<2:0> — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Writ e ‘0’; ignore read
bit 15-5 LMASK<10:0>: Line Mask bits
1 = Enables mask logic to force a match on the corresponding bit position in LTAG<19:0> bits
(CHETAG<23:4>) and the physical address
0 = Only writeable for values of CHEIDX<3:0> bits (CHEACC<3:0>) equal to 0x0A and 0x0B
(disables mask logic)
bit 4-0 Unimplemented: Write ‘0’; ignore read
REGISTER 9-5: CHEW0: CACHE WORD 0
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW0<31:24>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW0<23:16>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW0<15:8>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW0<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEW0<31:0>: Word 0 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code- protected.
2009-2016 Microchip Technology Inc. DS60001156J- page 107
PIC32MX5XX/6XX/7XX
REGISTER 9-6: CHEW1: CACHE WORD 1
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW1<31:24>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW1<23:16>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW1<15:8>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW1<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEW1<31:0>: Word 1 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code- protected.
REGISTER 9-7: CHEW2: CACHE WORD 2
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW2<31:24>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW2<23:16>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW2<15:8>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW2<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEW2<31:0>: Word 2 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code- protected.
PIC32MX5XX/6XX/7XX
DS60001156J-page 108 2009-2016 Microchip Technology Inc.
REGISTER 9-8: CHEW3: CACHE WORD 3
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW3<31:24>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW3<23:16>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW3<15:8>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW3<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEW3<31:0>: Word 3 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code- protected.
Note: This registe r is a window into the ca che dat a arra y and is only readabl e if th e devic e is not code-pro tected .
REGISTER 9-9: CHELRU: CACHE LRU REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0
— — — — — — — CHELRU<24>
23:16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHELRU<23:16>
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHELRU<15:8>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHELRU<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-25 Unimplemented: Writ e ‘0’; ignore read
bit 24-0 CHELRU<24:0>: Cache Least Recently Used State Encoding bits
Indicates the pseudo-LRU state of the cache.
2009-2016 Microchip Technology Inc. DS60001156J- page 109
PIC32MX5XX/6XX/7XX
REGISTER 9-10: CHEHIT: CACHE HIT STATISTICS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEHIT<31:24>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEHIT<23:16>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEHIT<15:8>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEHIT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEHIT<31:0>: Cache Hit Count bits
Incremented each time the processor issues an instruction fetch or load that hits the prefetch cache from a
cacheable region. Non-cacheable accesses do not modify this value.
REGISTER 9-11: CHEMIS: CACHE MISS STATISTICS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEMIS<31:24>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEMIS<23:16>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEMIS<15:8>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEMIS<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEMIS<31:0>: Cache Miss Count bits
Incremented each time the processor issues an instruction fetch from a cacheable region that misses the
prefetch cache. Non-cacheable accesses do not modify this value.
PIC32MX5XX/6XX/7XX
DS60001156J-page 110 2009-2016 Microchip Technology Inc.
REGISTER 9-12: CHEPFABT: PREFETCH CACHE ABORT ST ATISTICS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEPFABT<31:24>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEPFABT<23:16>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEPFABT<15:8>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEPFABT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEPFABT<31:0>: Prefab Abort Count bits
Increme nted each time a n automatic pref etch cache is aborted du e to a non-sequen tial instructio n fetch, load
or store.
2009-2016 Microchip Technology Inc. DS60001156J- page 111
PIC32MX5XX/6XX/7XX
10.0 DIRECT MEMORY ACCESS
(DMA) CONTROLLER
The Direct Memory Access (DMA) controller is a bus
master module useful for data transfers between
different device s w it hou t C PU in terv ent ion. The source
and destination of a DMA transfer can be any of the
memory mapped modules existent in the PIC3 2 (such
as SPI, UART, PMP, etc.) or memory itself.
Following are some of the key features of the DMA
controller module:
• Four identical channels, each featuring:
- Auto-increment source and destination address
registers
- Source and de stination pointers
- Memory to memory and memory to
peripheral transfers
• Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source and
destination
• Fixed priori ty ch ann el arbi trati on
• Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt) DMA
requests
- One-Shot or Auto-Repeat Block Transfer modes
- Channel-to-channel chaining
• Flexible DMA requests:
- A DMA requ est can be selected f rom any of the
peripheral interrupt sources
- Eac h channel can select an y (appropriat e)
observable interrupt as its DMA request source
- A DMA transfer abort ca n be sel ected fro m any of
the peripheral interrupt sources
- Pattern (data) match transfer termination
• Multiple DMA channel status interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external event
- Invalid DMA address generated
• DMA debug support features:
- Most recent address accessed by a DMA channel
- Most recent DMA channel to transfer data
• CRC Generation module:
- CRC mo dule can be assigned to any of the
available channels
- CRC module is highly co nfigurable
FIGURE 10-1: DMA BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 31. “Direct Mem-
ory Access (DMA) Controller”
(DS60001117) in the “PIC32 Family Ref-
erence Manual”, which is available from
the Microchip web site
(www.microchip.com/PIC32).
Address Decoder Channel 0 Control
Channel 1 Control
Chann el ‘n’ Cont rol
Global Control
(DMACON)
Bus Interface
Channel Prior i t y
Arbitration
SEL
SEL
Y
I
0
I
1
I
2
I
n
System IRQINT Controller
Device Bus + Bus Arbitration
Peripheral Bus
PIC32MX5XX/6XX/7XX
DS60001156J-page 112 2009-2016 Microchip Technology Inc.
10.1 Control Registers
TABLE 10-1: DMA GLOBAL REGISTER MAP
Virtual Address
(BF88_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
3000 DMACON
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON —— SUSPEND DMABUSY — — — — — — — — — — — 0000
3010 DMASTAT 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————————— RDWR DMACH<2:0>
(2)
0000
3020 DMAADDR 31:16 DMAADDR<31:0> 0000
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
2: DMACH<3> bit is not available on PIC32MX534/564/664/764 devices.
TABLE 10-2: DMA CRC REGISTER MAP
(1)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
3030 DCRCCON 31:16 —— BYTO<1:0> WBO —— BITO — — — — — — — — 0000
15:0 — — — PLEN<4:0> CRCEN CRCAPP CRCTYP —— CRCCH<2:0> 0000
3040 DCRCDATA 31:16 DCRCDATA<31:0> 0000
15:0 0000
3050 DCRCXOR 31:16 DCRCXOR<31:0> 0000
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2009-2016 Microchip Technology Inc. DS60001156J-page 113
PIC32MX5XX/6XX/7XX
TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
3060 DCH0CON 31:16 ————————————————0000
15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
3070 DCH0ECON 31:16 ———————— CHAIRQ<7:0> 00FF
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN ———FF00
3080 DCH0INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
3090 DCH0SSA 31:16 CHSSA<31:0> 0000
15:0 0000
30A0 DCH0DSA 31:16 CHDSA<31:0> 0000
15:0 0000
30B0 DCH0SSIZ 31:16 ————————————————0000
15:0 CHSSIZ<15:0> 0000
30C0 DCH0DSIZ 31:16 ————————————————0000
15:0 CHDSIZ<15:0> 0000
30D0 DCH0SPTR 31:16 ————————————————0000
15:0 CHSPTR<15:0> 0000
30E0 DCH0DPTR 31:16 ————————————————0000
15:0 CHDPTR<15:0> 0000
30F0 DCH0CSIZ 31:16 ————————————————0000
15:0 CHCSIZ<15:0> 0000
3100 DCH0CPTR 31:16 ————————————————0000
15:0 CHCPTR<15:0> 0000
3110 DCH0DAT 31:16 ————————————————0000
15:0 ———————— CHPDAT<7:0> 0000
3120 DCH1CON 31:16 ————————————————0000
15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
3130 DCH1ECON 31:16 ———————— CHAIRQ<7:0> 00FF
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN ———FF00
3140 DCH1INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
3150 DCH1SSA 31:16 CHSSA<31:0> 0000
15:0 0000
3160 DCH1DSA 31:16 CHDSA<31:0> 0000
15:0 0000
3170 DCH1SSIZ 31:16 ————————————————0000
15:0 CHSSIZ<15:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
PIC32MX5XX/6XX/7XX
DS60001156J-page 114 2009-2016 Microchip Technology Inc.
3180 DCH1DSIZ 31:16 ————————————————0000
15:0 CHDSIZ<15:0> 0000
3190 DCH1SPTR 31:16 ————————————————0000
15:0 CHSPTR<15:0> 0000
31A0 DCH1DPTR 31:16 ————————————————0000
15:0 CHDPTR<15:0> 0000
31B0 DCH1CSIZ 31:16 ————————————————0000
15:0 CHCSIZ<15:0> 0000
31C0 DCH1CPTR 31:16 ————————————————0000
15:0 CHCPTR<15:0> 0000
31D0 DCH1DAT 31:16 ————————————————0000
15:0 ———————— CHPDAT<7:0> 0000
31E0 DCH2CON 31:16 ————————————————0000
15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31F0 DCH2ECON 31:16 ———————— CHAIRQ<7:0> 00FF
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN ———FF00
3200 DCH2INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
3210 DCH2SSA 31:16 CHSSA<31:0> 0000
15:0 0000
3220 DCH2DSA 31:16 CHDSA<31:0> 0000
15:0 0000
3230 DCH2SSIZ 31:16 ————————————————0000
15:0 CHSSIZ<15:0> 0000
3240 DCH2DSIZ 31:16 ————————————————0000
15:0 CHDSIZ<15:0> 0000
3250 DCH2SPTR 31:16 ————————————————0000
15:0 CHSPTR<15:0> 0000
3260 DCH2DPTR 31:16 ————————————————0000
15:0 CHDPTR<15:0> 0000
3270 DCH2CSIZ 31:16 ————————————————0000
15:0 CHCSIZ<15:0> 0000
3280 DCH2CPTR 31:16 ————————————————0000
15:0 CHCPTR<15:0> 0000
TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
2009-2016 Microchip Technology Inc. DS60001156J-page 115
PIC32MX5XX/6XX/7XX
3290 DCH2DAT 31:16 ————————————————0000
15:0 ———————— CHPDAT<7:0> 0000
32A0 DCH3CON 31:16 ————————————————0000
15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
32B0 DCH3ECON 31:16 ———————— CHAIRQ<7:0> 00FF
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN ———FF00
32C0 DCH3INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
32D0 DCH3SSA 31:16 CHSSA<31:0> 0000
15:0 0000
32E0 DCH3DSA 31:16 CHDSA<31:0> 0000
15:0 0000
32F0 DCH3SSIZ 31:16 ————————————————0000
15:0 CHSSIZ<15:0> 0000
3300 DCH3DSIZ 31:16 ————————————————0000
15:0 CHDSIZ<15:0> 0000
3310 DCH3SPTR 31:16 ————————————————0000
15:0 CHSPTR<15:0> 0000
3320 DCH3DPTR 31:16 ————————————————0000
15:0 CHDPTR<15:0> 0000
3330 DCH3CSIZ 31:16 ————————————————0000
15:0 CHCSIZ<15:0> 0000
3340 DCH3CPTR 31:16 ————————————————0000
15:0 CHCPTR<15:0> 0000
3350 DCH3DAT 31:16 ————————————————0000
15:0 ———————— CHPDAT<7:0> 0000
3360 DCH4CON 31:16 ————————————————0000
15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
3370 DCH4ECON 31:16 ———————— CHAIRQ<7:0> 00FF
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN ———FF00
3380 DCH4INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
3390 DCH4SSA 31:16 CHSSA<31:0> 0000
15:0 0000
33A0 DCH4DSA 31:16 CHDSA<31:0> 0000
15:0 0000
TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
PIC32MX5XX/6XX/7XX
DS60001156J-page 116 2009-2016 Microchip Technology Inc.
33B0 DCH4SSIZ 31:16 ————————————————0000
15:0 CHSSIZ15:0> 0000
33C0 DCH4DSIZ 31:16 ————————————————0000
15:0 CHDSIZ<15:0> 0000
33D0 DCH4SPTR 31:16 ————————————————0000
15:0 CHSPTR<15:0> 0000
33E0 DCH4DPTR 31:16 ————————————————0000
15:0 CHDPTR<15:0> 0000
33F0 DCH4CSIZ 31:16 ————————————————0000
15:0 CHCSIZ<15:0> 0000
3400 DCH4CPTR 31:16 ————————————————0000
15:0 CHCPTR<15:0> 0000
3410 DCH4DAT 31:16 ————————————————0000
15:0 ———————— CHPDAT<7:0> 0000
3420 DCH5CON 31:16 ————————————————0000
15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
3430 DCH5ECON 31:16 ———————— CHAIRQ<7:0> 00FF
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN ———FF00
3440 DCH5INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
3450 DCH5SSA 31:16 CHSSA<31:0> 0000
15:0 0000
3460 DCH5DSA 31:16 CHDSA<31:0> 0000
15:0 0000
3470 DCH5SSIZ 31:16 ————————————————0000
15:0 CHSSIZ<15:0> 0000
3480 DCH5DSIZ 31:16 ————————————————0000
15:0 CHDSIZ<15:0> 0000
3490 DCH5SPTR 31:16 ————————————————0000
15:0 CHSPTR<15:0> 0000
34A0 DCH5DPTR 31:16 ————————————————0000
15:0 CHDPTR<15:0> 0000
34B0 DCH5CSIZ 31:16 ————————————————0000
15:0 CHCSIZ<15:0> 0000
34C0 DCH5CPTR 31:16 ————————————————0000
15:0 CHCPTR<15:0> 0000
TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
2009-2016 Microchip Technology Inc. DS60001156J-page 117
PIC32MX5XX/6XX/7XX
34D0 DCH5DAT 31:16 ————————————————0000
15:0 ———————— CHPDAT<7:0> 0000
34E0 DCH6CON 31:16 ————————————————0000
15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
34F0 DCH6ECON 31:16 ———————— CHAIRQ<7:0> 00FF
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN ———FF00
3500 DCH6INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
3510 DCH6SSA 31:16 CHSSA<31:0> 0000
15:0 0000
3520 DCH6DSA 31:16 CHDSA<31:0> 0000
15:0 0000
3530 DCH6SSIZ 31:16 ————————————————0000
15:0 CHSSIZ<15:0> 0000
3540 DCH6DSIZ 31:16 ————————————————0000
15:0 CHDSIZ<15:0> 0000
3550 DCH6SPTR 31:16 ————————————————0000
15:0 CHSPTR<15:0> 0000
3560 DCH6DPTR 31:16 ————————————————0000
15:0 CHDPTR<15:0> 0000
3570 DCH6CSIZ 31:16 ————————————————0000
15:0 CHCSIZ<15:0> 0000
3580 DCH6CPTR 31:16 ————————————————0000
15:0 CHCPTR<15:0> 0000
3590 DCH6DAT 31:16 ————————————————0000
15:0 ———————— CHPDAT<7:0> 0000
35A0 DCH7CON 31:16 ————————————————0000
15:0 CHBUSY ——————CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
35B0 DCH7ECON 31:16 ———————— CHAIRQ<7:0> 00FF
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN ———FF00
35C0 DCH7INT 31:16 ————————CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
15:0 ————————CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
35D0 DCH7SSA 31:16 CHSSA<31:0> 0000
15:0 0000
35E0 DCH7DSA 31:16 CHDSA<31:0> 0000
15:0 0000
TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
PIC32MX5XX/6XX/7XX
DS60001156J-page 118 2009-2016 Microchip Technology Inc.
35F0 DCH7SSIZ 31:16 ————————————————0000
15:0 CHSSIZ<15:0> 0000
3600 DCH7DSIZ 31:16 ————————————————0000
15:0 CHDSIZ<15:0> 0000
3610 DCH7SPTR 31:16 ————————————————0000
15:0 CHSPTR<15:0> 0000
3620 DCH7DPTR 31:16 ————————————————0000
15:0 CHDPTR<15:0> 0000
3630 DCH7CSIZ 31:16 ————————————————0000
15:0 CHCSIZ<15:0> 0000
3640 DCH7CPTR 31:16 ————————————————0000
15:0 CHCPTR<15:0> 0000
3650 DCH7DAT 31:16 ————————————————0000
15:0 ———————— CHPDAT<7:0> 0000
TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
2009-2016 Microchip Technology Inc. DS60001156J- page 119
PIC32MX5XX/6XX/7XX
REGISTER 10-1: DMACON: DMA CONTROLLER CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0
ON
(1)
—— SUSPEND DMABUSY — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: DMA On bit
(1)
1 = DMA module is enabled
0 = DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12 SUSPEND: DMA Suspend bit
1 = DMA tran sfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally
bit 11 DMABUSY: DMA Module Busy bit
1 = DMA module is active
0 = DMA module is disabled and not actively transferring data
bit 10-0 Unimplemented: Read as ‘0’
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
PIC32MX5XX/6XX/7XX
DS60001156J-page 120 2009-2016 Microchip Technology Inc.
REGISTER 10-2: DMASTAT: DMA STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — RDWR DMACH<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3 RDWR: Read/Write Status bit
1 = Last DMA bus access was a read
0 = Last DMA bus a c cess was a write
bit 2-0 DMACH<2:0>: DMA Channel bits
These bits contain the value of the most recent active DMA channel.
REGISTER 10-3: DMAADDR: DMA ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<31:24>
23:16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<23:16>
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<15:8>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DMAADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 31-0 DMAADDR<31:0>: DMA Module Address bits
These bits contain the address of the most recent DMA access.
2009-2016 Microchip Technology Inc. DS60001156J- page 121
PIC32MX5XX/6XX/7XX
REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0
—— BYTO<1:0> WBO
(1)
——BITO
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — PLEN<4:0>
7:0
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
CRCEN CRCAPP
(1)
CRCTYP —— CRCCH<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-30 Unimplemented: Read as ‘0’
bit 29-28 BYTO<1:0>: CRC Byte Order Selecti on bit s
11 = Endian byte swap on half-word boundaries (source half-word order with reverse source byte order
per half-word)
10 = Swap half-words on word boundaries (reverse source half-word order with source byte order
per half-word)
01 = Endian byte swap on word boundaries (reverse source byte order)
00 = No swapping (source byte order)
bit 27 WBO: CRC Write Byte Order Selection bit
(1)
1 = Source data is written to the destination re-ordered as defined by BYTO<1:0>
0 = Source data is written to the destination unaltered
bit 26-25 Unimplemented: Read as ‘0’
bit 24 BITO: CRC Bit Order Selection bit
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (reflected)
0 = The IP header checksum is calculated Most Significant bit (MSb) first (not reflected)
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
1 = The LFSR CRC is calculated Least Significant bit first (reflected)
0 = The LFSR CRC is calculated Most Significant bit first (not reflected)
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8 PLEN<4:0>: Polynomial Length bits
(1)
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
These bits are unused.
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Denotes the length of the polynomial – 1.
bit 7 CRCEN: CRC Ena ble bit
1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
PIC32MX5XX/6XX/7XX
DS60001156J-page 122 2009-2016 Microchip Technology Inc.
bit 6 CRCAPP: CRC Append Mode bit
(1)
1 = The DM A tran sf ers data from the sourc e i nto the CR C but not to the desti na tion . Wh en a bl oc k tra ns fer
completes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the
destination
bit 5 CRCTYP: CRC Type Selection bit
1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC
bit 4-3 Unimplemented: Read as ‘0’
bit 2-0 CRCCH<2:0>: CRC Channel Select bits
111 = CRC is assigned to Channel 7
110 = CRC is assigned to Channel 6
101 = CRC is assigned to Channel 5
100 = CRC is assigned to Channel 4
011 = CRC is assigned to Channel 3
010 = CRC is assigned to Channel 2
001 = CRC is assigned to Channel 1
000 = CRC is assigned to Channel 0
REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.
2009-2016 Microchip Technology Inc. DS60001156J- page 123
PIC32MX5XX/6XX/7XX
REGISTER 10-5: DCRCDATA: DMA CRC DATA REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCRCDATA<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCRCDATA<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCRCDATA<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCRCDATA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 DCRCDATA<31:0>: CRC Data Register bits
Wri tin g to th is regi ster will seed the CRC gen erator . Reading from this re gis ter will return the current value o f
the CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
Only the lower 16 bit s cont ain IP h eader che cksum in formation. The uppe r 16 bit s are a lways ‘ 0’. Data written
to this register is converted and read back in 1’s complement form (current IP header checksum value).
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Bits grea ter than PLEN will return ‘0’ on an y read .
REGISTER 10-6: DCRCX OR: DMA CRCXOR ENABLE REGISTE R
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCRCXOR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCRCXOR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCRCXOR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DCRCXOR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
This regis ter is unused.
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register
PIC32MX5XX/6XX/7XX
DS60001156J-page 124 2009-2016 Microchip Technology Inc.
REGISTER 10-7: DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
CHBUSY — — — — — — CHCHNS
(1)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R/W-0
CHEN
(2)
CHAED CHCHN CHAEN — CHEDET CHPRI<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 CHBUSY: Channel Bus y bit
1 = Channel is active or has been enabled
0 = Channel is inactive or has been disabled
bit 14-9 Unimplemented: Read as ‘0’
bit 8 CHCHNS: Chain Channel Selection bit
(1)
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
bit 7 CHEN: Channel Enable bit
(2)
1 = Channel is enabled
0 = Channel is disabled
bit 6 CHAED: Channel Allow Events If Disa bled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
bit CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained
0 = Do not allow channel to be chained
bit 4 CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
bit 3 Unimplemented: Read as ‘0’
bit 2 CHEDET: Channel Event Detected bit
1 = An event has been det ected
0 = No events have been detected
bit 1-0 CHPRI<1:0>: Ch annel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0
Note 1: The chain selection bit takes effect when chaining is enabled (CHCHN = 1).
2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.
2009-2016 Microchip Technology Inc. DS60001156J- page 125
PIC32MX5XX/6XX/7XX
REGISTER 10-8: DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
CHAIRQ<7:0>
(1)
15:8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
CHSIRQ<7:0>
(1)
7:0
S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
CFORCE CABORT PATEN SIRQEN AIRQEN — — —
Legend: S = Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits
(1)
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits
(1)
11111111 = Interrupt 255 will initiate a DMA transfer
•
•
•
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
bit 7 CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
bit 6 CABORT: DMA Abort Transfe r bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
bit 5 PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHE N on patt ern match
0 = Pattern match is disabled
bit 4 SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
bit 3 AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
bit 2-0 Unimplemented: Read as ‘0’
Note 1: See Table 7-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.
PIC32MX5XX/6XX/7XX
DS60001156J-page 126 2009-2016 Microchip Technology Inc.
REGISTER 10-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23 CHSDIE: Channel Source Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 16 CHERIE: Channel Address Error Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 15-8 Unimplemented: R ead as ‘0’
bit 7 CHSDIF: Channel Source Done Interrupt Flag bit
1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
0 = No interrupt is pending
bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit
1 = Channel Source Pointer ha s reached midpoint of so urce (CHSPTR = CHSSIZ/2)
0 = No interrupt is pending
2009-2016 Microchip Technology Inc. DS60001156J- page 127
PIC32MX5XX/6XX/7XX
bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit
1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
0 = No interrupt is pending
bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit
1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0 = No interrupt is pending
bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit
1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a
pattern match event occurs
0 = No interrupt is pending
bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
0 = No interrupt is pending
bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit
1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0 = No interrupt is pending
bit 0 CHERIF: Channel Address Error Interrupt Flag bit
1 = A channel address error has been detected (either the source or the destination address is invalid)
0 = No interrupt is pending
REGISTER 10-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED)
PIC32MX5XX/6XX/7XX
DS60001156J-page 128 2009-2016 Microchip Technology Inc.
REGISTER 10-10: DCHxSSA: DMA CHANNEL ‘x’ SOURCE START ADDRESS REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHSSA<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHSSA<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHSSA<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHSSA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHSSA<31:0> Channel Source Start Address bits
Channel source start address.
Note: This must be the physical address of the source.
REGISTER 10-11: DCHxDSA: DMA CHANNEL ‘x’ DESTINATION START ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHDSA<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHDSA<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHDSA<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHDSA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits
Chann el des tin ati on st art address .
Note: This must be the physical addres s of the destination.
2009-2016 Microchip Technology Inc. DS60001156J- page 129
PIC32MX5XX/6XX/7XX
REGISTER 10-12: DCHxSSIZ: DMA CHANNEL ‘x’ SOURCE SIZE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHSSIZ<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHSSIZ<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘ 0’
bit 15-0 CHSSIZ<15:0>: Channel Source Size bits
1111111111111111 = 65,535 byte source size
•
•
•
0000000000000010 = 2 byte source size
0000000000000001 = 1 byte source size
0000000000000000 = 65,536 byte source size
REGISTER 10-13: DCHxDSIZ: DMA CHANNEL ‘x’ DESTINATION SIZE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHDSIZ<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHDSIZ<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits
1111111111111111 = 65,535 byte destination size
•
•
•
0000000000000010 = 2 byte destination size
0000000000000001 = 1 byte destination size
0000000000000000 = 65,536 byte destination size
PIC32MX5XX/6XX/7XX
DS60001156J-page 130 2009-2016 Microchip Technology Inc.
REGISTER 10-14: DCHxSPTR: DMA CHANNEL ‘x’ SOURCE POINTER REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHSPTR<15:8>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHSPTR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits
1111111111111111 = Points to byte 65,535 of the source
•
•
•
0000000000000001 = Points to byte 1 of the source
0000000000000000 = Points to byte 0 of the source
Note: When in Pattern Detect mode, this register is reset on a pattern detect.
REGISTER 10-15: DCHxDPTR: DMA CHANNEL ‘x’ DESTINATION POINTER REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHDPTR<15:8>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHDPTR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits
1111111111111111 = Points to byte 65,535 of the destination
•
•
•
0000000000000001 = Points to byte 1 of the destination
0000000000000000 = Points to byte 0 of the destination
2009-2016 Microchip Technology Inc. DS60001156J- page 131
PIC32MX5XX/6XX/7XX
REGISTER 10-16: DCHxCSIZ: DMA CHANNEL ‘x’ CELL-SIZE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHCSIZ<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHCSIZ<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits
1111111111111111 = 65,535 bytes transferred on an event
•
•
•
0000000000000010 = 2 bytes transferred on an event
0000000000000001 = 1 byte transferred on an event
0000000000000000 = 65,536 bytes transferred on an event
REGISTER 10-17: DCHxCPTR: DMA CHANNEL ‘x’ CELL POINTER REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHCPTR<15:8>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHCPTR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CHCPTR<7:0>: Channel Cell Progress Pointer bits
1111111111111111 = 65,535 bytes have been transferred since the last event
•
•
•
0000000000000001 = 1 byte has been transferred since the last event
0000000000000000 = 0 bytes have been transferred since the last event
Note: When in Pattern Detect mode, this register is reset on a pattern detect.
PIC32MX5XX/6XX/7XX
DS60001156J-page 132 2009-2016 Microchip Technology Inc.
REGISTER 10-18: DCHxDAT: DMA CHANNEL ‘x’ PATTERN DATA REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CHPDAT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplem ented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 CHPDAT<7:0>: Channel Data Register bits
Pattern Terminate mode:
Data to be matched must be stored in this register to allow terminate on match.
All other modes:
Unused.
2009-2016 Microchip Technology Inc. DS60001156J- page 133
PIC32MX5XX/6XX/7XX
11.0 USB ON-THE-GO (OTG)
The Universal Serial Bus (USB) module contains
analog and digital components to provide a USB 2.0
full-speed and low-speed embedded Host, full-speed
Device or OTG implementation with a minimum of
external components. This module in Host mode is
intended for use as an embedded host and therefore
does not implement a UHCI or OHCI controller.
The USB module consists of the clock generator, the
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), a dedicated USB DMA control-
ler, pull-up and pull-down resistors, and the register
interface. A block diagram of the PIC32 USB OTG
module is presented in Figure 11-1.
The clock generator provides the 48 MHz clock
required for USB full-speed and low-speed communi-
cation. The volta ge comp arators mo nitor the vol tage on
the V
BUS
pin to determine the state of the bus. The
transceiver provides the analog translation between
the USB bus and the digital logic. The SIE is a state
machine that transfers data to and from the endpoint
buffers and generates the hardware protocol for data
transfers. The USB DMA controller transfers data
betwee n the data bu ffers in R AM and the SIE. The inte-
grated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface allows the CPU to configure and
communicate with the module.
The USB module includes the following features:
• USB Full-speed support for host and device
• Low-speed host support
• USB OTG support
• Integrated signaling resistors
• Integrated analog comparators for V
BUS
monitoring
• Integrated USB transceiver
• Transaction handshaking performed by hardware
• Endpoint buffering anywhere in system RAM
• Integrate d D MA to a cc es s sys te m RAM an d Fl as h
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 27. “USB On-The-
Go (OTG)” (DS60001126) in the “PIC32
Family Refe rence Man ual”, which is avail-
able from the Microchip web site
(www.microchip.com/PIC32).
Note: The implementation and use of the USB
specific ations, as well as other third party
specifications or technologies, may
require li censing ; includin g, but no t limited
to, USB Implementers Forum, Inc. (also
referred to as USB-IF). The user is fully
responsible for investigating and
satisfying any applicable licensing
obligations.
PIC32MX5XX/6XX/7XX
DS60001156J-page 134 2009-2016 Microchip Technology Inc.
FIGURE 11-1: PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM
OSC1
OSC2
Primary Oscillator
8MHzTypical
FRC
Oscillator
TUN<5:0>
(4)
PLL
48 MHz USB Clock
(7)
Div x
UPLLEN
(6)
(PB Out)
(1)
UFRCEN
(3)
(P
OSC
)
UPLLIDIV
(6)
UF
IN(5)
Div 2
V
USB
3
V
3
D+
(2)
D-
(2)
ID
(8)
Bus
Transceiver SIE
V
BUSON(8)
Comparators
USB
SRP Charge
SRP Discharge
Registers
and
Control
Interface
Transcei ver Power 3. 3V
To Clock Generator for Core and Peripherals
Sleep or Idle
Sleep
USBEN
USB Suspend
CPU Clock Not P
OSC
USB Module
Voltage
System
RAM
USB Suspend
Full-Speed Pull-up
Host Pull-down
Low-Speed Pull-up
Host Pull-down
ID Pull-up
DMA
Note 1: PB clock is only available on this pin for select EC modes.
2: Pins can be used as digital inputs when USB is not enabled.
3: This bit field is contained in the OSCCON register.
4: This bit field is contained in the OSCTRM register.
5: USB PLL U
F
IN
requirements: 4 MHz.
6: This bit field is contained in the DEVCFG2 register.
7: A 48 MHz clock is required for proper USB operation.
8: Pins can be used as GPIO when the USB module is disabled.
2009-2016 Microchip Technology Inc. DS60001156J-page 135
PIC32MX5XX/6XX/7XX
11.1 Control Registers
TABLE 11-1: USB REGISTER MAP
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
5040 U1OTGIR
(2)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF 0000
5050 U1OTGIE 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE 0000
5060 U1OTGSTAT
(3)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ————————ID —LSTATE — SESVD SESEND — VBUSVD 0000
5070 U1OTGCON 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000
5080 U1PWRC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ————————UACTPND
(4)
—— USLPGRD USBBUSY — USUSPEND USBPWR 0000
5200 U1IR
(2)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF 0000
DETACHIF 0000
5210 U1IE 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE 0000
DETACHIE 0000
5220 U1EIR
(2)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0000
EOFEF 0000
5230 U1EIE 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0000
EOFEE 0000
5240 U1STAT
(3)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— ENDPT<3:0>
(4)
DIR PPBI — — 0000
5250 U1CON 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ————————JSTATE
(4)
SE0
(4)
PKTDIS USBRST HOSTEN RESUME PPBRST USBEN 0000
TOKBUSY SOFEN 0000
5260 U1ADDR 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— LSPDEN DEVADDR<6:0> 0000
5270 U1BDTP1 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— BDTPTRL<7:1> —0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively . See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
2: This register does not have associated SET and INV registers.
3: This register does not have associated CLR, SET and INV registers.
4: Reset value for this bit is undefined.
PIC32MX5XX/6XX/7XX
DS60001156J-page 136 2009-2016 Microchip Technology Inc.
5280 U1FRML
(3)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — FRML<7:0> 0000
5290 U1FRMH
(3)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — — — FRMH<2:0> 0000
52A0 U1TOK 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — PID<3:0> EP<3:0> 0000
52B0 U1SOF 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— CNT<7:0> 0000
52C0 U1BDTP2 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— BDTPTRH<7:0> 0000
52D0 U1BDTP3 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— BDTPTRU<7:0> 0000
52E0 U1CNFG1 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— UTEYE UOEMON — USBSIDL — — — UASUSPND 0001
5300 U1EP0 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ———————— LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
5310 U1EP1 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
5320 U1EP2 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
5330 U1EP3 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
5340 U1EP4 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
5350 U1EP5 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
5360 U1EP6 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
5370 U1EP7 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
5380 U1EP8 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
5390 U1EP9 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
TABLE 11-1: USB REGISTER MAP (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively . See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
2: This register does not have associated SET and INV registers.
3: This register does not have associated CLR, SET and INV registers.
4: Reset value for this bit is undefined.
2009-2016 Microchip Technology Inc. DS60001156J-page 137
PIC32MX5XX/6XX/7XX
53A0 U1EP10 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
53B0 U1EP11 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
53C0 U1EP12 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
53D0 U1EP13 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
53E0 U1EP14 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
53F0 U1EP15 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
TABLE 11-1: USB REGISTER MAP (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively . See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
2: This register does not have associated SET and INV registers.
3: This register does not have associated CLR, SET and INV registers.
4: Reset value for this bit is undefined.
PIC32MX5XX/6XX/7XX
DS60001156J-page 138 2009-2016 Microchip Technology Inc.
REGISTER 11-1: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
7:0
R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 R/WC-0, HS
IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF
Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit
R = Readable bit W = Writable bi t U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 IDIF: ID State Change Indi cator bit
1 = Change in ID state detected
0 = No change in ID state detected
bit 6 T1MSECIF: 1 Millisecond Timer bit
1 = 1 millisecond timer has expired
0 = 1 millisecond timer has not expired
bit 5 LSTATEIF: Line State Stable Indicator bit
1 = USB line state has been stable for 1 ms, but different from last time
0 = USB line state has not been stable for 1 ms
bit 4 ACTVIF: Bus Activity Indicator bit
1 = Activity on the D+, D-, ID or V
BUS
pins has caused the device to wake-up
0 = Activity has not been detected
bit 3 SESVDIF: Session Valid Change Indicator bit
1 =V
BUS
voltage has dropped below the session end level
0 =V
BUS
voltage has not dropped below the session end level
bit 2 SESENDIF: B-Device V
BUS
Change Indicator bit
1 = A change on the session end input was detected
0 = No change on the session end input was detected
bit 1 Unimplemented: Read as ‘0’
bit 0 VBUSVDIF: A-Device V
BUS
Change Indicator bit
1 = Change on the session valid input detected
0 = No change on the session valid input detected
2009-2016 Microchip Technology Inc. DS60001156J- page 139
PIC32MX5XX/6XX/7XX
REGISTER 11-2: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE
Legend:
R = Readable bit W = Writable bi t U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 IDIE: ID Interrupt Enable bit
1 = ID interrupt enabled
0 = ID interrupt disabled
bit 6 T1MSECIE: 1 Mi llisecond Timer Interrupt Enable bit
1 = 1 millisecond timer interrupt enabled
0 = 1 millisecond timer interrupt disabled
bit 5 LSTATEIE: Line State Interrupt Enable bit
1 = Line state interrupt enabled
0 = Line state int erru pt disabled
bit 4 ACTVIE: Bus ACTIVITY Interrupt Enable bit
1 = ACTIVITY interrupt enabled
0 = ACTIVITY interrupt di sabled
bit 3 SESVDIE: Session Valid Interrupt Enable bit
1 = Session valid interrupt enabled
0 = Session valid interrupt disabled
bit 2 SESENDIE: B-Session End Interrupt Enable bit
1 = B-session end interrupt enabled
0 = B-session end interrupt disabled
bit 1 Unimplemented: Read as ‘0’
bit 0 VBUSVDIE: A-V
BUS
Valid Interrupt Enable bit
1 =A-V
BUS
valid interrupt enabled
0 =A-V
BUS
valid interrupt disabled
PIC32MX5XX/6XX/7XX
DS60001156J-page 140 2009-2016 Microchip Technology Inc.
REGISTER 11-3: U1OTGSTAT: USB OTG STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0
ID —LSTATE— SESVD SESEND — VBUSVD
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl eared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 ID: ID Pin State Indicator bit
1 = No cable is attached or a “type B” cable has been inserted into the USB receptacle
0 = A “type A” OTG cable has been inserted into the USB receptacle
bit 6 Unimplemented: Read as ‘0’
bit 5 LSTATE: Line State Stable Indicator bit
1 = USB line state (SE0 (U1CON<6> and JSTATE (U1CON<7>) has been stable for the previous 1 ms
0 = USB line state (SE0 (U1CON<6> and JSTATE (U1CON<7>) has not been stable for the previous 1 ms
bit 4 Unimplemented: Read as ‘0’
bit 3 SESVD: Session Valid Indicator bit
1 =V
BUS
voltage is above Session Valid on the A or B device
0 =V
BUS
voltage is below Session Valid on the A or B device
bit 2 SESEND: B-Device Session End Indicator bit
1 =V
BUS
voltage is below Session Valid on the B device
0 =V
BUS
voltage is above Session Valid on the B device
bit 1 Unimplemented: Read as ‘0’
bit 0 VBUSVD: A-Device V
BUS
Valid Indicator bit
1 =V
BUS
voltage is above Session Valid on the A device
0 =V
BUS
voltage is below Session Valid on the A device
2009-2016 Microchip Technology Inc. DS60001156J- page 141
PIC32MX5XX/6XX/7XX
REGISTER 11-4: U1OTGCON: USB OTG CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Re ad as ‘ 0’
bit 7 DPPULUP: D+ Pull-Up Enable bit
1 = D+ data line pull-up resistor is enabled
0 = D+ data line pull-up resistor is disabled
bit 6 DMPULUP: D- Pull-Up Enable bit
1 = D- data line pull-up resistor is enabled
0 = D- data line pull-up resistor is disabled
bit 5 DPPULDWN: D+ Pull-Down Enable bit
1 = D+ data line pull-down resistor is enabled
0 = D+ data line pull-down resistor is disabled
bit 4 DMPULDWN: D- Pull-Down Enable bit
1 = D- data line pull-down resistor is enabled
0 = D- data line pull-down resistor is disabled
bit 3 VBUSON: V
BUS
Power-on bit
1 =V
BUS
line is powered
0 =V
BUS
line is not powered
bit 2 OTGEN: OTG Functionality Enable bit
1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control
0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB ha rdware control
bit 1 VBUSCHG: V
BUS
Char ge Enable bit
1 =V
BUS
line is charged through a pull-up resistor
0 =V
BUS
line is not charged through a resistor
bit 0 VBUSDIS: V
BUS
Discharge Enable bit
1 =V
BUS
line is discharged through a pull-down resistor
0 =V
BUS
line is not discharged through a resistor
PIC32MX5XX/6XX/7XX
DS60001156J-page 142 2009-2016 Microchip Technology Inc.
REGISTER 11-5: U1PWRC: USB POWER CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
UACTPND —— USLPGRD USBBUSY — USUSPEND USBPWR
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 UACTPND: USB Activity Pending bit
1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet
0 = An interrupt is not pending
bit 6-5 Unimplemented: Read as ‘0’
bit 4 USLPGRD: USB Sleep Entry Guard bit
1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending
0 = USB module does not bloc k Sleep entry
bit 3 USBBUSY: USB Module Busy bit
1 = USB module is active or disabled, but not ready to be enabled
0 = USB module is not active and is ready to be enabled
Note: When USBPW R = 0 an d USBBUSY = 1, stat us from all other registers is invali d an d w ri tes to a ll
USB module registers produce undefined results.
bit 2 Unimplemented: Read as ‘0’
bit 1 USUSPEND: USB Suspend Mode bit
1 = USB module is placed in Suspend mode
(The 48 MHz USB clock will be ga ted off. The transceiver is placed in a low-power state.)
0 = USB module operates normally
bit 0 USBPWR: USB Operation Enable bit
1 = USB module is turned on
0 = USB module is disabled
(Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power
consumption.)
2009-2016 Microchip Technology Inc. DS60001156J- page 143
PIC32MX5XX/6XX/7XX
REGISTER 11-6: U1IR: USB INTERRUPT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 R/WC-0, HS
STALLIF ATTACHIF
(1)
RESUMEIF
(2)
IDLEIF TRNIF
(3)
SOFIF UERRIF
(4)
URSTIF
(5)
DETACHIF
(6)
Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 STALLIF: STALL Handshake Interrupt bit
1 = In Host mode a STALL handshake was received during the handshake phase of the transaction. In
Device mode, a STALL handshake was transmitted during the handshake phase of the transaction.
0 = STALL handshake has not been sent
bit 6 ATTACHIF: Peripheral Attach Interrupt bit
(1)
1 = Peripheral attachment was detected by the USB module
0 = Peripheral attachment was not detected
bit 5 RESUMEIF: Resu me Interrupt bit
(2)
1 = K-State is observed on the D+ or D- pin for 2.5 µs
0 = K-State is not observed
bit 4 IDLEIF: Idle Detect Interrupt bit
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3 TRNIF: Token Processing C om ple te Interru pt bit
(3)
1 = Processing of current tok en is com plete; a re ad of the U1STAT register will prov ide end poi nt inform ation
0 = Processing of current token not complete
bit 2 SOFIF: SOF Token Interrupt bit
1 = SOF token received by the peripheral or the SOF threshold reached by the host
0 = SOF token was not received nor threshold reached
bit 1 UERRIF: USB Error Condition Interrupt bit
(4)
1 = Unmasked error condition has occurred
0 = Unmasked error condition has not occurred
bit 0 URSTIF: USB Reset Interrupt bit (D evice mode )
(5)
1 = Valid USB Reset has occur red
0 = No USB Reset has occurred
DETACHIF: USB Detach Interrupt bit (Host mode)
(6)
1 = Peripheral detachment was detect ed by the US B modul e
0 = Peripheral detachment was not det ect ed
Note 1: This bit is only valid if the HOSTEN bit is set (see Register 11-11), there is no activity on the USB for
2.5 µs, and the current bus state is not SE0.
2: When not in Suspend mode, this interrupt should be disabled.
3: Clearing this bit will cause the STAT FIFO to advance.
4: Only error conditions enabled through the U1EIE register will set this bit.
5: Device mode.
6: Host mode.
PIC32MX5XX/6XX/7XX
DS60001156J-page 144 2009-2016 Microchip Technology Inc.
REGISTER 11-7: U1IE: USB INTERRUPT ENABLE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
——————— —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
——————— —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
——————— —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE
(1)
URSTIE
(2)
DETACHIE
(3)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt is enabled
0 = STALL interrupt is disabled
bit 6 ATTACHIE: ATTACH Interrupt Enable bit
1 = ATTACH interrupt is enabled
0 = ATTACH interrupt is disabled
bit 5 RESUMEIE: RESUME Interrupt Enable bit
1 = RESUME interrupt is enabled
0 = RESUME interrupt is disabled
bit 4 IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle interrupt is enabled
0 = Idle interrupt is disabled
bit 3 TRNIE: Token Processi ng Comp le te Interru pt Enable bit
1 = TRNIF interrupt is enabled
0 = TRNIF interrupt is disabled
bit 2 SOFIE: SOF Token Interrupt Enable bit
1 = SOFIF interrupt is enabled
0 = SOFIF interrupt is disabled
bit 1 UERRIE: USB Error Interrupt Enable bit
(1)
1 = USB Error interrupt is enabled
0 = USB Error interrupt is disabled
bit 0 URSTIE: USB Reset Interrupt Enab le bit
(2)
1 = URSTIF interrupt is enabled
0 = URSTIF interrupt is disabled
DETACHIE: USB Detach Interrupt Enable bit
(3)
1 = DATTCHIF interrupt is enabled
0 = DATTCHIF interrupt is disabled
Note 1: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set.
2: Device mode.
3: Host mode.
2009-2016 Microchip Technology Inc. DS60001156J- page 145
PIC32MX5XX/6XX/7XX
REGISTER 11-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS
BTSEF BMXEF DMAEF
(1)
BTOEF
(2)
DFN8EF CRC16EF CRC5EF
(4)
PIDEF
EOFEF
(3,5)
Legend: WC = Write ‘1’ to clear HS = Hardware Se ttable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Re ad as ‘ 0’
bit 7 BTSEF: Bit Stuff Error Flag bit
1 = Packet is rejected due to bit stuff error
0 = Packet is accepted
bit 6 BMXEF: Bus Matrix Error Flag bit
1 = Invalid base address of the BDT, or the address of an individual buffer pointed to by a BDT entry
0 = No address error
bit 5 DMAEF: DMA Error Flag bit
(1)
1 = USB DMA error condition detected
0 = No DMA error
bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit
(2)
1 = Bus turnaround time-out has occurred
0 = No bus turnaround time-out
bit 3 DFN8EF: Data Field Size Error Fl ag bit
1 = Data field received is not an integral number of bytes
0 = Data field received is an integral number of bytes
bit 2 CRC16EF: CRC16 Failure Flag bit
1 = Data packet is rejected due to CRC16 error
0 = Data packet is accepte d
bit 1 CRC5EF: CRC5 Host Error Flag bit
(4)
1 = Token packet is rejected due to CRC5 error
0 = Token packet is ac cepted
EOFEF: EOF Error Flag bit
(3,5)
1 = EOF error condition is detected
0 = No EOF error condition
bit 0 PIDEF: PID Check Failure Flag bit
1 = PID check is failed
0 = PID check is passed
Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)
has elapsed.
3: This type of error occurs wh en the module is transmitting or receiving data and the SOF counter has
reached zero.
4: Device mode.
5: Host mode.
PIC32MX5XX/6XX/7XX
DS60001156J-page 146 2009-2016 Microchip Technology Inc.
REGISTER 11-9: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE
(1)
PIDEE
EOFEE
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit
1 = BTSEF interrupt is enabled
0 = BTSEF interrupt is disabled
bit 6 BMXEE: Bus Matrix Error Interrupt Enable bit
1 = BMXEF interrupt is enabled
0 = BMXEF interrupt is disabled
bit 5 DMAEE: DMA Error Interrupt Enable bit
1 = DMAEF interrupt is enabled
0 = DMAEF interrupt is disabl ed
bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = BTOEF interrupt is enabled
0 = BTOEF interrupt is di sabled
bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit
1 = DFN8EF interrupt is enabled
0 = DFN8EF interrupt is disabled
bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16EF interrupt is enabled
0 = CRC16EF interrupt is disabled
bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit
(1)
1 = CRC5EF interrupt is enabled
0 = CRC5EF interrupt is disabled
EOFEE: EOF Error Interrupt Enable bit
(2)
1 = EOF interrupt is enable d
0 = EOF interrupt is disab led
bit 0 PIDEE: PID Check Failure Interrupt Enable bit
1 = PIDEF interrupt is enabled
0 = PIDEF interrupt is disabled
Note 1: Device mode.
2: Host mode.
Note: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set.
2009-2016 Microchip Technology Inc. DS60001156J- page 147
PIC32MX5XX/6XX/7XX
REGISTER 11-10: U1STAT: USB STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R-x R-x R-x R-x R-x R-x U-0 U-0
ENDPT<3:0> DIR PPBI — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Re ad as ‘ 0’
bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits
(Represents the number of the BDT, updated by the last USB transfer.)
1111 = Endpoint 15
1110 = Endpoint 14
•
•
•
0001 = Endpoint 1
0000 = Endpoint 0
bit 3 DIR: Last Buffer Descriptor Direction Indicator bit
1 = Last transaction was a transmit transfer (TX)
0 = Last transaction was a receive transfer (RX)
bit 2 PPBI: Ping-Pong Buffer Descriptor Pointer Indicator bit
1 = The last transaction was to the Odd buffer descriptor bank
0 = The last transaction was to the Even buffer descriptor bank
bit 1-0 Unimplemented: Read as ‘0’
Note: The U1STAT register is a windo w into a 4-byte FI FO mainta ined by the USB m odule. U1STAT value is only
valid when U1IR<TRNIF> is active. Clearing the U1IR<TRNIF> bit advances the FIFO. Data in register is
invalid when U1IR<TRNIF> = 0.
PIC32MX5XX/6XX/7XX
DS60001156J-page 148 2009-2016 Microchip Technology Inc.
REGISTER 11-11: U1CON: USB CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
JSTATE SE0 PKTDIS
(4)
USBRST HOSTEN
(2)
RESUME
(3)
PPBRST USBEN
(4)
TOKBUSY
(1,5)
SOFEN
(5)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl eared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 JSTATE: Live Differential Receiver JSTATE flag bit
1 = JSTATE was detected on the USB
0 = JST ATE was not detected
bit 6 SE0: Live Single-Ended Zero flag bit
1 = Single-ended z ero was detec ted on the US B
0 = Single-ended zero was not detected
bit 5 PKTDIS: Packet Transfer Disable bit
(4)
1 = Token and packet processing disabled (set upon SETUP token received)
0 = Token and pack et proces si ng enabled
TOKBUSY: Token Busy Indicator bit
(1,5)
1 = Token being executed by the USB module
0 = No token being executed
bit 4 USBRST: Module R eset bit
(5)
1 = USB reset is generated
0 = USB reset is terminated
bit 3 HOSTEN: Host Mode Enable bit
(2)
1 = USB host capability is enabled
0 = USB host capability is disabled
bit 2 RESUME: RESUME Signaling Enable bit
(3)
1 = RESUME si gnaling is activated
0 = RESUME signaling is disabled
Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 11-15).
2: All host control logic is reset any time that the value of this bit is toggled.
3: Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to
enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME
signaling when this bit is cleared.
4: Device mode.
5: Host mode.
2009-2016 Microchip Technology Inc. DS60001156J- page 149
PIC32MX5XX/6XX/7XX
bit 1 PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Ev en/Odd buffer pointer s to the Even buffer descriptor banks
0 = Even/Odd buffer pointe rs are not r eset
bit 0 USBEN: USB Module Enable bit
(4)
1 = USB module and supporting circuitry is enabled
0 = USB module and supporting circuitry is disabled
SOFEN: SOF Enable bit
(5)
1 = SOF token is sent every 1 ms
0 = SOF token is disabled
REGISTER 11-11: U1CON: USB CONTROL RE GISTER (CONTINUED)
Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 11-15).
2: All host control logic is reset any time that the value of this bit is toggled.
3: Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to
enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME
signaling when this bit is cleared.
4: Device mode.
5: Host mode.
PIC32MX5XX/6XX/7XX
DS60001156J-page 150 2009-2016 Microchip Technology Inc.
REGISTER 11-12: U1ADDR: USB ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LSPDEN DEVADDR<6:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl eared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 LSPDEN: Low-Speed Enable Indicator bit
1 = Next token command to be executed at low-speed
0 = Next token command to be executed at full-speed
bit 6-0 DEVADDR<6:0>: 7-bit USB Device Address bits
REGISTER 11-13: U1FRML: USB FRAME NUMBER LOW REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
FRML<7:0>
Legend:
R = Readable bit W = Writable bi t U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 FRML<7:0>: 11-bit Frame Number Lower bits
The register bits are updated with the current frame number whenever a SOF TOKEN is received.
2009-2016 Microchip Technology Inc. DS60001156J- page 151
PIC32MX5XX/6XX/7XX
REGISTER 11-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
— — — — — FRMH<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl eared x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2-0 FRMH<2:0>: Upper 3 bits of the Frame Numbers bits
These register bits are updated with the current frame number whenever a SOF TOKEN is received.
REGISTER 11-15: U1TOK: USB TOKEN REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PID<3:0> EP<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Re ad as ‘ 0’
bit 7-4 PID<3:0>: To ken Type Indicator bits
(1)
1101 = SETUP (TX) token type transaction
1001 = IN (RX) token type transaction
0001 = OUT (TX) token type transaction
Note: All other values not listed, are Reserved and must not be used.
bit 3-0 EP<3:0>: Token Command Endpoint Address bits
The four bit value must specify a valid endpoin t.
PIC32MX5XX/6XX/7XX
DS60001156J-page 152 2009-2016 Microchip Technology Inc.
REGISTER 11-16: U1SOF: USB SOF THRESHOLD REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CNT<7:0>
Legend:
R = Readable bit W = Writable bi t U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 CNT<7:0>: SOF Threshold Value bits
Typical values of the threshold are:
01001010 = 64-byte packet
00101010 = 32-byte packet
00011010 = 16-byte packet
00010010 = 8-byte packet
REGISTER 11-17: U1BDTP1: USB BUFFER DESCRIPTOR TABLE PAGE 1 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
BDTPTRL<15:9> —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Re ad as ‘ 0’
bit 7-1 BDTPTRL<15:9>: BDT Base Address bits
This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting
location of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
bit 0 Unimplemented: R ead as ‘0’
2009-2016 Microchip Technology Inc. DS60001156J- page 153
PIC32MX5XX/6XX/7XX
REGISTER 11-18: U1BDTP2: USB BUFFER DESCRIPTOR TABLE PAGE 2 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BDTPTRH<23:16>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 BDTPTRH<23:16>: BDT Base Address bits
This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting
location of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
REGISTER 11-19: U1BDTP3: USB BUFFER DESCRIPTOR TABLE PAGE 3 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BDTPTRU<31:24>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7-0 BDTPTRU<31:24>: BDT Base Address bits
This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location
of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
PIC32MX5XX/6XX/7XX
DS60001156J-page 154 2009-2016 Microchip Technology Inc.
REGISTER 11-20: U1CNFG1: USB CONFIGURATION 1 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0
UTEYE UOEMON —USBSIDL — — —UASUSPND
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 UTEYE: USB Eye-Pattern Test Enable bit
1 = Eye-Pattern Test is enabled
0 = Eye-Pattern Test is disabled
bit 6 UOEMON: USB OE Monitor Enable bit
1 =OE
signal is active; it indicates intervals during which the D+/D- lines are driving
0 =OE
signal is inactive
bit 5 Unimplemented: Read as ‘0’
bit 4 USBSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 3-1 Unimplemented: Read as ‘0’
bit 0 UASUSPND: Automatic Suspend Enable bit
1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit
(U1PWRC<1>) in Register 11-5.
0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the
USUSPEND bit (U1PWRC<1>) to suspend the module, including the USB 48 MHz clock.
2009-2016 Microchip Technology Inc. DS60001156J- page 155
PIC32MX5XX/6XX/7XX
REGISTER 11-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
7:0
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)
1 = Direct conne cti on to a low-speed device enable d
0 = Direct connecti on to a low- spe ed dev ic e disabl ed; hub required wi th PRE _PID
bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)
1 = Retry NAC K’d transactions disabled
0 = Retry NACK’d transactions en abled; retry done in hardware
bit 5 Unimplemented: Read as ‘0’
bit 4 EPCONDIS: Bidirect ional Endp oint C ontrol bit
If EPTXEN = 1 and EPRXEN = 1:
1 = Disable Endpoint ‘n’ from control transfers; only TX and RX transfers are allowed
0 = Enable Endpoint ‘n’ for control (SETUP) transfers; TX and RX transfers are also allowed
Otherwise, this bit is ignored.
bit 3 EPRXEN: Endpoint Receive Enable bit
1 = Endpoi nt ’n’ receive is enabl ed
0 = Endpoi nt ’n’ receive is disab led
bit 2 EPTXEN: Endpoint Transmit Enable bit
1 = Endpoi nt ’n’ transmit is enabl ed
0 = Endpoi nt ’n’ transmit is disab le d
bit 1 EPSTALL: Endpoint Stall Status bit
1 = Endpoi nt ’n’ was st all ed
0 = Endpoint ’n’ was not stalled
bit 0 EPHSHK: Endpoint Handshake Enable bit
1 = Endpoi nt Hand shake is enabled
0 = Endpoint Handshake is disabled (typ ically used for isochronous endpoints)
PIC32MX5XX/6XX/7XX
DS60001156J-page 156 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 157
PIC32MX5XX/6XX/7XX
12.0 I/O PORTS
General purpose I/O pins are the simplest of peripher-
als. They allow the PIC32 MCU to monitor and control
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the dev ice. In genera l, when a periph eral is func tioning,
that pin m ay n ot be used as a general pu rpose I/O pi n.
Following are some of the key features of this module:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up enable/disable
• Monitor selective inputs and generate interrupt
when change in pin state is detected
• Operation during Sleep and Idle modes
• Fast bit manipulation us ing CLR, SET and INV
registers
Figure 12-1 illustrates a block diagram of a typical
multipl ex ed I/O port.
FIGU RE 12-1: BLOC K DI A GRAM O F A TYPICAL M UL T IPL EX E D PO RT STRUCTU RE
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS60001120) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
Peripheral Output Data
Peripheral Module
Peri phe ral Output E nable
PIO Module
Peripheral Module Enable
WR LAT
I/O Pin
WR PORT
Data Bus
RD LAT
RD PORT
RD TRIS
WR TRIS
0
1
RD ODC
PBCLK
QD
CK
EN Q
QD
CK
EN Q
QD
CK
EN Q
QD
CK
Q
QD
CK
Q
0
1
PBCLK
WR ODC
ODC
TRIS
LAT
Sleep
1
0
1
0
Output Multip le xer s
I/O Cell
Synchronization
R
Perip he r al Input
Legend:
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
Note:
This bl ock diagram is a general represe ntation of a shared port/periphe ral structure is only for illustration purpo ses. The actual struct ure
for any specif i c port/per i pheral combination may be different than it is shown here.
Peripheral Input Buffer
PIC32MX5XX/6XX/7XX
DS60001156J-page 158 2009-2016 Microchip Technology Inc.
12.1 Parallel I/O (PIO) Ports
All port pins have three registers (TRIS, LAT and
PORT ) that are directly as sociate d with their opera tion.
TRIS is a Data Direction or Tri-State Control register
that determines whether a digital pin is an input or an
outp ut. Setti ng a T RIS x regis ter bit = 1, configures the
corresponding I/O pin as an input; setting a TRISx
register bit = 0, con figures th e corr espondin g I/O pi n as
an output. All port I/O pins are defined as inputs after a
device Reset. Certain I/O pins are shared with analog
peripherals and default to analog inputs after a device
Reset.
PORT is a register used to read the current state of the
signal applied to the port I/O pins. Writing to a PORTx
register performs a write to the port’s latch, LATx
register, latching the data to the port’s I/O pins.
LAT is a register used to write data to the port I/O pins.
The LATx Latch regis ter hold s the da ta w ritte n to eith er
the LATx or PORTx registers. Reading the LATx Latch
register reads the last value written to the
corresponding PORT or Latch register.
Not all port I/O pins ar e implemente d on some de vices,
therefore, the corresponding PORTx, LATx and TRISx
register bits will read as zeros.
12.1.1 CLR, SET AND INV REGISTERS
Every I/O module register has a corresponding Clear
(CLR), Set (SET) and Invert (INV) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not mo dified.
Reading SET, CLR and INV registers returns un defined
values . To see the affec ts of a write opera tion to a SET,
CLR or INV register, the base register must be read.
12.1.2 DIGITAL INPUTS
Pins are configured as digital inputs by setting the
corresp onding TRIS regi ster bit s = 1. When co nfigure d
as inputs, they are either TTL buffers or Schmitt
Triggers. Several digital pins share functionality with
analog inputs and default to the analog inputs at POR.
Setting the corresponding bit in the AD1PCFG
register = 1 enables the pin as a digital pin.
The maximum input voltage allowed on the input pins
is the same as the maximum V
IH
specifi cation. Refe r to
Section 32.0 “Electrical Characteristics” for V
IH
specification details.
12.1.3 ANALOG INPUTS
Cer ta in pin s can be confi gured as anal og inpu ts used
by the ADC and comparator modules. Setting the
corresponding bits in the AD1PCFG register = 0
enables the pin as an analog input pin and must have
the corresponding TRIS bit set = 1 (input). If the TRIS
bit is cleared = 0 (output), the di gital output level (V
OH
or V
OL
) will be converted. Any time a port I/O pin is
configured as analog, its digital input is disabled and
the corresponding PORTx register bit will read ‘0’. The
AD1PCFG register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
12.1.4 DIGITAL OUTPUTS
Pins are configured as digital outputs by setting the
corresponding TRIS register bits = 0. When co nfigure d
as digital outputs, these pins are CMOS drivers or can
be configured as open-drain outputs by setting the
corresponding bits in the Open-Drain Configuration
(ODCx) register.
The open-drain feature allows generation of outputs
higher than V
DD
(e.g., 5V) on any desired 5V tolerant
pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the
maximum V
IH
specification.
See the “Device Pin Tables” section for the available
pins and their functionality.
12.1.5 ANALOG OUTPUTS
Cert ain pins can be configure d as an alog outp uts, s uch
as the CV
REF
output voltage used by the comparator
module. Configuring the comparator reference module
to provide this output will present the analog output
voltage on the pin, independent of the TRIS register
setting for the corresponding pin.
12.1.6 INPUT CHANGE NOTIFICATION
The input change notification function of the I/O ports
(CNx) allows devices to generate interrupt requests in
response to change-of-state on selected pin.
Each CNx pin also has a weak pull-up, which acts as a
current source connected to the pin. The pull-ups are
enabled by se tting th e corres pondi ng bit i n the C NPUE
register.
Note: Using a PORTx INV regis ter to toggle a bit
is recom mended bec ause the op eration is
performed in hardware atomically, using
fewer instructions, as compared to the
traditional read-modify-write method, as
follows:
PORTC ^ = 0x0001;
Note: Analog levels on any pin that is defined as
a digital input (including the ANx pins)
may cause the input buffer to consume
current that exceeds the device
specifications.
2009-2016 Microchip Technology Inc. DS60001156J-page 159
PIC32MX5XX/6XX/7XX
12.2 Control Registers
TABLE 12-1: PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6000 TRISA 31:16 — — — — — — — — — — — — — — — — 0000
15:0 TRISA15 TRISA14 — — — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF
6010 PORTA 31:16 — — — — — — — — — — — — — — — — 0000
15:0 RA15 RA14 — — — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx
6020 LATA 31:16 — — — — — — — — — — — — — — — — 0000
15:0 LATA15 LATA14 — — — LATA10 LATA9 — LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx
6030 ODCA 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ODCA15 ODCA14 — — — ODCA10 ODCA9 — ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 12-2: PORTB REGISTER MAP
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6040 TRISB 31:16 ————————————————0000
15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
6050 PORTB 31:16 ————————————————0000
15:0 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
6060 LATB 31:16 ————————————————0000
15:0 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
6070 ODCB 31:16 ————————————————0000
15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 160 2009-2016 Microchip Technology Inc.
TABLE 12-3: PORTC REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6080 TRISC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — — — — — — F000
6090 PORTC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 RC15 RC14 RC13 RC12 — — — — — — — — — — — — xxxx
60A0 LATC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 LATC15 LATC14 LATC13 LATC12 — — — — — — — — — — — — xxxx
60B0 ODCC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — — — — — — — — — — — 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 12-4: PORTC REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6080 TRISC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 —F00F
6090 PORTC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 RC15 RC14 RC13 RC12 — — — — — — — RC4 RC3 RC2 RC1 —xxxx
60A0 LATC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 LATC15 LATC14 LATC13 LATC12 — — — — — — — LATC4 LATC3 LATC2 LATC1 —xxxx
60B0 ODCC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — — — — — — ODCC4 ODCC3 ODCC2 ODCC1 —0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more
information.
2009-2016 Microchip Technology Inc. DS60001156J-page 161
PIC32MX5XX/6XX/7XX
TABLE 12-5: PORTD REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
60C0 TRISD 31:16 ————————————————0000
15:0 ———— TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0FFF
60D0 PORTD 31:16 ————————————————0000
15:0 ———— RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx
60E0 LATD 31:16 ————————————————0000
15:0 ———— LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx
60F0 ODCD 31:16 ————————————————0000
15:0 ———— ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 12-6: PORTD REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
60C0 TRISD 31:16 — — — — — — — — — — — — — — — — 0000
15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF
60D0 PORTD 31:16 — — — — — — — — — — — — — — — — 0000
15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx
60E0 LATD 31:16 — — — — — — — — — — — — — — — — 0000
15:0 LAT15 LAT14 LAT13 LAT12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx
60F0 ODCD 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 162 2009-2016 Microchip Technology Inc.
TABLE 12-7: PORTE REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6100 TRISE 31:16 ————————————————0000
15:0 ———————— TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 00FF
6110 PORTE 31:16 ————————————————0000
15:0 ———————— RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx
6120 LATE 31:16 ————————————————0000
15:0 — — — — — — — — LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx
6130 ODCE 31:16 ————————————————0000
15:0 ————————ODCE7 0DCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 12-8: PORTE REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6100 TRISE 31:16 ————————————————0000
15:0 —————— TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF
6110 PORTE 31:16 ————————————————0000
15:0 —————— RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx
6120 LATE 31:16 ————————————————0000
15:0 ——————LATE9LATE8LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx
6130 ODCE 31:16 ————————————————0000
15:0 —————— ODCE9 ODCE8 ODCE7 0DCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2009-2016 Microchip Technology Inc. DS60001156J-page 163
PIC32MX5XX/6XX/7XX
TABLE 12-9: PORTF REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6140 TRISF 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —————————— TRISF5 TRISF4 TRISF3 — TRISF1 TRISF0 003B
6150 PORTF 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —————————— RF5 RF4 RF3 —RF1RF0xxxx
6160 LATF 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —————————— LATF5 LATF4 LATF3 — LATF1 LATF0 xxxx
6170 ODCF 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —————————— ODCF5 ODCF4 ODCF3 — ODCF1 ODCF0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 12-10: PORTF REGISTER MAP PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L,
PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L,
PIC32MX764F128L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6140 TRISF 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —— TRISF13 TRISF12 ——— TRISF8 —— TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 313F
6150 PORTF 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —— RF13 RF12 ———RF8—— RF5 RF4 RF3 RF2 RF1 RF0 xxxx
6160 LATF 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —— LATF13 LATF12 ——— LATF8 —— LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx
6170 ODCF 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —— ODCF13 ODCF12 ——— ODCF8 —— ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 164 2009-2016 Microchip Technology Inc.
TABLE 12-11: PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6180 TRISG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —————— TRISG9 TRISG8 TRISG7 TRISG6 —— TRISG3 TRISG2 — — 03CC
6190 PORTG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —————— RG9 RG8 RG7 RG6 ——RG3RG2— — xxxx
61A0 LATG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —————— LATG9 LATG8 LATG7 LATG6 ——LATG3LATG2— — xxxx
61B0 ODCG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 —————— ODCG9 ODCG8 ODCG7 ODCG6 —— ODCG3 ODCG2 — — 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 12-12: PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6180 TRISG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 TRISG15 TRISG14 TRISG13 TRISG12 —— TRISG9 TRISG8 TRISG7 TRISG6 —— TRISG3 TRISG2 TRISG1 TRISG0 F3CF
6190 PORTG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 RG15 RG14 RG13 RG12 —— RG9 RG8 RG7 RG6 —— RG3 RG2 RG1 RG0 xxxx
61A0 LATG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 LATG15 LATG14 LATG13 LATG12 —— LATG9 LATG8 LATG7 LATG6 —— LATG3 LATG2 LATG1 LATG0 xxxx
61B0 ODCG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ODCG15 ODCG14 ODCG13 ODCG12 —— ODCG9 ODCG8 ODCG7 ODCG6 —— ODCG3 ODCG2 ODCG1 ODCG0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2009-2016 Microchip Technology Inc. DS60001156J-page 165
PIC32MX5XX/6XX/7XX
TABLE 12-13: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L,
PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
61C0 CNCON 31:16 ————————————————0000
15:0 ON — SIDL —————————————0000
61D0 CNEN 31:16 —————————— CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16 0000
15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000
61E0 CNPUE 31:16 —————————— CNPUE21 CNPUE20 CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 12-14: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H,
PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC3 2MX 775F512 H AND PIC32MX79 5F512 H DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
61C0 CNCON 31:16 ————————————————0000
15:0 ON — SIDL —————————————0000
61D0 CNEN 31:16 ————————————— CNEN18 CNEN17 CNEN16 0000
15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000
61E0 CNPUE 31:16 ————————————— CNPUE18 CNPUE17 CNPUE16 0000
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 166 2009-2016 Microchip Technology Inc.
REGISTER 12-1: CNCON: CHANGE NOTICE CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
ON —SIDL— — — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Change Notice (CN) Control ON bit
1 = CN is enabled
0 = CN is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Control bit
1 = Idle mode halts CN operation
0 = Idle mode does not affect CN operation
bit 12-0 Unimplemented: Read as ‘0’
2009-2016 Microchip Technology Inc. DS60001156J- page 167
PIC32MX5XX/6XX/7XX
13.0 TIMER1
This fa mil y of PIC 32 de vi ce s fe atu re s on e synchr on ou s/
asynchronous 16-bit timer that can operate as a free-run-
ning interval timer for various timing applications and
counting external events. This timer can also be used
with the low-power Secondary Oscillator (S
OSC
) for
Real-Time Clock (RTC) applications. The following
modes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
13.1 Additional Supported Features
• Selec t ab le clock prescaler
• Timer operation during Idle and Sleep mode
• Fast bit manipulation us ing CLR, SET and INV
registers
• Asynchronous mode can be used with the S
OSC
to function as a Real-Time Clock (RTC)
A simplified block diagram of the Timer1 module is
illustrated in Figure 13-1.
FIGU RE 13-1: TIMER 1 BLO CK DI AG RAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
ON (T1CON<15>)
Sync
SOSCI
SOSCO/T1CK
PR1
T1IF
Equal 16-bit Comparator
TMR1
Reset
SOSCEN
(1)
Event Flag
1
0
TSYNC (T1CON<2>)
TGATE ( T1CON<7>)
TGATE (T1CON<7>)
PBCLK
1
0
TCS (T1CON<1>)
Gate
Sync
TCKPS<1:0>
Prescaler
2
1, 8, 64, 256
x 1
1 0
0 0
Q
QD
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCC ON<1>) during a dev ice Rese t is contr olled by t he FSOSCE N bit in
Configuration Word, DEVCFG1.
PIC32MX5XX/6XX/7XX
DS60001156J-page 168 2009-2016 Microchip Technology Inc.
13.2 Control Registers
TABLE 13-1: TIMER1 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0600 T1CON 31:16 ————————————————0000
15:0 ON — SIDL TWDIS TWIP ———TGATE— TCKPS<1:0> — TSYNC TCS —0000
0610 TMR1 31:16 ————————————————0000
15:0 TMR1<15:0> 0000
0620 PR1 31:16 ————————————————0000
15:0 PR1<15:0> FFFF
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2009-2016 Microchip Technology Inc. DS60001156J- page 169
PIC32MX5XX/6XX/7XX
REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0
ON
(1)
— SIDL TWDIS TWIP — — —
7:0
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0
TGATE — TCKPS<1:0> — TSYNC TCS —
Legend:
R = Readable bit W = Writable bit U = Unimpl emented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Timer On bit
(1)
1 = Timer is enabled
0 = Timer is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Conti nue operation when devi ce is in Idle mode
bit 12 TWDIS: Asynchronous Timer Write Disable bit
1 = Writes to TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
bit 11 TWIP: Asynchronous Ti mer Write in Progress bit
In Asynchronous Timer mode:
1 = Asynchronous write to TMR1 register in progress
0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as ‘0’.
bit 10-8 Unimplemented: Read as ‘0’
bit 7 TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits
11 = 1:256 prescale value
10 = 1:64 presca le va lue
01 = 1:8 prescale value
00 = 1:1 prescale value
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
PIC32MX5XX/6XX/7XX
DS60001156J-page 170 2009-2016 Microchip Technology Inc.
bit 3 Unimplemented: Read as ‘0’
bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
This bit is ignored.
bit 1 TCS: Timer Clock Source Select bit
1 = External clock from TxCKI pin
0 = Internal peripheral clock
bit 0 Unimplemented: Read as ‘0’
REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
2009-2016 Microchip Technology Inc. DS60001156J- page 171
PIC32MX5XX/6XX/7XX
14.0 TIMER2/ 3, TIMER4/5
This family of PIC32 devices features four synchronous
16-bit timers (default) that can operate as a free-
running interval timer for various timing applications
and cou nting ext ernal e vent s. The fo llo wing m odes a re
supported:
• Synchronous Internal 16-bit Ti mer
• Synchronous Internal 16-bit Gated Timer
• Synchronous External 16-bit Timer
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
The 32-bit timers can operate in three modes:
• Synchron ous Intern al 32-b it Timer
• Synchron ous Intern al 32-b it Gated Timer
• Synchron ous External 32-bit T imer
14.1 Additional Supported Features
• Selec t ab le clock prescaler
• Timers operational during CPU idle
• T ime base for Input Captu re and Outpu t Comp are
modules (only Timer2 and Timer3)
• ADC event trigger (only Timer3)
• Fast bit manipulation us ing CLR, SET and INV
registers
FIGU RE 14 -1: TIM ER2/ 3 AND T I MER4/5 BLOCK DI AGR AM (16 -BIT )
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS60001105) of the “PIC32 Family Ref-
erence Manual”, which is available from
the Microchip web site (www.micro-
chip.com/PIC32).
Note: In this chapter, references to registers,
TxCON, TMRx and PRx, use ‘x’ to
represen t Timer2 through Timer5 in 16-b it
modes. In 32-bit modes, ‘x’ represents
T imer 2 or T imer4; ‘y ’ represen ts T ime r3 or
Timer5.
Sync
PRx
TxIF
Equal Comparator x 16
TMRx
Reset
Event Flag
Q
QD
TGATE (TxCON<7>)
1
0
Gate
TxCK
(2)
Sync
ON (TxCON<15>)
TGATE (TxCON<7>)
TCS (TxCON<1>)
TCKPS (T xCON <6:4 >)
Prescaler
3
1, 2, 4, 8, 16,
32, 64, 256
x 1
1 0
0 0
PBCLK
Trigger
(1)
ADC Event
Note 1: ADC event trigger is only available on Timer3.
2: TxCK pins are not available on 64-pin devices.
PIC32MX5XX/6XX/7XX
DS60001156J-page 172 2009-2016 Microchip Technology Inc.
FIGU RE 14 -2: TIME R2/ 3 AND T IME R4/5 BLOCK DI AGRAM (32- BIT)
TMRy
TMRx
TyIF Event
Equal 32-bit Comparator
PRy
PRx
Reset
LS Half Word
MS Half Word
Flag
Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or T imer4; the use
of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
2: TxCK pins are not available on 64-pin devices.
3: ADC event trigger is only available on the Timer2 /3 pair.
TGATE (TxCON<7>)
0
1
PBCLK
Gate
TxCK
(2)
Sync
Sync
ADC Event
Trigger
(3)
ON (TxCON<15>)
TGATE (TxCON<7>)
TCS (TxCON<1>)
TCKPS (TxCON<6:4>)
Prescaler
3
1, 2, 4, 8, 16,
32, 64, 256
1 0
0 0
Q
QD
x 1
2009-2016 Microchip Technology Inc. DS60001156J-page 173
PIC32MX5XX/6XX/7XX
14.2 Control Registers
TABLE 14-1: TIMER2 THROUGH TIMER5 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0800 T2CON 31:16 ————————————————0000
15:0 ON — SIDL ————— TGATE TCKPS<2:0> T32 —TCS
(2)
—0000
0810 TMR2 31:16 ————————————————0000
15:0 TMR2<15:0> 0000
0820 PR2 31:16 ————————————————0000
15:0 PR2<15:0> FFFF
0A00 T3CON 31:16 ————————————————0000
15:0 ON — SIDL ————— TGATE TCKPS<2:0> ——TCS
(2)
—0000
0A10 TMR3 31:16 ————————————————0000
15:0 TMR3<15:0> 0000
0A20 PR3 31:16 ————————————————0000
15:0 PR3<15:0> FFFF
0C00 T4CON 31:16 ————————————————0000
15:0 ON — SIDL ————— TGATE TCKPS<2:0> T32 —TCS
(2)
—0000
0C10 TMR4 31:16 ————————————————0000
15:0 TMR4<15:0> 0000
0C20 PR4 31:16 ————————————————0000
15:0 PR4<15:0> FFFF
0E00 T5CON 31:16 ————————————————0000
15:0 ON — SIDL ————— TGATE TCKPS<2:0> ——TCS
(2)
—0000
0E10 TMR5 31:16 ————————————————0000
15:0 TMR5<15:0> 0000
0E20 PR5 31:16 ————————————————0000
15:0 PR5<15:0> FFFF
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: These bits are not available on 64-pin devices.
PIC32MX5XX/6XX/7XX
DS60001156J-page 174 2009-2016 Microchip Technology Inc.
REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
ON
(1,3)
—SIDL
(4)
— — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
TGATE
(3)
TCKPS<2:0>
(3)
T32
(2)
—TCS
(3)
—
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Timer On bit
(1,3)
1 = Module is enabled
0 = Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
(4)
1 = Discontinue operation when device enters Idle mode
0 = Continue operation when device is in Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7 TGATE: Timer Gated Time Accumulation Enable bit
(3)
When TCS = 1:
This bit is ignored and is read as ‘0’.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits
(3)
111 = 1:256 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
2: This bit is only availabl e on even numbered timers (Timer2 and Timer4).
3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Tim-
er5). All timer functions are set through the even numbered timers.
4: While op erat ing in 32-bit m ode, th is bit must b e clea red on o dd num bered ti mers t o enabl e the 3 2-bit tim er
in Idle mode.
2009-2016 Microchip Technology Inc. DS60001156J- page 175
PIC32MX5XX/6XX/7XX
bit 3 T32: 32-Bit Timer Mode Select bit
(2)
1 = Odd num bered and even numbered tim ers form a 32-bit timer
0 = Odd numbered and even numbered timers form a separate 16 -bit tim er
bit 2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer Clock Source Select bit
(3)
1 = External clock from TxCK pin
0 = Internal peripheral clock
bit 0 Unimplemented: Read as ‘0’
REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
2: This bit is only available on even numbered timers (Timer2 and Timer4).
3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Tim-
er5). All timer functions are set through the even numbered timers.
4: While op erat ing in 32-bit m ode, th is bit must b e clea red on o dd num bered ti mers t o enabl e the 3 2-bit tim er
in Idle mode.
PIC32MX5XX/6XX/7XX
DS60001156J-page 176 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 177
PIC32MX5XX/6XX/7XX
15.0 WATCHDOG TIMER (WDT)
This section describes the operation of the WDT and
Power-up Timer of the PIC32MX5XX/6XX/7XX.
The WDT, when enabled, operates from the internal
Low-Pow e r Os ci ll ator (LPRC) clock sou rce and can be
used to detect system software malfunctions by reset-
ting the device if the WDT is not cleared periodically in
software. Various WDT time-out periods can be
select ed usin g the WD T post sc aler. The WDT can also
be used to wake the device from Sleep or Idle mode.
The following are key features of the WDT module:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle mode
FIGURE 15-1: WATC HDOG TIMER AND POWER-UP TIMER BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Watchdog
Timer and Power-up Timer”
(DS60001114) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
Wake
WDTCLR = 1
WDT Enable
LPRC
Power Save
25-bit Counter
PWRT Enable
WDT Enable LPRC
WDT Counter Reset
Control
Oscillator
25 Device Reset
NMI (Wake-up)
PWRT
PWRT Enable
FWDTPS<4:0> (DEVCFG1<20:16>)
Clock
Decoder
1
1:64 Output
0
1
WDT Enable
Reset Event
PIC32MX5XX/6XX/7XX
DS60001156J-page 178 2009-2016 Microchip Technology Inc.
15.1 Control Registers
TABLE 15-1: WATCHDOG TIMER REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
(2)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0000 WDTCON 31:16 ————————————————0000
15:0 ON ———————— SWDTPS<4:0> — WDTCLR 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
2009-2016 Microchip Technology Inc. DS60001156J- page 179
PIC32MX5XX/6XX/7XX
REGISTER 15-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
ON
(1,2)
— — — — — — —
7:0
U-0 R-y R-y R-y R-y R-y R/W-0 R/W-0
— SWDTPS<4:0> WDTWINEN WDTCLR
Legend: y = Values set from Configuration bits on POR
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Watchdog Timer Enable bit
(1,2)
1 = Enables the WDT if it is not enabled by the device configuration
0 = Disable the WDT if it was enabled in software
bit 14-7 Unimplemented: Read as ‘0’
bit 6-2 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits
On reset, these bits are set to the values of the WDTPS <4:0> Configuration bits.
bit 1 WDTWINEN: Watchdog Timer Window Enable bit
1 = Enable windowed Watchdog Timer
0 = Disabl e windowed Watchdog Timer
bit 0 WDTCLR: Watchdog Timer Reset bit
1 = Writing a ‘1’ will clear the WDT
0 = Software cannot force this bit to a ‘ 0’
Note 1: A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software.
2: When using the 1:1 PBCLK divi sor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately followi ng the instruction that clears the module’s ON bit.
PIC32MX5XX/6XX/7XX
DS60001156J-page 180 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 181
PIC32MX5XX/6XX/7XX
16.0 INPUT CAPTURE
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
The Input Capture module captures the 16-bi t or 32-bit
value of the selected Time Base registers when an
event oc curs at the ICx pin. The fol lowing event s cause
capture ev ent s :
• Simple capture event modes:
- Capture timer value on every falling edge of input
at ICx pin
- Capture timer value on every rising edge of input
at ICx pin
• Capture timer value on every edge (rising and
falling)
• Capture timer value on every edge (rising and
falling), specified edge first.
• Prescaler capture event modes:
- Capture timer value on every 4th rising edge of
input at ICx pin
- Capture timer value on every 16th rising edge of
input at ICx pin
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base,
or two 16-bit timers (Timer2 and Timer3) together to
form a 32-bit timer. The selected timer can us e either
an internal or external clock.
Other operational features include:
• Device wake-up from capture pin during Sleep and
Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
Interrupt o ptionally generated after 1 , 2, 3 or 4 bu ffer
locations are filled
• Input Capture module can also be used to provide
additional sources of external interrupts
FIGURE 16-1: INPUT CAPTURE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 15. “Input Cap-
ture” (DS60001 122) of the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
Prescaler
1, 4, 16 Edge Detect
FIFO Control
Interrupt
Event
Generation
ICxBUF<31:16>
Interrupt
Timer3 Timer2
ICxCON ICI<1:0>
ICx Input
0
1
ICxBUF<15:0>
Data Space Interface
Peripheral Data Bus
C32
ICTMR
ICM<2:0>
FEDGE ICBNE
ICOV
ICM<2:0>
PIC32MX5XX/6XX/7XX
DS60001156J-page 182 2009-2016 Microchip Technology Inc.
16.1 Control Registers
TABLE 16-1: INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2000 IC1CON
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
2010 IC1BUF 31:16 IC1BUF<31:0> xxxx
15:0 xxxx
2200 IC2CON
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
2210 IC2BUF 31:16 IC2BUF<31:0> xxxx
15:0 xxxx
2400 IC3CON
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
2410 IC3BUF 31:16 IC3BUF<31:0> xxxx
15:0 xxxx
2600 IC4CON
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
2610 IC4BUF 31:16 IC4BUF<31:0> xxxx
15:0 xxxx
2800 IC5CON
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
2810 IC5BUF 31:16 IC5BUF<31:0> xxxx
15:0 xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
2009-2016 Microchip Technology Inc. DS60001156J- page 183
PIC32MX5XX/6XX/7XX
REGISTER 16-1: IC
X
CON: INPUT CAPTURE ‘
X
’ CONTROL REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
ON
(1)
—SIDL— — —FEDGEC32
7:0
R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0
ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Input Capture Module Enable bit
(1)
1= Module is enabled
0= Disable a nd res et mod ule, d isabl e cloc ks, dis able i nterrup t genera tion a nd allow SF R mo dific ations
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Control bit
1= Halt in Idle mode
0= Continue to operate in Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9 FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110)
1= Capture rising edge first
0= Capture falling edge first
bit 8 C32: 32-bit Capture Select bit
1= 32-bit timer resource capture
0= 16-bit timer resource capture
bit 7 ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is ‘1’)
1= Timer2 is the counter source for capture
0= Timer3 is the counter source for ca pture
bit 6-5 ICI<1:0>: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)
1= Input capture overflow is occurred
0= No input capture overflow is occurred
bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1= Input capture buffer is not empty; at least one mo re capture value can be read
0= Input capture buffer is empty
Note 1: When us ing the 1:1 PBC LK d ivi so r, the user’s sof tw a re s hou ld not r ead/write the per iph eral ’ s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
PIC32MX5XX/6XX/7XX
DS60001156J-page 184 2009-2016 Microchip Technology Inc.
bit 2-0 ICM<2:0>: Input Cap ture Mo de Sele ct bits
111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter
101 = Prescaled Capture Event mode – every sixteenth rising edge
100 = Prescaled Ca pture Event mode – every fourth rising edge
011 = Simple Capture Event mode – every rising edge
010 = Simple Capture Event mode – every falling edge
001 = Edge Detect mode – every edge (rising and falling)
000 = Input Capture module is disabled
REGISTER 16-1: IC
X
CON: INPUT CAPTURE ‘
X
’ CONTROL REGISTER (CONTINUED)
Note 1: When us ing the 1:1 PBC LK d ivi so r, the user’s sof tw a re s hou ld not r ead/write the per iph eral ’ s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
2009-2016 Microchip Technology Inc. DS60001156J- page 185
PIC32MX5XX/6XX/7XX
17. 0 OUT P UT COMP A RE
The Output Compare module is used to generate a
single pulse or a series of pulses in response to
selected time base events. For all modes of operation,
the Output Compare module compares the values
stored in the OCxR and/or the OCxRS registers to the
value in the selected timer. When a match occurs, the
Output Com pa re mo dule gen erates an event ba sed on
the selected mode of operation.
The following are key features of the Output Compare
module:
• Multiple Output Compare modules in a device
• Programmable interrupt generation on compare
event
• Single and Dual Compare modes
• Single and continuous output pulse generation
• Pulse-Wi dth Modulation (PWM ) mode
• Hardware-based PWM Fault detection and
automatic output disable
• Programmable selection of 16-bit or 32-bit time
bases
• Can operate from either of two available 16-bit
time bases or a single 32-bit time base
FIGURE 17-1: OUT PUT COM PARE MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, re fer to Section 16. “Output Com-
pare” (DS60001 111) in the “PIC32 Fami ly
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
OCxR
(1)
Comparator
Output
Logic QS
R
OCM<2:0>
Output E nab l e
OCx
(1)
Set Flag bit
OCxIF
(1)
OCxRS
(1)
Mode Select
3
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.
01
OCTSEL
01
16
16
OCF A or OCFB
(2)
TMR Register Inputs
from Time Bases
(3)
Period Match Signals
from Time Bases
(3)
Logic
Output
Enable
PIC32MX5XX/6XX/7XX
DS60001156J-page 186 2009-2016 Microchip Technology Inc.
17.1 Control Registers
TABLE 17-1: OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
3000 OC1CON 31:16 ————————————————0000
15:0 ON — SIDL ——————— OC32 OCFLT OCTSEL OCM<2:0> 0000
3010 OC1R 31:16 OC1R<31:0> xxxx
15:0 xxxx
3020 OC1RS 31:16 OC1RS<31:0> xxxx
15:0 xxxx
3200 OC2CON 31:16 ————————————————0000
15:0 ON — SIDL ——————— OC32 OCFLT OCTSEL OCM<2:0> 0000
3210 OC2R 31:16 OC2R<31:0> xxxx
15:0 xxxx
3220 OC2RS 31:16 OC2RS<31:0> xxxx
15:0 xxxx
3400 OC3CON 31:16 ————————————————0000
15:0 ON — SIDL ——————— OC32 OCFLT OCTSEL OCM<2:0> 0000
3410 OC3R 31:16 OC3R<31:0> xxxx
15:0 xxxx
3420 OC3RS 31:16
15:0 OC3RS<31:0> xxxx
xxxx
3600 OC4CON 31:16 ————————————————0000
15:0 ON — SIDL ——————— OC32 OCFLT OCTSEL OCM<2:0> 0000
3610 OC4R 31:16 OC4R<31:0> xxxx
15:0 xxxx
3620 OC4RS 31:16
15:0 OC4RS<31:0> xxxx
xxxx
3800 OC5CON 31:16 ————————————————0000
15:0 ON — SIDL ——————— OC32 OCFLT OCTSEL OCM<2:0> 0000
3810 OC5R 31:16 OC5R<31:0> xxxx
15:0 xxxx
3820 OC5RS 31:16 OC5RS<31:0> xxxx
15:0 xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2009-2016 Microchip Technology Inc. DS60001156J- page 187
PIC32MX5XX/6XX/7XX
REGISTER 17-1: OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
ON
(1)
—SIDL— — — — —
7:0
U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
—— OC32 OCFLT
(2)
OCTSEL OCM<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Output C ompare Module On bit
(1)
1 = Output Compare module is ena ble d
0 = Output Compare module is dis ab led
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters Idle mode
0 = Continue operation when CPU is in Idle mode
bit 12-6 Unimplemented: Read as ‘0’
bit 5 OC32: 32-bit Compare Mode bit
1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisons to the 32-bit timer source
0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source
bit 4 OCFLT: PWM Fault Condition Status bit
(2)
1 = PWM Fault condition has occurred (only cleared in hardware)
0 = PWM Fault condition has not occurred
bit 3 OCTSEL: Output Compar e Timer Sele ct bit
1 = Timer3 is the clock source for this Output Compare module
0 = Timer2 is the clock source for this Output Compare module
bit 2-0 OCM<2:0>: Output Compare Mode Select bits
111 = PWM mode on OCx ; Fault pin enabl ed
110 = PWM mode on OCx ; Fault pin disa ble d
101 = Initialize OCx pin low; generate continuous output pulses on OCx pin
100 = Initialize OCx pin low; generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high; compare event forces OCx pin low
001 = Initialize OCx pin low; compare event forces OCx pin high
000 = Output compare peripheral is disabled but continues to draw current
Note 1: When usin g the 1:1 PBCLK di vis or, the user’s software should not read/ w rite the peri ph eral ’ s SFR s in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
2: This bit is only used when OCM<2:0> = 111. It is read as ‘0’ in all other modes.
PIC32MX5XX/6XX/7XX
DS60001156J-page 188 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 189
PIC32MX5XX/6XX/7XX
18.0 SERIAL PERIPHERAL
INTERFACE (SPI)
The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
and other microcontroller devices. These peripheral
devices may be Serial EEPROMs, Shift registers, dis-
play drivers, Analog-to-Digital Converters, etc. The
PIC32 SPI module is compatible with Motorola
®
SPI
and SIOP interfaces.
The following are some of the key features of the SPI
module:
• Master mode and Slave mode support
• Four differen t clock fo rmats
• Enhanced Framed SPI protocol support
• User-configurable 8-bit, 16-bit and 32-bit data
width
• Separate SPI FIFO buffers for receive and transmit
- FIFO buffer s act as 4/8/ 16-l ev el dee p FIFO s
based on 32/16/8-bit data width
• Programm abl e inter r upt ev ent on eve ry 8-bi t,
16-bit and 32-bit data transfer
• Operation during Sleep and Idle modes
• Fast bit manipulation us ing CLR, SET and INV
registers
FIGURE 18-1: SP I MOD ULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference sourc e. To com -
plement the information in this data sheet,
refer to Section 23. “Serial Peripheral
Interface (SPI)” (DS60001106) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
Internal
Data Bus
SDIx
SDOx
SSx/F
SYNC
SCKx
SPIxSR
bit 0
Shift
Control Edge
Select
Enable Master Clock
Baud Rate
Slave Select
Sync Control
Clock
Control
Transmit
Receive
and Frame
Note: Access SP IxTX B and SPI xRX B FIFOs via SPIxBUF registe r.
FIFOs Share Address SPIxBUF
SPIxBUF
Generator PBCLK
WriteRead
SPIx TXB FIF O
SPIxRXB FIFO
PIC32MX5XX/6XX/7XX
DS60001156J-page 190 2009-2016 Microchip Technology Inc.
18.1 Control Registers
TABLE 18-1: SPI1 THROUGH SP I4 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
5E00 SPI1CON
(2)
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> — — — — — — SPIFE ENHBUF 0000
15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN — STXISEL<1:0> SRXISEL<1:0> 0000
5E10 SPI1STAT
(2)
31:16 ——— RXBUFELM<4:0> ——— TXBUFELM<4:0> 0000
15:0 ———— SPIBUSY —— SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008
5E20 SPI1BUF
(2)
31:16 DATA<31:0> 0000
15:0 0000
5E30 SPI1BRG
(2)
31:16 ————————————————0000
15:0 ———————BRG<8:0>0000
5800 SPI3CON 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> — — — — — — SPIFE ENHBUF 0000
15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN — STXISEL<1:0> SRXISEL<1:0> 0000
5810 SPI3STAT 31:16 ——— RXBUFELM<4:0> ——— TXBUFELM<4:0> 0000
15:0 ———— SPIBUSY —— SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008
5820 SPI3BUF 31:16 DATA<31:0> 0000
15:0 0000
5830 SPI3BRG 31:16 ————————————————0000
15:0 ———————BRG<8:0>0000
5A00 SPI2CON 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> — — — — — — SPIFE ENHBUF 0000
15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN — STXISEL<1:0> SRXISEL<1:0> 0000
5A10 SPI2STAT 31:16 ——— RXBUFELM<4:0> ——— TXBUFELM<4:0> 0000
15:0 ———— SPIBUSY —— SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008
5A20 SPI2BUF 31:16 DATA<31:0> 0000
15:0 0000
5A30 SPI2BRG 31:16 ————————————————0000
15:0 ———————BRG<8:0>0000
5C00 SPI4CON 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> — — — — — — SPIFE ENHBUF 0000
15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN — STXISEL<1:0> SRXISEL<1:0> 0000
5C10 SPI4STAT 31:16 ——— RXBUFELM<4:0> ——— TXBUFELM<4:0> 0000
15:0 ———— SPIBUSY —— SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008
5C20 SPI4BUF 31:16 DATA<31:0> 0000
15:0 0000
5C30 SPI4BRG 31:16 ————————————————0000
15:0 ———————BRG<8:0>0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively . See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
2: This register is not available on 64-pin devices.
2009-2016 Microchip Technology Inc. DS60001156J- page 191
PIC32MX5XX/6XX/7XX
REGISTER 18-1: SPIxCON: SPI CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0>
23:16
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SPIFE ENHBUF
(2)
15:8
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ON
(1)
— SIDL DISSDO MODE32 MODE16 SMP CKE
(3)
7:0
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEN CKP MSTEN — STXISEL<1:0> SRXISEL<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FRMEN: Framed SPI Support bit
1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output )
0 = Framed SPI support is disabled
bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (only Framed SPI mode)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
bit 29 FRMPOL: Frame Sync Polarity bit (only Framed SPI mode)
1 = Frame pulse is active-high
0 = Frame pulse is active-low
bit 28 MSSEN: Master Mode Slave Select Enable bit
1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in
Master mode. Polarity is determined by the FRMPOL bit.
0 = Slave select SPI support is disabled.
bit 27 FRMSYPW: Frame Sync Pulse Width bit
1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide
bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per
pulse. This bit is only valid in Framed Sync mode.
111 = Reserved
110 = Reserved
101 = Generate a frame sync pulse on every 32 data characters
100 = Generate a frame sync pulse on every 16 data characters
011 = Generate a frame sync pulse on every 8 data characters
010 = Generate a frame sync pulse on every 4 data characters
001 = Generate a frame sync pulse on every 2 data characters
000 = Generate a frame sync pulse on every data character
bit 23-18 Unimplemented: Read as ‘0’
bit 17 SPIFE: Frame Sync Pulse Edge Select bit (only Framed SPI mode)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
bit 16 ENHBUF: Enhanced Buffer Enable bit
(2)
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately followi ng the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode ( FRMEN = 1).
PIC32MX5XX/6XX/7XX
DS60001156J-page 192 2009-2016 Microchip Technology Inc.
bit 15 ON: SPI Peripheral On bit
(1)
1 = SPI Peripheral is enabled
0 = SPI Peripheral is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontin ue ope ratio n wh en CP U enters in Idle mode
0 = Continue operation in Idle mode
bit 12 DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by the module (pin is controlled by associated PORT register)
0 = SDOx pin is controlled by the module
bit 11- 10 MODE<32,16>: 32/16-Bit C om mu nicati on Select bits
MODE32 MODE16 Communication
1x32-bit
0116-bit
008-bit
bit 9 SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1 = Input data s ampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
bit 8 CKE: SPI Clock Edge Select bit
(3)
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
bit 7 SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin used for Slave mode
0 = SSx pin not used for Slave mode (pin is controlled by port function)
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 =Slave mode
bit 4 Unimplemented: Read as ‘0’
bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits
11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
10 = Interrupt is generated when the buffer is empty by one-half or more
01 = Interrupt is generated when the buffer is completely empty
00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are
complete
bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits
11 = Interrupt is generated when the buffer is full
10 = Interrupt is generated when the buffer is full by one-half or more
01 = Interrupt is generated when the buffer is not empty
00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
REGISTER 18-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately foll owing the instructio n that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode ( FRMEN = 1).
2009-2016 Microchip Technology Inc. DS60001156J- page 193
PIC32MX5XX/6XX/7XX
REGISTER 18-2: SPIxSTAT: SPI STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — RXBUFELM<4:0>
23:16
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — TXBUFELM<4:0>
15:8
U-0 U-0 U-0 U-0 R-0 U-0 U-0 R-0
— — — — SPIBUSY — — SPITUR
7:0
R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0
SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF
Legend: C = Clearable bit HS = Set in hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (only valid when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (only valid when ENHBUF = 1)
bit 15-12 Unimplemented: Read as ‘0’
bit 11 SPIBUSY: SPI Activi ty Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
bit 10-9 Unimplemented: Read as ‘0’
bit 8 SPITUR: Transmit Under Run bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only va lid in Fram ed Sync mod e; the unde rrun con dition must be cleare d by disa bling/re-en abling
the module.
bit 7 SRMT: Shift Register Empty bit (only valid when ENHBUF = 1)
1 = When SPI module shift register is empty
0 = When SPI module shift register is not empty
bit 6 SPIROV: Receive Overflow Flag bit
1 = A new data is compl etely received an d discarded. The user software h as not read th e previous data in
the SPIxBUF regist er.
0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
bit 5 SPIRBE: RX FIFO Empty bit (only valid when ENHBUF = 1)
1 = RX FIFO is empty (CRPTR = SWPTR)
0 = RX FIFO is not empty (CRPTR
SWPTR)
bit 4 Unimplemented: Read as ‘0’
bit 3 SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buff er, SPIxTXB is empty
0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
bit 2 Unimplemented: Read as ‘0’
PIC32MX5XX/6XX/7XX
DS60001156J-page 194 2009-2016 Microchip Technology Inc.
bit 1 SPITBF: SPI Transmit Buffer Full Status bit
1 = Transmit not yet started, SPITXB is full
0 = Transmit buffer is not full
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.
Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise
bit 0 SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full
0 = Receive buffer, SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise
REGISTER 18-2: SPIxSTAT: SPI STATUS REGISTER
2009-2016 Microchip Technology Inc. DS60001156J- page 195
PIC32MX5XX/6XX/7XX
19.0 INTER-INTEGRATED CIRCUIT
(I
2
C)
The I
2
C module provides complete hardware support
for both S lave and Mu lti-Maste r modes of the I
2
C serial
communication standard. Figure 19-1 illustrates the
I
2
C module block diagram.
Each I
2
C modul e h as a 2-pi n i nte rfac e: the SC Lx pi n i s
clock and the SDAx pin is data.
Each I
2
C module offers the following key features:
•I
2
C interface supporting both master and slave
operation
•I
2
C Slave mode suppo rts 7-bit a nd 10-b it addr essin g
•I
2
C Master mode supports 7-bit and 10-bit
addressing
•I
2
C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for the I
2
C port can
be used as a handshake mechanism to suspend
and resume serial transfer (SCLREL control)
•I
2
C supports multi-master operation; detects bus
collision and arbitrates accordingly
• Provides support for address bit masking
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 24. “Inter-
Integrated Circuit (I
2
C)” (DS60001116)
in the “PIC32 Family R efere nce Manua l”,
which is available from the Micro chip web
site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX
DS60001156J-page 196 2009-2016 Microchip Technology Inc.
FIGURE 19-1: I
2
C BLOCK DIAGRAM
Internal
Data Bus
SCLx
SDAx
Shift
Match Detect
I2CxADD
S tart and Stop
bit Detect
Clock
Address Match
Clock
Stretching
I2CxTRN LSB
Shift Clock
BRG Down Counter
Reload
Control
PBCLK
S tart and Stop
bit Generation
Acknowledge
Generation
Collision
Detect
I2CxCON
I2CxSTAT
Control Logic
Read
LSB
Write
Read
I2CxBRG
I2CxRSR
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
I2CxMSK
I2CxRCV
2009-2016 Microchip Technology Inc. DS60001156J-page 197
PIC32MX5XX/6XX/7XX
19.1 Control Registers
TABLE 19-1: I2C1THROUGH I2C5 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
5000 I2C3CON 31:16 ————————————————0000
15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
5010 I2C3STAT 31:16 ————————————————0000
15:0 ACKSTAT TRSTAT ——— BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
5020 I2C3ADD 31:16 ————————————————0000
15:0 —————— ADD<9:0> 0000
5030 I2C3MSK 31:16 ————————————————0000
15:0 —————— MSK<9:0> 0000
5040 I2C3BRG 31:16 ————————————————0000
15:0 ———— Baud Rate Generator Register 0000
5050 I2C3TRN 31:16 ————————————————0000
15:0 ———————— Transmit Register 0000
5060 I2C3RCV 31:16 ————————————————0000
15:0 ———————— Receive Register 0000
5100 I2C4CON 31:16 ————————————————0000
15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
5110 I2C4STAT 31:16 ————————————————0000
15:0 ACKSTAT TRSTAT ——— BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
5120 I2C4ADD 31:16 ————————————————0000
15:0 —————— ADD<9:0> 0000
5130 I2C4MSK 31:16 ————————————————0000
15:0 —————— MSK<9:0> 0000
5140 I2C4BRG 31:16 ————————————————0000
15:0 ———— Baud Rate Generator Register 0000
5150 I2C4TRN 31:16 ————————————————0000
15:0 ———————— Transmit Register 0000
5160 I2C4RCV 31:16 ————————————————0000
15:0 ———————— Receive Register 0000
5200 I2C5CON 31:16 ————————————————0000
15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
5210 I2C5STAT 31:16 ————————————————0000
15:0 ACKSTAT TRSTAT ——— BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
5220 I2C5ADD 31:16 ————————————————0000
15:0 —————— ADD<9:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus of fsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
2: This register is not available on 64-pin devices.
PIC32MX5XX/6XX/7XX
DS60001156J-page 198 2009-2016 Microchip Technology Inc.
5230 I2C5MSK 31:16 ————————————————0000
15:0 —————— MSK<9:0> 0000
5240 I2C5BRG 31:16 ————————————————0000
15:0 ———— Baud Rate Generator Register 0000
5250 I2C5TRN 31:16 ————————————————0000
15:0 ———————— Transmit Register 0000
5260 I2C5RCV 31:16 ————————————————0000
15:0 ———————— Receive Register 0000
5300 I2C1CON 31:16 ————————————————0000
15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
5310 I2C1STAT 31:16 ————————————————0000
15:0 ACKSTAT TRSTAT ——— BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
5320 I2C1ADD 31:16 ————————————————0000
15:0 —————— ADD<9:0> 0000
5330 I2C1MSK 31:16 ————————————————0000
15:0 —————— MSK<9:0> 0000
5340 I2C1BRG 31:16 ————————————————0000
15:0 ———— Baud Rate Generator Register 0000
5350 I2C1TRN 31:16 ————————————————0000
15:0 ———————— Transmit Register 0000
5360 I2C1RCV 31:16 ————————————————0000
15:0 ———————— Receive Register 0000
5400 I2C2CON
(2)
31:16 ————————————————0000
15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
5410 I2C2STAT
(2)
31:16 ————————————————0000
15:0 ACKSTAT TRSTAT ——— BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
5420 I2C2ADD
(2)
31:16 ————————————————0000
15:0 —————— ADD<9:0> 0000
5430 I2C2MSK
(2)
31:16 ————————————————0000
15:0 —————— MSK<9:0> 0000
5440 I2C2BRG
(2)
31:16 ————————————————0000
15:0 ———— Baud Rate Generator Register 0000
5450 I2C2TRN
(2)
31:16 ————————————————0000
15:0 ———————— Transmit Register 0000
5460 I2C2RCV
(2)
31:16 ————————————————0000
15:0 ———————— Receive Register 0000
TABLE 19-1: I2C1THROUGH I2C5 REGISTER MAP (CONTINUED)
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus of fsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
2: This register is not available on 64-pin devices.
2009-2016 Microchip Technology Inc. DS60001156J- page 199
PIC32MX5XX/6XX/7XX
REGISTER 19-1: I2C
X
CON: I
2
C CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
ON
(1)
— SIDL SCLREL STRICT A10M DISSLW SMEN
7:0
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
Legend: HC = Cl eared by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: I
2
C Enabl e bit
(1)
1 = Enables the I
2
C module and configures the SDA and SCL pins as serial port pins
0 = Disables the I
2
C module; all I
2
C pins are controlled by PORT functions
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation when device enters Idle mode
bit 12 SCLREL: SCLx Release Control bit (when operating as I
2
C slave)
1 = Release SCLx cloc k
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Cleared by hardware at
the beginning of a slave transmission and at the end of slave reception.
If STREN = 0:
Bit is R/S (software can only wri te ‘1’ to release cloc k). Cleared by hardware at the beginning of slave
transmission.
bit 11 STRICT: Strict I
2
C Reserved Address Rule Enable bit
1 = S trict reserved addressing is enforced. Device does not respond to reserved address space or gene rate
addresse s in reserved address space.
0 = Strict I
2
C reser ved address r ule is not enabled
bit 10 A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
PIC32MX5XX/6XX/7XX
DS60001156J-page 200 2009-2016 Microchip Technology Inc.
bit 7 GCEN: General Call Enable bit (when operating as I
2
C slave)
1 = Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0 = General call address is disabled
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I
2
C slave)
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
bit 5 ACKDT: Acknowledge Data bit (when operating as I
2
C master, applicable duri ng master receive)
Value that is transmitted when the software initiates an acknowledge sequence.
1 = Send NACK during an acknowledge
0 = Send ACK during an acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I
2
C master, applicable during master
receive)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence.
0 = Acknowledge sequence not in progress
bit 3 RCEN: Receive Enable bit (when operating as I
2
C master)
1 = Enables Receive mode for I
2
C. Hardware clear at end of eighth bit of master receive data byte.
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I
2
C master)
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I
2
C master)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated
Start sequence.
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I
2
C master)
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start conditio n is not in progre ss
REGISTER 19-1: I2C
X
CON: I
2
C CONTROL REGISTER (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
2009-2016 Microchip Technology Inc. DS60001156J- page 201
PIC32MX5XX/6XX/7XX
REGISTER 19-2: I2C
X
STAT: I
2
C STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC
ACKSTAT TRSTAT — — — BCL GCSTAT ADD10
7:0
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D_A P S R_W RBF TBF
Legend: HS = Set by hardware HSC = Hardware set/cleare d
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared C = Clearable bit
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ACKSTAT: Acknow ledge S t atus bit (when operating as I
2
C master, applicable to maste r transmit op eration)
This bit is set or cleared by hardware at the end of a slave Acknowledge.
1 = NACK received from slave
0 = ACK received from slave
bit 14 TRSTAT: Transmit Status bit (when operating as I
2
C master, applicable to master transmit operation)
This bit i s set by hardw are at the beginnin g of a master t ransmiss ion, and is cleare d by hardw are at the end
of a slave Acknowledge.
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
bit 13-11 Unimplemented: Read as ‘0’
bit 10 BCL: Master Bus Collision Detect bit
This bit is set by hardware at the detection of a bus collision.
1 = A bus collision has been detected during a master operation
0 = No collision
bit 9 GCSTAT: General Call Status bit
This bit is s et by hardware whe n the addr ess match es the gener al call addr ess, and is cleared by hardw are
clear at a Stop detection.
1 = General call address was received
0 = General call address was not received
bit 8 ADD10: 10-bit Address Status bit
This bit is set by hardware upon a match of the 2nd byte of the matched 10-bit address, and is cleared by
hardware at a Stop detection.
1 = 10-bit address was matched
0 = 10-bit address was not matched
bit 7 IWCOL: Write Collision Detect bit
This bit is set by hardware at the occurrence of a w rite to I2CxTRN while busy (cleared by software).
1 = An attempt to write the I2CxTRN register failed because the I
2
C module is busy
0 = No collision
bit 6 I2COV: Receive Overflow Flag bit
This bit is set by hardware at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
1 = A byte was re ceived while the I2CxRCV register is still holding t he previous byte
0 = No overflow
PIC32MX5XX/6XX/7XX
DS60001156J-page 202 2009-2016 Microchip Technology Inc.
bit 5 D_A: Data/Address bit (when operating as I
2
C slave)
This bit is cleared by hardware upon a device address match, and is set by hardware by reception of the
slave b yte.
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
bit 4 P: Stop bit
This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected.
1 = Indicates that a Stop bit has been detect ed last
0 = Stop bit was not detected last
bit 3 S: Start bit
This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected.
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
bit 2 R_W: Read/Write Information bit (when operating as I
2
C slave)
This bit is set or cleared by hardware after reception of an I
2
C device address byte.
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
bit 1 RBF: Receive Buffer Full Status bit
This bit is set by hardware when the I2CxRCV register is written with a received byte, and is cleared by
hardware when software reads I2CxRCV.
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
bit 0 TBF: Transmit Buffer Full Status bit
This bit is se t by hardw are when so ftw are wri tes to the I2Cx TRN regi ster, and is clear ed by hardwa re upon
completion of data transmission.
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
REGISTER 19-2: I2C
X
STAT: I
2
C STATUS REGISTER (CONTINUED)
2009-2016 Microchip Technology Inc. DS60001156J- page 203
PIC32MX5XX/6XX/7XX
20.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSM ITTER
(UART)
The UART module is one of the serial I/O modules
available in the PIC32MX5XX/6XX/7XX family of
devices. The UART is a full-duplex, asynchronous
communication channel that communicates with
peripheral devices and personal computers through
proto cols, such as RS-232, R S-485, LIN 1 .2 and IrDA
®
.
The module also supports the hardware flow control
option, with UxCTS and UxR TS pi ns, and also in cludes
an IrDA encoder and decoder.
The following are primary features of the UART
module:
• Full-duplex, 8-bit or 9-bit data transmission
• Even, Odd or No Parity opt ions (for 8-bit data)
• One or two Stop bits
• Hardware auto-baud feature
• Hardware flow control option
• Fully inte gra ted Bau d Rate G ene rato r (BRG) with
16-bit prescaler
• Baud rates ranging from 76 bps to 20 Mbps at
80 MHz
• 8-level deep First-In-First-Out (FIFO) transmit
data buffer
• 8-level deep FIFO receive data buffer
• Parity, framing and buffer overrun error detection
• Support for interrupt-only on address detect
(ninth bit = 1)
• Separate transmit and receive interrupts
• Loopback mode for diagnostic support
• LIN 2.1 Protocol support
• IrDA encoder and decoder with 16x baud clock
output for external IrDA encoder/decoder support
Figure 20-1 il lustrat es a sim plified bl ock di agram of th e
UART module.
FIGURE 20-1: UART SIMPLIFIED BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 21. “Universal
Asynchronous Receiver Transmitter
(UART)” (DS60001107) in the “PIC32
Family Refe rence Man ual”, which is avail-
able from the Microchip web site
(www.microchip.com/PIC32).
Baud Rate Generator
UxRX
Hardware Flow Control
UARTx Receiver
UARTx Transmitter UxTX
UxCTS
UxRTS
BCLKx
IrDA
®
Note: Not all pins are ava ilable for all UART mod ules. Refer to the device-specific pin diagram for more informa tion
(see “Device Pin Tables”).
PIC32MX5XX/6XX/7XX
DS60001156J-page 204 2009-2016 Microchip Technology Inc.
Figure 20-2 and Figure 20-3 illustrate typical receive
and transmit timing for the UART module.
FIGU RE 20-2: UART R E CEP TI O N
FIGU RE 20-3: TRANSMIS SI O N (8- BI T OR 9- B IT DA TA)
Start
1
Stop Start 2 Stop 4 Start 5 St op 10 Start 11 Stop 13
Cleared by
Software
Read to
UxRXREG
UxRX
RIDLE
OERR
UxRXIF
URXISEL =
00
UxRXIF
URXISEL =
01
UxRXIF
URXISEL =
10
Char 1 Char 2-4 Char 5-10 Char 11-13
Cleared by
Software
Cleared by
Software
StartStart Bit 0 Bit 1 Stop
Write to
TSR
BCLK/16
(Shift Clock)
UxTX
UxTXIF
UxTXIF
UTXISEL = 00
Bit 1
UxTXREG
UTXISEL = 01
UxTXIF
UTXISEL = 10
8 into TxBUF
Pull from Buffer
2009-2016 Microchip Technology Inc. DS60001156J-page 205
PIC32MX5XX/6XX/7XX
20.1 Control Registers
TABLE 20-1: UART1 THROUGH UART6 REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6000 U1MODE
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
6010 U1STA
(1)
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
6020 U1TXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — TX8 Transmit Register 0000
6030 U1RXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — RX8 Receive Register 0000
6040 U1BRG
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 BRG<15:0> 0000
6200 U4MODE
(1)
31:16
15:0 — — — — — — — — — — — — — — — — 0000
ON — SIDL IREN ———— WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
6210 U4STA
(1)
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
6220 U4TXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — TX8 Transmit Register 0000
6230 U4RXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — RX8 Receive Register 0000
6240 U4BRG
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 BRG<15:0> 0000
6400 U3MODE
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
6410 U3STA
(1)
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
6420 U3TXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — TX8 Transmit Register 0000
6430 U3RXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — RX8 Receive Register 0000
6440 U3BRG
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 BRG<15:0> 0000
6600 U6MODE
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON — SIDL IREN ———— WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
6610 U6STA
(1)
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 206 2009-2016 Microchip Technology Inc.
6620 U6TXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — TX8 Transmit Register 0000
6630 U6RXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — RX8 Receive Register 0000
6640 U6BRG
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 BRG<15:0> 0000
6800 U2MODE
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
6810 U2STA
(1)
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
6820 U2TXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — TX8 Transmit Register 0000
6830 U2RXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — RX8 Receive Register 0000
6840 U2BRG
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 BRG<15:0> 0000
6A00 U5MODE
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON — SIDL IREN ———— WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
6A10 U5STA
(1)
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
6A20 U5TXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — TX8 Transmit Register 0000
6A30 U5RXREG 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — RX8 Receive Register 0000
6A40 U5BRG
(1)
31:16 — — — — — — — — — — — — — — — — 0000
15:0 BRG<15:0> 0000
TABLE 20-1: UART1 THROUGH UART6 REGISTER MAP (CONTINUED)
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
2009-2016 Microchip Technology Inc. DS60001156J- page 207
PIC32MX5XX/6XX/7XX
REGISTER 20-1: UxMODE: UARTx MODE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ON
(1)
—SIDLIRENRTSMD—UEN<1:0>
7:0
R/W-0 R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL
Legend: HC = Cle ared by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: UARTx Enable bit
(1)
1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN
control bits.
0 = UAR Tx is disabl ed. All UAR Tx pins are co ntrolled by co rresponding b its in the POR Tx, TRI Sx and LATx
registers; UARTx power consumption is minimal.
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation when device enters Idle mode
bit 12 IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 =UxRTS
pin is in Simplex mode
0 =UxRTS
pin is in Flow Control mode
bit 10 Unimplemented: Read as ‘0’
bit 9-8 UEN<1:0>: UARTx Enable bits
11 = UxTX, UxRX and UxBCLK pi ns are en abl ed and used; UxCTS pi n is con trol led by correspond ing bit s
in the POR Tx regi ster
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the POR Tx regi ster
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
co rres ponding bi ts in the PORTx r egister
bit 7 WAKE: Enable Wake-up on Start bit De tect During Sleep Mode bit
1 = Wake-up is enabled
0 = Wake-up is disabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled
Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
PIC32MX5XX/6XX/7XX
DS60001156J-page 208 2009-2016 Microchip Technology Inc.
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55);
cleared by hardware upon completion
0 = Baud rate measurement disabled or completed
bit 4 RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = High-Speed mode – 4x baud clock enabled
0 = Standard Speed mode – 16x baud clock enabled
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Se lection bi t
1 = 2 Stop bits
0 = 1 Stop bit
REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
2009-2016 Microchip Technology Inc. DS60001156J- page 209
PIC32MX5XX/6XX/7XX
REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —ADM_EN
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADDR<7:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0 R-0 R-1
UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT
7:0
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/W-0, HS R-0
URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA
Legend: HS = Set by hardware HC = Cleared by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-25 Unimplemented: Read as ‘0’
bit 24 ADM_EN: Automatic Addre ss Detect Mode Enable bit
1 = Automatic Addre ss Dete ct mode is ena ble d
0 = Automatic Addre ss Dete ct mode is dis ab led
bit 23-16 ADDR<7:0>: Automatic Address Mask bits
When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic address
detection.
bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits
11 = Reserved, do not use
10 = Interrupt is generated and asserted while the transmit buffer is empty
01 = Interrupt is generated and asserted when all characters have been transmitted
00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13 UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is ‘0’):
1 = UxTX Idle st ate is ‘0’
0 = UxTX Idle state is ‘1’
If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is ‘1’):
1 = IrDA encoded UxTX Idle st ate is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12 URXEN: Receiver Enable bit
1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
0 = UARTx rec eiver is di sabled. UxRX pin is ignored by the UARTx module. UxRX pin is controll ed by port.
bit 11 UTXBRK: Transmit Break bit
1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by
hardware upon completion.
0 = Break transmission is disabled or completed
bit 10 UTXEN: Transmit Enable bit
1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is
controlled by port.
bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
PIC32MX5XX/6XX/7XX
DS60001156J-page 210 2009-2016 Microchip Technology Inc.
bit 8 TRMT: Transmit Shift Register is Empty bit (read-only)
1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
bit 7-6 URXISEL<1:0>: Receive I nterrupt Mode Selection bit
11 = Reserved
10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (has 6 or more data characters)
01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (has 4 or more data characters)
00 = Interrupt flag bit is asserted while receive buffer is not empty (has at least 1 data character)
bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect.
0 = Address Detect mode is disab led
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is idle
0 = Data is being received
bit 3 PERR: Parity Error Status bit (read -on ly)
1 = Parity error has been detected for t he current character
0 = Parity error has not bee n dete cte d
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit.
This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit
resets the receiver buffer and RSR to an empty state.
1 = Receive buffer h as ov erflowed
0 = Receive buffer h as not overflowed
bit 0 URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
2009-2016 Microchip Technology Inc. DS60001156J- page 211
PIC32MX5XX/6XX/7XX
21.0 PARALLEL MASTER PORT
(PMP)
The PMP is a parallel 8-bit/16-bit input/output module
specifically designed to communicate with a wide
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and
microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP module is
highly configurable. Figure 21-1 shows the PMP
module pinout and its connections to external devices.
The following are key features of the PMP module:
• 8-bit and 16-bit interface
• Up to 16 programma ble address lines
• Up to two Chip Select lines
• Programmable strobe options
- Individual read and write strobes, or
- Read/Write strobe with enable strobe
• Address auto-increment/auto-decrement
• Programmable address/data multiplexing
• Programmable polarity on control signals
• Parallel Slave Port support
- Legacy addressable
- Address support
- 4-byte deep auto-incrementing buffer
• Programmable wait states
• Operates during Sleep and Idle modes
• Fast bit manipulation us ing CLR, SET and INV
registers
FIGURE 21-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, re fer to Section 13. “Paralle l Mas-
ter Port (PMP)” (DS60001128) in the
“PI C32 Fami ly Re ferenc e Manua l” , which
is available from the Microchip web site
(www.microchip.com/PIC32).
Note: On 64-pin devices, the PMD<15:8> data
pins are not available.
PMA<0>
PMA<14>
PMA<15>
PMRD
PMWR
PMENB
PMRD/PMWR
PMCS1
PMA<1>
PMA<13:2>
PMALL
PMALH
PMCS2
Flash
Address Bus
Data Bus
Control Lines
PIC32MX5XX/6XX/7XX
LCD FIFO
Microcontroller
16/8-bit Data (with or without multiplexed addressing)
Up to 16-bit Address
Parallel
Buffer
PMD<15:8>
(1)
PMD<7:0>
Master Port
Note 1: On 64-pin devices, data pins, PMD<15:8>, are not available in 16-bit Master modes.
EEPROM
SRAM
PIC32MX5XX/6XX/7XX
DS60001156J-page 212 2009-2016 Microchip Technology Inc.
21.1 Control Registers
TABLE 21-1: PARALLEL MASTER PORT REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
7000 PMCON 31:16 ————————————————0000
15:0 ON — SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN CSF<1:0> ALP CS2P CS1P — WRSP RDSP 0000
7010 PMMODE 31:16 ————————————————0000
15:0 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000
7020 PMADDR 31:16 ————————————————0000
15:0
CS2EN/A15CS1EN/A14
ADDR<13:0> 0000
7030 PMDOUT 31:16 DATAOUT<31:0> 0000
15:0 0000
7040 PMDIN 31:16 DATAIN<31:0> 0000
15:0 0000
7050 PMAEN 31:16 ————————————————0000
15:0 PTEN<15:0> 0000
7060 PMSTAT 31:16 ————————————————0000
15:0 IBF IBOV —— IB3F IB2F IB1F IB0F OBE OBUF —— OB3E OB2E OB1E OB0E 008F
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2009-2016 Microchip Technology Inc. DS60001156J- page 213
PIC32MX5XX/6XX/7XX
REGISTER 21-1: PMCON: PARALLEL PORT CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ON
(1)
—SIDL
ADRMUX<1:0>
PMPTTL PTWREN PTRDEN
7:0
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
CSF<1:0>
(2)
ALP
(2)
—CS1P
(2)
— WRSP RDSP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Parallel Master Port Enable bit
(1)
1 = PMP is enabled
0 = PMP is disabled, no off-chip access performed
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Disco ntinue module operatio n when device enters Idle mode
0 = Continue module operation when device enters Idle mode
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = All 16 bits of address are multiplexed on PMD<15:0> pins
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<15:8>
00 = Address and data appear on separate pins
bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer
bit 9 PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 8 PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR por t is enabled
0 = PMRD/PMWR port is disabled
bit 7-6 CSF<1:0>: Chip Select Function bits
(2)
11 = Reserved
10 = PMC S2 and PMCS1 function as Chi p Select
01 = PMCS2 functions as Chip Select, PMCS1 functions as address bit 14
00 = PMCS2 an d PMCS1 function as address bits 15 and 14
(2)
bit 5 ALP: Address Latch Polarity bit
(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4 Unimplemented: Read as ‘0’
Note 1: When usin g the 1:1 PBC LK divisor, the user’s s of twa re should not read/write the perip hera l’s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
PIC32MX5XX/6XX/7XX
DS60001156J-page 214 2009-2016 Microchip Technology Inc.
bit 3 CS1P: Chip Select 0 Polarity bit
(2)
1 = Active-high (PMCS1)
0 =Active-low (PMCS1
)
bit 2 Unimplemented: Read as ‘0’
bit 1 WRSP: Write Strobe Polarity bit
For Slave Mo des and Master mode 2 (PMMODE<9:8> = 00,01,10):
1= Write strobe active-high (PMWR)
0= Write strobe active-low (PMWR)
For Master mode 1 (PMMODE<9 :8> = 11):
1= Enable strobe active-high (PMENB)
0= Enable strobe active-low (PMENB)
bit 0 RDSP: Read Strobe Polarity bit
For Slave mo des and Master mode 2 (PMMODE<9:8> = 00,01,10):
1= Read Strobe active-hi gh (PMRD )
0= Read Strobe active-low (PMRD)
For Master mode 1 (PMMODE<9 :8> = 11):
1= Read/write strobe active-high (PMRD/PMWR)
0= Read/write strobe active-low (PMRD/PMWR)
REGISTER 21-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
Note 1: When usin g the 1:1 PBC LK divisor, the user’s s of tw a re sho ul d not rea d/wri te the perip heral’s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.
2009-2016 Microchip Technology Inc. DS60001156J- page 215
PIC32MX5XX/6XX/7XX
REGISTER 21-2: PMMODE: PARALLEL PORT MODE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
BUSY IRQM<1:0> INCM<1:0> — MODE<1:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAITB<1:0>
(1)
WAITM<3:0>
(1)
WAITE<1:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unim plemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 BUSY: Busy bit (only Master mode)
1 = Port is busy
0 = Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
11 = Reserved
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> =11 (only Addressable Slave mode)
01 = Interrupt generated at the end of the read/write cycle
00 = Interrupt is not generated
bit 12-11 INCM<1:0>: Increment Mode bits
11 = Slave mode read and write buffers auto-increment (only PMMODE<1:0> = 00)
10 = D ecrement ADDR<10:2> and ADDR<14> by 1 every read/write cycle
(2)
01 = I ncrement ADDR<10:2> and ADDR<14> by 1 every read/write cycle
(2)
00 = No increment or decrement of address
bit 10 Unimplemented: Read as ‘0’
bit 9-8 MODE<1:0>: Pa ral lel Port Mode Sele ct bits
11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PM A<x:0>, and PMD<7:0>)
10 = Master mode 2 (PMCS1, PMRD, PMWR, PMA<x:0>, and PMD<7:0>)
01 = Enhanced Slave mo de, control signals (PMRD, PMWR, PMCS1, PMD<7:0>, and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD<7:0>)
bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits
(1)
11 = Data wait of 4 T
PB
; multiplexed address phase of 4 T
PB
10 = Data wait of 3 T
PB
; multiplexed address phase of 3 T
PB
01 = Data wait of 2 T
PB
; multiplexed address phase of 2 T
PB
00 = Data wait of 1 T
PB
; multiplexed address phase of 1 T
PB
(default)
Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 T
PBCLK
cycle f or a
write operation; WAITB = 1 T
PBCLK
cycle, WAITE = 0 T
PBCLK
cycles for a read operation.
2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.
PIC32MX5XX/6XX/7XX
DS60001156J-page 216 2009-2016 Microchip Technology Inc.
bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits
(1)
1111 = Wait of 16 T
PB
•
•
•
0001 = Wait of 2 T
PB
0000 = Wait of 1 T
PB
(default)
bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits
(1)
11 = Wait of 4 T
PB
10 = Wait of 3 T
PB
01 = Wait of 2 T
PB
00 = Wait of 1 T
PB
(default)
For Read operations:
11 = Wait of 3 T
PB
10 = Wait of 2 T
PB
01 = Wait of 1 T
PB
00 = Wait of 0 T
PB
(default)
REGISTER 21-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 T
PBCLK
cycle f or a
write operation; WAITB = 1 T
PBCLK
cycle, WAITE = 0 T
PBCLK
cycles for a read operation.
2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1.
2009-2016 Microchip Technology Inc. DS60001156J- page 217
PIC32MX5XX/6XX/7XX
REGISTER 21-3: PMADDR: PARALLEL PORT ADDRESS REGIST ER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CS2
(1)
CS1
(3)
ADDR<13:8>
ADDR15
(2)
ADDR14
(4)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 CS2: Chip Select 2 bit
(1)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive
bit 15 ADDR<15>: Destination Address bit 15
(2)
bit 14 CS1: Chip Select 1 bit
(3)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
bit 14 ADDR<14>: Destination Address bit 14
(4)
bit 13-0 ADDR<13:0>: Address bits
Note 1: When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01.
2: When the CSF<1:0> bits (PMCON<7:6>) = 00.
3: When the CSF<1:0> bits (PMCON<7:6>) = 10.
4: When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01.
PIC32MX5XX/6XX/7XX
DS60001156J-page 218 2009-2016 Microchip Technology Inc.
REGISTER 21-4: PMAEN: PARALLEL PORT PIN ENABLE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
—PTEN14——— PTEN<10:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTEN<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 15-14 PTEN14: PMCS1 Strobe Enable bits
1 = PMA14 functions as eit her PMA14 or PMCS1
(1)
0 = PMA14 functions as port I/O
bit 13-11 Unimplemented: R ead as ‘0’
bit 10-2 PTEN<10:2>: PMP Address Port Enable bits
1 = PMA<10:2> function as PMP address lines
0 = PMA<10:2> function as port I/O
bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL
(2)
0 = PMA1 and PMA0 pads function as port I/O
Note 1: The use of this pin as PMA14 or CS1 is selected by the CSF<1:0> bits in the PMCON register.
2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mo de
selected by bits ADRMUX<1:0> in the PMCON register.
2009-2016 Microchip Technology Inc. DS60001156J- page 219
PIC32MX5XX/6XX/7XX
REGISTER 21-5: PMSTAT: PARALLEL PORT STATUS REGISTER (ONLY SLAVE MODES)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R-0 R/W-0, HS, SC U-0 U-0 R-0 R-0 R-0 R-0
IBF IBOV — — IB3F IB2F IB1F IB0F
7:0
R-1 R/W-0, HS, SC U-0 U-0 R-1 R-1 R-1 R-1
OBE OBUF —— OB3E OB2E OB1E OB0E
Legend: HS = Set by Hardware SC = Cleared by software
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 IBF: Input Buffer Full Status bit
1 = All writable input buf fer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 14 IBOV: Input Buffer Ov erflow Status bit
1 = A write attempt to a full input byte buffer occurred (must be cleared in software)
0 = An overflow has not occurred
bit 13-12 Unimplemented: Read as ‘0’
bit 11- 8 IBxF: Input Buffer ‘x’ Status Full bits
1 = Input buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input buffer does not contain any unread data
bit 7 OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6 OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte buffer (must be cleared in software)
0 = An underflow has not occurred
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 OBxE: Out put Buffer ‘ x ’ Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted
PIC32MX5XX/6XX/7XX
DS60001156J-page 220 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 221
PIC32MX5XX/6XX/7XX
22.0 REAL-TIME CLOCK AND
CALENDAR (RTCC)
The PIC32 RTCC module is intended for applications
in which accurate time must be maintained for
extended periods of time with minimal or no CPU
intervention. Low-power optimization provides
extended battery lifetime while keeping track of time.
A simplified block diagram of the RTCC module is
illustrated in Figure 22-1.
Key features of the RTCC module include:
• Time: hours, minutes and seconds
• 24-hour format (military time)
• Visibility of one-half second period
• Provides calendar: Weekday, date, month and year
• Alarm intervals are configurable for half of a
second, one second, 10 seconds, one minute, 10
minutes , one hour, one da y, one week, on e month
and one year
• Alarm repeat with dec rem en tin g coun ter
• Alarm with indefinite repeat: Chime
• Year rang e: 2000 to 2099
• Leap year correc tion
• BCD format for smaller firmware overhead
• Optimized for long-term battery operation
• Fractional second synchronization
• User cali bration of the c lock cryst al frequency w ith
auto-adjust
• Calibration range: 0.66 seconds error per month
• Calibrates up to 260 ppm of crystal error
• Requirements: External 32.768 kHz clock crystal
• Alarm pulse or seconds clock output on RTCC pin
FIGURE 22-1: RTCC BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 29. “Real-Time
Clock and Calendar (RTCC)”
(DS60001125) in the “PIC32 Family Ref-
erence Manual”, which is available from
the Microchip web site (www.micro-
chip.com/PIC32).
Seconds Pulse
RTCC Prescalers
RTCC Timer
Comparator
Compare Regist ers
Repeat Counter
YEAR, MTH, DAY
WKDAY
HR, MIN, SEC
MTH, DAY
WKDAY
HR, MIN, SEC
with Masks
RTCC Interrupt Logic
Alarm
Event
32.768 kHz Inpu t
from Secondary
0.5s
Alarm Pulse
RTCC Interrupt
RTCVAL
ALRMVAL
RTCC Pin
RTCOE
Oscillator ( S
OSC
)
PIC32MX5XX/6XX/7XX
DS60001156J-page 222 2009-2016 Microchip Technology Inc.
22.1 Control Registers
TABLE 22-1: RTCC REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0200 RTCCON 31:16 — — — — — — CAL<9:0> 0000
15:0 ON — SIDL — — — — — RTSECSEL RTCCLKON —— RTCWREN RTCSYNC HALFSEC RTCOE 0000
0210 RTCALRM 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ALRMEN CHIME PIV ALRMSYNC AMASK<3:0> ARPT<7:0> 0000
0220 RTCTIME 31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx
15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00
0230 RTCDATE 31:16 YEAR10<3:0> YEAR01<3:0> MONTH10<3:0> MONTH01<3:0> xxxx
15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx00
0240 ALRMTIME 31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx
15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00
0250 ALRMDATE 31:16 — — — — — — — — MONTH10<3:0> MONTH01<3:0> 00xx
15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx0x
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2009-2016 Microchip Technology Inc. DS60001156J- page 223
PIC32MX5XX/6XX/7XX
REGISTER 22-1: RTCCON: RTC CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — —CAL<9:8>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CAL<7:0>
15:8
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
ON
(1,2)
—SIDL— — — — —
7:0
R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0
RTSECSEL
(3)
RTCCLKON ——RTCWREN
(4)
RTCSYNC HALFSEC
(5)
RTCOE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value
1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
•
•
•
1000000000 = Maximum negative adjustment, subtracts 512 clock pulses every one minute
0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute
•
•
•
0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute
0000000000 = No adjustment
bit 15 ON: RTCC On bit
(1,2)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode
0 = Continue normal operation in Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7 RTSECSEL: RTCC Seconds C lock Output Select bit
(3)
1 = RTCC Seconds Clock is selected for the RTCC pin
0 = RTCC Alarm Pulse is selected for the RTCC pin
bit 6 RTCCLKON: RTCC Clock Enable Status bit
1 = RTCC Clock is actively running
0 = RTCC Clock is not running
bit 5-4 Unimplemented: Read as ‘0’
Note 1: The ON bit is only writable when RTCWREN = 1.
2: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
3: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
4: The RTCWREN bit can only be set when the write sequence is enabled.
5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
Note: This register is on ly reset on a Power-on Reset (POR).
PIC32MX5XX/6XX/7XX
DS60001156J-page 224 2009-2016 Microchip Technology Inc.
bit 3 RTCWREN: RTC Value Regist ers Wr i te Enab le bit
(4)
1 = RTC Value registers can be written to by the user
0 = RTC Value registers are locked out from being written to by the user
bit 2 RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data
read. If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = RTC Value registers can be read wi thout concern about a rollover ripple
bit 1 HALFSEC: Half-Second Status bit
(5)
1 = Second half per iod of a se cond
0 = First half period of a second
bit 0 RTCOE: RTCC Output Enab le bit
1 = RTCC clock output is enabled (clock presented onto an I/O)
0 = RTCC clock output is disabled
REGISTER 22-1: RTCCON: RTC CONTROL REGISTER (CONTINUED)
Note 1: The ON bit is only writable when RTCWREN = 1.
2: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
3: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
4: The RTCWREN bit can only be set when the write sequence is enabled.
5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
Note: This register is on ly reset on a Power-on Reset (POR).
2009-2016 Microchip Technology Inc. DS60001156J- page 225
PIC32MX5XX/6XX/7XX
REGISTER 22-2: RTCALRM: RTC ALARM CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
ALRMEN
(1,2)
CHIME
(2)
PIV
(2)
ALRMSYNC
(3)
AMASK<3:0>
(2)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ARPT<7:0>
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ALRMEN: Alarm Enable bit
(1,2)
1 = Alarm is enabled
0 = Alarm is disabled
bit 14 CHIME: Chime Enable bit
(2)
1 = Chime is enabled – ARPT<7:0> is allowed to rollover from 0x00 to 0xFF
0 = Chime is disabled – ARPT<7:0> stops once it reaches 0x00
bit 13 PIV: Alar m Pulse Initia l Value bit
(3)
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Puls e.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
bit 12 ALRMSYNC: Alarm Sync bit
(3)
1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read.
The ARPT mu st be read repea tedly until th e same value is read twic e. This must b e done since mu ltiple
bits may be changing, which are then synchronized to the PB clock domain.
0 = ARPT<7:0> and ALRM EN can be read w ithout conc erns o f rollov er beca use the presca ler is > 32 RT C
clocks away from a half-second rollover
bit 11- 8 AMASK<3:0>: Alarm Mask Configuration bits
(2)
1111 = Reserved
•
•
•
1010 = Reserved
1001 = O nce a year (except when configured for February 29, once every four years)
1000 = Once a month
0111 = Once a week
0110 = Once a day
0101 = Every hour
0100 = Every 10 minutes
0011 = Every minute
0010 = Every 10 seconds
0001 = Every second
0000 = Every half-second
Note 1: Hardwa re clears the A LRME N bit anytime the alarm event occurs, when ARPT<7: 0> = 00 and
CHIME = 0.
2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
3: This assumes a CPU read will execute in less than 32 PBCLKs.
Note: This register is on ly reset on a Power-on Reset (POR).
PIC32MX5XX/6XX/7XX
DS60001156J-page 226 2009-2016 Microchip Technology Inc.
bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits
(2)
11111111 = Alarm will trigger 256 times
•
•
•
00000000 = Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
REGISTER 22-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED)
Note 1: Hardware clears the A LRME N bit anytime the al arm event occurs, when ARPT< 7:0> = 00 and
CHIME = 0.
2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
3: This assumes a CPU read will execute in less than 32 PBCLKs.
Note: This register is on ly reset on a Power-on Reset (POR).
2009-2016 Microchip Technology Inc. DS60001156J- page 227
PIC32MX5XX/6XX/7XX
REGISTER 22-3: RTCTIME: RTC TIME VALUE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
HR10<3:0> HR01<3:0>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
MIN10<3:0> MIN01<3:0>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SEC10<3:0> SEC01<3:0>
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 HR10<3:0>: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10<3:0>: Binary-Coded De cimal Value of Mi nutes bits, 10 di gits; contains a value from 0 to 5
bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1 digit; contai ns a value from 0 to 9
bit 15-12 SEC10<3:0>: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5
bit 11- 8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0 Unimplemented: Read as ‘0’
Note: This register is only writable when RTCWREN = 1 (RTCCON<3>).
PIC32MX5XX/6XX/7XX
DS60001156J-page 228 2009-2016 Microchip Technology Inc.
REGISTER 22-4: RTCDATE: RTC DATE VALUE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
YEAR10<3:0> YEAR01<3:0>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
MONTH10<3:0> MONTH01<3:0>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
DAY10<3:0> DAY01<3:0>
7:0
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
— — — — WDAY01<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10 digits
bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1 digit
bit 23-20 MONTH10<3:0>: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01<3:0>: Binary-Coded D ecimal Value of Months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10<3:0>: Binary-Coded Decimal Value of D ays bits, 10 digits; contains a value from 0 to 3
bit 11- 8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9
bit 7-4 Unimplemented: Read as ‘ 0’
bit 3-0 WDAY01<3:0>: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6
Note: This register is only writable when RTCWREN = 1 (RTCCON<3>).
2009-2016 Microchip Technology Inc. DS60001156J- page 229
PIC32MX5XX/6XX/7XX
REGISTER 22-5: ALRMTIME: ALARM TIME VALUE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
HR10<3:0> HR01<3:0>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
MIN10<3:0> MIN01<3:0>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SEC10<3:0> SEC01<3:0>
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 HR10<3:0>: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10<3:0>: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10<3:0>: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5
bit 11- 8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0 Unimplemented: Read as ‘0’
PIC32MX5XX/6XX/7XX
DS60001156J-page 230 2009-2016 Microchip Technology Inc.
REGISTER 22-6: ALRMDATE: ALARM DATE VALUE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
MONTH10<3:0> MONTH01<3:0>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
DAY10<1:0> DAY01<3:0>
7:0
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
— — — — WDAY01<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-20 MONTH10<3:0>: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10<3:0>: Binary Coded Decimal value of days bits, 10 digits; contains a value f rom 0 to 3
bit 11- 8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9
bit 7-4 Unimplemented: Read as ‘ 0’
bit 3-0 WDAY01<3:0>: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6
2009-2016 Microchip Technology Inc. DS60001156J- page 231
PIC32MX5XX/6XX/7XX
23.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (ADC)
The PIC32MX5XX/6XX/7XX 10-bit Analog-to-Digital
Converter (ADC) includes the following features:
• Successive Approximation Register (SAR)
conversion
• Up to 1 Msps conversion speed
• Up to 16 anal og input pins
• External voltage reference input pins
• One unipolar, differential Sample and Hold (S&H)
circuit
• Automatic Channel Scan mode
• Selectable conversion trigger source
• 16-word conversion result buffer
• Select ab le buffer fill modes
• Eight conversion result format opt ion s
• Operation during Sleep and Idle modes
A block diagram of the 10-bit ADC is illustrated in
Figure 23-1. The 10-bi t ADC has up to 16 an alo g inp ut
pins, designated AN0-AN15. In addition, there are two
analog input pins for external voltage reference
connections. These voltage reference inputs may be
shared with other analog input pins and may be
common to other analog module references.
The analog inputs are connected through two multi-
plexers to o ne S&H . The ana log inp ut m ul tip lex ers ca n
be switched between two sets of analog inputs
betwee n conversi ons. Unip olar dif ferentia l conversi ons
are p ossible on all c hannels, other tha n the pin used a s
the reference, using a reference input pin (see
Figure 23-1).
The Analog Input Scan mode sequentially converts
user-specified channels. A control register specifies
which analog input channels will be included in the
scanni ng sequence.
The 10-bi t ADC is co nnected t o a 16-wor d result bu ffer.
Each 10-bit result is converted to one of eight 32-bit
output formats when it is read from the result buffer.
FIGURE 23-1: ADC1 MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 17. “10-bit Ana-
log-to-Digital Converter (ADC)”
(DS60001104) in the “PIC32 Family Ref-
erence Manual”, which is available from
the Microchip web site
(www.microchip.com/PIC32).
SAR ADC
S&H
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUFF
ADC1BUFE
AN0
AN15
AN1
V
REFL
CH0SB<4:0>
CH0NA CH0NB
+
-
CH0SA<4:0>
Channel
Scan
CSCNA
Alternate
V
REF
+
(1)
AV
DD
AV
SS
V
REF
-
(1)
Note 1:
V
REF
+ and V
REF
- inputs can be multiplexed with other analog inputs.
Input Selection
V
REFH
V
REFL
VCFG<2:0>
PIC32MX5XX/6XX/7XX
DS60001156J-page 232 2009-2016 Microchip Technology Inc.
FIGURE 23-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
1
0
T
PB
ADC Conversion
Clock M ultip lier
2, 4,..., 512
ADRC
T
AD
8
ADCS<7:0>
FRC
2
2009-2016 Microchip Technology Inc. DS60001156J-page 233
PIC32MX5XX/6XX/7XX
23.1 Control Registers
TABLE 23-1: ADC REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
9000 AD1CON1
(1)
31:16 ————————————————0000
15:0 ON — SIDL —— FORM<2:0> SSRC<2:0> CLRASAM — ASAM SAMP DONE 0000
9010 AD1CON2
(1)
31:16 ————————————————0000
15:0 VCFG2 VCFG1 VCFG0 OFFCAL — CSCNA ——BUFS— SMPI<3:0> BUFM ALTS 0000
9020 AD1CON3
(1)
31:16 ————————————————0000
15:0 ADRC —— SAMC<4:0> ADCS<7:0> 0000
9040 AD1CHS
(1)
31:16 CH0NB ——— CH0SB<3:0> CH0NA — — — CH0SA<3:0> 0000
15:0 ————————————————0000
9060 AD1PCFG
(1)
31:16 ————————————————0000
15:0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
9050 AD1CSSL
(1)
31:16 ————————————————0000
15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000
9070 ADC1BUF0 31:16 ADC Result Word 0 (ADC1BUF0<31:0>) 0000
15:0 0000
9080 ADC1BUF1 31:16 ADC Result Word 1 (ADC1BUF1<31:0>) 0000
15:0 0000
9090 ADC1BUF2 31:16 ADC Result Word 2 (ADC1BUF2<31:0>) 0000
15:0 0000
90A0 ADC1BUF3 31:16 ADC Result Word 3 (ADC1BUF3<31:0>) 0000
15:0 0000
90B0 ADC1BUF4 31:16 ADC Result Word 4 (ADC1BUF4<31:0>) 0000
15:0 0000
90C0 ADC1BUF5 31:16 ADC Result Word 5 (ADC1BUF5<31:0>) 0000
15:0 0000
90D0 ADC1BUF6 31:16 ADC Result Word 6 (ADC1BUF6<31:0>) 0000
15:0 0000
90E0 ADC1BUF7 31:16 ADC Result Word 7 (ADC1BUF7<31:0>) 0000
15:0 0000
90F0 ADC1BUF8 31:16 ADC Result Word 8 (ADC1BUF8<31:0>) 0000
15:0 0000
9100 ADC1BUF9 31:16 ADC Result Word 9 (ADC1BUF9<31:0>) 0000
15:0 0000
9110 ADC1BUFA 31:16 ADC Result Word A (ADC1BUFA<31:0>) 0000
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 234 2009-2016 Microchip Technology Inc.
9120 ADC1BUFB 31:16 ADC Result Word B (ADC1BUFB<31:0>) 0000
15:0 0000
9130 ADC1BUFC 31:16 ADC Result Word C (ADC1BUFC<31:0>) 0000
15:0 0000
9140 ADC1BUFD 31:16 ADC Result Word D (ADC1BUFD<31:0>) 0000
15:0 0000
9150 ADC1BUFE 31:16 ADC Result Word E (ADC1BUFE<31:0>) 0000
15:0 0000
9160 ADC1BUFF 31:16 ADC Result Word F (ADC1BUFF<31:0>) 0000
15:0 0000
TABLE 23-1: ADC REGISTER MAP (CONTINUED)
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
2009-2016 Microchip Technology Inc. DS60001156J- page 235
PIC32MX5XX/6XX/7XX
REGISTER 23-1: AD1CON1: ADC CONTROL REGISTER 1
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
ON
(1)
—SIDL——FORM<2:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC R /C-0, HSC
SSRC<2:0> CLRASAM — ASAM SAMP
(2)
DONE
(3)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: ADC Operating Mode bit
(1)
1 = ADC module is operating
0 = ADC module is not operating
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Disco ntinue module operation when dev ice enters Idle mode
0 = Continue module operation in Idle mode
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8 FORM<2:0>: Data O u tput For mat bits
111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000)
110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000)
101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd)
100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000)
010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000)
001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd)
000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits
111 = Internal counter ends sampling and starts conversion (auto convert)
110 = Reserved
101 = Reserved
100 = Reserved
011 = CTMU ends sampling and starts conversion
010 = Timer 3 period match ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing the SAMP bit ends sampling and starts conversion
Note 1: When usin g the 1:1 PBCLK di vi sor, the user’s sof tw are s hou ld no t read /w rite the pe riph era l’s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC<2:0> = 000, software can write a ‘0’ to end sampling and start conversion. If
SSRC<2:0>
‘000’, this bit is automatically cleared by hardware to end sampling and start conversion.
3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
PIC32MX5XX/6XX/7XX
DS60001156J-page 236 2009-2016 Microchip Technology Inc.
bit 4 CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated)
1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the
ADC interrupt is generated.
0 = Normal operation, buffer contents will be overwritten by the next conversion sequence
bit 3 Unimplemented: Read as ‘0’
bit 2 ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set
0 = Sampling begins when SAMP bit is set
bit 1 SAMP: ADC Sample Enable bit
(2)
1 = The ADC S&H circuit is sampling
0 = The ADC S&H circuit is holding
When ASAM = 0, writing ‘1’ to this bit starts sampling.
When SSRC<2:0> = 000, writing ‘0’ to this bit will end sampling and start conversion.
bit 0 DONE: Analog-to-Digital Conversion Status bit
(3)
Clearing this bit will not af fec t any ope rati on in prog res s.
1 = Analog-to-digital conversion is done
0 = Analog-to-digital conversion is not done or has not started
REGISTER 23-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED)
Note 1: When usin g the 1:1 PBCLK di vi sor, the user’s sof tw are s hou ld no t read /w rite the pe riph era l’s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC<2:0> = 000, software can write a ‘0’ to end sampling and start conversion. If
SSRC<2:0>
‘000’, this bit is automatically cleared by hardware to end sampling and start conversion.
3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.
2009-2016 Microchip Technology Inc. DS60001156J- page 237
PIC32MX5XX/6XX/7XX
REGISTER 23-2: AD1CON2: ADC CONTROL REGISTER 2
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0
VCFG<2:0> OFFCAL — CSCNA — —
7:0
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS — SMPI<3:0> BUFM ALTS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
Bit Value V
REFH
V
REFL
1xx AV
DD
AVss
011 External V
REF
+ pin External V
REF
- pin
010 AV
DD
External V
REF
- pin
001 External V
REF
+ pin AV
SS
000 AV
DD
AVss
bit 12 OFFCAL: Input Offset Calibration Mode Select bit
1 = Enable Offset Calibration mode
Positive and negative inputs of the S&H circui t are connected to V
REFL
.
0 = Disable Offset Calibration mode
The inputs to the S&H circuit are controlled by AD1CHS or AD1CSSL.
bit 11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Input Scan Select bit
1 = Scan inputs
0 = Do not scan inputs
bit 9-8 Unimplemented: Read as ‘0’
bit 7 BUFS: Buffer Fill Status bit
Only valid when BUFM = 1.
1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
0 = ADC is currently filling buffer 0x0-0x7, us er should access data in 0x8-0xF
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16
th
sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15
th
sample/convert sequence
•
•
•
0001 = Interrupts at the completion of conversion for each 2
nd
sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: ADC Result Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8
0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses Sample A inpu t mu lti ple xe r sett ing s fo r first sam pl e, an d then al terna te s bet ween Sample B and
Sample A input multiplexer settings for all subsequent samples
0 = Always use Sample A input multiplexer set tings
PIC32MX5XX/6XX/7XX
DS60001156J-page 238 2009-2016 Microchip Technology Inc.
REGISTER 23-3: AD1CON3: ADC CONTROL REGISTER 3
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC —— SAMC<4:0>
(1)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W R/W-0
ADCS<7:0>
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ADRC: ADC Conversion Clock Source bit
1 = Clock derived from FRC
0 = Clock derived from Peripheral Bus Clock (PBCLK)
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits
(1)
11111 =31 T
AD
•
•
•
00001 =1 T
AD
00000 =0 T
AD
(Not allowe d)
bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits
(2)
11111111 =T
PB
• 2 • (ADC S<7: 0> + 1) = 512 • T
PB
= T
AD
•
•
•
00000001 =T
PB
• 2 • (ADC S<7: 0> + 1) = 4 • T
PB
= T
AD
00000000 =T
PB
• 2 • (ADC S<7: 0> + 1) = 2 • T
PB
= T
AD
Note 1: This bit is only used if the SSRC<2:0> bits (AD1CON1<7:5>) = 111.
2: This bit is not used if the ADRC bit (AD1CON3<15>) = 1.
2009-2016 Microchip Technology Inc. DS60001156J- page 239
PIC32MX5XX/6XX/7XX
REGISTER 23-4: AD1CHS: ADC INPUT SELECT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB — — — CH0SB<3:0>
23:16
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NA — — — CH0SA<3:0>
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 CH0NB: Negative Input Select bit for Sample B
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
REFL
bit 30-28 Unimplemented: Read as ‘0’
bit 27-24 CH0SB<3:0>: Positive Input Select bits for Sample B
1111 = Channel 0 positive input is AN15
•
•
•
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 23 CH0NA: Negative Input Select bit for Sample A Multiplexer Setting
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
REFL
bit 22-20 Unimplemented: Read as ‘0’
bit 19-16 CH0SA<3:0>: Positive Input Select bits for Sample A Multiplexer Setting
1111 = Channel 0 positive input is AN15
•
•
•
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 15-0 Unimplemented: Read as ‘0’
PIC32MX5XX/6XX/7XX
DS60001156J-page 240 2009-2016 Microchip Technology Inc.
REGISTER 23-5: AD1CSSL: ADC INPUT SCAN SELECT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 CSSL<15:0>: ADC Input Pin Scan Selec tion bits
(1)
1 = Select ANx for input scan
0 = Skip ANx for input scan
Note 1: CSSL = ANx, where ‘x ’ = 0-15.
2009-2016 Microchip Technology Inc. DS60001156J- page 241
PIC32MX5XX/6XX/7XX
24.0 CONTROLLER AREA
NETWORK (CAN)
The Controller Area Network (CAN) module supports
the following key features:
• Standards Complianc e:
- Full CAN 2.0B compliance
- Programmable bit rate up to 1 Mbps
• Messa ge Re ce pti on and Transmis sion:
- 32 message FIFOs
- Each FIFO can have up to 32 messages for a
total of 1024 messages
- FIFO can be a transmit message FIFO or a
receive message FIFO
- User-defined priority levels for message
FIFOs used for transmission
- 32 acceptance filters for message filtering
- Four acceptance filter mask registers for
message filtering
- Automatic response to remote transmit request
- DeviceNet™ addressing support
• Additional Features:
- Loopback, Listen All Messages, and Listen
Only modes for self-test, system di agnostic s
and bus monitoring
- Low-power o perating modes
- CAN module is a bus master on the PIC32
system bus
- Use of DMA is not required
- Dedicated time-stamp timer
- Dedicated DMA channels
- Data-only Message Reception mode
Figure 24-1 i llus trates t he gen eral s tructure of th e CAN
module.
FIGURE 24-1: PI C32 C AN MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 34. “Controller
Area Network (CAN)” (DS60001154) in
the “PIC32 Family Reference Manual”,
which is available from the Micro chip web
site (www.microchip.com/PIC32).
Message Buf fer 31
Message Buffer 1
Message Buffer 0
Message Buffer 31
Message Buffer 1
Message Buffer 0
Message Buf fer 31
Message Buffer 1
Message Buffer 0
FIFO0 FIFO1 FIFO31
System RAM
Up to 32 Message Buffers
CAN Message FIFO (up to 32 FIFOs)
Message
Buffer Size
2 or 4 Words
System Bus
CPU
CAN Module
32 Filters
4 Masks
CxTX
CxRX
PIC32MX5XX/6XX/7XX
DS60001156J-page 242 2009-2016 Microchip Technology Inc.
24.1 Control Registers
TABLE 24-1: CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L,
PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
B000 C1CON 31:16 — — — — ABAT REQOP<2:0> OPMOD<2:0> CANCAP — — — — 0480
15:0 ON —SIDLE— CANBUSY — — — — — — DNCNT<4:0> 0000
B010 C1CFG 31:16 — — — — — — — — — WAKFIL — — — SEG2PH<2:0> 0000
15:0 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> SJW<1:0> BRP<5:0> 0000
B020 C1INT 31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE — — — — — — — MODIE CTMRIE RBIE TBIE 0000
15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF — — — — — — — MODIF CTMRIF RBIF TBIF 0000
B030 C1VEC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — FILHIT<4:0> — ICODE<6:0> 0040
B040 C1TREC 31:16 — — — — — — — — — — TXBO TXBP RXBP TXWARN RXWARN EWARN 0000
15:0 TERRCNT<7:0> RERRCNT<7:0> 0000
B050 C1FSTAT 31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000
15:0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 0000
B060 C1RXOVF 31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
B070 C1TMR 31:16 CANTS<15:0> 0000
15:0 CANTSPRE<15:0> 0000
B080 C1RXM0 31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
15:0 EID<15:0> xxxx
B090 C1RXM1 31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
15:0 EID<15:0> xxxx
B0A0 C1RXM2 31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
15:0 EID<15:0> xxxx
B0B0 C1RXM3 31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
15:0 EID<15:0> xxxx
B0C0 C1FLTCON0 31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0> 0000
15:0 FLTEN1 MSEL1<1:0> FSEL1<4:0> FLTEN0 MSEL0<1:0> FSEL0<4:0> 0000
B0D0 C1FLTCON1 31:16 FLTEN7 MSEL7<1:0> FSEL7<4:0> FLTEN6 MSEL6<1:0> FSEL6<4:0> 0000
15:0 FLTEN5 MSEL5<1:0> FSEL5<4:0> FLTEN4 MSEL4<1:0> FSEL4<4:0> 0000
B0E0 C1FLTCON2 31:16 FLTEN11 MSEL11<1:0> FSEL11<4:0> FLTEN10 MSEL10<1:0> FSEL10<4:0> 0000
15:0 FLTEN9 MSEL9<1:0> FSEL9<4:0> FLTEN8 MSEL8<1:0> FSEL8<4:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2009-2016 Microchip Technology Inc. DS60001156J-page 243
PIC32MX5XX/6XX/7XX
B0F0 C1FLTCON3 31:16 FLTEN15 MSEL15<1:0> FSEL15<4:0> FLTEN14 MSEL14<1:0> FSEL14<4:0> 0000
15:0 FLTEN13 MSEL13<1:0> FSEL13<4:0> FLTEN12 MSEL12<1:0> FSEL12<4:0> 0000
B100 C1FLTCON4 31:16 FLTEN19 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000
15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0> 0000
B110 C1FLTCON5 31:16 FLTEN23 MSEL23<1:0> FSEL23<4:0> FLTEN22 MSEL22<1:0> FSEL22<4:0> 0000
15:0 FLTEN21 MSEL21<1:0> FSEL21<4:0> FLTEN20 MSEL20<1:0> FSEL20<4:0> 0000
B120 C1FLTCON6 31:16 FLTEN27 MSEL27<1:0> FSEL27<4:0> FLTEN26 MSEL26<1:0> FSEL26<4:0> 0000
15:0 FLTEN25 MSEL25<1:0> FSEL25<4:0> FLTEN24 MSEL24<1:0> FSEL24<4:0> 0000
B130 C1FLTCON7 31:16 FLTEN31 MSEL31<1:0> FSEL31<4:0> FLTEN30 MSEL30<1:0> FSEL30<4:0> 0000
15:0 FLTEN29 MSEL29<1:0> FSEL29<4:0> FLTEN28 MSEL28<1:0> FSEL28<4:0> 0000
B140 C1RXFn
(n = 0-31) 31:16 SID<10:0> -— EXID — EID<17:16> xxxx
15:0 EID<15:0> xxxx
B340 C1FIFOBA 31:16 C1FIFOBA<31:0> 0000
15:0 0000
B350 C1FIFOCONn
(n = 0-31) 31:16 — — — — — — — — — — — FSIZE<4:0> 0000
15:0 —FRESETUINCDONLY— — — — TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
B360 C1FIFOINTn
(n = 0-31)
31:16 — — — — — TXNFULLIE TXHALFIE TXEMPTYIE ———— RXOVFLIE RXFULLIE RXHALFIE RXN
EMPTYIE 0000
15:0 — — — — — TXNFULLIF TXHALFIF TXEMPTYIF ———— RXOVFLIF RXFULLIF RXHALFIF RXN
EMPTYIF 0000
B370 C1FIFOUAn
(n = 0-31) 31:16 C1FIFOUA<31:0> 0000
15:0 0000
B380 C1FIFOCIn
(n = 0-31) 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — C1FIFOCI<4:0> 0000
TABLE 24-1: CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L,
PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 244 2009-2016 Microchip Technology Inc.
TABLE 24-2: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
C000 C2CON 31:16 — — — — ABAT REQOP<2:0> OPMOD<2:0> CANCAP — — — — 0480
15:0 ON — SIDLE — CANBUSY — — — — — — DNCNT<4:0> 0000
C010 C2CFG 31:16 — — — — — — — — —WAKFIL— — — SEG2PH<2:0> 0000
15:0 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> SJW<1:0> BRP<5:0> 0000
C020 C2INT 31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE — — — — — — — MODIE CTMRIE RBIE TBIE 0000
15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF — — — — — — — MODIF CTMRIF RBIF TBIF 0000
C030 C2VEC 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — —FILHIT<4:0>—ICODE<6:0>
0040
C040 C2TREC 31:16 — — — — — — — — — — TXBO TXBP RXBP TXWARN RXWARN EWARN 0000
15:0 TERRCNT<7:0> RERRCNT<7:0> 0000
C050 C2FSTAT 31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000
15:0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 0000
C060 C2RXOVF 31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
C070 C2TMR 31:16 CANTS<15:0> 0000
15:0 CANTSPRE<15:0> 0000
C080 C2RXM0 31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
15:0 EID<15:0> xxxx
C0A0 C2RXM1 31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
15:0 EID<15:0> xxxx
C0B0 C2RXM2 31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
15:0 EID<15:0> xxxx
C0B0 C2RXM3 31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
15:0 EID<15:0> xxxx
C0C0 C2FLTCON0 31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0> 0000
15:0 FLTEN1 MSEL1<1:0> FSEL1<4:0> FLTEN0 MSEL0<1:0> FSEL0<4:0> 0000
C0D0 C2FLTCON1 31:16 FLTEN7 MSEL7<1:0> FSEL7<4:0> FLTEN6 MSEL6<1:0> FSEL6<4:0> 0000
15:0 FLTEN5 MSEL5<1:0> FSEL5<4:0> FLTEN4 MSEL4<1:0> FSEL4<4:0> 0000
C0E0 C2FLTCON2 31:16 FLTEN11 MSEL11<1:0> FSEL11<4:0> FLTEN10 MSEL10<1:0> FSEL10<4:0> 0000
15:0 FLTEN9 MSEL9<1:0> FSEL9<4:0> FLTEN8 MSEL8<1:0> FSEL8<4:0> 0000
C0F0 C2FLTCON3 31:16 FLTEN15 MSEL15<1:0> FSEL15<4:0> FLTEN14 MSEL14<1:0> FSEL14<4:0> 0000
15:0 FLTEN13 MSEL13<1:0> FSEL13<4:0> FLTEN12 MSEL12<1:0> FSEL12<4:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2009-2016 Microchip Technology Inc. DS60001156J-page 245
PIC32MX5XX/6XX/7XX
C100 C2FLTCON4 31:16 FLTEN19 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000
15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0: 0000
C110 C2FLTCON5 31:16 FLTEN23 MSEL23<1:0> FSEL23<4:0> FLTEN22 MSEL22<1:0> FSEL22<4:0> 0000
15:0 FLTEN21 MSEL21<1:0> FSEL21<4:0> FLTEN20 MSEL20<1:0> FSEL20<4:0> 0000
C120 C2FLTCON6 31:16 FLTEN27 MSEL27<1:0> FSEL27<4:0> FLTEN26 MSEL26<1:0> FSEL26<4:0> 0000
15:0 FLTEN25 MSEL25<1:0> FSEL25<4:0> FLTEN24 MSEL24<1:0> FSEL24<4:0> 0000
C130 C2FLTCON7 31:16 FLTEN31 MSEL31<1:0> FSEL31<4:0> FLTEN30 MSEL30<1:0> FSEL30<4:0> 0000
15:0 FLTEN29 MSEL29<1:0> FSEL29<4:0> FLTEN28 MSEL28<1:0> FSEL28<4:0> 0000
C140 C2RXFn
(n = 0-31) 31:16 SID<10:0> -— EXID — EID<17:16> xxxx
15:0 EID<15:0> xxxx
C340 C2FIFOBA 31:16 C2FIFOBA<31:0> 0000
15:0 0000
C350 C2FIFOCONn
(n = 0-31) 31:16 — — — — — — — — — — — FSIZE<4:0> 0000
15:0 — FRESET UINC DONLY ———— TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
C360 C2FIFOINTn
(n = 0-31)
31:16 — — — — — TXNFULLIE TXHALFIE TXEMPTYIE ———— RXOVFLIE RXFULLIE RXHALFIE RXN
EMPTYIE 0000
15:0 — — — — — TXNFULLIF TXHALFIF TXEMPTYIF ———— RXOVFLIF RXFULLIF RXHALFIF RXN
EMPTYIF 0000
C370 C2FIFOUAn
(n = 0-31) 31:16 C2FIFOUA<31:0> 0000
15:0 0000
C380 C2FIFOCIn
(n = 0-31) 31:16 — — — — — — — — — — — — — — — — 0000
15:0 — — — — — — — — — — — C2FIFOCI<4:0> 0000
TABLE 24-2: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 246 2009-2016 Microchip Technology Inc.
REGISTER 24-1: CiCON: CAN MODULE CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 S/HC-0 R/W-1 R/W-0 R/W-0
— — — — ABAT REQOP<2:0>
23:16
R-1 R-0 R-0 R/W-0 U-0 U-0 U-0 U-0
OPMOD<2:0> CANCAP — — — —
15:8
R/W-0 U-0 R/W-0 U-0 R-0 U-0 U-0 U-0
ON
(1)
—SIDLE— CANBUSY — — —
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DNCNT<4:0>
Legend: HC = Hardware Clear S = Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 Unimplemented: Read as ‘0’
bit 27 ABAT: Abort All Pending Transmissions bit
1 = Signal all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions aborted
bit 26-24 REQOP<2:0>: Request Operation Mode bits
111 = Set Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Set Configuration mode
011 = Set Listen Only mode
010 = Set Loopback mode
001 = Set Di sable mode
000 = Set Normal Operation mode
bit 23-21 OPMOD<2:0>: Operation Mode Status bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Rese rved
100 = Module is in Configuration mode
011 = Module is in Listen Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 20 CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit
1 = CANTMR value is stored on valid message reception and is stored with the message
0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserv e power
bit 19-16 Unimplemented: Read as ‘0’
bit 15 ON: CAN On bit
(1)
1 = CAN module is enabled
0 = CAN module is disabled
bit 14 Unimplemented: Read as ‘0’
Note 1: If the us er appl icati on cle ars thi s bit, it ma y t ake a num ber of cycl es bef ore the CAN modul e comple tes th e
current transaction and responds to this request. The user application should poll the CANBUSY bit to
verify that the request has been honored.
2009-2016 Microchip Technology Inc. DS60001156J- page 247
PIC32MX5XX/6XX/7XX
bit 13 SIDLE: CAN Stop in Idle bit
1 = CAN Stops operation when system enters Idle mode
0 = CAN continues operation when system enters Idle mode
bit 12 Unimplemented: Read as ‘0’
bit 11 CANBUSY: CAN Mod ule is Busy bit
1 = The CAN module is active
0 = The CAN module is completely disabled
bit 10-5 Unimplemented: Read as ‘0’
bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits
10011-11111 = Invalid Selection (compare up to 18-bits of da ta with EID)
10010 = Compare up to data byte 2 bit 6 with EID17 (CiRXFn<17>)
•
•
•
00001 = Compare up to data byte 0 bit 7 with EID0 (CiRXFn<0>)
00000 = Do not compare data bytes
REGISTER 24-1: CiCON: CAN MODULE CONTROL REGIS TER (CONTIN UED)
Note 1: If the us er appl icati on cle ars thi s bit, it ma y t ake a num ber of cycl es bef ore the CAN modul e comple tes th e
current transaction and responds to this request. The user application should poll the CANBUSY bit to
verify that the request has been honored.
PIC32MX5XX/6XX/7XX
DS60001156J-page 248 2009-2016 Microchip Technology Inc.
REGISTER 24-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— WAKFIL — — — SEG2PH<2:0>
(1,4)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEG2PHTS
(1)
SAM
(2)
SEG1PH<2:0> PRSEG<2:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SJW<1:0>
(3)
BRP<5:0>
Legend: HC = Hardware Clear S = Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0’
bit 22 WAKFIL: CAN Bus Line Filter Enable bit
1 = Use CAN bus line filter for wake-up
0 = CAN bus li ne filter is not used for wake-up
bit 21-19 Unimplemented: Read as ‘0’
bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits
(1,4)
111 = Length is 8 x T
Q
•
•
•
000 = Length is 1 x T
Q
bit 15 SEG2PHTS: Phase Segment 2 Time Select bit
(1)
1 = Freely programmable
0 = Maximum of SEG1PH or Information Processing Time, whichever is greater
bit 14 SAM: Sample of the CAN Bus Line bit
(2)
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits
(4)
111 = Length is 8 x T
Q
•
•
•
000 = Length is 1 x T
Q
Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.
2: 3 Time bit sampling is not allowed for BRP < 2.
3: SJW SEG2PH.
4: The Time Quanta per bit must be greater than 7 (that is, T
QBIT
> 7).
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:2 1>) = 100).
2009-2016 Microchip Technology Inc. DS60001156J- page 249
PIC32MX5XX/6XX/7XX
bit 10-8 PRSEG<2:0>: Propagation Time Segment bits
(4)
111 = Length is 8 x T
Q
•
•
•
000 = Length is 1 x T
Q
bit 7-6 SJW<1:0>: Synchronization Jump Width bits
(3)
11 = Length is 4 x T
Q
10 = Length is 3 x T
Q
01 = Length is 2 x T
Q
00 = Length is 1 x T
Q
bit 5-0 BRP<5:0>: Baud Rate Prescaler bits
111111 = T
Q
= (2 x 64)/F
SYS
111110 = T
Q
= (2 x 63)/F
SYS
•
•
•
000001 = T
Q
= (2 x 2)/F
SYS
000000 = T
Q
= (2 x 1)/F
SYS
REGISTER 24-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED)
Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.
2: 3 Time bit sampling is not allowed for BRP < 2.
3: SJW SEG2PH.
4: The Time Quanta per bit must be greater than 7 (that is, T
QBIT
> 7).
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).
PIC32MX5XX/6XX/7XX
DS60001156J-page 250 2009-2016 Microchip Technology Inc.
REGISTER 24-3: CiINT: CAN INTERRUPT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
IVRIE WAKIE CERRIE SERRIE RBOVIE — — —
23:16
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
———— MODIE CTMRIE RBIE TBIE
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
IVRIF WAKIF CERRIF SERRIF
(1)
RBOVIF — — —
7:0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
———— MODIF CTMRIF RBIF TBIF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 IVRIE: Invalid Message Received Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 30 WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 29 CERRIE: CAN Bus Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 28 SERRIE: System Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 27 RBOVIE: Receive Buffer Overf low Interrupt En able bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 26-20 Unimplemented: Read as ‘0’
bit 19 MODIE: Mode Change Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 18 CTMRIE: CAN Timestamp Timer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 17 RBIE: Receive Buffe r Interrupt Enable bi t
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 16 TBIE: Tran smit Buffer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 15 IVRIF: Invalid Message Received Interrupt Flag bit
1 = An invalid messages interrupt has occurred
0 = An invalid message interrupt has not occurred
Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON<15>).
2009-2016 Microchip Technology Inc. DS60001156J- page 251
PIC32MX5XX/6XX/7XX
bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit
1 = A bus wake -up activity interrupt has occurred
0 = A bus wake-up activity interrupt has not occurred
bit 13 CERRIF: CAN Bus Error Interrupt Flag bit
1 = A CAN bus error has occurred
0 = A CAN bus error has not occurred
bit 12 SERRIF: System Error Interrupt Flag bit
1 = A system error occurred (typically an illegal address was presented to the system bus)
0 = A system error has not occurred
bit 11 RBOVIF: Receive Buffer Overflow Interrupt Flag bit
1 = A receive buffer overflow has occurred
0 = A receive buffer overflow has not occurred
bit 10-4 Unimplemented: Read as ‘0’
bit 3 MODIF: CAN Mode Change Interrupt Flag bit
1 = A CAN module mode change has occurred (OPMOD<2:0> has changed to reflect REQOP)
0 = A CAN module mode change has not occurred
bit 2 CTMRIF: CAN Timer Overflow Interrupt Flag bit
1 = A CAN timer (CANTMR) overflow has occurred
0 = A CAN timer (CANTMR) overflow has not occurred
bit 1 RBIF: Receive Buffer Interrupt Flag bit
1 = A receive buffer interrupt is pending
0 = A receive buffer interrupt is not pending
bit 0 TBIF: Transmit Buffer Interrupt Flag bit
1 = A transmit buffer interrupt is pending
0 = A transmit buffer interrupt is not pending
REGISTER 24-3: CiINT: CAN INTERRUPT REGISTER (CONTINUED)
Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON<15>).
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DS60001156J-page 252 2009-2016 Microchip Technology Inc.
REGISTER 24-4: CiVEC: CAN INTERRUPT CODE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — —FILHIT<4:0>
7:0
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— ICODE<6:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-13 Unimplemented: Read as ‘0’
bit 12-8 FILHIT<4:0>: Filter Hit Number bit
11111 = Filter 31
11110 = Filter 30
•
•
•
00001 = Filter 1
00000 = Filter 0
bit 7 Unimplemented: Read as ‘0’
bit 6-0 ICODE<6:0>: Interrupt Flag Code bits
(1)
1111111 = Reserved
•
•
•
1001001 = Reserved
1001000 = Invalid message received (IVRIF)
1000111 = CAN module mode change (MODIF)
1000110 = CAN timestamp timer (CTMRIF)
1000101 = Bus bandwidth error (SER RIF)
1000100 = Address error interrupt (SERRIF)
1000011 = Receive FIFO overflow interrupt (RBOVIF)
1000010 = Wake-up interrupt (WAKIF)
1000001 = Error Interrupt (CERRIF)
1000000 = No interrupt
0111111 = Reserved
•
•
•
0100000 = Reserved
0011111 = FIFO31 Interrupt (CiFSTAT<31> set)
0011110 = FIFO30 Interrupt (CiFSTAT<30> set)
•
•
•
0000001 = FIFO1 Interrupt (CiFSTAT<1> set)
0000000 = FIFO0 Interrupt (CiFSTAT<0> set)
Note 1: These bits are only updated for enabled interrupts.
2009-2016 Microchip Technology Inc. DS60001156J- page 253
PIC32MX5XX/6XX/7XX
REGISTER 24-5: CiTREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
—— TXBO TXBP RXBP TXWARN RXWARN EWARN
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TERRCNT<7:0>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RERRCNT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-22 Unimplemented: Read as ‘0’
bit 21 TXBO: Tran smitter in Error State Bus OFF (TERRCNT 256)
bit 20 TXBP: Transmitter in Error State Bus Passive (TERRCNT 128)
bit 19 RXBP: Receiver in Error State Bus Passive (RERRCNT 128)
bit 18 TXWARN: Transmitter in Error State Warning (128 > TERRCNT 96)
bit 17 RXWARN: Receiver in Error State Warning (128 > RERRCNT 96)
bit 16 EWARN: Transmitter or Receiver is in Error State Warning
bit 15-8 TERRCNT<7:0>: Transmit Error Counter
bit 7-0 RERRCNT<7:0>: Receive Error Counter
REGISTER 24-6: CiFSTAT: CAN FIFO STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24
23:16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 FIFOIP<31:0>: FIF On Interrupt Pending bits
1 = One or more enabled FIFO interrupts are pending
0 = No FIFO interrupts are pending
PIC32MX5XX/6XX/7XX
DS60001156J-page 254 2009-2016 Microchip Technology Inc.
REGISTER 24-7: CiRXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24
23:16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 RXOVF<31:0>: FIFOn Receive Overflow In terrupt Pending bit
1 = FIFO has overflowed
0 = FIFO has not overflowed
REGISTER 24-8: CiTMR: CAN TIMER REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CANTS<15:8>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CANTS<7:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CANTSPRE<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CANTSPRE<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CANTS<15:0>: CAN Time Stamp Timer bits
This is a free-running timer that increments every CANTSPRE system clocks when the CANCAP bit
(CiCON<20>) is set.
bit 15-0 CANTSPRE<15:0>: CAN Time Stamp Timer Prescaler bits
1111 1111 1111 1111 = CAN time stamp timer (CANTS) increments every 65,535 system clocks
•
•
•
0000 0000 0000 0000 = CAN time stamp timer (CANTS) increments every system clock
Note 1: CiTMR will be paused when CANCAP = 0.
2: The CiTMR prescaler count will be reset on any write to CiTMR (CANTSPRE will be unaffected).
2009-2016 Microchip Technology Inc. DS60001156J- page 255
PIC32MX5XX/6XX/7XX
REGISTER 24-9: CiRXMn: CAN ACCEPTANCE FILTER MASK ‘n’ REGISTER (n = 0, 1, 2 OR 3)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SID<10:3>
23:16
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
SID<2:0> —MIDE— EID<17:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EID<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EID<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-21 SID<10:0>: Standard Identifier bit s
1 = Include the SIDx bit in filter comparison
0 = The S IDx bit is a ‘don’t care’ in filter operation
bit 20 Unimplemented: Read as ‘0’
bit 19 MIDE: Identifier Receive Mode bit
1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter
0 = Match eit her standard or ex te nde d a ddre ss m essag e i f fi lters match (tha t is, if (Filter SID) = (M ess ag e
SID) or if (FILTER SID/EID) = (Message SID/EID))
bit 18 Unimplemented: Read as ‘0’
bit 17-0 EID<17:0>: Extended Identifier bits
1 = Include the EIDx bit in filter comparison
0 = The EIDx bit is a ‘don’t care’ in filter operation
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).
PIC32MX5XX/6XX/7XX
DS60001156J-page 256 2009-2016 Microchip Technology Inc.
REGISTER 24-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN3 MSEL3<1:0> FSEL3<4:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN2 MSEL2<1:0> FSEL2<4:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN1 MSEL1<1:0> FSEL1<4:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN0 MSEL0<1:0> FSEL0<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FLTEN3: Filter 3 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL3<1:0>: Filter 3 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL3<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN2: Filter 2 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL2<1:0>: Filter 2 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL2<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2016 Microchip Technology Inc. DS60001156J- page 257
PIC32MX5XX/6XX/7XX
bit 15 FLTEN1: Filter 1 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL1<1:0>: Filter 1 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL1<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN0: Filter 0 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL0<1:0>: Filter 0 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL0<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
REGISTER 24-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 (CONTINUED)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
PIC32MX5XX/6XX/7XX
DS60001156J-page 258 2009-2016 Microchip Technology Inc.
REGISTER 24-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN7 MSEL7<1:0> FSEL7<4:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN6 MSEL6<1:0> FSEL6<4:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN5 MSEL5<1:0> FSEL5<4:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN4 MSEL4<1:0> FSEL4<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FLTEN7: Filter 7 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL7<1:0>: Filter 7 Mask Se lect bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL7<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN6: Fi lter 6 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL6<1:0>: Filter 6 Mask Se lect bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL6<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
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PIC32MX5XX/6XX/7XX
bit 15 FLTEN5: Filter 17 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL5<1:0>: Filter 5 Mask Se lect bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL5<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN4: Filter 4 Enable b it
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL4<1:0>: F ilter 4 M ask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL4<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
REGISTER 24-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
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REGISTER 24-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN11 MSEL11<1:0> FSEL11<4:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN10 MSEL10<1:0> FSEL10<4:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN9 MSEL9<1:0> FSEL9<4:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN8 MSEL8<1:0> FSEL8<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 31 FLTEN11: Filter 11 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL11<1:0>: Filter 11 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL11<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN10: Filter 10 En able bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL10<1:0>: Filter 10 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL10<4:0>: FIFO Selectio n bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
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PIC32MX5XX/6XX/7XX
bit 15 FLTEN9: Filter 9 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL9<1:0>: Filter 9 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL9<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN8: Filter 8 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL8<1:0>: Filter 8 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL8<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
REGISTER 24-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
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REGISTER 24-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN15 MSEL15<1:0> FSEL15<4:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN14 MSEL14<1:0> FSEL14<4:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN13 MSEL13<1:0> FSEL13<4:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN12 MSEL12<1:0> FSEL12<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FLTEN15: Filter 15 En able bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL15<1:0>: Filter 15 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL15<4:0>: FIFO Selectio n bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN14: Filter 14 En able bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL14<1:0>: Filter 14 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL14<4:0>: FIFO Selectio n bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2016 Microchip Technology Inc. DS60001156J- page 263
PIC32MX5XX/6XX/7XX
bit 15 FLTEN13: Filter 13 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL13<1:0>: Filter 13 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL13<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN12: Filter 12 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL12<1:0>: Filter 12 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL12<4:0>: FIFO Selectio n bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
REGISTER 24-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 (CONTINUED)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
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,4
REGISTER 24-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN19 MSEL19<1:0> FSEL19<4:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN18 MSEL18<1:0> FSEL18<4:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN17 MSEL17<1:0> FSEL17<4:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN16 MSEL16<1:0> FSEL16<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FLTEN19: Filter 19 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL19<1:0>: Filter 19 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL19<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN18: Filter 18 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL18<1:0>: Filter 18 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL18<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2016 Microchip Technology Inc. DS60001156J- page 265
PIC32MX5XX/6XX/7XX
bit 15 FLTEN17: Filter 13 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL17<1:0>: Filter 17 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL17<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN16: Filter 16 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL16<1:0>: Filter 16 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL16<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
REGISTER 24-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 (CONTINUED)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
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REGISTER 24-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN23 MSEL23<1:0> FSEL23<4:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN22 MSEL22<1:0> FSEL22<4:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN21 MSEL21<1:0> FSEL21<4:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN20 MSEL20<1:0> FSEL20<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FLTEN23: Filter 23 E nable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL23<1:0>: Filter 23 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL23<4:0>: FIFO Selectio n bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN22: Filter 22 E nable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL22<1:0>: Filter 22 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL22<4:0>: FIFO Selectio n bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
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PIC32MX5XX/6XX/7XX
bit 15 FLTEN21: Filter 21 E nable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL21<1:0>: Filter 21 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL21<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN20: Filter 20 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL20<1:0>: Filter 20 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL20<4:0>: FIFO Selectio n bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
REGISTER 24-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 (CONTINUED)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
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REGISTER 24-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN27 MSEL27<1:0> FSEL27<4:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN26 MSEL26<1:0> FSEL26<4:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN25 MSEL25<1:0> FSEL25<4:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN24 MSEL24<1:0> FSEL24<4:0>
Legend:
R = Readable bit W = Writable bit U = Unim plemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FLTEN27: Filter 27 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL27<1:0>: Filter 27 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL27<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN26: Filter 26 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL26<1:0>: Filter 26 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL26<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
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PIC32MX5XX/6XX/7XX
bit 15 FLTEN25: Filter 25 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL25<1:0>: Filter 25 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL25<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN24: Filter 24 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL24<1:0>: Filter 24 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL24<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
REGISTER 24-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 (CONTINUED)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
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REGISTER 24-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN31 MSEL31<1:0> FSEL31<4:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN30 MSEL30<1:0> FSEL30<4:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN29 MSEL29<1:0> FSEL29<4:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN28 MSEL28<1:0> FSEL28<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FLTEN31: Filter 31 Enab le bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL31<1:0>: Filter 31 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL31<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN30: Filter 30Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL30<1:0>: Filter 30M as k Sele ct bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL30<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
2009-2016 Microchip Technology Inc. DS60001156J- page 271
PIC32MX5XX/6XX/7XX
bit 15 FLTEN29: Filter 29 Enab le bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL29<1:0>: Filter 29 Mas k Select bit s
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL29<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN28: Filter 28 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL28<1:0>: Filter 28 Mask Select bit s
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL28<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
REGISTER 24-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 (CONTINUED)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.
PIC32MX5XX/6XX/7XX
DS60001156J-page 272 2009-2016 Microchip Technology Inc.
REGISTER 24-18: CiRXFn: CAN ACCEPTANCE FILTER ‘n’ REGISTER 7 (n = 0 THROUGH 31)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID<10:3>
23:16
R/W-x R/W-x R/W-x U-0 R/W-0 U-0 R/W-x R/W-x
SID<2:0> — EXID —EID<17:16>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID<15:8>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID<7:0>
Legend:
R = Readable bit W = Writable bit U = Unim plemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-21 SID<10:0>: Standard Identifier bits
1 = Message address bit SIDx must be ‘1’ to match filter
0 = Message address bit SIDx must be ‘0’ to match filter
bit 20 Unimplemented: Read as ‘0’
bit 19 EXID: Extended Identifier Enable bits
1 = Match only messages with extended identifier addresses
0 = Match only messages with standard identifier address es
bit 18 Unimplemented: Read as ‘0’
bit 17-0 EID<17:0>: Extended Identifier bits
1 = Message address bit EIDx must be ‘1’ to match filter
0 = Message address bit EIDx must be ‘0’ to match filter
Note: This register can only be modified when the filter is disabled (FLTENn = 0).
2009-2016 Microchip Technology Inc. DS60001156J- page 273
PIC32MX5XX/6XX/7XX
REGISTER 24-19: CiFIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CiFIFOBA<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CiFIFOBA<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CiFIFOBA<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
(1)
R-0
(1)
CiFIFOBA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CiFIFOBA<31:0>: CAN FIFO Base Address bits
These bits define the base address of all message buffers. Individual message buffers are located based
on the size of the previous message buffers. This address is a physical address. Bits <1:0> are read-only
and read as ‘0’, forcing the messages to be 32-bit word-aligned in device RAM.
Note 1: This bit is unimplemented and will always read ‘0’, which forces word-alignment of messag es.
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).
PIC32MX5XX/6XX/7XX
DS60001156J-page 274 2009-2016 Microchip Technology Inc.
REGISTER 24-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (n = 0 THROUGH 31)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
———FSIZE<4:0>
(1)
15:8
U-0 S/HC-0 S/HC-0 R/W-0 U-0 U-0 U-0 U-0
— FRESET UINC DONLY
(1)
— — — —
7:0
R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
TXEN TXABAT
(2)
TXLARB
(3)
TXERR
(3)
TXREQ RTREN TXPR<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-21 Unimplemented: Read as ‘0’
bit 20-16 FSIZE<4:0>: FIFO Size bits
(1)
11111 = FIFO is 32 messages deep
•
•
•
00010 = FIFO is 3 messages deep
00001 = FIFO is 2 messages deep
00000 = FIFO is 1 message deep
bit 15 Unimplemented: Read as ‘0’
bit 14 FRESET: FIFO Reset bits
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should
poll whether this bit is clear before taking any action.
0 = No effect
bit 13 UINC: Increment Head/Tail bit
TXEN = 1: (FIFO configured as a Transmit FIFO)
When this bit is set the FIFO head will increment by a single message
TXEN = 0: (FIFO configured as a Receive FIFO)
When this bit is set the FIFO tail will increment by a single message
bit 12 DONLY: Store Message Data Only bit
(1)
TXEN = 1: (FIFO configured as a Transmit FIFO)
This bit is not used and has no effect.
TXEN = 0: (FIFO configured as a Receive FIFO)
1 = Only data bytes will be stored in the FIFO
0 = Full message is stored, including identifier
bit 11- 8 Unimplemented: Read as ‘0’
bit 7 TXEN: TX/RX Buf fer Sele cti on bit
1 = FIFO is a Transmit FIFO
0 = FIFO is a Receive FIFO
Note 1: These bi ts can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits
(CiCON<23:2 1>) = 100).
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the FIFO is reset.
2009-2016 Microchip Technology Inc. DS60001156J- page 275
PIC32MX5XX/6XX/7XX
bit 6 TXABAT: Message Aborted bit
(2)
1 = Message was aborted
0 = Message completed successfully
bit 5 TXLARB: Message Lost Arbitration bit
(3)
1 = Messag e lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4 TXERR: Error Detected During Transmission bit
(3)
1 = A bus error occured while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3 TXREQ: Message Send Request
TXEN = 1: (FIFO configured as a Transmit FIFO)
Setting this bit to ‘1’ requests sending a message.
The bit will automatically clear wh en all the messa ges queue d in the FIFO are successfully sent.
Clearing the bit to ‘0’ while set (‘1’) will request a message abort.
TXEN = 0: (FIFO configured as a receive FIFO)
This bit has no effect.
bit 2 RTREN: Auto RTR Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
bit 1-0 TXPR<1:0>: Message Transmit Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
REGISTER 24-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (n = 0 THROUGH 31)
Note 1: These bi ts can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits
(CiCON<23:21>) = 100).
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the FIFO is reset.
PIC32MX5XX/6XX/7XX
DS60001156J-page 276 2009-2016 Microchip Technology Inc.
REGISTER 24-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — TXNFULLIE TXHALFIE TXEMPTYIE
23:16
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
———— RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE
15:8
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
— — — — —TXNFULLIF
(1)
TXHALFIF TXEMPTYIF
(1)
7:0
U-0 U-0 U-0 U-0 R/W-0 R-0 R-0 R-0
———— RXOVFLIF RXFULLIF
(1)
RXHALFIF
(1)
RXNEMPTYIF
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit
1 = Interrupt enabled for FIFO not full
0 = Interrupt disabled for FIFO not full
bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO empty
0 = Interrupt disabled for FIFO empty
bit 23-20 Unimplemented: Read as ‘0’
bit 19 RXOVFLIE: Overflow Interrupt Enable bit
1 = Interrupt enabled for overflow event
0 = Interrupt disabled for overflow event
bit 18 RXFULLIE: Full Interrupt Enable bit
1 = Interrupt enabled for FIFO full
0 = Interrupt disabled for FIFO full
bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 16 RXNEMPTYIE: Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO not empty
0 = Interrupt disabled for FIFO not empty
bit 15-11 Unimplemented: Read as ‘0’
bit 10 TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is not full
0 = FIFO is full
TXEN = 0: (FIFO configured as a receive buffer)
Unused, reads ‘0’
Note 1: This bit is read-only and reflects the status of the FIFO.
2009-2016 Microchip Technology Inc. DS60001156J- page 277
PIC32MX5XX/6XX/7XX
bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is half full
0 = FIFO is > half full
TXEN = 0: (FIFO configured as a receive buffer)
Unused, reads ‘0’
bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is empty
0 = FIFO is not empty, at least 1 message queued to be transmitted
TXEN = 0: (FIFO configured as a receive buffer)
Unused, reads ‘0’
bit 7-4 Unimplemented: Read as ‘0’
bit 3 RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = Overflow event has occurred
0 = No overflow event occured
bit 2 RXFULLIF: Receive FIFO Full Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = FIFO is full
0 = FIFO is not full
bit 1 RXHALFIF: Receive FIFO Half Full Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = FIFO is half full
0 = FIFO is < half full
bit 0 RXNEMPTYIF: Rece ive Buffer Not Empty Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = FIFO is not empty, has at least 1 message
0 = FIFO is empty
REGISTER 24-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31)
Note 1: This bit is read-only and reflects the status of the FIFO.
PIC32MX5XX/6XX/7XX
DS60001156J-page 278 2009-2016 Microchip Technology Inc.
REGISTER 24-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER ‘n’ (n = 0 THROUGH 31)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R-x R-x R-x R-x R-x R-x R-x R-x
CiFIFOUAn<31:24>
23:16
R-x R-x R-x R-x R-x R-x R-x R-x
CiFIFOUAn<23:16>
15:8
R-x R-x R-x R-x R-x R-x R-x R-x
CiFIFOUAn<15:8>
7:0
R-x R-x R-x R-x R-x R-x R-0
(1)
R-0
(1)
CiFIFOUAn<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 31-0 CiFIFOUAn<31:0>: CAN FIFO User Address bits
TXEN = 1: (FIFO configured as a transmit buffer)
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN = 0: (FIFO configured as a receive buffer)
A read of this register will return the address where the next message is to be read (FIFO tail).
Note 1: This bit will always read ‘0’, which forces byte-alignment of messages.
Note: This regis ter is not guaran teed to read corre ctly in C onfig uration mod e, and shou ld on ly b e acces sed when
the module is not in Configuration mode.
REGISTER 24-23: CiFIFOCIN: CAN MODULE MESSAGE INDEX REGISTER ‘n’ (n = 0 THROUGH 31)
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
7:0
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
——— CiFIFOCI<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-5 Unimplemented: Read as ‘0’
bit 4-0 CiFIFOCIn<4:0>: CAN Side FIFO Message Index bits
TXEN = 1: (FIFO configured as a transmit buffer)
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
TXEN = 0: (FIFO configured as a receive buffer)
A read of this register will return an index to the message that the FIFO will use to save the next message.
2009-2016 Microchip Technology Inc. DS60001156J- page 279
PIC32MX5XX/6XX/7XX
25.0 ETHERNET CONTR OLLER
The Ethernet controller is a bus master module that
interfaces with an off-chip Physical Layer (PHY) to
implement a complete Ethernet node in a system.
Key features of the Ethernet Controller include:
• Supports 10/100 Mbps data transfer rates
• Supports full-duplex and half-duplex operation
• Supports RMII and MII PHY interface
• Supports MIIM PHY management int erfac e
• Supports both manual and automatic Flow Control
• RAM descriptor-based DMA operation for both
receive and transmit path
• Fully configurable interrupts
• Configurable receive pack et filtering
- CRC check
- 64-byte patt ern ma tch
- Broadcast, multicast and unicast packets
- Magic Packet™
- 64-bit hash table
- Runt packet
• Supports packet payload checksum calculation
• Supports various hardware statistics counters
Figure 25-1 illustrates a block diagram of the Ethernet
controller.
FIGURE 25-1: ETHERNET CONTROLLER BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 35. “Ethernet
Controller” (DS60001155) in the “PIC32
Family Refe rence Man ual”, which is avail-
able from the Microchip web site
(www.microchip.com/PIC32).
TX Bus
Master
System Bus
RX Bus
Master
TX DMA
TX Flow Control
Host IF
RX DMA
RX Filter
Checksum
MAC External
PHY
MII/RMII
IF
MIIM
IF
MAC Control
and
Configuration
Registers
TX Function
RX Function
DMA
Control
Registers
Fast Peripheral
Bus
Ethernet Controller
RX Flow
Control
Ethernet DMA
RX BM
TX BM
TX
FIFO
RX
FIFO
PIC32MX5XX/6XX/7XX
DS60001156J-page 280 2009-2016 Microchip Technology Inc.
Table 25-1, Table 25-2, Table 25-3 and Table 25-4
show four interfaces and the associated pins that can
be us ed with the Et hernet Controller.
TABLE 25-1: MII MODE DEFAULT
INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 1)
Pin Name Descripti on
EMDC Management C lock
EMDIO Management I/O
ETXCLK Transmit Clock
ETXEN Transmit Enable
ETXD0 Transmit Data
ETXD1 Transmit Data
ETXD2 Transmit Data
ETXD3 Transmit Data
ETXERR Transmit Error
ERXCLK Receive Clock
ERXDV Receive Data Valid
ERXD0 Receive Data
ERXD1 Receive Data
ERXD2 Receive Data
ERXD3 Receive Data
ERXERR Receive Error
ECRS Carrier Sense
ECOL Collision Indicati on
TABLE 25-2: RMII MODE DEFAULT
INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 1)
Pin Name Descripti on
EMDC Management C lock
EMDIO Management I/O
ETXEN Transmit Enable
ETXD0 Transmit Data
ETXD1 Transmit Data
EREFCLK Reference Clock
ECRSDV Carrier Sense – Receive Data Valid
ERXD0 Receive Data
ERXD1 Receive Data
ERXERR Receive Error
Note: Ethernet controller pins that are not used
by selected interface can be used by
other peripherals.
TABLE 25-3: MII MODE ALTERNATE
INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 0)
Pin Name Descriptio n
AEMDC Man age me nt Cloc k
AEMDIO Management I/O
AETXCLK Transmit Cloc k
AETXEN Transmit Enable
AETXD0 Transmit Data
AETXD1 Transmit Data
AETXD2 Transmit Data
AETXD3 Transmit Data
AETXERR Transm it Error
AERXCLK Receive Clock
AERXDV Receive Data Valid
AERXD0 Receive Data
AERXD1 Receive Data
AERXD2 Receive Data
AERXD3 Receive Data
AERXERR Receive Error
AECRS Carrier Sense
AECOL Colli si on Ind ica tion
Note: The MII mode Alternate Interface is not
available on 64-pin devices.
TABLE 25-4: RMII MODE ALTERNATE
INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 0)
Pin Name Descriptio n
AEMDC Man age me nt Cloc k
AEMDIO Management I/O
AETXEN Transmit Enable
AETXD0 Transmit Data
AETXD1 Transmit Data
AEREFCLK Ref erence Clock
AECRSDV Carrier Sense – Receive Data Valid
AERXD0 Receive Data
AERXD1 Receive Data
AERXERR Receive Error
2009-2016 Microchip Technology Inc. DS60001156J-page 281
PIC32MX5XX/6XX/7XX
25.1 Control Registers
TABLE 25-5: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
9000 ETHCON1 31:16 PTV<15:0>
0000
15:0 ON —SIDL——— TXRTS RXEN AUTOFC ——MANFC— — — BUFCDEC
0000
9010 ETHCON2 31:16 ————————————————
0000
15:0 —————RXBUFSZ<6:0>— — — —
0000
9020 ETHTXST 31:16 TXSTADDR<31:16>
0000
15:0 TXSTADDR<15:2> — —
0000
9030 ETHRXST 31:16 RXSTADDR<31:16>
0000
15:0 RXSTADDR<15:2> — —
0000
9040 ETHHT0 31:16 HT<31:0>
0000
15:0
0000
9050 ETHHT1 31:16 HT<63:32>
0000
15:0
0000
9060 ETHPMM0 31:16 PMM<31:0>
0000
15:0
0000
9070 ETHPMM1 31:16 PMM<63:32>
0000
15:0
0000
9080 ETHPMCS 31:16 ————————————————
0000
15:0 PMCS<15:0>
0000
9090 ETHPMO 31:16 ————————————————
0000
15:0 PMO<15:0>
0000
90A0 ETHRXFC 31:16 ————————————————
0000
15:0 HTEN MPEN — NOTPM PMMODE<3:0> CRC
ERREN CRC
OKEN RUNT
ERREN RUNTEN UCEN NOT
MEEN MCEN BCEN
0000
90B0 ETHRXWM 31:16 ————————RXFWM<7:0>
0000
15:0 ———————— RXEWM<7:0>
0000
90C0 ETHIEN 31:16 ————————————————
0000
15:0 —TX
BUSEIE RX
BUSEIE ———EW
MARKIE FW
MARKIE RX
DONEIE PK
TPENDIE RX
ACTIE —TX
DONEIE TX
ABORTIE RX
BUFNAIE RX
OVFLWIE
0000
90D0 ETHIRQ 31:16 ————————————————
0000
15:0 — TXBUSE RXBUSE ——— EWMARK FWMARK RXDONE PKTPEND RXACT — TXDONE TXABORT RXBUFNA RXOVFLW
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
2: Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
DS60001156J-page 282 2009-2016 Microchip Technology Inc.
90E0 ETHSTAT 31:16 ———————— BUFCNT<7:0>
0000
15:0 ———————— BUSY TXBUSY RXBUSY — — — — —
0000
9100 ETH
RXOVFLOW 31:16 ————————————————
0000
15:0 RXOVFLWCNT<15:0>
0000
9110 ETH
FRMTXOK 31:16 ————————————————
0000
15:0 FRMTXOKCNT<15:0>
0000
9120 ETH
SCOLFRM 31:16 ————————————————
0000
15:0 SCOLFRMCNT<15:0>
0000
9130 ETH
MCOLFRM 31:16 ————————————————
0000
15:0 MCOLFRMCNT<15:0>
0000
9140 ETH
FRMRXOK 31:16 ————————————————
0000
15:0 FRMRXOKCNT<15:0>
0000
9150 ETH
FCSERR 31:16 ————————————————
0000
15:0 FCSERRCNT<15:0>
0000
9160 ETH
ALGNERR 31:16 ————————————————
0000
15:0 ALGNERRCNT<15:0>
0000
9200 EMAC1
CFG1
31:16 ————————————————
0000
15:0 SOFT
RESET SIM
RESET — — RESET
RMCS RESET
RFUN RESET
TMCS RESET
TFUN ——— LOOPBACK TXPAUSE RXPAUSE PASSALL RXENABLE
800D
9210 EMAC1
CFG2
31:16 ————————————————
0000
15:0 —EXCESS
DFR BP
NOBKOFF NOBKOFF —— LONGPRE PUREPRE AUTOPAD VLANPAD PAD
ENABLE CRC
ENABLE DELAYCRC HUGEFRM LENGTHCK FULLDPLX
4082
9220 EMAC1
IPGT 31:16 ————————————————
0000
15:0 —————————B2BIPKTGP<6:0>
0012
9230 EMAC1
IPGR 31:16 ————————————————
0000
15:0 — NB2BIPKTGP1<6:0> — NB2BIPKTGP2<6:0>
0C12
9240 EMAC1
CLRT 31:16 ————————————————
0000
15:0 —— CWINDOW<5:0> ———— RETX<3:0>
370F
9250 EMAC1
MAXF 31:16 ————————————————
0000
15:0 MACMAXF<15:0>
05EE
TABLE 25-5: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
2: Reset values default to the factory programmed value.
2009-2016 Microchip Technology Inc. DS60001156J-page 283
PIC32MX5XX/6XX/7XX
9260 EMAC1
SUPP
31:16 ————————————————
0000
15:0 ————RESET
RMII — — SPEED
RMII ————————
1000
9270 EMAC1
TEST 31:16 ————————————————
0000
15:0 ———————————
—
— TESTBP TESTPAUSE SHRTQNTA
0000
9280 EMAC1
MCFG
31:16 ————————————————
0000
15:0 RESET
MGMT ————————— CLKSEL<3:0> NOPRE SCANINC
0020
9290 EMAC1
MCMD 31:16 ————————————————
0000
15:0 ——————————————SCANREAD
0000
92A0 EMAC1
MADR 31:16 ————————————————
0000
15:0 ——— PHYADDR<4:0> ——— REGADDR<4:0>
0100
92B0 EMAC1
MWTD 31:16 ————————————————
0000
15:0 MWTD<15:0>
0000
92C0 EMAC1
MRDD 31:16 ————————————————
0000
15:0 MRDD<15:0>
0000
92D0 EMAC1
MIND 31:16 ————————————————
0000
15:0 ———————————— LINKFAIL NOTVALID SCAN MIIMBUSY
0000
9300 EMAC1
SA0
(2)
31:16 ————————————————
xxxx
15:0 STNADDR6<7:0> STNADDR5<7:0>
xxxx
9310 EMAC1
SA1
(2)
31:16 ————————————————
xxxx
15:0 STNADDR4<7:0> STNADDR3<7:0>
xxxx
9320 EMAC1
SA2
(2)
31:16 ————————————————
xxxx
15:0 STNADDR2<7:0> STNADDR1<7:0>
xxxx
TABLE 25-5: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
Virtual Address
(BF88_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
2: Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
DS60001156J-page 284 2009-2016 Microchip Technology Inc.
REGISTER 25-1: ETHCON1: ETHERNET CONTROLLER CONTROL REGISTE R 1
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTV<15:8>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTV<7:0>
15:8
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
ON —SIDL— — — TXRTS RXEN
(1)
7:0
R/W-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0
AUTOFC ——MANFC— — — BUFCDEC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 PTV<15:0>: PAUSE Timer Value bits
PAUSE Timer Value used for Flow Control.
This register should only be written when RXEN (ETHCON1<8>) is not set.
These bits are only used for Flow Control operations.
bit 15 ON: Ethernet ON b it
1 = Ethernet module is enabled
0 = Ethernet module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Ethernet Stop in Idle Mode bit
1 = Ethernet module transfers are paused during Idle mo de
0 = Ethernet module transfers continue during Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9 TXRTS: Transmit Request to Send bit
1 = Activate the TX logic and send the packet(s) defined in the TX EDT
0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware)
After the bit is written with a ‘1’ , it wi ll c le ar t o a ‘0’ whenever the transmit logic has finished transmitting
the requested packets in the Ethernet Descriptor Table (EDT). If a ‘0’ is written by the CPU, the transmit
logic finishes the current packet’s transmission and then stops any further.
This bit only affects TX operations.
bit 8 RXEN: Rec eive Enable bit
(1)
1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter
configuration
0 = Disable RX logic, no pac kets are received in the RX buffer
This bit only affects RX operations.
Note 1: It is not recomm end ed to cl ear the RXEN bit and then m ake cha nge s to an y R X relate d fie ld/r egister. The
Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
2009-2016 Microchip Technology Inc. DS60001156J- page 285
PIC32MX5XX/6XX/7XX
bit 7 AUTOFC: Automatic Flow Control bit
1 = Automatic Flow Control is enabled
0 = Automatic Flow Control is disabled
Setting this bit will enable automatic Flow Control. If set, the full and empty watermarks are used to
automatically enable and disable the Flow Control, respectively. When the number of received buffers
BUFCNT (ETHSTAT<16:23>) rises to the full watermark, Flow Control is automatically enabled. When
the BUFCNT falls to the empty watermark, Flow Control is automatically disabled.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 6-5 Unimplemented: Read as ‘0’
bit 4 MANFC: Manual Flow Control bit
1 = Manual Flow Control is enabled
0 = Manual Flow Control is disabled
Setting this bit will enable manual Flow Control. If set, the Flow Control logic will send a PAUSE frame
using the PAUSE timer value in the PTV register. It will then resend a PAUSE frame every 128 *
PTV<15:0>/2 TX clock cycles until the bit is cleared.
Note: For 10 Mbp s op erat ion , TX cloc k run s at 2.5 MHz. For 10 0 Mbps operation, TX cloc k run s at
25 MHz.
When this bit is cleared, the Flow Control logic will automatically send a PAUSE frame with a 0x0000
PAUSE timer value to disable Flow Control.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 3-1 Unimplemented: Read as ‘0’
bit 0 BUFCDEC: Descri ptor Buffer Count Decrement bit
The BU FCDEC bi t is a write-1 bit t hat rea ds as ‘ 0’. When writte n with a ‘1’, the Descriptor Buffer Counter ,
BUFCNT, will dec rement by one. If BUFCNT is increm ented by the RX lo gic at the same time that this b it
is written, the BUFCNT value will remain unchanged. Writing a ‘0’ will have no effect.
This bit is only used for RX operations.
REGISTER 25-1: ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED)
Note 1: It is not recomm end ed to cl ear the RXEN bit and then ma ke cha nge s to an y R X relate d fie ld/register. The
Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.
PIC32MX5XX/6XX/7XX
DS60001156J-page 286 2009-2016 Microchip Technology Inc.
REGISTER 25-2: ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — RXBUFSZ<6:4>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
RXBUFSZ<3:0> — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-11 Unimplemented: Read as ‘0’
bit 10-4 RXBUFSZ<6:0>: RX Data Buffer Size for All RX Descriptors (in 16-byte increments) bits
1111111 = RX data Buffer size for descriptors is 2032 bytes
•
•
•
1100000 = RX data Buffer size for descriptors is 1536 bytes
•
•
•
0000011 = RX data Buffer size for descriptors is 48 bytes
0000010 = RX data Buffer size for descriptors is 32 bytes
0000001 = RX data Buffer size for descriptors is 16 bytes
0000000 = Reserv ed
bit 3-0 Unimplemented: R ead as ‘0’
Note 1: Thi s registe r is only used f or RX operations.
2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
2009-2016 Microchip Technology Inc. DS60001156J- page 287
PIC32MX5XX/6XX/7XX
REGISTER 25-3: ETHTXST: ETHERNET CONTROLLER TX PACKET DESCRIPTOR START
ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXSTADDR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXSTADDR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXSTADDR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
TXSTADDR<7:2> — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-2 TXSTADDR<31:2>: Starting Addres s of First Transmit Descriptor bits
This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be ‘00’).
bit 1-0 Unimplemented: Read as ‘0’
Note 1: This register is only used for TX ope rations .
2: This reg is ter w i ll b e u pda ted by hardware with the l as t de sc rip tor u se d by the last succ ess fu lly tra nsm it ted
packet.
REGISTER 25-4: ETHRXST: ETHERNET CONTROLLER RX PACKET DESCRIPTOR START
ADDRESS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RXSTADDR<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RXSTADDR<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RXSTADDR<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
RXSTADDR<7:2> — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
bit 31-2 RXSTADDR<31:2>: Starting Address of First Receive Descriptor bits
This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be ‘00’).
bit 1-0 Unimplemented: Read as ‘0’
Note 1: This register is only used for RX operations.
2: This reg is ter w ill be up dated by hardw are with the last desc rip tor u se d b y the las t s uc ce ss ful ly tra ns mi tted
packet.
PIC32MX5XX/6XX/7XX
DS60001156J-page 288 2009-2016 Microchip Technology Inc.
REGISTER 25-5: ETHH T0 : ETHERNET CONTROLLER HASH TABLE 0 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HT<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HT<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 HT<31:0>: Hash Table Bytes 0-3 bits
Note 1: Thi s registe r is only used f or RX operations.
2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit
(ETHRXFC<15>) = 0.
REGISTER 25-6: ETHH T1 : ETHERNET CONTROLLER HASH TABLE 1 REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HT<63:56>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HT<55:48>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HT<47:40>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HT<39:32>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 HT<63:32>: Hash Table Bytes 4-7 bits
Note 1: Thi s registe r is only used f or RX operations.
2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit
(ETHRXFC<15>) = 0.
2009-2016 Microchip Technology Inc. DS60001156J- page 289
PIC32MX5XX/6XX/7XX
REGISTER 25-7: ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMM<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMM<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMM<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMM<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 PMM<31:24>: Pattern Match Mask 3 bits
bit 23-16 PMM<23:16>: Pattern Match Mask 2 bits
bit 15-8 PMM<15:8>: Patter n Match Mask 1 bits
bit 7-0 PMM<7:0>: Pattern Match Mask 0 bits
Note 1: This register is only used for RX operations.
2: The bit s in this register ma y o nl y b e c han ged whi le t he R XEN bit (ETHCON1<8> ) = 0 o r the PMMO DE bi t
(ETHRXFC<11 :8>) = 0.
REGISTER 25-8: ETHPMM1: ETHERNET CONTROLLER PATTERN MATCH MASK 1 REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMM<63:56>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMM<55:48>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMM<47:40>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMM<39:32>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 PMM<63:56>: Pattern Match Mask 7 bits
bit 23-16 PMM<55:48>: Pattern Match Mask 6 bits
bit 15-8 PMM<47:40>: Pattern Match Mask 5 bits
bit 7-0 PMM<39:32>: Pattern Match Mask 4 bits
Note 1: This register is only used for RX operations.
2: The bit s in this reg ister ma y only be changed while the RXEN bit (E THCON1 <8>) = 0 or the PMMODE bit
(ETHRXFC<11 :8>) = 0.
PIC32MX5XX/6XX/7XX
DS60001156J-page 290 2009-2016 Microchip Technology Inc.
REGISTER 25-9: ETHPMCS: ETHERNET CONTROLLER PATTERN MATCH CHECKSUM
REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMCS<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMCS<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8 PMCS<15:8>: Pattern Match Checksum 1 bits
bit 7-0 PMCS<7:0>: Pattern Match Checksum 0 bits
Note 1: Thi s registe r is only used f or RX operations.
2: The bit s in this reg ister ma y only be changed while the RXEN bit (ETHCON1 <8>) = 0 or the PMMODE bit
(ETHRXFC<11 :8>) = 0.
REGISTER 25-10: ETHPMO: ETHERNET CONTROLLER PATTERN MATCH OFFSET REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMO<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMO<7:0>
Legend:
R = Readable bit W = Writable bi t U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 PMO<15:0>: Pattern Match Offset 1 bits
Note 1: Thi s registe r is only used f or RX operations.
2: The bit s in this reg ister ma y only be changed while the RXEN bit (ETHCON1 <8>) = 0 or the PMMODE bit
(ETHRXFC<11 :8>) = 0.
2009-2016 Microchip Technology Inc. DS60001156J- page 291
PIC32MX5XX/6XX/7XX
REGISTER 25-11: ETHRXFC: ETHERNET CONTROLLER RECEIV E FILTER CONFIGURATION
REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HTEN MPEN — NOTPM PMMODE<3:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CRCERREN CRCOKEN RUNTERREN RUNTEN UCEN NOTMEEN MCEN BCEN
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 HTEN: Enable Hash Table Filtering bit
1 = Enable Hash Table Filtering
0 = Disable Hash Table Filtering
bit 14 MPEN: Magic Packet™ Enable bit
1 = Enable Magic Packet Filtering
0 = Disable Magic Packet Filteri ng
bit 13 Unimplemented: Read as ‘0’
bit 12 NOTPM: Pattern Match Invers ion bit
1 = The Pattern Match Chec ksum must not match for a successful Pattern Match to occur
0 = The Pattern Match Checksum must match for a successful Pattern Match to occur
This bit determines whether Pattern Match Checksum must match in order for a successful Pattern Match
to occur.
bit 11- 8 PMMODE<3:0>: Pattern Match Mode bi ts
1001 = Pattern match is successf ul if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Packet = Magic Packet)
(1,3)
1000 = Pattern match is successf ul if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Hash Table Filter match)
(1,2)
0111 = Pattern match is successf ul if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Broadcast Address)
(1)
0110 = Pattern match is successf ul if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Broadcast Address)
(1)
0101 = Pattern match is successf ul if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Unicast Address)
(1)
0100 = Pattern match is successf ul if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Unicast Address)
(1)
0011 = Pattern match is successf ul if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Station Address)
(1)
0010 = Pattern match is successf ul if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Station Address)
(1)
0001 = Pattern match is successf ul if (NOTPM = 1 XOR Pattern Match Checksum matches)
(1)
0000 = Pattern Match is disabled; pattern match is always unsuccessful
Note 1: XOR = True when either one or the other conditions are true, but not both.
2: This Hash Table Filter match is active regardless of the value of the HTEN bit.
3: This Magic Packet Filter match is active regardless of the value of the MPEN bit.
Note 1: This register is only used for RX operations.
2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
PIC32MX5XX/6XX/7XX
DS60001156J-page 292 2009-2016 Microchip Technology Inc.
bit 7 CRCERREN: CRC Error Collection Enable bit
1 = The received packet CRC must be invalid for the pa cket to be accepted
0 = Disable CRC Error Collection filtering
This bit allows the user to collect all packets that have an invalid CRC.
bit 6 CRCOKEN: CRC OK Enable bit
1 = The received packet CRC must be valid for the packet to be accepted
0 = Disable CRC filtering
This bit allows the user to reject all packets that have an invalid CRC.
bit 5 RUNTERREN: Runt Error Collection Enable bit
1 = The received packet must be a runt packet for the packet to be accepted
0 = Disable Runt Error Collection filtering
This bit a llo w s th e us er to coll ec t all packets that are runt packets. For th is filter , a ru nt packet is defin ed as
any packet with a size of less than 64 by tes (when CRCOKEN = 0) or any packet with a size of less than
64 bytes that has a valid CRC (when CRCOKEN = 1).
bit 4 RUNTEN: Runt Enable bit
1 = The received packet must not be a runt packet for the packet to be accepted
0 = Disable Runt filtering
This bit al lows the us er to rejec t all runt p acke ts . For this filt er, a runt packet is de fined as any pac ket wit h a
size of less than 64 bytes.
bit 3 UCEN: Unicast Enable bit
1 = Enable Unicast Filtering
0 = Disable Unicast Filtering
This bit allows the user to accept all unicast packets whose Destination Address matches the Station
Address.
bit 2 NOTMEEN: Not Me Unicast Enable bit
1 = Enable Not Me Unicast Filtering
0 = Disable Not Me Unicast Filtering
This bi t allows the user to ac cept all u nicast p acket s whose Destin ation Addre ss does not mat ch the Station
Address.
bit 1 MCEN: Multicast Enable bit
1 = Enable Mu lticast Filtering
0 = Disable Multicast Filtering
This bit allows the user to accept all Multicast Address packets.
bit 0 BCEN: Broadcast Enable bit
1 = Enable Broadcast Filtering
0 = Disable Broadcast Filtering
This bit allows the user to acce pt all Broadcast Address packets.
REGISTER 25-11: ETHRXFC: ETHERNET CONTROLLER RECEIV E FILTER CONFIGURATION
REGISTER
(CONTINUED)
Note 1: XOR = True when either one or the other conditions are true, but not both.
2: This Hash Table Filter match is active regardless of the value of the HTEN bit.
3: This Magic Packet Filter match is active regardless of the value of the MPEN bit.
Note 1: Thi s registe r is only used f or RX operations.
2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.
2009-2016 Microchip Technology Inc. DS60001156J- page 293
PIC32MX5XX/6XX/7XX
REGISTER 25-12: ETHRXWM: ETHERNET CONTROLLER RECEIVE WATERMARKS REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RXFWM<7:0>
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RXEWM<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 RXFWM<7:0>: Receive Full Watermark bits
The software controlled RX Buffer Full Watermark Pointer is compared against the RX BUFCNT to
determine the full watermark condition for the FWMARK interrupt and for enabling Flow Control when
automatic Flow C ontrol i s enabled. The Full W atermark Pointer should a lways be g reater tha n the Empty
Watermark Pointer.
bit 15-8 Unimplemented: R ead as ‘0’
bit 7-0 RXEWM<7:0>: Rece ive Empty Watermark bits
The software controlled RX Buffer Empty Watermark Pointer is compared against the RX BUFCNT to
determine the empty watermark con dition for t he EWMARK i nterrupt and for disabli ng Flow Contro l when
automatic Flow Control is enabled. The Empty Watermark Pointer should always be less than the Full
Watermark Pointer.
Note: This register is only used for RX opera tions.
PIC32MX5XX/6XX/7XX
DS60001156J-page 294 2009-2016 Microchip Technology Inc.
REGISTER 25-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
— TXBUSEIE
(1)
RXBUSEIE
(2)
— — — EWMARKIE
(2)
FWMARKIE
(2)
7:0
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
RXDONEIE
(2)
PKTPENDIE
(2)
RXACTIE
(2)
— TXDONEIE
(1)
TXABORTIE
(1)
RXBUFNAIE
(2)
RXOVFLWIE
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14 TXBUSEIE: Transmit BVCI Bus Error Interrupt Enable bit
(1)
1 = Enable TXBUS Error Interrupt
0 = Disable TXBUS Error Interrupt
bit 13 RXBUSEIE: Receive BVCI Bus Error Interrupt Enable bit
(2)
1 = Enable RXBUS Error Interrupt
0 = Disable RXBUS Error Interrupt
bit 12-10 Unimplemented: Read as ‘0’
bit 9 EWMARKIE: Empty Watermark Interru pt Enab le bit
(2)
1 = Enable EWMARK Interrupt
0 = Disable EWMARK Inte rrup t
bit 8 FWMARKIE: Full Watermark Interrupt Enable bit
(2)
1 = Enable FWMARK Interrupt
0 = Disable FWMARK Interrupt
bit 7 RXDONEIE: Receiver Done Interrupt Enable bit
(2)
1 = Enable RXDONE Interrupt
0 = Disable RXDONE Interrupt
bit 6 PKTPENDIE: Packet Pending Interrupt Enable bit
(2)
1 = Enable PKTPEND Interrupt
0 = Disable PKTPEND Interrupt
bit 5 RXACTIE: RX Activity Interrupt Enable bit
1 = Enable RXACT Interrupt
0 = Disable RXACT Interrupt
bit 4 Unimplemented: Read as ‘0’
bit 3 TXDONEIE: Transmitter Done Interrupt Enable bit
(1)
1 = Enable TXDONE Interrupt
0 = Disable TXDONE Interrupt
bit 2 TXABORTIE: Transmitter Abort Interrupt Enable bit
(1)
1 = Enable TXABORT Interrupt
0 = Disable TXABORT Interrupt
bit 1 RXBUFNAIE: Receive Buffer Not Available Interrupt Enable bit
(2)
1 = Enable RXBUFNA Interrupt
0 = Disable RXBUFNA Interrupt
bit 0 RXOVFLWIE: Receive FIFO Overflow Interrupt Enable bit
(2)
1 = Enable RXOVFLW Interrupt
0 = Disable RXOVFLW Interrupt
Note 1: This bit is only used for TX operati ons .
2: This bit is only used for RX operations.
2009-2016 Microchip Technology Inc. DS60001156J- page 295
PIC32MX5XX/6XX/7XX
REGISTER 25-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
— TXBUSE RXBUSE — — — EWMARK FWMARK
7:0
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
RXDONE PKTPEND RXACT — TXDONE TXABORT RXBUFNA RXOVFLW
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14 TXBUSE: Transmit BVCI Bus Error Interrupt bit
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
This bit is set when the TX DMA encounters a BVCI Bus error during a me mory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 13 RXBUSE: Receive BVCI Bus Error Interrupt bit
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
This bit is set when the RX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 12-10 Unimplemented: Read as ‘0’
bit 9 EWMARK: Empty Watermark Interrupt bit
1 = Empty Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is less than or equal to the value in the
RXEWM bit (ETHRXWM<0:7>) value. It is cleared by BUFCNT bit (ETHSTAT<16:23>)
being incremented by hardware. Writing a ‘0’ or a ‘1’ has no effect.
bit 8 FWMARK: Full Watermark Interrupt bit
1 = Full Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is greater than or equal to the value in the RXFWM
bit (ETHRXWM<16:23>) field. It is cleared by writing the BUFCDEC (ETHCON1<0>) bit to decrement
the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
bit 7 RXDONE: Receive Done Interrupt bit
1 = RX packet was successfully received
0 = No interrupt pending
This bit is set whenever an RX packet is successfully received. It is cleared by either a Reset or CPU
write of a ‘1’ to the CLR register.
Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
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DS60001156J-page 296 2009-2016 Microchip Technology Inc.
bit 6 PKTPEND: Packet Pending Interrupt bit
1 = RX packet pending in memory
0 = RX packet is not pending in memory
This bit is set when the BUFCNT counter has a value other than ‘0’. It is cleared by either a Reset or by
writing the BUFCDEC bit to decrement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
bit 5 RXACT: Receive Activity Interrupt bit
1 = RX packet data was successfully received
0 = No interrupt pending
This bit is set whenever RX pack et data is stored in the RXBM FIFO. It is cleared by either a Reset or
CPU write of a ‘1’ to the CLR register.
bit 4 Unimplemented: Read as ‘0’
bit 3 TXDONE: Transmit Done Interrupt bit
1 = TX packet was successfully sent
0 = No interrupt pending
This bit is set when the curren tly transmitted TX packet co mpletes tran smissi on, and the T ran smit S t atus
Vector is loaded into the first descriptor used for the packet. It is cleared by either a Reset or CPU write
of a ‘1’ to the CLR register.
bit 2 TXABORT: Transmit Abort Condition Interrupt bit
1 = TX abort condition occurr ed on the l ast TX packet
0 = No interrupt pending
This bit is set when the MAC aborts the transmission of a TX packet for one of the following reasons:
• Jumbo TX packet abort
• Underrun abort
• Excessive defer abort
• Late collision abort
• Excessive collisions abort
This bit is cleared by either a Reset or CPU write of a ‘1’ to the CLR register.
bit 1 RXBUFNA: Receive Buffer Not Available Interrupt bit
1 = RX Buffer Descriptor Not Available condition has occurred
0 = No interrupt pending
This bit is set by a RX Buf f er D esc riptor Overrun co ndi tio n. It is cl eare d b y e ith er a R ese t o r a C PU wr i te
of a ‘1’ to the CLR register.
bit 0 RXOVFLW: Receive FIFO Over Flow Error bit
1 = RX FIFO Overflow Error condition has occurred
0 = No interrupt pending
RXOVFLW is set by the RXBM Logic for an RX FIFO Overflow condition. It is cleared by either a Reset
or CPU write of a ‘1’ to the CLR regis ter.
REGISTER 25-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
2009-2016 Microchip Technology Inc. DS60001156J- page 297
PIC32MX5XX/6XX/7XX
REGISTER 25-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFCNT<7:0>
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
ETHBUSY
(1)
TXBUSY
(2)
RXBUSY
(2)
— — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 BUFCNT<7:0>: Packet Buffer Count bits
Number of p a cket buffers receiv ed in memory. Once a packet has bee n suc c ess fu lly rece iv ed, thi s reg is ter
is increm ented by hardware based on the number of descriptors used by the packet. Software decrements
the counter (by writing to the BUFCDEC bit (ETHCON1<0>) for each descriptor used) after a packet has
been read out of the b uf fer. The registe r does not rol l over (0xFF to 0x00) when hard ware tries to incre ment
the register and the register is already at 0xFF. Conversely, the register does not roll under (0x00 to 0xFF)
when sof tware tries to decrement th e register and the register is a lready at 0x000 0. When sof tware attempt s
to decr ement the c ounter at the s ame time that t he hardwa re attempt s to incre ment the co unter, the counter
value will remain unchanged.
When this register value reaches 0xFF, the RX logic will halt (only if automatic Flow Control is enabled)
awaiting software to write the BUFCDEC bit in order to decrement the register below 0xFF.
If automatic Flow Control is disabled, the RXDMA will continue processing and the BUFCNT will saturate at
a value of 0xFF.
When this register is non-zero, the PKTPEND status bit will be set and an interrupt may be generated,
depending on the value of the ETHIEN bit <PKTPENDIE> register.
When the ETHRXST register is written, the BUFCNT counter is automatically cleared to 0x00.
Note: BUFCNT will no t b e cleared when ON is set to ‘0’. This enables software to continue to utilize
and decrement this count.
bit 15-8 Unimplemented: Read as ‘0’
bit 7 ETHBUSY: Ethernet Module busy bit
(1)
1 = Ethernet logic has been turned on (ON (ETHCON1<15>) = 1) or is completing a transaction
0 = Ethernet logic is idle
This bit indicates that the module has been turned on or is comp leting a transaction after being turned off.
bit 6 TXBUSY: Transmit Busy bit
(2)
1 = TX logic is receiving data
0 = TX logic is idle
This bit indicates that a packet is currently being transmitted. A change in this status bit is not necessarily
reflected by the TXDONE interrupt, as TX packets may be aborted or rejected by the MAC.
Note 1: This bit will be set when the ON bit (ETHCON1<15>) = 1.
2: This bit will be cleared when the ON bit (ETHCON1<15>) = 0.
PIC32MX5XX/6XX/7XX
DS60001156J-page 298 2009-2016 Microchip Technology Inc.
bit 5 RXBUSY: Receive Busy bit
(2)
1 = RX logic is receiving data
0 = RX logic is idle
This bit indicates that a packet is currently being received. A change in this status bit is not necessarily
reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter.
bit 4-0 Unimplemented: Read as ‘0’
REGISTER 25-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED)
Note 1: This bit will be set when the ON bit (ETHCON1<15>) = 1.
2: This bit will be cleared when the ON bit (ETHCON1<15>) = 0.
2009-2016 Microchip Technology Inc. DS60001156J- page 299
PIC32MX5XX/6XX/7XX
REGISTER 25-16: ETHRXOVFLOW: ETHERNET CONTROLLER RECEIVE OVERFLOW ST ATISTICS
REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RXOVFLWCNT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RXOVFLWCNT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 RXOVFLWCNT<15:0>: Dropped Receive Frames Count bits
Incremen t counter for frames accepted by the RX filte r and su bsequent ly droppe d due to internal receive
error (RXFIFO overrun). This even t also sets the RXOVFLW bit (ETHIRQ<0>) interrupt flag.
Note 1: This register is only used for RX operations.
2: This register is automatically cleared by hardware after a read operation, unless the byte enables for
byt es 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
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DS60001156J-page 300 2009-2016 Microchip Technology Inc.
REGISTER 25-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK
STATISTICS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FRMTXOKCNT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FRMTXOKCNT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 FRMTXOKCNT<15:0>: Frame Transmitted OK Count bits
Increment counter for frames successful ly transmitted.
Note 1: This register is only used for TX ope rations.
2: This regi ster is au tomatical ly cleared by hardware after a re ad operatio n, unless the byte en ables for b ytes
0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
2009-2016 Microchip Technology Inc. DS60001156J- page 301
PIC32MX5XX/6XX/7XX
REGISTER 25-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES
STATISTICS REGISTER
Bit Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SCOLFRMCNT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SCOLFRMCNT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 SCOLFRMCNT<15:0>: Single Collision Frame Count bits
Increment count for frames that were successfully transmitted on the second try.
Note 1: This register is only used for TX ope rations.
2: This register is automatically cleared by hardware after a read operation, unless the byte enables for
byt es 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
PIC32MX5XX/6XX/7XX
DS60001156J-page 302 2009-2016 Microchip Technology Inc.
REGISTER 25-19: ETHMCOLFRM: ETHERNET CONTROLLER MULTIPLE COLLISION FRAMES
STATISTICS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MCOLFRMCNT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MCOLFRMCNT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 MCOLFRMCNT<15:0>: Multiple Collision Frame Count bits
Increment count for frames that were successfully transmitted after there was more than one collision.
Note 1: This register is only used for TX ope rations.
2: This regi ster is au tomatical ly cleared by hardware after a re ad operatio n, unless the byte en ables for b ytes
0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
2009-2016 Microchip Technology Inc. DS60001156J- page 303
PIC32MX5XX/6XX/7XX
REGISTER 25-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK
STATISTICS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FRMRXOKCNT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FRMRXOKCNT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 FRMRXOKCNT<15:0>: Frames Received OK Count bits
Increment count for frames received successfully by the RX Filter. This count will not be incremented if
there is a Fram e Check Sequence ( FCS) or Alignment error.
Note 1: This register is only used for RX operations.
2: This register is automatically cleared by hardware after a read operation, unless the byte enables for
byt es 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.
PIC32MX5XX/6XX/7XX
DS60001156J-page 304 2009-2016 Microchip Technology Inc.
REGISTER 25-21: ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR
STATISTICS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FCSERRCNT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FCSERRCNT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 FCSERRCNT<15:0>: FCS Error Count bits
Increment count for frames received with FCS error and the frame length in bits is an integral multiple of
8bits.
Note 1: Thi s registe r is only used f or RX operations.
2: This regi ster is au tomatical ly cleared by hardware after a re ad operatio n, unless the byte en ables for b ytes
0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should be only done for debug/test purposes.
2009-2016 Microchip Technology Inc. DS60001156J- page 305
PIC32MX5XX/6XX/7XX
REGISTER 25-22: ETHALGNERR: ETHERNET CONTROLLER ALIGNMENT ERRORS STATISTICS
REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ALGNERRCNT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ALGNERRCNT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 ALGNERRCNT<15:0>: Alignment Error Count bi ts
Increment count for frames with alignment errors. Note that an alignment error is a frame that has an FCS
error and the frame length in bits is not an integral multiple of 8 bits (a.k.a., dribble nibble)
Note 1: This register is only used for RX operations.
2: This re gister is a utoma tical ly c leared by h ardware af ter a read operat ion, u nless the byte ena bles for by tes
0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should be only done for debug/test purposes.
PIC32MX5XX/6XX/7XX
DS60001156J-page 306 2009-2016 Microchip Technology Inc.
REGISTER 25-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-1 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
SOFT
RESET SIM
RESET — — RESET
RMCS RESET
RFUN RESET
TMCS RESET
TFUN
7:0
U-0 U-0 U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1
— — — LOOPBACK TX
PAUSE RX
PAUSE PASSALL RX
ENABLE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 SOFTRESET: Soft Reset bit
Setting this bit will put the MACMII in reset. Its default value is ‘1’.
bit 14 SIMRESET: Simulati on Reset bit
Setting this bit will cause a reset to the random number generator within the Transmit Function.
bit 13-12 Unimplemented: Read as ‘0’
bit 11 RESETRMCS: Reset MCS/RX bit
Setting this bit will put the MAC Control Sub-layer/Receive domain logic in reset.
bit 10 RESETRFUN: Reset RX Function bit
Setting this bit will put the MAC Receive function logic in reset.
bit 9 RESETTMCS: Reset MCS/TX bit
Setting this bit will put the MAC Control Sub-layer/TX domain logic in reset.
bit 8 RESETTFUN: Reset TX Function bit
Setting this bit will put the MAC Transmit function logic in reset.
bit 7-5 Unimplemented: Read as ‘ 0’
bit 4 LOOPBACK: MAC Loopback mode bit
1 = MAC Transmit interface is loop backed to the MAC Receive interface
0 = MAC normal operation
bit 3 TXPAUSE: MAC TX Flow Control bit
1 = PAUSE Flow Control frames are allowed to be transmitted
0 = PAUSE Flow Control frames are blocked
bit 2 RXPAUSE: MAC RX Flow Control bit
1 = The MAC acts upon received PAUSE Flow Control frames
0 = Received PAUSE Flow Co ntrol frames are ignored
bit 1 PASSALL: MAC Pass all Receive Frames bit
1 = The MAC will accept all frames regardless of type (Normal vs. Control)
0 = The received Control frames are ignored
bit 0 RXENABLE: MAC Receive Enable bit
1 = Enable the MAC receiving of frames
0 = Disable th e MAC receiving of frames
Note: Both 16-bit and 32-bit acces ses are allowed to thes e registers (includi ng the SET, CLR and INV register s).
8-bit accesses are not allowed and are ignored by the hardware.
2009-2016 Microchip Technology Inc. DS60001156J- page 307
PIC32MX5XX/6XX/7XX
REGISTER 25-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
25/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
—EXCESS
DFR BPNOBK
OFF NOBK
OFF —— LONGPRE PUREPRE
7:0
R/W-1 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
AUTO
PAD
(1,2)
VLAN
PAD
(1,2)
PAD
ENABLE
(1,3)
CRC
ENABLE DELAYCRC HUGEFRM LENGTHCK FULLDPLX
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: R ead as ‘0’
bit 14 EXCESSDER: Excess Defer bit
1 = The MAC will defer to carrier indefinitely as per the Standard
0 = The MAC will abort when the excessive deferral limit is reached
bit 13 BPNOBKOFF: Backpressure/No Backoff bit
1 = The MAC after incidentally causing a collision during backpressure will immediately retransmit wi thout
backoff reducing the chance of further collisions and ensuring transmit packets get sent
0 = The MAC will not remove the backoff
bit 12 NOBKOFF: No Backoff bit
1 = Follow ing a c ollision, th e MAC wil l immedia tely retran smit rath er than us ing the Bi nary Exponen tial Back -
off algorithm as specified in the Standard
0 = Following a collision, the MAC will use the Binary Exponential Backoff algorithm
bit 11-10 Unimplemented: Read as ‘0’
bit 9 LONGPRE: Long Preamble Enforcement bit
1 = The MAC only allows receive packets which contain preamble fields less than 12 bytes in length
0 = The MAC allows any length preamble as per the Standard
bit 8 PUREPRE: Pure Preamble Enforcement bit
1 = The MAC will ve rify the content of th e preamble to ensure it c ontains 0x 55 and is error-free. A packet w ith
errors in its preamble is discarded
0 = The MAC does not perform any preamble checki ng
bit 7 AUTOPAD: Automatic Detect Pad Enable bit
(1,2)
1 = The MAC will automatically detect the type of frame, either tagged or untagged, by comparing the two
octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly
0 = The MAC does not perform automatic detection
Note 1: Table 25-6 provides a description of the pad function based on the configuration of this register.
2: This bit is ignored if the PADENABLE bit is cleared.
3: This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
Note: Both 16-bi t and 32-b it acces ses are all owed to th ese reg isters (includin g the SET, CLR and INV regi sters ).
8-bit accesses are not allowed and are ignored by the hardware
PIC32MX5XX/6XX/7XX
DS60001156J-page 308 2009-2016 Microchip Technology Inc.
TABLE 25-6: PAD OPERATION
bit 6 VLANPAD: VLAN Pad Enable bit
(1,2)
1 = The MAC will pad all short frames to 64 bytes and append a valid CRC
0 = The MAC does not perform padding of short frames
bit 5 PADENABLE: Pad/CRC Enable bit
(1,3)
1 = The MAC will pad all short frames
0 = The frames presented to the MAC have a valid length
bit 4 CRCENABLE: CRC Enable1 bit
1 = The MAC will append a CRC to every frame whether padding was required or not. Must be set if the
PADENABLE bit is set.
0 = The frames presented to the MAC have a valid CRC
bit 3 DELAYCRC: Delayed CRC bit
This bit determ ines the nu mber of byt es, if any, of propr ieta ry he ader in format ion th at exi st on the f ront of the
IEEE 802.3 frames.
1 = Four bytes o f header (ignored by the CRC function)
0 = No proprietary header
bit 2 HUGEFRM: Huge Frame enable bit
1 = Frames of any length are transmitted and received
0 = Huge frames are not allowed for receive or transmit
bit 1 LENGTHCK: Frame Length checkin g bit
1 = Both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field
represents a length then the check is performed. Mismatches are reported on the transmit/receive
sta tis tic s ve ctor.
0 = Length/Type field check is not performed
bit 0 FULLDPLX: Full-Duplex Operation bit
1 = The MAC operates in Full-Duplex mode
0 = The MAC operates in Half-Duplex mode
REGISTER 25-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
(CONTINUED)
Note 1: Table 25-6 provides a description of the pad function based on the configuration of this register.
2: This bit is ignored if the PADENABLE bit is cleared.
3: This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
Note: Both 16-bi t and 32-b it acces ses are all owed to th ese reg isters (includin g the SET, CLR and INV reg isters ).
8-bit accesses are not allowed and are ignored by the hardware
Type AUTOPAD VLANPAD PADENABLE Action
Any xx0No pad, check CRC
Any 001Pad to 60 Bytes, append CRC
Any x11Pad to 64 Bytes, append CRC
Any 101If untagged: Pad to 60 Bytes, append CRC
If VLAN tagged: Pad to 64 Bytes, append CRC
2009-2016 Microchip Technology Inc. DS60001156J- page 309
PIC32MX5XX/6XX/7XX
REGISTER 25-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET
GAP REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
— B2BIPKTGP<6:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-7 Unimplemented: Read as ‘0’
bit 6-0 B2BIPKTGP<6:0>: Back-to-Back Interpacket Gap bits
This is a programmable field representing the nibble time offset of the minimum possible period between
the end of any transmitted packet, to the beginning of the next. In Full-Duplex mode, the register value
should be the desired period in ni bble times minus 3. In Half-D uplex mode, the regist er value should be the
desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which rep-
resents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps). In Half-Duplex mode, the rec-
ommended setting is 0x12 (18d), which also represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6
µs (in 10 Mbps).
Note: Both 16-bit and 32-bit ac cesses are al lowed to these registers (includin g the SET, CLR and INV r egisters ).
8-bit accesses are not allowed and are ignored by the hardware.
PIC32MX5XX/6XX/7XX
DS60001156J-page 310 2009-2016 Microchip Technology Inc.
REGISTER 25-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK
INTERPACKET GAP REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0
— NB2BIPKTGP1<6:0>
7:0
U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
— NB2BIPKTGP2<6:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14-8 NB2BIPKTGP1<6:0>: Non-Back-to-Back Interpacket Gap Part 1 bits
This is a programmable field representing the optional carrierSense window referenced in section
4.2.3.2.1 “Defere nc e” o f t he IEEE 8 0.2 3 Specification. If the carrier is d etec te d d urin g t he timin g o f IPGR1,
the MAC defe rs to the ca rrier . If, however, the carrier comes a fter IPGR1 , the MAC con tinues ti ming IPGR2
and transmits, knowingly causing a collision, thus ensuring fair access to the medium. Its range of values
is 0x0 to IPGR2. Its recommend value is 0xC (12d).
bit 7 Unimplemented: Read as ‘0’
bit 6-0 NB2BIPKTGP2<6:0>: Non-B ack-to-Back Interpacket Gap Part 2 bits
This is a prog ramma ble fiel d repres entin g the non -back-to-b ack I nter- Packet -Gap. Its recomme nded value
is 0x12 (18d), which represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps).
Note: Both 16-b it and 32 -bit ac cesses are a llowed to the se reg isters (i nclud ing th e SET, CLR a nd IN V regis ters).
8-bit accesses are not allowed and are ignored by the hardware.
2009-2016 Microchip Technology Inc. DS60001156J- page 311
PIC32MX5XX/6XX/7XX
REGISTER 25-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY
LIMIT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1
—— CWINDOW<5:0>
7:0
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
— ——— RETX<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13-8 CWINDOW<5:0>: Collision Window bits
This is a programmable field representing the slot time or collision window during which collisions occur in
properly configured networks. Since the collision window starts at the beginning of transmi ssion, the pre-
amble and SFD is incl uded. Its defaul t of 0x 37 (55 d) co rres po nds to the cou nt of fra me bytes at the end of
the wind ow.
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 RETX<3:0>: Retransmission Maximum bits
This is a programmable field specifying the number of retransmission attempts following a collision before
aborting the packet due to excessive collisions. The Standard specifies the maximum number of attempts
(attemptLimit) to be 0xF (15d). Its default is ‘0xF’.
Note: Both 16-bit and 32-bit ac cesses are al lowed to these registers (includin g the SET, CLR and INV r egisters ).
8-bit accesses are not allowed and are ignored by the hardware.
PIC32MX5XX/6XX/7XX
DS60001156J-page 312 2009-2016 Microchip Technology Inc.
REGISTER 25-28: EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH
REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
MACMAXF<15:8>
(1)
7:0
R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0
MACMAXF<7:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 MACMAXF<15:0>: Maximum Frame Length bits
(1)
These bits reset to 0x05EE, which represents a maximum receive frame of 1518 octets. An untagged
maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If
a shorter/longer maximum length restriction is desired, program this 16-bit field.
Note 1: If a proprietary header is allowed, this bit should be adjusted accordingly. For example, if 4-byte headers
are prepended to frames, MACMAXF could be set to 1527 octets. This would allow the maximum VLAN
tagged frame plus the 4-byte header.
Note: Both 16-b it and 32 -bit ac cesses are a llowed to the se reg isters (i nclud ing th e SET, CLR a nd IN V regis ters).
8-bit accesses are not allowed and are ignored by the hardware.
2009-2016 Microchip Technology Inc. DS60001156J- page 313
PIC32MX5XX/6XX/7XX
REGISTER 25-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
— — — — RESETRMII
(1)
—— SPEEDRMII
(1)
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11 RESETRMII: Reset RMII Logic bit
(1)
1 = Reset the MAC RMII module
0 = Normal operation.
bit 10-9 Unimplemented: Read as ‘0’
bit 8 SPEEDRMII: RMII S p eed bit
(1)
This bit configures the Reduced MII logic for the current operating speed.
1 = RMII is running at 100 Mbps
0 = RMII is running at 10 Mbps
bit 7-0 Unimplemented: Read as ‘0’
Note 1: This bit is only used for the RMII module.
Note: Both 16-bit an d 32-bit ac cesses are allowed to the se register s (including th e SET, CLR and IN V registe rs).
8-bit accesses are not allowed and are ignored by the hardware.
PIC32MX5XX/6XX/7XX
DS60001156J-page 314 2009-2016 Microchip Technology Inc.
REGISTER 25-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — TESTBP TESTPAUSE
(1)
SHRTQNTA
(1)
Legend:
R = Readable bit W = Writab le bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-3 Unimplemented: Read as ‘0’
bit 2 TESTBP: Test Backpressure bit
1 = The M A C w il l a ssert backpressure on the link. Bac kp res su re c au ses p ream bl e t o b e transmitted, rais ing
carrier sense. A transmit packet from the system will be sent during backpressure.
0 = Normal operation
bit 1 TESTPAUSE: Test PAUSE bit
(1)
1 = The MAC Control sub-layer will inhibit transmissions, just as if a PAUSE Receive Control frame with a
non-zero pause time parameter was received
0 = Normal operation
bit 0 SHRTQNTA: Shortcut PAUSE Quanta bit
(1)
1 = The MAC reduces the effective PAUSE Quanta from 64 byte-times to 1 byte-time
0 = Normal operation
Note 1: This bit is only for testing purposes.
Note: Both 16-b it and 32 -bit ac cesses are a llowed to the se reg isters (i nclud ing th e SET, CLR a nd IN V regis ters).
8-bit accesses are not allowed and are ignored by the hardware.
2009-2016 Microchip Technology Inc. DS60001156J- page 315
PIC32MX5XX/6XX/7XX
TABLE 25-7: MIIM CLOCK SELECTION
REGISTER 25-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT
CONFIGURATION REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
RESETMGMT — — — — — — —
7:0
U-0 U-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CLKSEL<3:0>
(1)
NOPRE SCANINC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 RESETMGMT: Test Reset MII Management bit
1 = Reset the MII Management module
0 = Normal Operation
bit 14-6 Unimplemented: Read as ‘0’
bit 5-2 CLKSEL<3:0>: MII Management Clock Select 1 bits
(1)
These bi ts ar e used by the clock div ide log ic in cr eating the MII Ma nagem ent Cloc k (MDC), which the IEEE
802.3 Specification defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz.
bit 1 NOPRE: Suppress Preamble bit
1 = The MII Management will perform read/write cycles without the 32-bit preamble field. Some PHYs
support suppre ss ed prea mb le
0 = Nor m al read/write cycles are pe rformed
bit 0 SCANINC: Scan Increment bit
1 = The M II Managemen t module will perform read cyc les across a ra nge of PHYs. The read cycles wil l start
from address 1 through the value set in EMAC1MADR<PHYADDR>
0 = Continuous reads of the same P HY
Note 1: Table 25-7 provides a description of the clock divider encoding.
Note: Both 16-bit an d 32-bit acc esses are al lowed to these registers (inclu ding the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
MIIM Clock Select EMAC1MCFG<5:2>
SYSCLK divided by 4 000x
SYSCLK divided by 6 0010
SYSCLK divided by 8 0011
SYSCLK divided by 10 0100
SYSCLK divided by 14 0101
SYSCLK divided by 20 0110
SYSCLK divided by 28 0111
SYSCLK divided by 40 1000
Undefined Any other combination
PIC32MX5XX/6XX/7XX
DS60001156J-page 316 2009-2016 Microchip Technology Inc.
REGISTER 25-32: EMAC1MCMD: ETHERNET CONTROLLER MAC MII MANAGEMENT COMMAND
REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SCAN READ
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-2 Unimplemented: Read as ‘0’
bit 1 SCAN: MII Management Scan Mode bit
1 = The MII Management module will perform read cycles continuously (for example, useful for monitoring
the Link Fail)
0 = Normal Operation
bit 0 READ: MII Management Read Command bit
1 = The MII Management module will perform a single read cycle. The read data is returned in the
EMAC1MRDD register
0 = The MII Man ageme nt modu le will pe rform a w rite cycle . The wri te dat a is t aken fro m the EMAC1M WTD
register
Note: Both 16-bi t and 32 -bit acces ses are allow ed to thes e register s (including the SET, CLR a nd INV register s).
8-bit accesses are not allowed and are ignored by the hardware.
2009-2016 Microchip Technology Inc. DS60001156J- page 317
PIC32MX5XX/6XX/7XX
REGISTER 25-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS
REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
— — — PHYADDR<4:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — REGADDR<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-13 Unimplemented: Read as ’0’
bit 12-8 PHYADDR<4:0>: MII Management PHY Address bits
This fiel d repres ent s the 5-bit PHY Ad dress fiel d of Mana gemen t cycl es. Up to 31 PHYs can be addres sed
(0 is reserved).
bit 7-5 Unimplemented: Read as ’0’
bit 4-0 REGADDR<4:0>: MII Management Register Address bits
This field represents the 5-bit Register Address field of Management cycles. Up to 32 registers can be
accessed.
Note: Both 16-bit and 32-bit ac cesses are al lowed to these registers (includin g the SET, CLR and INV r egisters ).
8-bit accesses are not allowed and are ignored by the hardware.
PIC32MX5XX/6XX/7XX
DS60001156J-page 318 2009-2016 Microchip Technology Inc.
REGISTER 25-34: EMAC1MWTD: ETHERNET CONTROLLER MAC MII MANAGEMENT WRITE
DATA REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MWTD<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MWTD<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ’0’
bit 15-0 MWTD<15:0>: MII Management Write Data bits
When wri tten, a MII M anage ment write cycl e is perf ormed using the 1 6-bit d at a an d the p re-conf igured PHY
and Register addresses from the EMAC1MADR register.
Note: Both 1 6-bit a nd 32-bit a ccesses are al lowed t o thes e regis ters (in cluding the SET, C LR and INV registe rs) .
8-bit accesses are not allowed and are ignored by the hardware.
REGISTER 25-35: EMAC1MRDD: ETHERNET CONTROLLER MAC MII MANAGEMENT READ DATA
REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MRDD<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MRDD<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-0 MRDD<15:0>: MII Management Read Data bits
Following a MII Management Read Cycle, the 16-bit data can be read from this location.
Note: Both 16-bit and 32-bit ac cesses are al lowed to these registers (includin g the SET, CLR and INV r egister s).
8-bit accesses are not allowed and are ignored by the hardware.
2009-2016 Microchip Technology Inc. DS60001156J- page 319
PIC32MX5XX/6XX/7XX
REGISTER 25-36: EMAC1MIND: ETHERNET CONTROLLER MAC MII MANAGEMENT INDICATORS
REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — LINKFAIL NOTVALID SCAN MIIMBUSY
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Unimplemented: Re ad as ‘0’
bit 3 LINKFAIL: Link Fail bit
When ‘1’ is returned - i ndicates link fail h as occu rred. This b it reflect s the val ue last re ad from th e PHY sta tus
register.
bit 2 NOTVALID: MII Management Read Data Not Valid bit
When ‘1’ is retu rne d - indicates an M II management read cy cl e h as no t c om ple ted and the Read D a t a is not
yet valid.
bit 1 SCAN: MII Management Scanning bit
When ‘1’ is returned - indicates a sc an operation (continuous MII Management Read cycles) is in progress.
bit 0 MIIMBUSY: MII Management Busy bit
When ‘1’ is returned - indicates MII Management module is currently performing an MII Management Read
or Wri te cycle .
Note: Both 16-b it and 32 -bit ac cesses are a llowed to the se reg isters (i nclud ing th e SET, CLR a nd IN V regis ters).
8-bit accesses are not allowed and are ignored by the hardware.
PIC32MX5XX/6XX/7XX
DS60001156J-page 320 2009-2016 Microchip Technology Inc.
REGISTER 25-37: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
STNADDR6<7:0>
7:0
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
STNADDR5<7:0>
Legend: P = Programmable bit
R = Readable bit W = Writable bit U = Unimpl emented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cl eared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8 STNADDR6<7:0>: Station Address Octet 6 bits
These bits hold the sixth transmitted octet of the station address.
bit 7-0 STNADDR5<7:0>: Station Address Octet 5 bits
These bits hold the fifth transmitted octet of the station address.
Note 1: Both 16-b it and 32-bit acce sses are allow ed t o thes e regi sters (inclu ding th e SET, CLR a nd INV reg isters ).
8-bit accesses are not allowed and are ignored by the hardware.
2: This register is loaded at reset from the factory preprogrammed station address.
2009-2016 Microchip Technology Inc. DS60001156J- page 321
PIC32MX5XX/6XX/7XX
REGISTER 25-38: EMAC1SA1: ETHERNET CONTROLLER MAC STATION ADDRESS 1 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
STNADDR4<7:0>
7:0
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
STNADDR3<7:0>
Legend: P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15-8 STNADDR4<7:0>: Station Address Octet 4 bits
These bits hold the fourth transmitted octet of the station address.
bit 7-0 STNADDR3<7:0>: Station Address Octet 3 bits
These bits hold the third transmitted octet of the station address.
Note 1: Both 16-bit and 32-bit a ccesses a re allowed to these regi sters (inc luding the SET, CLR and INV registers) .
8-bit accesses are not allowed and are ignored by the hardware.
2: This register is loaded at reset from the factory preprogrammed station address.
PIC32MX5XX/6XX/7XX
DS60001156J-page 322 2009-2016 Microchip Technology Inc.
REGISTER 25-39: EMAC1SA2: ETHERNET CONTROLLER MAC STATION ADDRESS 2 REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
STNADDR2<7:0>
7:0
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
STNADDR1<7:0>
Legend: P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Reserved: Maintain as ‘0’; ignore read
bit 15-8 STNADDR2<7:0>: Station Address Octet 2 bits
These bits hold the second transmitted octet of the station address.
bit 7-0 STNADDR1<7:0>: Station Address Octet 1 bits
These bits hold the most significant (first transmitted) octet of the station address.
Note 1: Both 16-bit and 32-b it accesses are allowed to these registers (in cluding the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2: This register is loaded at reset from the factory preprogrammed station address.
2009-2016 Microchip Technology Inc. DS60001156J- page 323
PIC32MX5XX/6XX/7XX
26.0 COMPARATOR
The Comparator module contains two comparators that
can be configured in a variety of ways.
Key features of the Comparator module include:
• Selectable inputs ava i lable include:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute volt age referenc e (IV
REF
)
- Comparat or voltage reference (CV
REF
)
• Output s can be inverte d
• Select ab le int errup t gene ration
A block diagram of the Comparator module is
illustrated in Figure 26-1.
FIGURE 26-1: COMPAR ATOR MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in thi s dat a
sheet, refer to Section 19.
“Comparator” (DS60001110) in the
“PI C32 Fami ly Re ferenc e Manua l” , which
is available from the Microchip web site
(www.microchip.com/PIC32).
C1
CV
REF(2)
C1IN+
(1)
C1IN+
C1IN-
C1OUT
COUT (CM1CON<8>)
CREF
CCH<1:0>
CPOL
COE
ON
C2IN+
IV
REF(2)
C1OUT (CMSTAT<0>)
C2
CV
REF(2)
C2IN+
C2IN+
C2IN-
C2OUT
COUT (CM2CON<8>)
CREF CPOL
COE
ON
C1IN+
IV
REF(2)
C2OUT (CMSTAT<1>)
Comparator 2
Comparator 1
CCH<1:0>
Note 1: On devices with a USB module, and when the module i s enabled, this pin is controlled by the USB module,
and therefore, is not available as a c omparator input.
2: Internally connected. See Section 27.0 “Comparator Voltage Reference (CV
REF
)”.
PIC32MX5XX/6XX/7XX
DS60001156J-page 324 2009-2016 Microchip Technology Inc.
26.1 Control Registers
TABLE 26-1: COMPARATOR REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
A000 CM1CON 31:16 ————————————————0000
15:0 ON COE CPOL ———— COUT EVPOL<1:0> — CREF —— CCH<1:0> 00C3
A010 CM2CON 31:16 ————————————————0000
15:0 ON COE CPOL ———— COUT EVPOL<1:0> — CREF —— CCH<1:0> 00C3
A060 CMSTAT 31:16 ————————————————0000
15:0 ——SIDL——————————— C2OUT C1OUT 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Sect io n 12.1.1 “CL R, SE T an d INV Regi s te r s”
for more information.
2009-2016 Microchip Technology Inc. DS60001156J- page 325
PIC32MX5XX/6XX/7XX
REGISTER 26-1: CMxCON: COMPARATOR ‘x’ CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R-0
ON
(1)
COE CPOL
(2)
— — — —COUT
7:0
R/W-1 R/W-1 U-0 R/W-0 U-0 U-0 R/W-1 R/W-1
EVPOL<1:0> —CREF—— CCH<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Comp arator ON bit
(1)
Clearing this bit does not affect the other bits in this register.
1 = Module is enabled. Setting this bit does not affect the other bits in this register
0 = Module is disabled and does not consume current.
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is driven on the output CxOUT pin
0 = Comparator output is not driven on the output CxOUT pin
bit 13 CPOL: Comparator Ou tput Inversion bit
(2)
1 = Output is inverted
0 = Output is not inverted
bit 12-9 Unimplemented: Read as ‘ 0’
bit 8 COUT: C ompara tor Output bit
1 = Output of the Comparator is a ‘1’
0 = Output of the Comparator is a ‘0’
bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits
11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
10 = Comparator interrupt is generated on a high-to-low transition of the comparator output
01 = Comparator interrupt is generated on a low-to-high transition of the comparator output
00 = Comparator interrupt generation is disabled
bit 5 Unimplemented: Re ad as ‘0’
bit 4 CREF: Comparator Positive Input Configure bit
1 = Comparator non-inverting input is connected to the internal CV
REF
0 = Comparator non-inverti ng input is connected to the C
X
IN+ pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator
11 = Comparator inverting input is connected to the IV
REF
10 = Comparator inverting input is connected to the C2IN+ pin for C1 and C1IN+ pin for C2
01 = Comparator inverting input is connected to the C1IN+ pin for C1 and C2IN+ pin for C2
00 = Comparator inverting input is connected to the C1IN- pin for C1 and C2IN- pin for C2
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
2: Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an
interr upt bei ng gen erat ed on the opp osi te edg e from the one sele cted by EVPOL<1:0 >.
PIC32MX5XX/6XX/7XX
DS60001156J-page 326 2009-2016 Microchip Technology Inc.
REGISTER 26-2: CMSTAT: COMPARATOR STATUS REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
——SIDL— — — — —
7:0
U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0
— — — — — — C2OUT C1OUT
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Control bit
1 = All Comparator modules are disabled while in Idle mode
0 = All Comparator modules continue to operate while in Idle mode
bit 12-2 Unimplemented: Read as ‘0’
bit 1 C2OUT: Comparator Outp ut bit
1 = Output of Comparator 2 is a ‘1’
0 = Output of Comparator 2 is a ‘0’
bit 0 C1OUT: Comparator Outp ut bit
1 = Output of Comparator 1 is a ‘1’
0 = Output of Comparator 1 is a ‘0’
2009-2016 Microchip Technology Inc. DS60001156J- page 327
PIC32MX5XX/6XX/7XX
27.0 COMPARATOR VOLTAGE
REFERENCE (CV
REF
)
The CV
REF
module is a 16-tap, resistor ladder network
that provides a selectable reference voltage. Although
its primary purpose is to provide a reference for the
analog comparators, it also may be used indepe ndently
of them.
A block diagram of the module is illustrated in
Figure 27-1. The resistor ladder is segmented to
provide two ranges of vo ltage reference values and has
a power-down function to conserve power when the
reference is not being u sed. The modu le’s supply refer-
ence can be provided from either device V
DD
/V
SS
or an
external voltage reference. The CV
REF
output is avail-
able for the comparators and typically available for pin
output.
Key features of the CV
REF
module include:
• High and low range selection
• Sixteen output levels available for each range
• Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
FIGURE 27-1: COMPARATOR VOLTAGE REFERENCE MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference sourc e. To com -
plement the information in this data sheet,
refer to Section 20. “Comp arator Voltage
Reference (CV
REF
)” (DS60001109) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
16-to-1 MUX
CVR<3:0>
8R
R
CVREN
CVRSS = 0
AV
DD
V
REF
+CVRSS = 1
8R
CVRSS = 0
V
REF
-CVR S S = 1
R
R
R
R
R
R
16 S teps
CVRR
CV
REFOUT
AV
SS
CVROE (CVRCON<6>)
CV
REF
V
REFSEL(1)
IV
REF
1.2V
0.6V
BGSEL<1:0>
(1)
CV
RSRC
Note 1:
This bit is not availabl e on PI C32MX575/67 5/695/775/795 devices . On these de vice s CV
REF
is gener ated by th e
Register
network and IV
REF
is connected to 0.6V.
PIC32MX5XX/6XX/7XX
DS60001156J-page 328 2009-2016 Microchip Technology Inc.
27.1 Control Register
TABLE 27-1: COMPARATOR VOLTAGE REFERENCE REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
(1)
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
9800 CVRCON 31:16 — — — — — — — — — — — — — — — — 0000
15:0 ON ———— VREFSEL
(2)
BGSEL<1:0>
(2)
— CVROE CVRR CVRSS CVR<3:0> 0100
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “C L R, S ET an d IN V R egi s te rs”
for more information.
2: These bits are not available on PIC32MX575/675/695/775/795 devices. On these devices, reset value for CVRCON is ‘0000’.
2009-2016 Microchip Technology Inc. DS60001156J- page 329
PIC32MX5XX/6XX/7XX
REGISTER 27-1: CVR CON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1
ON
(1)
— — — — VREFSEL
(2)
BGSEL<1:0>
(2)
7:0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CVROE CVRR CVRSS CVR<3:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Comparator Voltage Reference On bit
(1)
Setting or clearing this bit does not affect the other bits in this register.
1= Module is enabled
0= Module is disabled and does not consume current
bit 14-11 Unimplemented: Re ad as ‘0’
bit 10 VREFSEL: Voltage R eferen c e Select bit
(2)
1=CV
REF
= V
REF
+
0=CV
REF
is generated by the resistor network
bit 9-8 BGSEL<1:0>: Band Gap Reference Source bits
(2)
11 =IV
REF
= V
REF
+
10 =Reserved
01 =IV
REF
= 0.6V (nominal, default)
00 =IV
REF
= 1.2V (nominal)
bit 7 Unimplemented: Read as ‘0’
bit 6 CVROE: CV
REFOUT
Enable bit
1= Voltage level is output on CV
REFOUT
pin
0= Voltage level is disconnected from CV
REFOUT
pin
bit 5 CVRR: CV
REF
Range Selection bit
1= 0 to 0.625 CV
RSRC
, with CV
RSRC
/24 step size
0= 0.25 CV
RSRC
to 0.719 CV
RSRC
, with CV
RSRC
/32 step size
bit 4 CVRSS: CV
REF
Source Selection bit
1= Comparator voltage reference source, CV
RSRC
= (V
REF
+) – (V
REF
-)
0= Comparator voltage reference source, CV
RSRC
= AV
DD
– AV
SS
bit 3-0 CVR<3:0>: CV
REF
Value Selection 0 CVR<3:0> 15 bi ts
When CVRR = 1:
CV
REF
= (CVR<3:0>/24) (CV
RSRC
)
When CVRR = 0:
CV
REF
=1/4 (CV
RSRC
) + (CVR<3:0>/32) (CV
RSRC
)
Note 1: When using the 1:1 PBCLK di visor, the user’s software shoul d no t rea d/w rit e th e pe riph era l’s SFRs in the
SYSCLK cycle im mediately following the instruction that clears the module’s ON bit.
2: These bits are not available on PIC32MX575/675/775/795 devices. On these devices, the reset value for
CVRON is ‘0000’.
PIC32MX5XX/6XX/7XX
DS60001156J-page 330 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 331
PIC32MX5XX/6XX/7XX
28.0 POWER-SAVING FEATURES
This section describes power-saving features for the
PIC32MX5XX/6XX/7XX family of devices. These
devices offer a total of nine methods and modes,
organized into two categories, that allow the user to
balance power consumption with device performance.
In all of the methods and modes described in this
section, power-savin g is co ntrolled by sof tw are.
28.1 Power-Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency,
lowering the Peripheral Bus Clock (PBCLK) and by
individually disabling modules. These methods are
grouped into the following categories:
• FRC Run mode: the CPU is clocked from the FRC
clock source with or without postscalers.
• LPRC Run mode: the CPU is clocked from the
LPRC cl ock source.
•S
OSC
Run mode: the CPU is clocked from the
S
OSC
clock sourc e.
In addition, the Pe ripheral Bus Scaling m ode is available
where peripherals are clocked at the programmable
fraction of the CPU clock (SYSCLK).
28.2 CPU Halted Methods
The device supports two power-saving modes, Sleep
and Idl e, both of which Halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
•P
OSC
Idle mo de: the system cloc k is derived from
the P
OSC
. The system clock source continues to
operate. Peripherals continue to operate, but can
optionally be ind ividually disabl ed.
•FRC Idle mode: the system cloc k is derived from
the FRC with or without postscalers. Peripherals
continue to operate, bu t can optionally be
individually disabled.
•S
OSC
Idle mode: the system clock i s derived from
the S
OSC
. Peripherals continue to operate, but
can optionally be individually disabled.
•LPRC Idle mode: the system clock is derived
from the LPRC. Periph era ls co ntin ue to operate,
but can optionally be indiv idu all y di sa ble d. Thi s is
the low est po wer mode for the devic e wi th a cl ock
running.
•Sleep mode: the CPU, the system clock source
and any peri phe rals that operate from the system
clock source are Halted. Some peripherals can
operate in Sleep using specific clock sources.
This is the lowest power mode for the device.
28.3 Power-Saving Operation
Peripherals and the CPU can be halted or disabled to
further reduce power consumption.
28.3.1 SLEEP MO DE
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual
peripheral module sections for descriptions of
behavior in Sleep.
Sleep mode includes the following characteristics:
• The CPU is halted
• The system clock source is typically shutdown.
See Section 28.3.3 “Peripheral Bus Scaling
Method” for specific information.
• There can be a wake-up delay based on the
oscillator selection
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode
• The BOR circuit, if enabled, remains operative
during Sleep mode
• The WD T, if enabled, is n ot automatically cleared
prior to entering Sleep mode
• Some peripherals can continue to operate at
limited functionality in Sleep mode. These
peripherals include I/O pins that detect a change
in the input signal, WDT, ADC, UART and
periphera ls tha t us e an ext erna l c loc k i npu t or th e
internal LPRC oscillator (e.g., RTCC, Ti mer1 and
Input Capture).
• I/O pins continue to sink or source current in the
same m anner as they d o when the devi ce i s not in
Sleep
• Modules can be individually disabled by software
prior to entering Sleep in order to further reduce
consumption
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference sourc e. To com -
plement the information in this data
sheet, refer to Se ct io n 1 0. “Pow er -S av -
ing Features” (DS60001130) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX
DS60001156J-page 332 2009-2016 Microchip Technology Inc.
The processo r will exit, or ‘w ake-up’, from Sleep mode
on one of the following events:
• On any interrupt from an enabled source that is
operating in Sleep mode. The interrupt priority
must be greater than the current CPU priority.
• On any form of device Reset
• On a WDT time-out
If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
PBCLK will start running and the device will enter into
Idle mode.
28.3.2 IDLE MODE
In Idle mode, the CPU is Halted but the System Clock
(SYSCLK) sourc e is sti ll enabl ed. Thi s allows periph er-
als to continue operation when the CPU is Halted.
Periphera ls can be i ndividua lly confi gured to Ha lt when
entering Idle by setting their respective SIDL bit.
Latency, when exiti ng Idle m ode , is v ery low d ue to the
CPU oscillator source remaining active.
The device enters Idle mode when the SLPEN bit
(OSCCON<4>) is clear and a WAIT instruction is
executed.
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt event for which the interrupt
source is ena ble d. The prio rity of the interru pt
event must be greater than the current priority of
the CPU. If the priority of the interrupt event is
lower than or equal to current priority of the CPU,
the CPU will remain Halted and the device will
remain in Idle mode.
• On any form of device Reset
• On a WDT time-out interrupt
28.3.3 PERIPHERAL BUS SCALING
METHOD
Most of the peripherals on the device are clocked using
the PBCLK. The Peripheral Bus (PB) can be scaled rel-
ative to the SYSCLK to minimize the dynamic power
consumed by the peripherals. The PBCLK divisor is con-
trolled by PBDIV<1:0> (OSCCON<20:19>), allowing
SYSCLK to PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All
peripherals using PBCLK ar e affected when the divisor
is changed. Peripherals such as USB, interrupt control-
ler, DMA, bus matrix and prefetch cache are clocked
directly from SYSCLK. As a result, they are not affected
by PBCLK divisor changes.
Changing the PBCLK divisor affects:
• The CPU to peripheral access latency. The CPU
has to wait for next PBCLK edge for a read to
complete. In 1:8 mode, this results in a latency of
one to seven SYSCLKs.
• The pow er consum ption of the peri pherals. Power
consumption is directly proportional to the fre-
quency at which the peripherals are clocked. The
greate r the divi sor , the lower the power consumed
by the per ipheral s.
To minimize dynamic power, the PB divisor should be
chosen to run the peripherals at the lowest frequency
that provides acceptable system performance. When
selecting a PBCLK divider, peripheral clock require-
ments, such as baud rate accuracy, should be taken
into account. For example, the UART peripheral may
not be able to achieve all baud rate values at some
PBCLK divider depending on the SYSCLK value.
Note 1: Changing the PBCLK divider ratio
requires recalculation of peripheral tim-
ing. For example, assume the UART is
configu r ed for 9600 bau d with a PB cl oc k
ratio of 1:1 and a P
OSC
of 8 MHz. When
the PB clock divisor of 1:2 is used, the
input fre que ncy to th e ba ud cl ock i s cut in
half; therefore, the baud rate is reduced
to 1/2 its former value. Due to numeric
truncation in calculations (such as the
baud rate divisor), the actual baud rate
may be a tiny percentage different than
expected. For this reason, any timing cal-
culation required for a peripheral should
be performed with the new PB clock fre-
quency instead of scaling the previous
value based on a change in the PB divisor
ratio.
2: Oscillator start-up and PLL lock delays
are applied when switching to a clock
source that was disabled and that uses a
crystal and/or the PLL. For example,
assume the clock source is switched from
P
OSC
to LPRC just prior to entering Sleep
in or der to s ave pow er . No osci llator start-
up delay would be applied when exiting
Idle. However, when switching back to
P
OSC
, the appropriate PLL and/or
oscillator start-up/lock delays would be
applied.
2009-2016 Microchip Technology Inc. DS60001156J- page 333
PIC32MX5XX/6XX/7XX
29.0 SPECIAL FEATURES
The PIC32MX5XX/6XX/7XX family of devices include
several features intended to maximize application
flexibility and reliability and minimize cost through
elimination of external components. Key features
include:
• Flexible device configuration
• Watchdog Timer (WDT)
• Joint Test Action Group (JTAG) interface
• In-Circuit Serial Programming™ (ICSP™)
29.1 Configuration Bits
The Configuration bits can be programmed using the
following registers to select various device
configurations.
•DEVCFG0: Device Configuration Word 0
•DEVCFG1: Device Configuration Word 1
•DEVCFG2: Device Configuration Word 2
•DEVCFG3: Device Configuration Word 3
•DEVID: Device and Revision ID Register
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Sect ion 33. “Pr ogramming
and Diagnostics” (DS60001129) in the
“PIC32 Family Reference Manual”, which
are available from the Microchip web site
(www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX
DS60001156J-page 334 2009-2016 Microchip Technology Inc.
TABLE 29-1: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
Virtual Address
(BFC0_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
2FF0 DEVCFG3 31:16 FVBUSONIO FUSBIDIO — — — FCANIO FETHIO FMIIEN — — — — — FSRSSEL<2:0> xxxx
15:0 USERID<15:0> xxxx
2FF4 DEVCFG2 31:16 — — — — — — — — — — — — — FPLLODIV<2:0> xxxx
15:0
UPLLEN
— — — — UPLLIDIV<2:0> — FPLLMUL<2:0> — FPLLIDIV<2:0> xxxx
2FF8 DEVCFG1 31:16 — — — — — — — —FWDTEN—— WDTPS<4:0> xxxx
15:0 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0> IESO — FSOSCEN —— FNOSC<2:0> xxxx
2FFC DEVCFG0 31:16 — — —CP———BWP————PWP<7:4>xxxx
15:0 PWP<3:0> — — — — — — — — ICESEL — DEBUG<1:0> xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 29-2: DEVICE ID, REVISION, AND CONFIGURATION SUMMARY
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
F200 DDPCON 31:16 ————————————————0000
15:0 ————————————JTAGENTROEN—TDOEN0008
F220 DEVID 31:16 VER<3:0> DEVID<27:16> xxxx
15:0 DEVID<15:0> xxxx
F230 SYSKEY 31:16 SYSKEY<31:0> 0000
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset values are dependent on the device variant. Refer to “PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification” (DS80000480) for more information.
2009-2016 Microchip Technology Inc. DS60001156J- page 335
PIC32MX5XX/6XX/7XX
REGISTER 29-1: DEVCFG0: DEVICE CONFIGURATION WORD 0
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P
— — —CP— — —BWP
23:16
r-1 r-1 r-1 r-1 R/P R/P R/P R/P
— — — —PWP<7:4>
15:8
R/P R/P R/P R/P r-1 r-1 r-1 r-1
PWP<3:0> — — — —
7:0
r-1 r-1 r-1 r-1 R/P r-1 R/P R/P
— — — — ICESEL — DEBUG<1:0>
Legend: r = Reserved bit P = Programmable bi t
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: Write ‘0’
bit 30-29 Reserved: Write ‘1’
bit 28 CP: Code-Protect bit
Prevents boot and program Flash memo ry from being rea d or modified by an ext ernal program ming devi ce.
1 = Protection is disabled
0 = Protection is enabled
bit 27-25 Reserved: Write ‘1’
bit 24 BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1 = Boot Flash is writable
0 = Boot Flash is not writable
bit 23-20 Reserved: Write ‘1’
bit 19-12 PWP<7:0>: Program Flash Write-Protect bits
Prevents sel ected program Flash memory pa ges fro m bei ng mod ified during code execut ion. T he PWP b its
represent the 1’s complement of the number of write-protected program Flash memory pages.
11111111 = Disabled
11111110 = 0xBD00_0FFF
11111101 = 0xBD00_1FFF
11111100 = 0xBD00_2FFF
11111011 = 0xBD00_3FFF
11111010 = 0xBD00_4FFF
11111001 = 0xBD00_5FFF
11111000 = 0xBD00_6FFF
11110111 = 0xBD00_7FFF
11110110 = 0xBD00_8FFF
11110101 = 0xBD00_9FFF
11110100 = 0xBD00_AFFF
11110011 = 0xBD00_BFFF
11110010 = 0xBD00_CFFF
11110001 = 0xBD00_DFFF
11110000 = 0xBD00_EFFF
11101111 = 0xBD00_FFFF
•
•
•
01111111 = 0xBD07_FFFF
bit 11- 4 Reserved: Write ‘1’
PIC32MX5XX/6XX/7XX
DS60001156J-page 336 2009-2016 Microchip Technology Inc.
bit 3 ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit
1 = PGEC 2/PGED2 pair is used
0 = PGEC 1/PGED1 pair is used
bit 2 Reserved: Write ‘1’
bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = Debugger is disabled
10 = Debugger is enabled
01 = Reserved (same as ‘11’ setting)
00 = Reserv ed (same as ‘11’ setting)
REGISTER 29-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
2009-2016 Microchip Technology Inc. DS60001156J- page 337
PIC32MX5XX/6XX/7XX
REGISTER 29-2: DEVCFG1: DEVICE CONFIGURATION WORD 1
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
23:16
R/P r-1 r-1 R/P R/P R/P R/P R/P
FWDTEN —— WDTPS<4:0>
15:8
R/P R/P R/P R/P r-1 R/P R/P R/P
FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0>
7:0
R/P r-1 R/P r-1 r-1 R/P R/P R/P
IESO — FSOSCEN ——FNOSC<2:0>
Legend: r = Reserved bit P = Programmable bi t
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Reserved: Write ‘1’
bit 23 FWDTEN: Watchdog Timer Enable bit
1 = The WDT is enabled and cannot be disabled by software
0 = The WDT is not enabled; it can be enabled in software
bit 22-21 Reserved: Write ‘1’
bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100
bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Note 1: Do not disable the P
OSC
(POSCMOD = 11) when using this oscillator source.
PIC32MX5XX/6XX/7XX
DS60001156J-page 338 2009-2016 Microchip Technology Inc.
bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits
11 = PBCLK is SYSCLK divided by 8
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
bit 11 Reserved: Write ‘1’
bit 10 OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output is disabled
0 = CLKO output signal is active on the OSCO pin; the Primary Oscillator must be disabled or configured
for External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00)
bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits
11 = Primary Oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = External Clock mode is selected
bit 7 IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6 Reserved: Write ‘1’
bit 5 FSOSCEN: Secondary Oscillator Enable bit
1 = Enable the Secondary Oscillator
0 = Disable the Secon dary Oscillator
bit 4-3 Reserved: Write ‘1’
bit 2-0 FNOSC<2:0>: Oscillator Selection bits
111 = Fast RC Oscillator with divide-by-N (FRCDIV)
110 = FRCDIV16 Fast RC Osci llator with fixed divide-by-16 postscaler
101 = Low-Power RC Oscillator (LPRC)
100 = Seconda r y Oscillator (S
OSC
)
011 = Primary Os cillator (P
OSC
) with PLL module (XT+PLL, HS+PLL, EC+PLL)
010 = Primary Os cillator (XT, HS, EC)
(1)
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
000 = Fast RC Oscillator (FRC)
REGISTER 29-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
Note 1: Do not disable the P
OSC
(POSCMOD = 11) when using this oscillator source.
2009-2016 Microchip Technology Inc. DS60001156J- page 339
PIC32MX5XX/6XX/7XX
REGISTER 29-3: DEVCFG2: DEVICE CONFIGURATION WORD 2
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
— — — — — — — —
23:16
r-1 r-1 r-1 r-1 r-1 R/P R/P R/P
— — — — — FPLLODIV<2:0>
15:8
R/P r-1 r-1 r-1 r-1 R/P R/P R/P
UPLLEN — — — — UPLLIDIV<2:0>
7:0
r-1 R/P-1 R/P R/P-1 r-1 R/P R/P R/P
—FPLLMUL<2:0>— FPLLIDIV<2:0>
Legend: r = Reserved bit P = Programmable bi t
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-19 Reserved: Write ‘1’
bit 18-16 FPLLODIV<2:0>: PLL Output Divider bits
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
bit 15 UPLLEN: USB PLL Enable bit
1 = Disabl e and bypass U SB PLL
0 = Enable USB PLL
bit 14-11 Reserved: Write ‘1’
bit 10-8 UPLLIDIV<2:0>: USB PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
bit 7 Reserved: Write ‘1’
bit 6-4 FPLLMUL<2:0>: PLL Multiplier bit s
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier
bit 3 Reserved: Write ‘1’
PIC32MX5XX/6XX/7XX
DS60001156J-page 340 2009-2016 Microchip Technology Inc.
bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
REGISTER 29-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)
2009-2016 Microchip Technology Inc. DS60001156J- page 341
PIC32MX5XX/6XX/7XX
REGISTER 29-4: DEVCFG3: DEVICE CONFIGURATION WORD 3
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
R/P R/P r-1 r-1 r-1 R/P R/P R/P
FVBUSONIO FUSBIDIO — — — FCANIO
(1)
FETHIO
(2)
FMIIEN
(2)
23:16
r-1 r-1 r-1 r-1 r-1 R/P R/P R/P
— — — — — FSRSSEL<2:0>
15:8
R/P R/P R/P R/P R/P R/P R/P R/P
USERID<15:8>
7:0
R/P R/P R/P R/P R/P R/P R/P R/P
USERID<7:0>
Legend: r = Reserved bit P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FVBUSONIO: USB V
BUSON
Selection bit
1 = VB
USON
pin is controlled by the USB module
0 = VB
USON
pin is controlled by the port function
bit 30 FUSBIDIO: USB USBID Selection bit
1 = USBID pin is controlled by the USB module
0 = USBID pin is controlled by the port function
bit 29-27 Reserved: Write ‘1’
bit 26 FCANIO: CAN I/O Pin Selection bit
(1)
1 = Default CAN I/O Pins
0 = Alternate CAN I/O Pins
bit 25 FETHIO: Ethernet I/O Pin Selection bit
(2)
1 = Default Ethernet I/O Pins
0 = Alternate Ethernet I/O Pins
bit 24 FMIIEN: Ethernet MI I Ena ble bit
(2)
1 = MII is enabled
0 = RMII is enabled
bit 23-19 Reserved: Write ‘1’
bit 18-16 FSRSSEL<2:0>: SRS Select bits
111 = Assign Interrupt Priority 7 to a shadow register set
110 = Assign Interrupt Priority 6 to a shadow register set
•
•
•
001 = Assign Interrupt Priority 1 to a shadow register set
000 = All interrupt priorities are assigned to a shadow register set
bit 15-0 USERID<15:0>: User ID bits
This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG.
Note 1: This bit is Reserved and reads ‘1’ on PIC32MX664/675/695 devices.
2: This bit is Reserved and reads ‘1’ on PIC32MX534/564/575 devices.
PIC32MX5XX/6XX/7XX
DS60001156J-page 342 2009-2016 Microchip Technology Inc.
REGISTER 29-5: DEVID: DEVICE AND REVISION ID REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
RRRRRRRR
VER<3:0>
(1)
DEVID<27:24>
(1)
23:16
RRRRRRRR
DEVID<23:16>
(1)
15:8
RRRRRRRR
DEVID<15:8>
(1)
7:0
RRRRRRRR
DEVID<7:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-28 VER<3:0>: Revision Identifier bits
(1)
bit 27-0 DEVID<27:0>: Device ID bits
(1)
Note 1: See the “PIC32 Flash Programming Specification” (DS60001145) for a list of Revision an d Device ID v alues.
REGISTER 29-6: DDPCON: DEBUG DATA PORT CONTROL REGISTER
Bit
Range Bit
31/23/15/7 Bit
30/22/14/6 Bit
29/21/13/5 Bit
28/20/12/4 Bit
27/19/11/3 Bit
26/18/10/2 Bit
25/17/9/1 Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
7:0
U-0 U-0 U-0 U-0 R/W-1 R/W-0 U-0 R/W-0
————JTAGENTROEN—TDOEN
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3 JTAGEN: JTAG Port Enable bit
1 = Enable the JTAG port
0 = Disable the JTAG port
bit 2 TROEN: Trace Output Enable bit
1 = Enable the trace port
0 = Disable the trace port
bit 1 Unimplemented: Read as ‘0’
bit 0 TDOEN: TDO Enable for 2-Wire JTAG
1 = 2-wire JTAG protocol uses TDO
0 = 2-wire JTAG protocol does not use TDO
2009-2016 Microchip Technology Inc. DS60001156J- page 343
PIC32MX5XX/6XX/7XX
29.2 On-Chip Voltage Regulator
All PIC32MX5XX/6XX/7XX devices’ core and digital
logic are designed to operate at a nominal 1.8V. To
simplify system designs, most de vices in the PIC32MX-
5XX/6XX/7XX family incorporate an on-chip regulator
providi ng the required core logic volt a ge from V
DD
.
A low-ESR capacitor (such as tantalum) must be
connected to the V
CAP
pin (see Figure 29-1). This
helps to maintain the stability of the regulator. The
recommended value for the filter capacitor is provided
in S ec tion 32. 1 “DC Char ac ter is tics” .
29.2.1 ON-CHIP REGULATOR AND POR
It t akes a fi xed dela y for the o n-chip re gulator to generate
an output. During this time, designated as T
PU
, code
execution is disabled. T
PU
is applied every time the
device resumes operation after any power-down,
inclu di ng Sl eep mode.
29.2.2 ON-CHIP REGULATOR AND BOR
PIC32MX5XX/6XX/7XX devices also have a simple
brown-out capability. If the voltage supplied to the
regulator is inadequate to maintain a regulated level,
the regulator Reset circuitry will generate a Brown-out
Reset (BOR). This event is captured by the BOR flag
bit (RCON<1>). The brown-out voltage levels are
specified in Section 32.1 “DC Characteristics”.
FIGURE 29-1: CONNECTIONS FOR THE
ON-CHIP REGULATOR
29.3 Programming and Diagnostics
PIC32MX5XX/6XX/7XX devices provide a complete
range of pro gramming and diagn ostic f eatures tha t can
increase the flexibility of any application using them.
These features allow system designers to include:
• Simplified field programmability using two-wire
In-Circuit Serial Programming™ (ICSP™)
interfaces
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
• JTAG boun dary sc an tes ting for d evice and boa rd
diagnostics
PIC32 de vices inco rporate two pro gramming and dia g-
nostic modules, and a trace controller, that provide a
range of functions to the application developer.
FIGURE 29-2: PROGRAMMING,
DEBUGGING, AND TRACE
PORTS BLOCK DIAGRAM
Note: It is important that the low-ESR capacitor
is plac ed as c lose as pos sible to the V
CAP
pin.
V
DD
V
CAP
V
SS
PIC32
C
EFC(2)
3.3V
(1)
Note 1: These are typical operating voltages. Refer to
Section 32.1 “D C Characte ristics”
for the full
operating ranges of V
DD
.
2:
It is important that the low-ESR capacitor is
placed as close as possible to the V
CAP
pin.
(10 F typical)
TDI
TDO
TCK
TMS
JTAG
Controller
ICSP™
Controller
Core
JTAGEN DEBUG<1:0>
Instruction Trace
Controller
DEBUG<1:0>
ICESEL
PGEC1
PGED1
PGEC2
PGED2
TRCLK
TRD0
TRD1
TRD2
TRD3
Note 1:
Trace is not avai lable on 64-pin devices.
(see
Note 1
)
PIC32MX5XX/6XX/7XX
DS60001156J-page 344 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 345
PIC32MX5XX/6XX/7XX
30.0 INSTRUCTION SET
The PIC32MX5XX/6XX/7XX family instruction set
complies with the MIPS32 Release 2 instruction set
arch itecture. The PIC32 dev ice family does not supp ort
the following features:
• Core Extend instructions
• Coproce ssor 1 instructi ons
• Coproce ssor 2 instructi ons
Note: Refer to “MIPS32
®
Architecture for
Programmers Volume II: The MIPS32
®
Instruction Set” at www.imgtec.com for
more information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 346 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 347
PIC32MX5XX/6XX/7XX
31.0 DEVELOPMENT SUPPORT
The PIC
®
microcontrollers (MCU) and dsPIC
®
digital
signal controllers (DSC) are supported wi th a full range
of software and hardware development tools:
• Integrated Development Envi ronment
- MPLAB
®
X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASM
TM
Assembler
-MPLINK
TM
Object Linker/
MPLIB
TM
Object Librarian
- MPLAB Assembler/Linker/L ibra rian for
Various Devi ce Families
• Simulators
- MPLAB X SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation K its and Starte r Kits
• Third-party development tools
31.1 MPLAB X Integrated Devel opment
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows
®
,
Linux and Mac OS
®
X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With com plete projec t managem ent, visual cal l graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multipl e project s with simu ltane ous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Ri ch Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as yo u type
• Automati c c od e f orm atti ng bas ed on us er-d efi ned
rules
• L ive parsing
User-Friendly, Custom izabl e Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• L ocal file hist ory feat ure
• Built-in support for Bugzilla issue tracker
PIC32MX5XX/6XX/7XX
DS60001156J-page 348 2009-2016 Microchip Technology Inc.
31.2 MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Co mpilers i nclude an asse mbler , li nker and
utilities. The assembler generates relocatable object
files that can then b e arc hiv ed o r l in ked wi th other relo-
catable object files and archives to create an execut-
able file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assem-
bler inclu de:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
31.3 MPAS M Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker, Intel
®
stan dard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directi ves that allow complete control over the
assembly process
31.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB O bject Li brarian manage s the cre ation an d
modification of library files of precompiled code. When
a routine from a l ibra ry is c al led fro m a source file, o nl y
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
31.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or li nk ed with other relocat ab le object
files and archives to create an executable file. Notable
features of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB X IDE compatibility
2009-2016 Microchip Technology Inc. DS60001156J- page 349
PIC32MX5XX/6XX/7XX
31.6 MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most periph erals and int ernal registe rs.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
developm ent tool .
31.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB R EAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cable s.
31.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 int erface and is connected to t he target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
31.9 PICkit 3 In-Circuit De bugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most
af fordable pr ice point us ing the powerfu l graphica l user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the tar-
get via a Microchip debug (RJ-11) connector (compati-
ble with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
31.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at V
DDMIN
and V
DDMAX
for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer ca n read, verif y and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MP LAB PM3 h as high-spe ed co mmunicat ions and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
PIC32MX5XX/6XX/7XX
DS60001156J-page 350 2009-2016 Microchip Technology Inc.
31.11 Demonstration/Development
Boards, Evaluation Ki ts, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
use d in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a l ine of evaluation k its an d demonstra-
tion software for analog fil ter desi gn, K
EE
L
OQ
®
security
ICs, CAN, IrDA
®
, PowerSmart battery management,
SEEVAL
®
evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience t he specified d evice. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
31.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace S ystems
• Protoc ol Anal yz er s from com p a nies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent
®
and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika
®
2009-2016 Microchip Technology Inc. DS60001156J- page 351
PIC32MX5XX/6XX/7XX
32.0 ELECTRIC AL CHARACTERISTICS
This sec tion provides an ov erview of the PIC32MX5XX/6 XX/7XX electric al characteris tics. Additional informa tion will be
provided in future revisions of this document as it becomes available.
Absolute m aximum ra tings fo r the PIC32 MX5XX/6XX/ 7XX devic es a re listed below. Exposure to th ese maxim um ratin g
conditions for extended periods may affect device reliability. Functional operation of the device at these or any other
conditions, above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings
(See Note 1)
Ambient temperature under bias.............................................................................................................-40°C to +105°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on V
DD
with respect to V
SS
......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to V
SS
(Note 3).........................................-0.3V to (V
DD
+ 0.3V)
Voltage on any 5V tolerant pin with respect to V
SS
when V
DD
2.3V (Note 3)........................................ -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to V
SS
when V
DD
< 2.3V (Note 3)........................................ -0.3V to +3.6V
Voltage on V
BUS
with respect to V
SS
....................................................................................................... -0.3V to +5.5V
Maximum curr ent o ut of V
SS
pin(s).......................................................................................................................300 mA
Maximum curr ent i nto V
DD
pin(s) (Note 2)............................................................................................................300 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA
Note 1: Stresses abo ve those lis ted under “Abs olute Ma xim um Ra tings ” m ay c ause permanent damage to the
device . This is a st ress rati ng only an d functi onal ope ration of the devic e at those or any other con dition s,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 32-2).
3: See the “Device Pin Tables” section for the 5V tolerant pins.
PIC32MX5XX/6XX/7XX
DS60001156J-page 352 2009-2016 Microchip Technology Inc.
32.1 DC Characteristics
TABLE 32-1: OPERATING MIPS VS. VOLTAGE
Characteristic V
DD
Range
(in Volts)
(1)
Temp. Range
(in °C)
Max. Frequency
PIC32MX5XX/6XX/7XX
DC5 2.3-3.6V -40°C to +85°C 80 MHz
DC5b 2.3-3.6V -40°C to +105°C 80 MHz
Note 1: Overal l funct ional d evic e opera tion at V
BORMIN
< V
DD
< V
DDMIN
is tested, but not cha racteri zed. Al l devi ce
Analog mo dul es , su ch as ADC, etc., will function, but with degrade d perf orm anc e be low V
DDMIN
. Refer to
parameter BO10 in Table 32-10 for BOR values.
TABLE 32-2: THERMAL OPERATING CONDITIONS
Rating Symbol Min. Typical Max. Unit
Industrial Temperature Devices
Operating Junction Temperature Range T
J
-40 — +125 °C
Operating Ambient Temperature Range T
A
-40 — +85 °C
V-Tem p Temperature Dev ices
Operating Junction Temperature Range T
J
-40 — +140 °C
Operating Ambient Temperature Range T
A
-40 — +105 °C
Power Dissipation:
Internal Chip Power Dissipation:
P
INT
= V
DD
x (I
DD
– S I
OH
) P
D
P
INT
+ P
I
/
O
W
I/O Pin Power Dissipation:
I/O = S (({V
DD
– V
OH
} x I
OH
) + S (V
OL
x I
OL
))
Maximum Allo wed Power Dissipation P
DMAX
(T
J
– T
A
)/
JA
W
TABLE 32-3: THERMAL PACKAGING CHARACTERISTICS
Characteristics Symbol Typical Max. Unit See
Note
Package Thermal Resistance, 121-Pin TFBGA (10x10x1.1 mm)
JA
40 — °C/W 1
Package Thermal Res istance, 100-Pin TQFP (14x14x1 mm)
JA
43 — °C/W 1
Package Thermal Res istance, 100-Pin TQFP (12x12x1 mm)
JA
43 — °C/W 1
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm)
JA
47 — °C/W 1
Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm)
JA
28 — °C/W 1
Package Thermal Resistance, 124-Pin VTLA (9x9x0.9 mm)
JA
21 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-
JA
(
JA
) numbers are achieved by package simulations.
2009-2016 Microchip Technology Inc. DS60001156J- page 353
PIC32MX5XX/6XX/7XX
TABLE 32-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C fo r V-Temp
Param.
No. Symbol Characteristics Min. Typical Max. Units Conditions
Operating Voltage
DC10 V
DD
Supply Voltage 2.3 — 3.6 V —
DC12 V
DR
RAM Data Retention Voltage
(1)
1.75 — — V —
DC16 V
POR
V
DD
Start Voltag e to Ensure
Internal Power-on Reset Signal 1.75 — 2.1 V —
DC17 S
VDD
V
DD
Rise Rate to Ensure
Internal Power-on Reset Signal 0.00005 — 0.115 V/s—
Note 1: This is the limit to which V
DD
can be lowered without losing RAM data.
2: Overal l functi onal dev ice op eration at V
BORMIN
< V
DD
< V
DDMIN
is tested, bu t not chara cterized . All devic e
Analog modules, such as ADC, etc., will function, but with degraded performance below V
DDMIN
. Refer to
parameter BO10 in Table 32-10 for BOR values.
PIC32MX5XX/6XX/7XX
DS60001156J-page 354 2009-2016 Microchip Technology Inc.
TABLE 32-5: DC CHARACTERISTICS: OPERATING CURRENT (I
DD
)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C fo r V-Temp
Param.
No. Typical
(3)
Max. Units Conditions
Operating Current (I
DD
)
(1,2,4)
for PIC32M X575/675/695/775/795 Family Devices
DC20 6 9 mA Code executing from Flash
-40ºC,
+25ºC,
+85ºC —4 MHz
DC20b 7 10 +105ºC
DC20a 4 — Code executing from SRAM —
DC21 37 40 mA Code executing from Flash —— 25 MHz
DC21a 25 — Code executing from SRAM
DC22 64 70 mA Code executing from Flash —— 60 MHz
DC22a 61 — Code executing from SRAM
DC23 85 98 mA Code executing from Flash
-40ºC,
+25ºC,
+85ºC —80 MHz
DC23b 90 120 +105ºC
DC23a 85 — Code executing from SRAM —
DC25a 125 150 µA — +25°C 3.3V LPRC (31 kHz)
Note 1: A device’s I
DD
supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as we ll as temperature, can have an impact on the current consumption.
2: The test conditions for I
DD
measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail , (OSC1 input clock input over/undershoot < 100 mV required)
• OS C2/ CLKO is config ured as an I/O input pin
• USB PLL osci llator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait
states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
SS
•MCLR = V
DD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
4: All parameters are characterized, but only those paramete rs listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.
2009-2016 Microchip Technology Inc. DS60001156J- page 355
PIC32MX5XX/6XX/7XX
Operating Current (I
DD
)
(1,2)
for PIC32MX534/564/664/764 Family Devices
DC20c 6 9 mA Code ex ecu tin g from Fla sh
-40ºC,
+25ºC,
+85ºC —4 MHz
DC20d 7 10 +105ºC
DC20e 2 — Code executing from SRAM —
DC21b 19 32 mA Code executing from Flash —— 25 MHz
(Note 4)
DC21c 14 — Code executing from SRAM
DC22b 31 50 mA Code executing from Flash —— 60 MHz
(Note 4)
DC22c 29 — Code executing from SRAM
DC23c 39 65 mA Code ex ecu tin g from Fla sh
-40ºC,
+25ºC,
+85ºC —80 MHz
DC23d 49 70 +105ºC
DC23e 39 — Code executing from SRAM —
DC25b 100 150 µA — +25°C 3.3V LPRC (31 kHz)
(Note 4)
TABLE 32-5: DC CHARACTERISTICS: OPERATING CURRENT (I
DD
) (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C fo r V-Temp
Param.
No. Typical
(3)
Max. Units Conditions
Note 1: A device’s I
DD
supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as we ll as temperature, can have an impact on the current consumption.
2: The test conditions for I
DD
measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail , (OSC1 input clock input over/undershoot < 100 mV required)
• OS C2/ CLKO is config ured as an I/O input pin
• USB PLL osci llator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait
states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
SS
•MCLR = V
DD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
4: All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.
PIC32MX5XX/6XX/7XX
DS60001156J-page 356 2009-2016 Microchip Technology Inc.
TABLE 32-6: DC CHARACTERISTICS: IDLE CURRENT (I
IDLE
)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Parameter
No. Typical
(2)
Max. Units Conditions
Idle Current (I
IDLE
)
(1,3)
for PIC32MX575/675/695/775/795 Family Devices
DC30 4.5 6.5 mA -40ºC, +25ºC, +85ºC —4 MHz
DC30b 5 7 +105°C
DC31 13 15 mA -40ºC, +25ºC, +85ºC — 25 MHz
DC32 28 30 mA -40ºC, +25ºC, +85ºC — 60 MHz
DC33 36 42 mA -40ºC, +25ºC, +85ºC —80 MHz
DC33b 39 45 mA +105°C
DC34
—
40
µA
-40°C
2.3V
LPRC (31 kHz)
DC34a 75 +25°C
DC34b 800 +85°C
DC34c 1000 +105°C
DC35 35
—µA
-40°C
3.3V
DC35a 65 +25°C
DC35b 600 +85°C
DC35c 800 +105°C
DC36
—
43
µA
-40°C
3.6V
DC36a 106 +25°C
DC36b 800 +85°C
DC36c 1000 +105°C
Note 1: The test conditions for I
IDLE
current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail , (OSC1 input clock input over/undershoot < 100 mV required)
• OS C2/ CLKO is config ured as an I/O input pin
• USB PLL osci llator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode, program Flash memory W ait states = 111, Program Cach e and P refet ch are dis-
abl ed and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
SS
•MCLR = V
DD
• RTCC and JTAG are disabled
2: Dat a in “Typical” col umn is a t 3.3V, 25°C unless otherwi se st ated. Param eters are f or design guidance only
and are not tested.
3: This parameter is characterized, but not tested in manufacturing.
4: All parameters are characterized, but only those paramete rs listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.
2009-2016 Microchip Technology Inc. DS60001156J- page 357
PIC32MX5XX/6XX/7XX
Idle Current (I
IDLE
)
(1)
for PIC32MX534/564/664/764 Family Devices
DC30a 1.5 5 mA -40ºC, +25ºC, +85ºC —4 MHz
DC30c 3.5 6 +105ºC
DC31a 7 11 -40ºC, +25ºC, +85ºC — 25 MHz (Note 3)
DC32a 13 20 mA -40ºC, +25ºC, +85ºC — 60 MHz (Note 3)
DC33a 17 25 mA -40ºC, +25ºC, +85ºC —80 MHz
DC33c 20 27 +105ºC
DC34c
—
40
µA
-40°C
2.3V
LPRC (31 kHz)
(Note 3)
DC34d 75 +25°C
DC34e 800 +85°C
DC34f 1000 +105ºC
DC35c 30
—µA
-40°C
3.3V
DC35d 55 +25°C
DC35e 230 +85°C
DC35f 800 +105ºC
DC36c
—
43
µA
-40°C
3.6V
DC36d 106 +25°C
DC36e 800 +85°C
DC36f 1000 +105ºC
TABLE 32-6: DC CHARACTERISTICS: IDLE CURRENT (I
IDLE
) (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Parameter
No. Typical
(2)
Max. Units Conditions
Note 1: The test conditions for I
IDLE
current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail , (OSC1 input clock input over/undershoot < 100 mV required)
• OS C2/ CLKO is config ured as an I/O input pin
• USB PLL osci llator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode, program Flash memory W ait states = 111, Program Cach e and P refet ch are dis-
abl ed and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
SS
•MCLR = V
DD
• RTCC and JTAG are disabled
2: Dat a in “Typical” col umn is a t 3.3V, 25°C unless otherwi se st ated. Param eters are f or design guidance only
and are not tested.
3: This parameter is characterized, but not tested in manufacturing.
4: All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.
PIC32MX5XX/6XX/7XX
DS60001156J-page 358 2009-2016 Microchip Technology Inc.
TABLE 32-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I
PD
)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwis e stated)
Operating t emperature -40°C T
A
+85°C for Indu stri al
-40°C T
A
+105°C for V-Temp
Param.
No. Typical
(2)
Max. Units Conditions
Power-Down Current (I
PD
)
(1)
for PIC32MX575/675/695/775/795 Family Devices
DC40 10 40
A
-40°C
2.3V Base Power-Down Current (Note 6)
DC40a 36 100 +25°C
DC40b 400 720 +85°C
DC40h 900 1800 +105°C
DC4 0c 41 12 0 +25°C 3.3V Base Power-D own Curr ent
DC40d 22 80 -40°C
3.6V Base Power-Down Current (Note 6)
DC40e 42 120 +25°C
DC40g 315 400
(5)
+70°C
DC40f 410 800 +85°C
DC40i 1000 2000 +105°C
Module Differential Current for PIC32MX575/675/695/775/795 Family Devices
DC41 — 10
A—
2.3V Watchdog Timer Current: I
WDT
(No tes 3,6)
DC41a 5 — 3.3V Watchdog Timer Current: I
WDT
(Note 3)
DC41b — 20 3.6V Watchdog Timer Current: I
WDT
(No te 3,6)
DC42 — 40
A—
2.3V RTCC + Timer1 w/32 kHz Crystal: I
RTCC
(Notes 3,6)
DC42a 23 — 3.3V RTCC + Timer1 w/32 kHz Crystal: I
RTCC
(Note 3)
DC42b — 50 3.6V RTCC + Timer1 w/32 kHz Crystal: I
RTCC
(No te 3,6)
DC43 — 1300
A—
2.5V ADC: I
ADC
(Notes 3,4, 6)
DC43a 1100 — 3.3V ADC: I
ADC
(Notes 3,4)
DC43b — 1300 3.6V ADC: I
ADC
(Notes 3,4, 6)
Note 1: The test conditions for I
PD
current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail , (OSC1 input clock input over/undershoot < 100 mV required)
• OS C2/ CLKO is config ured as an I/O input pin
• USB PLL osci llator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cach e and Prefe tch are
disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
SS
•MCLR = V
DD
• RTCC and JTAG are disabled
2: Dat a in the “Typical” colum n is at 3.3 V, 25°C unless otherwi se st ated. Paramete rs are for des ign gu idanc e
only and are not tested.
3: The current is the additional current consumed when the module is enabled. This current should be
added to the base I
PD
current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.
6: This parameter is characterized, but not tested in manufacturing.
2009-2016 Microchip Technology Inc. DS60001156J- page 359
PIC32MX5XX/6XX/7XX
Power-Down Current (I
PD
)
(1)
for PIC32MX534/564/664/764 Family Devices
DC40g 12 40
A
-40°C
2.3V Base Power-Down Current (Note 6)
DC40h 20 120 +25°C
DC40i 210 600 +85°C
DC40o 400 1000 +105°C
DC4 0j 20 120 +25°C 3.3V Base Pow er-Dow n Current
DC40k 15 80 -40°C
3.6V Base Power-Down Current
DC40l 20 120 +25°C
DC40m 113 350
(5)
+70°C
DC40n 220 650 +85°C
DC40p 500 1000 +105°C
Module Differential Current for PIC32MX534/564/664/764 Family Devices
DC41c — 10
A—
2.5V Watchdog Timer Current: I
WDT
(No tes 3,6)
DC41d 5 — 3.3V Watchdog Timer Current: I
WDT
(Note 3)
DC41e — 20 3.6V Watchdog Timer Current: I
WDT
(Note 3)
DC42c — 40
A—
2.5V RTCC + Ti mer1 w/32 kHz Crystal: I
RTCC
(Notes 3,6)
DC42d 23 — 3.3V RTCC + Timer1 w/32 kHz Crystal: I
RTCC
(Note 3)
DC42e — 50 3.6V RTCC + Timer1 w/32 kHz Crystal: I
RTCC
(Note 3)
DC43c — 1300
A—
2.5V ADC: I
ADC
(Notes 3,4, 6)
DC43d 1100 — 3.3V ADC: I
ADC
(Notes 3,4)
DC43e — 1300 3.6V ADC: I
ADC
(Notes 3,4)
TABLE 32-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I
PD
) (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwis e stated)
Ope rating temper ature -40°C T
A
+85°C for Indu stri al
-40°C T
A
+105°C for V-Temp
Param.
No. Typical
(2)
Max. Units Conditions
Note 1: The test conditions for I
PD
current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail , (OSC1 input clock input over/undershoot < 100 mV required)
• OS C2/ CLKO is config ured as an I/O input pin
• USB PLL osci llator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cach e and Prefe tch are
disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to V
SS
•MCLR = V
DD
• RTCC and JTAG are disabled
2: Dat a in the “Typical” colum n is at 3.3 V, 25°C unless otherwi se st ated. Paramete rs are for des ign gu idanc e
only and are not tested.
3: The current is the additional current consumed when the module is enabled. This current should be
added to the base I
PD
current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.
6: This parameter is characterized, but not tested in manufacturing.
PIC32MX5XX/6XX/7XX
DS60001156J-page 360 2009-2016 Microchip Technology Inc.
TABLE 32-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics Min. Typical
(1)
Max. Units Conditions
V
IL
Input Low Voltage
DI10 I/O Pins:
with TTL Buffer V
SS
—0.15V
DD
V
with Schmitt Trigger Buffer V
SS
—0.2V
DD
V
DI15 MCLR
(2)
V
SS
—0.2V
DD
V
DI16 OSC1 (XT mode) V
SS
—0.2V
DD
V(Note 4)
DI17 OSC1 (HS mode) V
SS
—0.2V
DD
V(Note 4)
DI18 SDAx, SCLx V
SS
—0.3V
DD
V SMBus disabled
(Note 4)
DI19 SDAx, SCLx V
SS
— 0.8 V SMBus enable d
(Note 4)
V
IH
Input High Voltage
DI20 I/O Pins not 5V-tolerant
(5)
0.65 V
DD
—V
DD
V(No te 4,6)
I/O Pins 5V-tolerant with
PMP
(5)
0.25 V
DD
+ 0.8V — 5 .5 V (No te 4,6)
I/O Pins 5V-tolerant
(5)
0.65 V
DD
—5.5V
DI28 SDAx, SCLx 0.65 V
DD
— 5.5 V SMBus disab led
(No te 4,6)
DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled,
2.3V V
PIN
5.5
(No te 4,6)
DI30 I
CNPU
Change Notification
Pull-up Current ——-50AV
DD
= 3.3V, V
PIN
= V
SS
(No te 3,6)
DI31 I
CNPD
Change Notification
Pull-down Current
(4)
—50—µAV
DD
= 3.3V, V
PIN
= V
DD
Note 1: Data in “T yp ic al” colum n is at 3. 3V, 25°C unless oth erw is e s t ate d. Pa ram ete rs are for de si gn guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Device Pin Tables” section for the 5V-tolerant pins.
6: The V
IH
specification is only in relation to externally applied inputs and not with respect to the user-select-
able pull-ups. Exte rnal ly ap pl ied hi gh impedance or op en drai n input signa ls ut ili zi ng the PIC32 internal pull-
ups are guaranteed to be recognized as a logic “high” internally to the PIC32 device, provided that the
external load does not exceed the maximum value of I
CNPU
.
7: V
IL
source < (V
SS
- 0.3). Characterized but not tested .
8: V
IH
source > (V
DD
+ 0.3) for non-5V tolerant pins only.
9: Digital 5V tolerant pins do not have an internal hi gh side diode to V
DD
, and therefore, cannot tolerate any
“positive” input injection current.
10: Injection curr ents > | 0 | ca n af fect the AD C resul ts by ap proximate ly 4 to 6 c ount s (i.e ., V
IH
Source > ( V
DD
+
0.3) or V
IL
source < (V
SS
- 0.3)).
11: Any number and/or combination of I/O pins not excluded under I
ICL
or I
ICH
conditions are permitted pro-
vided the “abso lut e ins t antaneous” sum of the in put in jec tion currents fr om all pins do not exceed the speci -
fied lim it. If Note 7, I
ICL
= (((Vss - 0.3) - V
IL
source) / Rs). If Note 8, I
ICH
= ((I
ICH
source - ( V
DD
+ 0.3)) / RS).
RS = R esist ance betwe en inp ut sou rce volt age and dev ice p in. If (V
SS
- 0.3) V
SOURCE
(V
DD
+ 0.3), inj ec-
tion current = 0.
2009-2016 Microchip Technology Inc. DS60001156J- page 361
PIC32MX5XX/6XX/7XX
I
IL
Input Leak age Current
(3)
DI50 I/O Ports — — +1AV
SS
V
PIN
V
DD
,
Pin at high-impedance
DI51 A nalog Input Pins — — +1AV
SS
V
PIN
V
DD
,
Pin at high-impedance
DI55 MCLR
(2)
——+1AV
SS
V
PIN
V
DD
DI56 OSC1 — — +1AV
SS
V
PIN
V
DD
,
XT and HS modes
DI60a I
ICL
Input Low Injection
Current 0—-5
(7,10)
mA
This parameter app li es
to all pi ns , with the
excep tion of RB10.
Maximum I
ICH
current
for this e x ce ption is
0mA.
DI60b I
ICH
Input High Injection
Current 0—+5
(8,9,10)
mA
This parameter app li es
to all pi ns , with the
excep tion of all 5V toler -
ant pins, SOSCI, and
RB10. Maximum I
ICH
curr en t fo r t he se
exceptions is 0 mA.
DI60c I
ICT
Total Input Injection
Current (sum of all I/O
and control pins)
-20
(11)
—+20
(11)
mA Absolute instantaneo us
sum of all ± input
injection currents from
all I/O pins
(| I
ICL
+ | I
ICH
|) I
ICT
TABLE 32-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics Min. Typical
(1)
Max. Units Conditions
Note 1: Data in “T yp ic al” colum n is at 3. 3V, 25°C unless oth erw is e s t ate d. Pa ram ete rs are for de si gn guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Device Pin Tables” section for the 5V-tolerant pins.
6: The V
IH
specification is only in relation to externally applied inputs and not with respect to the user-select-
able pull-ups. E xte rnal ly ap pl ied high impe dan ce or op en drain input si gna ls utilizing the PIC32 internal pu ll -
ups are guaranteed to be recognized as a logic “high” internally to the PIC32 device, provided that the
external load does not exceed the maximum value of I
CNPU
.
7: V
IL
source < (V
SS
- 0.3). Characterized but not tested .
8: V
IH
source > (V
DD
+ 0.3) for non-5V tolerant pins only.
9: Digital 5V tolerant pins do not have an internal hi gh side diode to V
DD
, and therefore, cannot tolerate any
“positive” input injection current.
10: Injection curr ents > | 0 | ca n af fect the AD C resul ts by ap proximate ly 4 to 6 c ount s (i.e ., V
IH
Source > ( V
DD
+
0.3) or V
IL
source < (V
SS
- 0.3)).
11: Any number and/or combination of I/O pins not excluded under I
ICL
or I
ICH
conditions are permitted pro-
vided the “abso lut e ins t antaneous” sum of the in put in jec tion currents fr om all pins do not exceed the speci -
fied lim it. If Note 7, I
ICL
= (((Vss - 0.3) - V
IL
source) / Rs). If Note 8, I
ICH
= ((I
ICH
source - ( V
DD
+ 0.3)) / RS).
RS = R esist ance betwe en inp ut sou rce volt age and dev ice p in. If (V
SS
- 0.3) V
SOURCE
(V
DD
+ 0.3), inj ec-
tion current = 0.
PIC32MX5XX/6XX/7XX
DS60001156J-page 362 2009-2016 Microchip Technology Inc.
TABLE 32-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise st ated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-temp
Param. Symbol Characteristic Min. Typ. Max. Units Conditions
DO10 V
OL
Output Low Voltage
I/O Pins:
4x Sink Driver Pins - All I/O
output pins not defined as 8x
Sink Driv er pins
——0.4VI
OL
10 mA, V
DD
= 3.3V
Output Low Voltage
I/O Pins:
8x Sink Driver Pins - RC15 ——0.4VI
OL
15 mA, V
DD
= 3.3V
DO20 V
OH
Output High Voltage
I/O Pins:
4x Source Driver Pins - All I/O
output pins not defined as 8x
Source Driver pins
2.4 — — V I
OH
-10 mA, V
DD
= 3.3V
Output High Voltage
I/O Pins:
8x Source Driver Pins - RC15 2.4 — — V I
OH
-15 mA, V
DD
= 3.3V
DO20A V
OH
1
Output High Voltage
I/O Pins:
4x Source Driver Pins - All I/O
output pins not defined as 8x
Sink Driv er pins
1.5
(1)
——
V
I
OH
-14 mA, V
DD
= 3.3V
2.0
(1)
—— I
OH
-12 mA, V
DD
= 3.3V
3.0
(1)
—— I
OH
-7 mA, V
DD
= 3.3V
Output High Voltage
I/O Pins:
8x Source Driver Pins - RC15
1.5
(1)
——
V
I
OH
-22 mA, V
DD
= 3.3V
2.0
(1)
—— I
OH
-18 mA, V
DD
= 3.3V
3.0
(1)
—— I
OH
-10 mA, V
DD
= 3.3V
Note 1:
Parameters are ch arac teri ze d, but not tes ted .
2:
This driver pin only applies to devices with less than 64 pins.
3:
This driver pin only applies to devices with 64 pins.
TABLE 32-10: ELECTRICAL CHARACTERISTICS: BOR
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwis e stated)
Operating temperature -40°C T
A
+85° C for Industri al
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics Min.
(1)
Typical Max. Units Conditions
BO10 V
BOR
BOR Event on V
DD
transitio n
high-to-low (
Note 2
)2.0 — 2.3 V —
Note 1:
Parameters are for design guidance only and are not tested in manufacturing.
2:
Overall fun cti ona l dev ic e ope rati on at V
BORMIN
< V
DD
< V
DDMIN
is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below V
DDMIN
.
2009-2016 Microchip Technology Inc. DS60001156J- page 363
PIC32MX5XX/6XX/7XX
TABLE 32-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS
TABLE 32-11: DC CHARACTERISTICS: PROGRAM MEMORY
(3)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics Min. Typ.
(1)
Max. Units Conditions
D130 E
P
Cell Endurance 1000 — — E/W —
D130a E
P
Cell Endurance 20,000 — — E/W See
Note 5
D131 V
PR
V
DD
for Read 2.3 — 3.6 V —
D132 V
PEW
V
DD
for Erase or Write 3.0 — 3.6 V —
D132a V
PEW
V
DD
for Erase or Write 2.3 — 3.6 V See
Note 5
D134 T
RETD
Charac teri st ic R eten tio n 20 — — Year Provided n o other specif ica tio ns
are violat ed
D135 I
DDP
Supply Current during
Programming —10— mA —
D138 T
WW
Word Write Cycle Time
(4)
— 411 — FRC Cycles —
D136 T
RW
Row Write Cycle Time
(2,4)
— 26067 — FRC Cycles —
D137 T
PE
Page Erase Cycle Time
(4)
— 201060 — FRC Cycles —
D139 T
CE
Chip Erase Cycle Time
(4)
— 804652 — FRC Cycles —
Note 1:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2:
The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activiti es
during row prog ramming , suc h as susp ending any memory -to-mem ory DM A opera tions . If he avy bus l oads
are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default
Arbitration mode is mode 1 (CPU has lowest priority).
3:
Refer to “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during
programmi ng and erase cy cl es .
4:
This parameter depends on the FRC accuracy (see Table 32-19) and the FRC tuning values (see
Register 8-2).
5:
This parameter only applies to PIC32MX534/564/664/764 devices.
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherw ise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Required Flash Wait States SYSCLK Units Comments
0 Wait State 0 to 30 MHz —
1 Wait State 31 to 60
2 Wait States 61 to 80
PIC32MX5XX/6XX/7XX
DS60001156J-page 364 2009-2016 Microchip Technology Inc.
TABLE 32-13: COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions (see Note 3): 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics Min. Typical Max. Units Comments
D300 V
IOFF
Input Offset Voltage — ±7.5 ±25 mV A
VDD
= V
DD
,
A
VSS
= V
SS
D301 V
ICM
Input Common Mode Voltage 0 — V
DD
VA
VDD
= V
DD
,
A
VSS
= V
SS
(Note 2)
D302 CMRR Common Mode Rejection Ratio 55 — — dB Max V
ICM
= (V
DD
- 1)V
(Note 2)
D303 T
RESP
Resp onse Time — 150 400 ns AV
DD
= V
DD
,
AV
SS
= V
SS
(Notes 1, 2)
D304 ON2
OV
Comparator Enab led to Output
Valid ——10s Comparator module is
configured before setting
the comparator ON bit
(Note 2)
D305 IV
REF
Internal Vo ltage Reference 0.57 0.6 0.63 V For devices without
BGSEL<1:0>
1.14 1.2 1.26 V BGSEL<1:0> = 00
0.57 0.6 0.63 V BGSEL<1:0> = 01
Note 1:
Response time measured with one comparator input at (V
DD
– 1.5)/2, while the other input transitions
from V
SS
to V
DD
.
2:
These parameters are characterized but not tested.
3:
The Comp ara tor mod ule is functi onal a t V
BORMIN
< V
DD
< V
DDMIN
, but with deg raded p erfor mance. U nles s
otherwise stated, module functionality is tested, but not characterized.
2009-2016 Microchip Technology Inc. DS60001156J- page 365
PIC32MX5XX/6XX/7XX
TABLE 32-14: VOLTAGE REFERENCE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C fo r V-Temp
Param.
No. Symbol Characteristics Min. Typical Max. Units Comments
D312 T
SET
Internal 4-bit DAC
Compar ator Reference
Settling time.
—— 10 µsSee
Note 1
D313 DAC
REFH
CV
REF
Input Voltage
Refere nce Range AV
SS
—AV
DD
VCV
RSRC
with CVRSS = 0
V
REF
-— V
REF
+VCV
RSRC
with CVRSS = 1
D314 DV
REF
CV
REF
Programmable
Output Range 0 — 0.625 x
DAC
REFH
V 0 to 0.625 DAC
REFH
with
DAC
REFH
/24 step size
0.25 x
DAC
REFH
— 0.719 x
DAC
REFH
V0.25 x DAC
REFH
to 0.719
DAC
REFH
with DAC
REFH
/32
step size
D315 DAC
RES
Resolution — — DAC
REFH
/
24 CVRCON<CVRR> = 1
——DAC
REFH
/
32 CVRCON<CVRR> = 0
D316 DAC
ACC
Absolute Accuracy
(2)
——1/4LSBDAC
REFH
/24,
CVRCON<CVRR> = 1
——1/2LSBDAC
REFH
/32,
CVRCON<CVRR> = 0
Note 1:
Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. This p aramete r
is characterized, but not tested in manufacturing.
2:
These parameters are characterized but not tested.
TABLE 32-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwis e stated)
Ope rating temper ature -40°C T
A
+85°C for Indu stri al
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics Min. Typical Max. Units Comments
D321 C
EFC
External Filter Capacitor Value 8 10 — F Cap acito r mus t be low se ries
resistance (1 ohm)
D322 T
PWRT
Power-up Timer Period — 64 — ms —
PIC32MX5XX/6XX/7XX
DS60001156J-page 366 2009-2016 Microchip Technology Inc.
32.2 AC Characteristics and Ti ming
Parameters
The information contained in this section defines
PIC32MX5XX/6XX/7XX AC characteristics and timing
parameters.
FIGURE 32-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
FIGURE 32-2: EX T ER N A L CLOCK TIMING
V
DD
/2
C
L
R
L
Pin
Pin
V
SS
V
SS
C
L
R
L
=464
C
L
= 50 pF for all pins
50 pF for OSC2 pin (EC mode)
Load Cond itio n 1 – for all pins except OSC2 Load Condition 2 – for OSC2
TABLE 32-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operati ng tem pe rature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics Min. Typical
(1)
Max. Units Conditions
DO50 Cosco OSC2 pin — — 15 pF In XT and HS modes when an
external crystal is used to drive
OSC1
DO56 C
IO
All I/O pins and OSC2 — — 50 pF In EC mode
DO58 C
B
SCLx, SDAx — — 400 pF In I
2
C mode
Note 1:
Data i n “T ypic al” column is at 3.3V, 25°C unless oth erwise st ated. Param eters are for de sign guid ance only
and are not tested.
OSC1
OS20 OS30
OS30
OS31
OS31
2009-2016 Microchip Technology Inc. DS60001156J- page 367
PIC32MX5XX/6XX/7XX
TABLE 32-17: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics Min. Typical
(1)
Max. Units Conditions
OS10 F
OSC
External CLKI Frequency
(External clo ck s onl y a llo w ed
in EC and ECPLL modes)
DC
4—
—50
50 MHz
MHz EC
(Note 4)
ECPLL
(Note 3)
OS11 Oscillator Crystal Frequency 3 — 10 MHz XT
(Note 4)
OS12 4 — 10 MHz XTPLL
(Notes 3,4)
OS13 10 — 25 MHz HS
(Note 4)
OS14 10 — 25 MHz HSPLL
(Notes 3,4)
OS15 32 32.768 100 kHz S
OSC
(Note 4)
OS20 T
OSC
T
OSC
= 1/F
OSC
= T
CY(2)
— — — — See parame ter
OS10 for F
OSC
value
OS30 T
OS
L,
T
OS
HExternal Clock
In (OSC1)
High or Low Time 0.45 x T
OSC
——nsEC
(Note 4)
OS31 T
OS
R,
T
OS
FExternal Clock
In (OSC1)
Rise or Fall Time — — 0.05 x T
OSC
ns EC
(Note 4)
OS40 T
OST
Oscillator Start-up Timer Period
(Only applies to HS, HSPLL,
XT, XTPLL and S
OSC
Clock
Oscillator modes)
— 1024 — T
OSC
(Note 4)
OS41 T
FSCM
Primary Clock Fail Safe
Time-out Period —2—ms
(Note 4)
OS42 G
M
External Oscillator
Transconductance (Primary
Oscillator only)
—12—mA/VV
DD
= 3.3V,
T
A
= +25°C
(Note 4)
Note 1:
Data in “T y pical” c olumn is a t 3.3V, 25°C unle ss otherw ise st ated. Pa rameters are characteri zed b ut are not
tested.
2:
Instructio n cycle peri od (T
CY
) equals the input oscil lator time bas e period. All sp ecified va lues are base d on
characteri zation data for that part ic ula r oscillator type under stand ard ope rati ng con di t ion s with the dev ic e
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin.
3:
PLL input requi rem en t s: 4 MH
Z
F
PLLIN
5 MH
Z
(use PLL prescaler to reduce F
OSC
). This parameter is
characterized, but is only tested at 10 MHz at manufacturing.
4:
This parameter is characterized, but not tested in manufacturing.
PIC32MX5XX/6XX/7XX
DS60001156J-page 368 2009-2016 Microchip Technology Inc.
TABLE 32-18: PLL CLOCK TIMING SPECIFICATIONS (V
DD
= 2.3V TO 3.6V)
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwis e stated)
Ope rating temper ature -40°C T
A
+85°C for Indu stri al
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typical Max. Units Conditions
OS50 F
PLLI
PLL Voltage Con troll ed
Oscill ator (VC O) Input
Frequency Range
3.92 — 5 MHz ECPLL, HSPLL, XTPLL,
FRCPLL mo des
OS51 F
SYS
On-Chip VCO System
Frequency 60 — 120 MHz —
OS52 T
LOCK
PLL Start-up Time (Lock Time) — — 2 ms —
OS53 D
CLK
CLKO Stability
(2)
(Period Jitter or Cumulative) -0.25 — +0.25 % Measured over 100 ms
period
Note 1:
These parameters are characterized, but not tested in manufacturing.
2:
This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective ji tter for
individual time-bases on communicatio n clocks, use the follow ing formula:
For example, if SYSCLK = 80 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:
EffectiveJitter D
CLK
SYSCLK
CommunicationClock
----------------------------------------------------------
--------------------------------------------------------------=
EffectiveJitter D
CLK
80
20
------
--------------D
CLK
2
--------------==
TABLE 32-19: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Characteristics Min. Typical Max. Units Conditions
Internal FRC Accuracy @ 8.00 MHz
(1)
for PIC32MX575/675/695/775/795 Family Devices
F20a FRC -2 — +2 % —
Internal FRC Accuracy @ 8.00 MHz
(1)
for PIC32MX534/564/664/764 Family Devices
F20b FRC -0.9 — +0.9 % —
Note 1:
Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.
2009-2016 Microchip Technology Inc. DS60001156J- page 369
PIC32MX5XX/6XX/7XX
FIGURE 32-3: I/O TI MING CHARACTERISTICS
TABLE 32-20: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwis e stated)
Operating temperature -40°C T
A
+85° C for Industri al
-40°C T
A
+105°C for V-Temp
Param.
No. Characteristics Min. Typical Max. Units Conditions
LPRC @ 31.25 kHz
(1)
F21 LPRC -15 — +15 % —
Note 1:
Change of LPRC frequency as V
DD
chang es .
Note:
Refer to Figure 32-1 for load conditions.
I/O Pin
(Input)
I/O Pin
(Output)
DI35
DI40
DO31
DO32
TABLE 32-21: I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwis e stated)
Ope rating temper ature -40°C T
A
+85°C for Indu stri al
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(2)
Min. Typical
(1)
Max. Units Conditions
DO31 T
IO
R Port Output Rise Time — 5 15 ns V
DD
< 2.5V
—510nsV
DD
> 2.5V
DO32 T
IO
F Port Output Fall Time — 5 15 ns V
DD
< 2.5V
—510nsV
DD
> 2.5V
DI35 T
INP
INTx Pin High or Low Time 10 — — ns —
DI40 T
RBP
CNx High or Low Time (input) 2 — — T
SYSCLK
—
Note 1:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2:
This parameter is characterized, but not tested in manufacturing.
PIC32MX5XX/6XX/7XX
DS60001156J-page 370 2009-2016 Microchip Technology Inc.
FIGURE 32-4: POWER-ON RESET TIMING CHARACTERISTICS
V
DD
V
POR
Note 1:
The power-up period will be extended if the power-up sequence com pletes before the device exits from BOR
(V
DD
< V
DDMIN
).
2:
Includes interval voltage regulator stabilization delay.
SY00
Power-up Sequence
(Note 2)
Internal Voltage Regu lator Enabled
(T
PU
)SY10 CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, XT, XTPLL and S
OSC
)
V
DD
V
POR
SY00
Power-up Sequence
(Note 2)
Internal Voltage Regulator Enabled
(T
PU
)
(T
SYSDLY
)
CPU S tarts Fetching Code
(Note 1)
(Note 1)
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
(T
OST
)
SY02
(T
SYSDLY
)
SY02
2009-2016 Microchip Technology Inc. DS60001156J- page 371
PIC32MX5XX/6XX/7XX
FIGURE 32-5: EXTERNAL RESET TIMING CHARACTERISTICS
TABLE 32-22: RESETS TIMING
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherw ise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typical
(2)
Max. Units Conditions
SY00 T
PU
Power-up Period
Internal Voltage Regulator Enabled — 400 600 s -40°C to +85°C
SY02 T
SYSDLY
System Delay Period:
Time Required to Reload Device
Configu ration Fus es plus S YSCLK
Delay before First instruction is
Fetched.
—1 µs +
8 SYSCLK
cycles
— — -40°C to +85°C
SY20 T
MCLR
MCLR Pulse Width (low) — 2 — s -40°C to +85°C
SY30 T
BOR
BOR Pulse Width (low) — 1 — s -40°C to +85°C
Note 1:
These parameters are characterized, but not tested in manufacturing.
2:
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
MCLR
(SY20)
Reset Sequence
(SY10)
CPU Starts Fetching Code
BOR
(SY30)
T
OST
T
MCLR
T
BOR
Reset Sequence
CPU Start s Fetching Code
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Clock Sources = (HS, HSPLL, XT, XTPLL and S
OSC
)
(T
SYSDLY
)
SY02
(T
SYSDLY
)
SY02
PIC32MX5XX/6XX/7XX
DS60001156J-page 372 2009-2016 Microchip Technology Inc.
FIGURE 32-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
Note:
Refer to Figure 32-1 for load conditions.
Tx11
Tx15
Tx10
Tx20
TMRx
OS60
TxCK
TABLE 32-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
(1)
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwis e stated)
Operating temperature -40°C T
A
+ 85°C for Indu stri al
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(2)
Min. Typical Max. Units Conditions
TA10 T
TX
HTxCK
High Time Synchronous,
with presca le r [(12.5 ns or 1 T
PB
)/N]
+ 25 ns — — ns Must also meet
parameter TA15
Asynchronous,
with presca le r 10 — — ns —
TA11 T
TX
LTxCK
Low Time Synchronous,
with presca le r [(12.5 ns or 1 T
PB
)/N]
+ 25 ns — — ns Must also meet
parameter TA15
Asynchronous,
with presca le r 10 — — ns —
TA15 T
TX
PTxCK
Input Period Synchronous,
with presca le r [(Greater of 25 ns or
2 T
PB
)/N] + 30 ns ——nsV
DD
> 2.7V
[(Greater of 25 ns or
2 T
PB
)/N] + 50 ns ——nsV
DD
< 2.7V
Asynchronous,
with presca le r 20 — — ns V
DD
> 2.7V
(Note 3)
50 — — ns V
DD
< 2.7V
(Note 3)
OS60 F
T
1 SOSC1/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting
TCS bit (T1CON<1>))
32 — 100 kHz —
TA20 T
CKEXTMRL
Delay from External TxCK
Clock Edge to Timer
Increment
——1T
PB
—
Note 1:
Timer1 is a Type A.
2:
This para meter is ch aracterized, but not t ested in ma nufacturing.
3:
N = Prescale Value (1, 8, 64, 256).
2009-2016 Microchip Technology Inc. DS60001156J- page 373
PIC32MX5XX/6XX/7XX
TABLE 32-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHAR ACTE RISTI CS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Max. Units Conditions
TB10 T
TX
HTxCK
High T ime Synchronous, with
prescaler [(12.5 ns or 1 T
PB
)/N]
+ 25 ns — ns Must also meet
pa ra me t e r
TB15
N = prescale
value
(1, 2, 4, 8,
16, 32, 64,
256)
TB11 T
TX
LTxCK
Low Time Synchronous, with
prescaler [(12.5 ns or 1 T
PB
)/N]
+ 25 ns — ns Must also meet
pa ra me t e r
TB15
TB15 T
TX
PTxCK
Input
Period
Synchronous, with
prescaler [(Greater of [(25 ns or
2 T
PB
)/N] + 30 ns —nsV
DD
> 2.7V
[(Greater of [(25 ns or
2 T
PB
)/N] + 50 ns —nsV
DD
< 2.7V
TB20 T
CKEXTMRL
Delay f r om E xte r n a l T xCK
Clock Edge to T imer Increment —1T
PB
—
Note 1:
These parameters are characterized, but not tested in manufacturing.
PIC32MX5XX/6XX/7XX
DS60001156J-page 374 2009-2016 Microchip Technology Inc.
FIGURE 32-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
FIGURE 32-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
TABLE 32-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
ICx
IC10 IC11
IC15
Note:
Refer to Figure 32-1 for load conditions.
TABLE 32-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operati ng tem per ature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Max. Units Conditions
IC10 T
CC
L ICx Input Low Time [(12.5 ns or 1 T
PB
)/N]
+ 25 ns — ns Must also
meet
parameter
IC15.
N = prescale
value (1, 4, 16)
IC11 T
CC
H ICx Input High Time [(12.5 ns or 1 T
PB
)/N]
+ 25 ns — ns Must also
meet
parameter
IC15.
IC15 T
CC
P ICx Input Period [(25 ns or 2 T
PB
)/N]
+ 50 ns —ns —
Note 1:
These parameters are characterized, but not tested in manufacturing.
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typical
(2)
Max. Units Conditions
OC10 T
CC
F OCx Output Fall Time — — — ns See parameter DO32
OC11 T
CC
R OCx Output Rise Time — — — ns See parameter DO31
Note 1:
These parameters are characterized, but not tested in manufacturing.
2:
Dat a in “T y pical” colum n is at 3.3V, 25°C unles s otherwi se stat ed. Paramete rs are for des ign guidan ce only
and are not tested.
OCx
OC11 OC10
(Output Compar e
Note:
Refer to Figure 32-1 for load conditions.
or PWM mode)
2009-2016 Microchip Technology Inc. DS60001156J- page 375
PIC32MX5XX/6XX/7XX
FIGURE 32-9: OCx/PWM MODULE TIMING CHARACTERISTICS
OCFA/OCFB
OCx
OC20
OC15
Note:
Refer to Figure 32-1 for load conditions.
OCx is tri-stated
TABLE 32-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherw ise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param
No. Symbol Characteristics
(1)
Min Typical
(2)
Max Units Conditions
OC15 T
FD
Fault Input to PWM I/O Change — — 50 ns —
OC20 T
FLT
Fault Input Puls e Width 50 — — ns —
Note 1:
These parameters are characterized, but not tested in manufacturing.
2:
Data in “T ypical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
PIC32MX5XX/6XX/7XX
DS60001156J-page 376 2009-2016 Microchip Technology Inc.
FIGURE 32-10 : SPIx MODULE MAS TER MO DE (CKE = 0) TIMING CHARACTERISTICS
TABLE 32-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwis e stated)
Operating temperature -40°C T
A
+ 85°C for Indu stri al
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typical
(2)
Max. Units Conditions
SP10 T
SC
LSCKx Output Low Time
(3)
T
SCK
/2 — — ns —
SP11 T
SC
H SCKx Output High Ti me
(3)
T
SCK
/2 ——ns —
SP20 T
SC
F SCKx Output Fall Time
(4)
———ns
See parameter DO32
SP21 T
SC
R SCKx Output Rise Time
(4)
———
ns See parameter DO31
SP30 T
DO
F S DOx Data Output Fall Time
(4)
———
ns See parameter DO32
SP31 T
DO
R SDOx Data Output Rise
Time
(4)
———
ns See parameter DO31
SP35 T
SC
H2
DO
V,
T
SC
L2
DO
VSDOx Data Output Valid after
SCKx Edge ——
15 ns V
DD
> 2.7V
——
20 ns V
DD
< 2.7V
SP40 T
DI
V2
SC
H,
T
DI
V2
SC
LSetup Time of SDIx Data Input
to SCKx Edge 10 ——ns —
SP41 T
SC
H2
DI
L,
T
SC
L2
DI
LHold Time of SDIx Data Input
to SCKx Edge 10 ——ns —
Note 1:
These parameters are characterized, but not tested in manufacturing.
2:
Data in “Typical” colu mn is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3:
The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4:
Assumes 50 pF load on all SPIx pins.
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
SP11 SP10
SP40 SP41
SP21
SP20
SP35
SP20
SP21
MSb LSb
Bit 14 - - - - - -1
MSb In LSb In
Bit 14 - - - -1
SP30
SP31
Note:
Refer to Figure 32-1 for load conditions.
2009-2016 Microchip Technology Inc. DS60001156J- page 377
PIC32MX5XX/6XX/7XX
FIGURE 32-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
TABLE 32-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwis e stated)
Operating temperature -40°C T
A
+85°C for Industri al
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typ.
(2)
Max. Units Conditions
SP10 T
SC
L SCKx Output Low Time
(3)
T
SCK
/2 — — ns —
SP11 T
SC
H SCKx Output High Time
(3)
T
SCK
/2 — — ns —
SP20 T
SC
F SCKx Output Fall Time
(4)
— — — ns See parameter DO32
SP21 T
SC
R SCKx Output Rise Time
(4)
— — — ns See parameter DO31
SP30 T
DO
F SDOx Data Output Fall Time
(4)
— — — ns See parameter DO32
SP31 T
DO
R SDOx Data Output Rise Time
(4)
— — — ns See parameter DO31
SP35 T
SC
H2
DO
V,
T
SC
L2
DO
VSDOx Data Output Valid after
SCKx Edge ——15nsV
DD
> 2.7V
——20nsV
DD
< 2.7V
SP36 T
DO
V2
SC
,
T
DO
V2
SC
LSDOx Data Output Setup to
First SCKx Edge 15 — — ns —
SP40 T
DI
V2
SC
H,
T
DI
V2
SC
LSetup Time of SDIx Data Input to
SCKx Edge 15 — — ns V
DD
> 2.7V
20 — — ns V
DD
< 2.7V
SP41 T
SC
H2
DI
L,
T
SC
L2
DI
LHold Time of SDIx Data Input
to SCKx Edge 15 — — ns V
DD
> 2.7V
20 — — ns V
DD
< 2.7V
Note 1:
These parameters are characterized, but not tested in manufacturing.
2:
Data i n “T ypi cal” column is at 3.3V, 25°C unless ot herwise s tated. Parameters ar e for design guidance o nly
and are not tested.
3:
The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4:
Assumes 50 pF load on all SPIx pins.
SCK
X
(CKP = 0)
SCK
X
(CKP = 1)
SDO
X
SDI
X
SP36
SP30,SP31
SP35
MSb Bit 14 - - - - - -1
LSb In
Bit 14 - - - -1
LSb
Note:
Refer to Figure 32-1 for load conditions.
SP11 SP10
SP21
SP20
SP40 SP41
SP20
SP21
MSb In
PIC32MX5XX/6XX/7XX
DS60001156J-page 378 2009-2016 Microchip Technology Inc.
FIGURE 32-12 : SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SS
X
SCK
X
(CKP = 0)
SCK
X
(CKP = 1)
SDO
X
SP50
SP40 SP41
SP30,SP31 SP51
SP35
MSb LSb
Bit 14 - - - - - -1
Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP71 SP70
Note:
Re fe r to Figure 32-1 for load conditions.
SDI
X
MSb In
TABLE 32-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENT S
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operati ng tem pe rature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typ.
(2)
Max. Units Conditions
SP70 T
SC
L SCKx Input Low Time
(3)
T
SCK
/2 — — ns —
SP71 T
SC
H SCKx Input High Time
(3)
T
SCK
/2 — — ns —
SP72 T
SC
F SCKx Input Fall Time — — — ns See parameter DO32
SP73 T
SC
R SCKx Input Rise Time — — — ns See parameter DO31
SP30 T
DO
F SDOx Data Output Fall Time
(4)
— — — ns See parameter DO32
SP31 T
DO
R SDOx Data Output Rise Time
(4)
— — — ns See parameter DO31
SP35 T
SC
H2
DO
V,
T
SC
L2
DO
VSDOx Data Output Valid after
SCKx Edge — — 15 ns V
DD
> 2.7V
— — 20 ns V
DD
< 2.7V
SP40 T
DI
V2
SC
H,
T
DI
V2
SC
LSetup Time of SDIx Data Input
to SCKx Edge 10 — — ns —
SP41 T
SC
H2
DI
L,
T
SC
L2
DI
LHold Time of SDIx Data Input
to SCKx Edge 10 — — ns —
SP50 T
SS
L2
SC
H,
T
SS
L2
SC
LSSx to SCKx or SCKx Input 175 — — ns —
SP51 T
SS
H2
DO
Z SSx to SDOx Output
High-Impedance
(3)
5 — 25 ns —
SP52 T
SC
H2
SS
H
T
SC
L2
SS
HSSx after SCKx Edge T
SCK
+ 20 — — ns —
Note 1:
These parameters are characterized, but not tested in manufacturing.
2:
Data i n “T ypic al” column is at 3.3V, 25°C unless oth erwise st ated. Param eters are for de sign guid ance only
and are not tested.
3:
The minimum clock period for SCKx is 40 ns.
4:
Assumes 50 pF load on all SPIx pins.
2009-2016 Microchip Technology Inc. DS60001156J- page 379
PIC32MX5XX/6XX/7XX
FIGURE 32-13 : SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDI
SP60
SDIx
SP30,SP31
MSb Bit 14 - - - - - -1 LSb
SP51
MSb In Bit 14 - - - -1 LSb In
SP52
SP73
SP72
SP72
SP73
SP71
SP40 SP41
Note:
Refer to Figure 32-1 for load conditions.
SP50
SP70
SP35
TABLE 32-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105 °C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typical
(2)
Max. Units Conditions
SP70 T
SC
L SCKx Input Low Time
(3)
T
SCK
/2 — — ns —
SP71 T
SC
H SCKx Input High T i m e
(3)
T
SCK
/2 — — ns —
SP72 T
SC
F SCKx Input Fall Time — 5 10 ns —
SP73 T
SC
R SCKx Input Rise Time — 5 10 ns —
SP30 T
DO
F SDOx Da t a Ou tp ut Fall Time
(4)
— — — ns See p ara me ter DO32
SP31 T
DO
R SDOx D a t a Output Ris e Time
(4)
— — — ns See p ara me ter DO31
SP35 T
SC
H2
DO
V,
T
SC
L2
DO
VSDOx Data Output Valid after
SCKx Edge — — 20 ns V
DD
> 2.7V
— — 30 ns V
DD
< 2.7V
SP40 T
DI
V2
SC
H,
T
DI
V2
SC
LSetup Time of SDIx Data Input
to SCKx Edge 10 — — ns —
SP41 T
SC
H2
DI
L,
T
SC
L2
DI
LHold Time of SDIx Data Input
to SCKx Edge 10 — — ns —
SP50 T
SS
L2
SC
H,
T
SS
L2
SC
LSSx to SCKx or SCKx Input 175 — — ns —
Note 1:
These parameters are characterized, but not tested in manufacturing.
2:
Data in “T ypical” col umn is at 3.3V, 25°C unless otherwise st ated. Param eters are for desig n guidance only
and are not tested.
3:
The minimum clock period for SCKx is 40 ns.
4:
Assumes 50 pF load on all SPIx pins.
PIC32MX5XX/6XX/7XX
DS60001156J-page 380 2009-2016 Microchip Technology Inc.
SP51 T
SS
H2
DO
Z SSx to SDO
X
Output
High-Impedance
(4)
5 — 25 ns —
SP52 T
SC
H2
SS
H
T
SC
L2
SS
HSSx afte r SCKx Edge T
SCK
+
20 ——ns —
SP60 T
SS
L2
DO
V SDOx Data Output Valid after
SSx Edge — — 25 ns —
TABLE 32-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105 °C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typical
(2)
Max. Units Conditions
Note 1:
These parameters are characterized, but not tested in manufacturing.
2:
Data in “T ypical” col umn is at 3.3V, 25°C unless otherwise st ated. Param eters are for desig n guidance only
and are not tested.
3:
The minimum clock period for SCKx is 40 ns.
4:
Assumes 50 pF load on all SPIx pins.
2009-2016 Microchip Technology Inc. DS60001156J- page 381
PIC32MX5XX/6XX/7XX
FIGURE 32-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
FIGURE 32-15: I2Cx BUS DATA T IMING CHARACTERISTICS (MASTER MODE)
SCLx
SDAx
Start
Condition Stop
Condition
Note:
Refer to Figure 32-1 for load conditions.
IM30
IM31 IM34
IM33
IM11 IM10 IM33
IM11 IM10
IM20
IM26 IM25
IM40 IM40 IM45
IM21
SCLx
SDAx
In
SDAx
Out
Note:
Refer to Figure 32-1 for load conditions.
PIC32MX5XX/6XX/7XX
DS60001156J-page 382 2009-2016 Microchip Technology Inc.
TABLE 32-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standa rd Oper at ing Condit ions: 2.3V t o 3.6V
(unless otherwise stated)
Opera ting te m perature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C fo r V- Tem p
Param.
No. Symbol Characteristics Min.
(1)
Max. Units Conditions
IM10 T
LO
:
SCL
Clock Low Time 100 kHz mo de T
PB
* (BRG + 2) — s—
400 kHz mo de T
PB
* (BRG + 2) — s—
1 MHz mode
(2)
T
PB
* (BRG + 2) — s—
IM11 T
HI
:
SCL
Clock H igh Time 100 kHz mode T
PB
* (BRG + 2) — s—
400 kHz mo de T
PB
* (BRG + 2) — s—
1 MHz mode
(2)
T
PB
* (BRG + 2) — s—
IM20 T
F
:
SCL
SDAx an d SCLx
Fall Time 100 kH z mode — 30 0 ns C
B
is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 C
B
300 ns
1 MHz mode
(2)
—100ns
IM21 T
R
:
SCL
SDAx an d SCLx
Rise T ime 100 kHz mode — 100 0 ns C
B
is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 C
B
300 ns
1 MHz mode
(2)
—300ns
IM25 T
SU
:
DAT
Data Input
Setup Time 100 kH z mode 250 — ns —
400 kHz mo de 100 — ns
1 MHz mode
(2)
100 — ns
IM26 T
HD
:
DAT
Data Input
Hold T ime 100 kH z mode 0 — s—
400 kHz mo de 0 0.9 s
1 MHz mode
(2)
0 0.3 s
IM30 T
SU
:
STA
St art Conditi on
Setup Time 100 kH z mode T
PB
* (BRG + 2) — ns Only relevant fo r
Repeated S t art
condition
400 kHz mo de T
PB
* (BRG + 2) — ns
1 MHz mode
(2)
T
PB
* (BRG + 2) — ns
IM31 T
HD
:
STA
Start Con di t io n
Hold T ime 100 kH z mode T
PB
* (BRG + 2) — ns After this period, the
first clock pulse is
generated
400 kHz mo de T
PB
* (BRG + 2) — ns
1 MHz mode
(2)
T
PB
* (BRG + 2) — ns
IM33 T
SU
:
STO
St op Condition
Setup Time 100 kH z mode T
PB
* (BRG + 2) — ns —
400 kHz mo de T
PB
* (BRG + 2) — ns
1 MHz mode
(2)
T
PB
* (BRG + 2) — ns
IM34 T
HD
:
STO
St op Condition 100 kHz mode T
PB
* (BRG + 2) — ns —
Hold Time 400 kHz mode T
PB
* (BRG + 2) — ns
1 MHz mode
(2)
T
PB
* (BRG + 2) — ns
IM40 T
AA
:
SCL
Output Valid from
Clock 100 kHz mo de — 3 500 ns —
400 kHz mo de — 1 00 0 ns —
1 MHz mode
(2)
—350ns —
IM45 T
BF
:
SDA
Bus Free Time 100 kH z mode 4. 7 — s The amount of time the
bus must be free before
a new
transmi ssion can star t
400 kHz mo de 1.3 — s
1 MHz mode
(2)
0.5 — s
IM50 C
B
Bus Capac itive Loading — 400 pF —
IM51 T
PGD
Pulse Gobbler Delay
(3)
52 312 ns —
Note 1: BRG is th e val ue of the I
2
C Baud Rate Generator.
2: Maximum pin capaci tanc e = 10 pF for all I2Cx pins (only fo r 1 MH z mode).
3:
The typical value for this parameter is 104 ns.
2009-2016 Microchip Technology Inc. DS60001156J- page 383
PIC32MX5XX/6XX/7XX
FIGURE 32-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
FIGURE 32-17: I2Cx BUS DATA T IMING CHARACTERISTICS (SLAVE MODE)
IS34
SCLx
SDAx
Start
Condition Stop
Condition
IS33
Note:
Refer to Figure 32-1 for load conditions.
IS31
IS30
IS30 IS31 IS33
IS11
IS10
IS20
IS26 IS25
IS40 IS40 IS45
IS21
SCLx
SDAx
In
SDAx
Out
Note:
Refer to Figure 32-1 for load c onditions.
PIC32MX5XX/6XX/7XX
DS60001156J-page 384 2009-2016 Microchip Technology Inc.
TABLE 32-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industri al
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics Min. Max. Units Conditions
IS10 T
LO
:
SCL
Clock Low Time 100 kHz mode 4.7 — s PBCLK must operate at a
minimum of 800 kHz
400 kHz mode 1.3 — s PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(1)
0.5 — s—
IS11 T
HI
:
SCL
Clock High Time 100 kHz mode 4.0 — s PBCLK must operate at a
minimum of 800 kHz
400 kHz mode 0.6 — s PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(1)
0.5 — s—
IS20 T
F
:
SCL
SDAx and SCLx
Fall Time 100 kHz mode — 300 ns C
B
is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 C
B
300 ns
1 MHz mode
(1)
— 100 ns
IS21 T
R
:
SCL
SDAx and SCLx
Rise Time 100 kHz mode — 1000 ns C
B
is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 C
B
300 ns
1 MHz mode
(1)
— 300 ns
IS25 T
SU
:
DAT
Data Input
Setup Time 100 kHz mode 250 — ns —
400 kHz mode 100 — ns
1 MHz mode
(1)
100 — ns
IS26 T
HD
:
DAT
Data Input
Hold Time 100 kHz mode 0 — ns —
400 kHz mode 0 0.9 s
1 MHz mode
(1)
00.3s
IS30 T
SU
:
STA
Start Cond iti on
Setup Time 100 kHz mode 4700 — ns Only relevant for Repeated
Start condition
400 kHz mode 600 — ns
1 MHz mode
(1)
250 — ns
IS31 T
HD
:
STA
Start Cond iti on
Hold Time 100 kHz mode 4000 — ns After this period, the first
clock pulse is generated
400 kHz mode 600 — ns
1 MHz mode
(1)
250 — ns
IS33 T
SU
:
STO
Stop Condition
Setup Time 100 kHz mode 4000 — ns —
400 kHz mode 600 — ns
1 MHz mode
(1)
600 — ns
IS34 T
HD
:
STO
Stop Condition
Hold Time 100 kHz mode 4000 — ns —
400 kHz mode 600 — ns
1 MHz mode
(1)
250 ns
IS40 T
AA
:
SCL
Output Valid from
Clock 100 kHz mode 0 3500 ns —
400 kHz mode 0 1000 ns
1 MHz mode
(1)
0 350 ns
IS45 T
BF
:
SDA
Bus Free Time 100 kHz mode 4.7 — s The amount of time the bus
must be free before a new
transmission can start
400 kHz mode 1.3 — s
1 MHz mode
(1)
0.5 — s
IS50 C
B
Bus Capacitive Loading — 400 pF —
Note 1:
Maximum pin capacitance = 10 pF for all I2Cx pins (only for 1 MHz mode).
2009-2016 Microchip Technology Inc. DS60001156J- page 385
PIC32MX5XX/6XX/7XX
FIGURE 32-18: CAN MODULE I/O TIMING CHARACTERISTICS
TABLE 32-34: CAN MODULE I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param
No. Symbol Characteristic
(1)
Min Typ
(2)
Max Units Conditions
CA10 TioF Port Output Fall Time — — — ns See para me ter DO32
CA11 Ti oR Port Output Rise Time — — — n s See parameter DO31
CA20 Tcwf Pulse Width to Trigger
CAN Wa ke-up Filter 700 — — ns —
Note 1:
These parameters are characterized but not tested in manufacturing.
2:
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
CiTx Pin
(output)
CA10
CA11
Old Val u e New Value
CA20
CiRx Pin
(input)
PIC32MX5XX/6XX/7XX
DS60001156J-page 386 2009-2016 Microchip Technology Inc.
TABLE 32-35: ETHERNET MODULE SPECIFICATIONS
FIGURE 32-19: MDIO SOURCED BY THE PIC32 DEVICE
FIGURE 32-20: MDIO SOURCED BY THE PHY
AC CHARACTERISTICS
Standard Operating Conditions (see Note 1): 2.9V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Characteristic Min. Typical Max. Units Conditions
MIIM Timing Requirements
ET1 MDC Duty Cycle 40 — 60 % —
ET2 MDC Period 400 — — ns —
ET3 MDIO Output Setup and Hold 10 — 10 ns See Figure 32-19
ET4 MDIO Input Setup and Hold 0 — 300 ns See Figure 32-20
MII Timing Requirements
ET5 TX Clock Frequency — 25 — MHz —
ET6 TX Clock Duty Cycle 35 — 65 % —
ET7 ETXDx, ETEN, ETXERR Output Delay 0 — 25 ns See Figure 32-21
ET8 RX Clock Frequency — 25 — MHz —
ET9 RX Clock Duty Cycle 35 — 65 % —
ET10 ERXDx, ERXDV, ERXERR Setup and Hold 10 — 30 ns See Figure 32-22
RMII Timing Requi re me nts
ET11 Reference Clock Frequency — 50 — MHz —
ET12 Reference Clock Duty Cycle 35 — 65 % —
ET13 ETXDx, ETEN, Setup and Hold 2 — 4 ns —
ET14 ERXDx, ERXDV, ERXERR Setup and Hold 2 — 4 ns —
Note 1:
The Ethernet mo dule is functional at V
BORMIN
< V
DD
< 2.9V, but with degr ade d perf orm anc e. Unl es s ot her-
wise stated, module functionality is tested, but not characterized.
ET3 (Hold)
(Setup) ET3
MDC
MDIO
V
IHMIN
V
ILMAX
V
IHMIN
V
ILMAX
V
IHMIN
V
ILMAX
V
IHMIN
V
ILMAX
ET4
MDC
MDIO
2009-2016 Microchip Technology Inc. DS60001156J- page 387
PIC32MX5XX/6XX/7XX
FIGURE 32-21: TRANSMIT SIGNAL TIMING RELATIONSHIPS AT THE MII
FIGURE 32-22 : RECEIV E SIGNAL TIMING RELATIONSHIPS AT THE MII
ET7
TX Clock
ETXD<3:0>,
V
IHMIN
V
ILMAX
V
IHMIN
V
ILMAX
ETEN,
ETXERR
ET10 (Hold)
RX Clock
ERXD<3:0>,
V
IHMIN
V
ILMAX
V
IHMIN
V
ILMAX
(Setup) ET10
ERXDV,
ERXERR
PIC32MX5XX/6XX/7XX
DS60001156J-page 388 2009-2016 Microchip Technology Inc.
TABLE 32-36: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions (see Note 5): 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics Min. Typical Max. Units Conditions
Device Supply
AD01 AV
DD
Module V
DD
Supply G reater of
V
DD
– 0.3
or 2.5
— Lesser of
V
DD
+ 0.3
or 3.6
V—
AD02 AV
SS
Module V
SS
Supply V
SS
—V
SS
+ 0.3 V —
Reference Inputs
AD05
AD05a V
REFH
Reference Voltage High AV
SS
+ 2.0
2.5 —
—AV
DD
3.6 V
V
(Note 1)
V
REFH
= AV
DD
(Note 3)
AD06 V
REFL
Reference Voltage Low AV
SS
—V
REFH
– 2.0 V
(Note 1)
AD07 V
REF
Absolute Reference
Voltage (V
REFH
– V
REFL
)2.0 — AV
DD
V
(Note 3)
AD08
AD08a I
REF
Current Drain —
—250
—400
3A
AADC operating
ADC off
Analog Input
AD12 V
INH
-V
INL
Full-Scale Input Span V
REFL
—V
REFH
V—
AD13 V
INL
Absolute V
INL
Input
Voltage AV
SS
– 0.3 — AV
DD
/2 V —
AD14 V
IN
Absolute Input Voltage AV
SS
– 0.3 — AV
DD
+ 0.3 V —
AD15 Leakage Curren t — ±0.001 ±0.610 AV
INL
= AV
SS
= V
REFL
= 0V,
AV
DD
= V
REFH
= 3.3V
Source Impedance = 10 k
AD17 R
IN
Recommended
Im pedance of Analog
Voltage Source
——5K
(Note 1)
ADC Accuracy – Measurements with External V
REF
+/V
REF
-
AD20c Nr Resolution 10 data bits bits —
AD21c INL Integral Nonlinearity > -1 — < 1 LSb V
INL
= AV
SS
= V
REFL
= 0V,
AV
DD
= V
REFH
= 3.3V
AD22c DNL Differential Nonlinearity > -1 — < 1 LSb V
INL
= AV
SS
= V
REFL
= 0V,
AV
DD
= V
REFH
= 3.3V
(Note 2)
AD23c G
ERR
Gain Error > -1 — < 1 LSb V
INL
= AV
SS
= V
REFL
= 0V,
AV
DD
= V
REFH
= 3.3V
AD24c E
OFF
Offset Error > -1 — < 1 LSb V
INL
= AV
SS
= 0V,
AV
DD
= 3.3V
AD25c — Monotonicity — — — — Guaranteed
Note 1:
These parameters are not characterized or tested in manufacturing.
2:
With no missing codes.
3:
These parameters are characterized, but not tested in manufacturing.
4:
Characte riz ed with a 1 kHz sine wave .
5:
The ADC m odule is fu nction al at V
BORMIN
< V
DD
< 2.5V, but w ith d egraded perform ance. U nles s otherw ise
stated, module functionality is tested, but not characterized.
2009-2016 Microchip Technology Inc. DS60001156J- page 389
PIC32MX5XX/6XX/7XX
ADC Accuracy – Measurements with Internal V
REF
+/V
REF
-
AD20d Nr Resolution 10 data bits bits
(Note 3)
AD21d INL Integral Nonlinearity > -1 — < 1 LSb V
INL
= AV
SS
= 0V,
AV
DD
= 2.5V to 3.6V
(Note 3)
AD22d DNL Differential Nonlinearity > -1 — < 1 LSb V
INL
= AV
SS
= 0V,
AV
DD
= 2.5V to 3.6V
(Notes 2,3)
AD23d G
ERR
Gain Error > -4 — < 4 LSb V
INL
= AV
SS
= 0V,
AV
DD
= 2.5V to 3.6V
(Note 3)
AD24d E
OFF
Offset Error > -2 — < 2 LSb V
INL
= AV
SS
= 0V,
AV
DD
= 2.5V to 3.6V
(Note 3)
AD25d — Monotonicity — — — — Guaranteed
Dynamic Performance
AD31b SINAD Signal to Noise and
Distortion 55 58.5 — dB
(Notes 3,4)
AD34b ENOB Effective Number of Bits 9.0 9.5 — bits
(Notes 3,4)
TABLE 32-36: ADC MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS
Standard Operating Conditions (see Note 5): 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics Min. Typical Max. Units Conditions
Note 1:
These parameters are not characterized or tested in manufacturing.
2:
With no missing codes.
3:
These parameters are characterized, but not tested in manufacturing.
4:
Characte riz ed with a 1 kHz sine wave .
5:
The ADC m odule is fu nction al at V
BORMIN
< V
DD
< 2.5V, but w ith d egraded perform ance. U nles s otherw ise
stated, module functionality is tested, but not characterized.
PIC32MX5XX/6XX/7XX
DS60001156J-page 390 2009-2016 Microchip Technology Inc.
TABLE 32-37: 10-BIT ADC CONVERSION RATE PARAMETERS
Standard Operating Conditions (see Note 3): 2.5V to 3.6V
(unless otherwise stated)
Ope rati ng tem pera ture -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
ADC Speed
(2)
T
AD
Minimum
Sampling
Time
Minimum
R
S
Maximum V
DD
ADC Channels Configu r ation
1 Msps t o
400 ksps
(1)
65 ns 132 ns 5003.0V to 3.6V
Up to 400 ksps 200 ns 200 ns 5.0 k2.5V to 3.6V
Note 1:
External V
REF
- and V
REF
+ pins must be used for correct operation.
2:
These parameters are characterized, but not tested in manufacturing.
3:
The ADC module is functional at V
BORMIN
< V
DD
< 2.5V, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
V
REF
-V
REF
+
ADC
AN
x
S&HCH
X
V
REF
-V
REF
+
ADC
AN
x
S&HCH
X
AN
x or V
REF
-
or
AV
SS
or
AV
DD
2009-2016 Microchip Technology Inc. DS60001156J- page 391
PIC32MX5XX/6XX/7XX
TABLE 32-38: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions (see Note 4): 2.5V to 3.6V
(unless otherwis e stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C fo r V-Temp
Param.
No. Symbol Characteristics Min. Typical
(1)
Max. Units Conditions
Clock Parameters
AD50 T
AD
Analog-to-Digital Clock Period
(2)
65 — — ns See Table 32-37
Conversion Rate
AD55
TCONV
Conversion Time — 12 T
AD
—— —
AD56 F
CNV
Throughput Rate
(Sampling Speed) — — 1000 ksps AV
DD
= 3.0V to 3.6V
——400kspsAV
DD
= 2.5V to 3.6V
AD57 T
SAMP
Sample Time 1 T
AD
———T
SAMP
must be 132 ns
Timing Parameters
AD60
TPCS
Conversion Start from Sample
Trigger
(3)
— 1.0 T
AD
— — Auto -Conv ert Trigger
(SSRC<2:0> = 111)
not selected
AD61
TPSS
Sample Start from Setting
Sample (SAMP) bit 0.5 T
AD
—1.5 T
AD
——
AD62
TCSS
Conversion Completion to
Sample Start (ASAM = 1)
(3)
— 0.5 T
AD
—— —
AD63
TDPU
Time to Stabilize Analog Stage
from Analog-to-Digital Off to
Analog-to-Digita l On
(3)
—— 2s—
Note 1:
These parameters are characterized, but not tested in manufacturing.
2:
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
3:
Characterized by design but not tested.
4:
The ADC mo dule i s func tiona l at V
BORMIN
< V
DD
< 2.5V, but with degrade d perfo rmanc e. Unles s othe rwise
stated, module functionality is tested, but not characterized.
PIC32MX5XX/6XX/7XX
DS60001156J-page 392 2009-2016 Microchip Technology Inc.
FIGURE 32-23: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING
CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000)
AD55
T
SAMP
Clear SAMPSet SAMP
AD61
ADCLK
Instruction
SAMP
ch0_dischrg
AD60
CONV
ADxIF
Buffer(
0
)
Buffer(
1
)
1 2 3 4 5 6 8 5 6 7
1– Software sets ADxCON. SAMP to start sampling.
2– Sampling starts after discharge period. T
SAMP
is described in Section 17. “10-bit A/D Converter” (DS60001104) of the
3– Software clears ADxCON. SAM P to start conversion.
4– Sampling ends, conversion sequence starts.
5– Convert bit 9.
8– One T
AD
for end of conversion.
AD50
ch0_samp
eoc
7
AD55
8
6– Convert bit 8.
7– Convert bit 0.
Execution
“PIC32 Family Reference Manual”.
2009-2016 Microchip Technology Inc. DS60001156J- page 393
PIC32MX5XX/6XX/7XX
FIGURE 32-24: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(ASAM = 1, SSRC <2 :0> = 111, SAMC<4 : 0> = 00001)
AD55
T
SAMP
Set ADON
ADCLK
Instruction
SAMP
ch0_dischrg
CONV
ADxIF
Buffer(0)
Buffer(1)
1 2 3 4 5 6 4 5 6 8
1– Software sets ADxCON. ADON to start AD operation.
2– Sampling starts after discharge period.
3– Convert bit 9.
4– Convert bit 8.
5– Convert bit 0.
AD50
ch0_samp
eoc
7 3
AD55
6– One T
AD
for end of conversion.
7– Begin conversion of next channel.
8– Sample for time specified by SAMC<4:0>.
T
SAMP
T
CONV
3 4
Execution
T
SAMP
is described in Section 17. “10-bit A/D Converter”
(DS60001104) of the “PIC32 Family Reference Manual.
PIC32MX5XX/6XX/7XX
DS60001156J-page 394 2009-2016 Microchip Technology Inc.
FIGURE 32-25: PARALLEL SLAVE PORT TIMING
CS
RD
WR
PMD<7:0>
PS1
PS2
PS3
PS4
PS5
PS6
PS7
TABLE 32 -39: PARALLEL SLAVE PORT REQU IREMENT S
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherw ise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typical Max. Units Conditions
PS1 TdtV2wrH Data In Valid before WR or CS
Inactive (setup time) 20 — — ns —
PS2 TwrH2dtI WR or CS Inactive to Data-In
Invalid (hold time) 40 — — ns —
PS3 TrdL2dtV RD and CS Active to Data-Out
Valid — — 60 ns —
PS4 TrdH2dtI RD Activeor CS Inactive to
Data-Out Invalid 0 — 10 ns —
PS5 Tcs CS Active Time T
PB
+ 40 — — ns —
PS6 T
WR
WR Active Time T
PB
+ 25 — — ns —
PS7 T
RD
RD Active Time T
PB
+ 25 — — ns —
Note 1:
These parameters are characterized, but not tested in manufacturing.
2009-2016 Microchip Technology Inc. DS60001156J- page 395
PIC32MX5XX/6XX/7XX
FIGURE 32-26: PARALLEL MASTER P ORT READ TIMING DIAGRAM
T
PB
T
PB
T
PB
T
PB
T
PB
T
PB
T
PB
T
PB
PB Clock
PMALL/PMALH
PMD<7:0>
PMA<13:18>
PMRD
PMCS<2:1>
PMWR
PM5
Data
Address<7:0>
PM1
PM3
PM6
Data
PM7
Address<7:0>
Address
PM4
PM2
TABLE 32-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherw ise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typical Max. Units Conditions
PM1 T
LAT
PMALL/PMALH Pulse Width — 1 T
PB
—— —
PM2 T
ADSU
Address Out Valid to PM ALL/
PMALH Invalid (address setup
time)
—2 T
PB
—— —
PM3 T
ADHOLD
PMALL/PMALH Inva lid to Address
Out Invalid (address hold time) —1 T
PB
—— —
PM4 T
AHOLD
PMRD Inactive to Addres s Out
Invalid
(address hold time)
5——ns —
PM5 T
RD
PMRD Pulse Width — 1 T
PB
—— —
PM6 T
DSU
PMRD or PMENB Active to Data In
Valid (data setup time) 15 — — ns —
PM7 T
DHOLD
PMRD or PMENB Inactive to Data
In Invalid (data hold time) 1 T
PBCLK
— — ns PMP PBCLK
Note 1:
These parameters are characterized, but not tested in manufacturing.
PIC32MX5XX/6XX/7XX
DS60001156J-page 396 2009-2016 Microchip Technology Inc.
FIGURE 32-27: PARALLEL MASTER PORT WRITE TIMING DIAGRAM
T
PB
T
PB
T
PB
T
PB
T
PB
T
PB
T
PB
T
PB
PB Clock
PMALL/PMALH
PMD<7:0>
PMA<13:18>
PMWR
PMCS<2:1>
PMRD
PM12 PM13
PM11
Address
Address<7:0> Data
PM2 + PM3
PM1
TABLE 32-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typical Max. Units Conditions
PM11 T
WR
PMWR Pulse Width — 1 T
PB
—— —
PM12 T
DVSU
Data Out Valid before PMWR or
PMENB goes Inactive (data setup
time)
—2 T
PB
—— —
PM13 T
DVHOLD
PMWR or PMEMB Invalid to Data
Out Invalid (data hold time) —1 T
PB
—— —
Note 1:
These parameters are characterized, but not tested in manufacturing.
2009-2016 Microchip Technology Inc. DS60001156J- page 397
PIC32MX5XX/6XX/7XX
TABLE 32-42: USB OTG ELECTRICAL SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C T
A
+85°C for Industrial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Characteristics
(1)
Min. Typical Max. Units Conditions
USB313 V
USB
3
V
3
USB Voltage 3.0 — 3.6 V Voltage on V
USB
3
V
3
must be in this range for
proper USB operation
USB315 V
ILUSB
Input Low Voltage for USB Buffer — — 0.8 V —
USB316 V
IHUSB
Input High Voltage for USB Buffer 2.0 — — V —
USB318 V
DIFS
Differential Input Sensitivity — — 0.2 V The difference between
D+ and D- must exceed
this value while VCM is
met
USB319 VCM Differential Common Mode Range 0.8 — 2.5 V —
USB320 Z
OUT
Driver Output Impedance 28.0 — 44.0 —
USB321 V
OL
Voltage Output Low 0.0 — 0.3 V 1.425 k load
connected to V
USB
3
V
3
USB322 V
OH
Voltage Output High 2.8 — 3.6 V 14.25 k load
connected to ground
Note 1:
These parameters are characterized, but not tested in manufacturing.
PIC32MX5XX/6XX/7XX
DS60001156J-page 398 2009-2016 Microchip Technology Inc.
FIGURE 32-28: EJTA G TIMING CHARACTERISTICS
T
TCKcyc
T
TCKhigh
T
TCKlow
T
rf
T
rf
T
rf
T
rf
T
Tsetup
T
Thold
T
TDOout
T
TDOzstate
Defined Undefined
T
TRST*low
T
rf
TCK
TDO
TRST*
TDI
TMS
TABLE 32-43: EJTAG TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operati ng tem pera ture -40°C T
A
+85°C for Indust rial
-40°C T
A
+105°C for V-Temp
Param.
No. Symbol Description
(1)
Min. Max. Units Conditions
EJ1 T
TCKCYC
TCK Cycle Time 25 — ns —
EJ2 T
TCKHIGH
TCK High Time 10 — ns —
EJ3 T
TCKLOW
TCK Low Time 10 — ns —
EJ4 T
TSETUP
TAP Signals Setup Time Before
Rising TCK 5—ns —
EJ5 T
THOLD
TAP Signals Hold Time After
Rising TCK 3—ns —
EJ6 T
TDOOUT
TDO Output Delay Time from
Falling TCK —5ns —
EJ7 T
TDOZSTATE
TDO 3-State Delay Time from
Falling TCK —5ns —
EJ8 T
TRSTLOW
TRST Low T ime 25 — n s —
EJ9 T
RF
TAP Signals Rise/Fall Time, All
Input and Outpu t ——ns —
Note 1:
These parameters are characterized, but not tested in manufacturing.
2009-2016 Microchip Technology Inc. DS60001156J-page 399
PIC32MX5XX/6XX/7XX
33.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS
FIGURE 33-1: V
OH
– 4x DRIVER PINS
FIGURE 33-2: V
OH
– 8x DRIVER PINS
FIGURE 33-3: V
OL
– 4x DRIVER PINS
FIGURE 33-4: V
OL
– 8x DRIVER PINS
Note:
The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The p erformance c haracteristics l isted herein a re not tested or guaranteed. In some graphs , the data p resented may be outsid e the specifi ed operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
-0.050
-0.045
-0.040
-0.035
-0.030
-0.025
-0.020
IOH(A)
VOH (V)
-0.050
-0.045
-0.040
-0.035
-0.030
-0.025
-0.020
-0.015
-0.010
-0.005
0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
IOH(A)
VOH (V)
3V
3.3V
3.6V
Absolute Maximum
-0.080
-0.070
-0.060
-0.050
-0.040
0 030
IOH(A)
VOH(V)
-0.080
-0.070
-0.060
-0.050
-0.040
-0.030
-0.020
-0.010
0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
IOH(A)
VOH(V)
3V
3.3V
3.6V
Absolute Maximum
0.015
0.020
0.025
0.030
0.035
0.040
0.045
0.050
IOH(A)
VOL(V)
0.000
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.040
0.045
0.050
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
IOH(A)
VOL(V)
3V
3.3V
3.6V
Absolute Maximum
0020
0.030
0.040
0.050
0.060
0.070
0.080
IOH(A)
VOL(V) 8X
0.000
0.010
0.020
0.030
0.040
0.050
0.060
0.070
0.080
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
IOH(A)
VOL(V) 8X
3V
3.3V
3.6V
Absolute Maximum
PIC32MX5XX/6XX/7XX
DS60001156J-page 400 2009-2016 Microchip Technology Inc.
NOTES:
2009-2016 Microchip Technology Inc. DS60001156J- page 401
PIC32MX5XX/6XX/7XX
34.0 PACKAGING INFORMATION
34.1 Package Marking Information
PIC32MX575F
512H-80I/PT
0510017
3
e
Legend:
XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note:
In the event th e full Mi croch ip pa rt numbe r can not be ma rked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
64-Lead TQFP (10x10x1 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
100-Lead TQFP (12x12x1 mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
PIC32MX575F
512L-80I/PT
0510017
3
e
100-Lead TQFP (14x14x1 mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
PIC32MX575F
512L-80I/PF
0510017
3
e
PIC32MX5XX/6XX/7XX
DS60001156J-page 402 2009-2016 Microchip Technology Inc.
34.1 Package Marking Inf ormation (Continued)
XXXXXXXXXX
64-Lead QFN (9x9x0.9 mm)
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC32MX575F
Example
512H-80I/MR
0510017
3
e
XXXXXXXXXX
121-Lead TFBGA (10x10x1.1 mm)
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC32MX575F
Example
512H-80I/BG
0510017
3
e
Legend:
XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (las t 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Al pha nu me ric trac ea bil ity code
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note:
In the even t the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
XXXXXXXXXX
124-Lead VTLA (9x9x0.9 mm)
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC32MX795F
Example
512L-80I/TL
0510017
3
e
2009-2016 Microchip Technology Inc. DS60001156J- page 403
PIC32MX5XX/6XX/7XX
34.2 Package Details
The following sections give the technical details of the packages.
0.20 CA-B D
64 X b
0.08 CA-B D
C
SEATING
PLANE
4X N/4 TIPS
TOP VIEW
SIDE VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing C04-085C Sheet 1 of 2
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
D
EE1
D1
D
A B
0.20 HA-B D
4X
D1/2
e
A
0.08 C
A1
A2
SEE DETAIL 1
AA
E1/2
NOTE 1
NOTE 2
123
N
0.05
PIC32MX5XX/6XX/7XX
DS60001156J-page 404 2009-2016 Microchip Technology Inc.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
13°12°11°
E
Mold Draft Angle Bottom
13°12°11°
D
Mold Draft Angle Top
0.270.220.17
b
Lead Width
0.20-0.09
c
Lead Thickness
10.00 BSC
D1
Molded Package Length
10.00 BSCE1Molded Package Width
12.00 BSCDOverall Length
12.00 BSCEOverall Width
7°3.5°0°
I
Foot Angle
0.750.600.45LFoot Length
0.15-0.05A1Standoff
1.051.000.95A2Molded Package Thickness
1.20--AOverall Height
0.50 BSC
e
Lead Pitch
64NNumber of Leads
MAXNOMMINDimension Limits
MILLIMETERSUnits
Footprint L1 1.00 REF
2. Chamfers at corners are optional; size may vary.
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
Notes:
Microchip Technology Drawing C04-085C Sheet 2 of 2
L
(L1)
E
c
H
X
X=A—B OR D
e/2
DETAIL 1
SECTION A-A
T
2009-2016 Microchip Technology Inc. DS60001156J- page 405
PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC32MX5XX/6XX/7XX
DS60001156J-page 406 2009-2016 Microchip Technology Inc.
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2009-2016 Microchip Technology Inc. DS60001156J- page 407
PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC32MX5XX/6XX/7XX
DS60001156J-page 408 2009-2016 Microchip Technology Inc.
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'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
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1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
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2YHUDOO:LGWK ( %6&
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D
D1
E
E1
e
bN
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2009-2016 Microchip Technology Inc. DS60001156J- page 409
PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC32MX5XX/6XX/7XX
DS60001156J-page 410 2009-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2016 Microchip Technology Inc. DS60001156J- page 411
PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC32MX5XX/6XX/7XX
DS60001156J-page 412 2009-2016 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2016 Microchip Technology Inc. DS60001156J- page 413
PIC32MX5XX/6XX/7XX
B
A
0.10 C
0.10 C
(DATUM B)
(DATUM A)
2X
TOP VIEW
SIDE VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOTE 1
Microchip Technology Drawing C04-148 Rev F Sheet 1 of 2
D
E
2X
L
K
J
H
G
F
E
D
C
B
A
DETAIL B
e
D1
E1
e
A
BOTTOM VIEW
DETAIL A
A1
121-Ball Plastic Thin Profile Fine Pitch Ball Grid Array (BG) -
10x10x1.10 mm Body [TFBGA]
PIC32MX5XX/6XX/7XX
DS60001156J-page 414 2009-2016 Microchip Technology Inc.
Microchip Technology Drawing C04-148 Rev F Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
121-Ball Plastic Thin Profile Fine Pitch Ball Grid Array (BG) -
Dimension Limits
Units
D
Overall Width
Overall Length
Array Length
Array Width
D1
E1
E
MILLIMETERS
MIN MAX
10.00 BSC
Contact Diameter b
Notes:
1.
NOM
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Ball Height A1
Overall Height A
Contact Pitch e0.80 BSC
Number of Contacts N 121
0.25
0.40
10.00 BSC
1.20
8.00 BSC
8.00 BSC
3.
1.101.00
0.30 0.35
NX Øb
0.15 C A B
0.08 C
C
0.10 C
DETAIL A
DETAIL B
0.35 0.45
4. Ball interface to package body: 0.37mm nominal diameter.
Ball A1 visual index feature may vary, but must be located within the hatched area.
Dimensioning and tolerancing per ASME Y14.5M.
The outer rows and colums of balls are located with respect to datums A and B.
10x10x1.10 mm Body [TFBGA]
2009-2016 Microchip Technology Inc. DS60001156J- page 415
PIC32MX5XX/6XX/7XX
PIC32MX5XX/6XX/7XX
DS60001156J-page 416 2009-2016 Microchip Technology Inc.
2009-2016 Microchip Technology Inc. DS60001156J- page 417
PIC32MX5XX/6XX/7XX
PIC32MX5XX/6XX/7XX
DS60001156J-page 418 2009-2016 Microchip Technology Inc.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
RECOMMENDED LAND PATTERN
SILK SCREEN
Dimension Limits
Units
C1
Optional Center Pad Length
Contact Pad Spacing
Contact Pad Spacing
Optional Center Pad Chamfer (X4)
C2
W3
W2
0.10
6.60
MILLIMETERS
MIN MAX
8.50
8.50
Contact Pad Length (X124)
Contact Pad Width (X124)
X2
X1
0.30
0.30
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2193A
NOM
Optional Center Pad Width T2
Contact to Center Pad Clearance (X4) G5
Pad Clearance G4
Pad Clearance G3
Pad Clearance G2
Contact Pitch 0.50 BSCE
Pad Clearance G1
6.60
0.30
0.20
0.20
0.20
0.20
E
E/2
W2
W3
G2
G4
X1
G5
X4
C2
C1
G3
G1
X2
E
T2
124-Very Thin Leadless Array Package (TL) – 9x9x0.9 mm Body [VTLA]
2009-2016 Microchip Technology Inc. DS60001156J- page 419
PIC32MX5XX/6XX/7XX
APPENDIX A: MIGRATING FROM PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX
DEVICES
This appendix provides an overview of considerations
for migrating from PIC32MX3XX/4XX devices to the
PIC32MX5XX/6XX/7XX family of devices. The code
developed for the PIC32MX3XX/4XX devices can be
ported to the PIC32MX5XX/6XX/7XX devices after
making the appropriate changes outlined below.
A.1 DMA
PIC32MX5XX/6XX/7XX devices do not support
stopping DMA transfers in Idle mode.
A.2 Interrupts
PIC32MX5XX/6XX/7XX devices have persistent
interrupts for some of the peripheral modules. This
means that th e inte rrupt c onditi on for t hese periphe rals
must be cleared before the interrupt flag can be
cleared.
For example, to clear a UART receive interrupt, the
user application must first read the UART Receive
register to clear the interrupt condition and then clear
the associated UxIF flag to clear the pending UART
interrupt. In other words, the UxIF flag cannot be
cleared by software until the UART Receive register is
read.
Table A-1 outlines the peripherals and associated
interrupts that are implemented differently on
PIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XX
devices.
In addition, on the SPI module, the IRQ numbers for the
receive done interrupts were changed from 25 to 24
and the transf er done interrupt s were ch anged from 24
to 25.
TABLE A-1: PIC32MX3XX/4XX VERSUS PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION
DIFFERENCES
Module Interrupt Implementation
Input Capture To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of
capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits).
SPI Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF
register to obtain the number of data to receive/transmit below the level specified by the
SRXISEL<1:0> and STXISEL<1:0> bits.
UART TX interrupt will be generated as soon as the UART module is enabled.
Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits,
respec tiv ely. To clear an interrupt source, da ta must be rea d from, or written to, the UxR XRE G or
UxTXREG registers to obtain the number of data to receive/transmit below the level specified by
the URXISEL<1:0> and UTXISEL<1:0> bits.
ADC All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source.
PMP To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT)
register.
PIC32MX5XX/6XX/7XX
DS60001156J-page 420 2009-2016 Microchip Technology Inc.
APPENDIX B: REVISION HISTORY
Revision A (August 2009)
This is the initial released version of this document.
Revision B (November 2009)
The revision includes the following global update:
Added No te 2 to the shaded table that appears
at the beginning of each chapter. This new note
provide s informat ion regardin g the availabi lity of
registers and their associated bits.
Other major changes are referenc ed by their respective
chapter/ section in Table B-1.
TABLE B-1: MAJOR SECTION UPDATES
Section Name Update Description
“High-Performance, USB, CAN and
Ethernet 32-b it Flash
Microcontrollers”
Added the follow i ng dev ic es:
- PIC32MX575F256L
- PIC32MX695F512L
- PIC32MX695F512H
The 100-pi n TQ FP pi n dia gra ms hav e be en u pda ted to refl ec t the c urre nt pi n
name locations (see the
“Pin Diagrams”
section).
Added the 121-pin Ball Grid Array (XBGA) pin diagram.
Updated Table 1: “PIC32 USB and CAN – Features”
Added the follow i ng t ab les :
- Table 4: “Pin Names: PIC32MX534F064L, PIC32MX564F064L,
PIC32MX564F128L, PIC32MX575F256L and PIC32MX575F512L
Devices”
- Table 5: “Pin Names: PIC32MX664F064L, PIC32MX664F128L,
PIC32MX675F256L, PIC32MX675F512L and PIC32MX695F512L
Devices”
- Table 6: “Pin Names: PIC32MX775F256L, PIC32MX775F512L and
PIC32MX795F512L Devices”
Updated the following pins as 5V tolerant:
- 64-pin QFN: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 64-pin TQFP: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 100-pin TQFP: Pin 56 (D-/RG3) and Pin 57 (D+/RG2)
1.0 “Guidelines for Ge tting Started
with 32-bit Microc ontroll er s”
Removed the last sentence of
1.3.1 “Internal Regulator Mode”
.
Removed Section 2.3.2 “External Regulator Mode”
2009-2016 Microchip Technology Inc. DS60001156J- page 421
PIC32MX5XX/6XX/7XX
4.0 “Memory Organization”
Updated all register tables to include the Virtual Address and All Resets
columns.
Updated the title of Figure 4-4 to include the PIC32MX575F256L device.
Updated the title of Figure 4-6 to include the PIC32MX695F512L and
PIC32MX695F512H devices. Also changed PIC32MX795F512L to
PIC32MX795F512
H
.
Updated the title of Table 4-3 to include the PIC32MX695F512H device.
Updated the title of Table 4-5 to include the PIC32MX575F5256L device.
Updated the title of Table 4-6 to include the PIC32MX695F512L device.
Reversed the order of Table 4-11 and Table 4-12.
Reversed the order of Table 4-14 and Table 4-15.
Updated the title of Table 4-15 to include the PIC32MX575F256L and
PIC32MX695F512L devices.
Updated the title of Table 4-45 to include the PIC32MX575F256L device.
Updated the title of Table 4-47 to include the PIC32MX695F512H and
PIC32MX695F512L devices.
1.0 “I/O Ports”
Updated the second paragraph of
1.1.2 “Digital Inputs”
and removed Table
12-1.
22.0 “10-bit Analog-to-Dig ital
Converter (ADC)”
Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2).
1.0 “Special Features”
Removed references to the ENVREG pin in
1.3 “On-Chip Voltage
Regulator”
.
Updated the first sentence of
1.3.1 “On-Chip Regulator and POR”
and
1.3.2 “On-Chip Regulato r and BOR”
.
Updated the Connections for the On-Chip Regu lator (see Figure 1-2).
1.0 “Electrical Characteristics”
Updated the Absolute Maximum Ratings and added Note 3.
Added Thermal Packaging Characteristics for the 121-pin XBGA package
(see Table 1-3).
Updated the Operating Current (I
DD
) DC Characteristics (see Table 1-5).
Updated the Idle Current (I
IDLE
) DC Characteristics (see Table 1-6).
Updated the Power-Down Current (I
PD
) DC Characteristic s (see Table 1-7).
Removed Note 1 from the Program Flash Memory Wait State Characteristics
(see Table 1-12).
Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics,
changin g SP52 to SP35 betwee n the MSb and Bit 14 on SDOx (see Figu re 1-
13).
1.0 “Packaging Information”
Added the 121-pin XBGA package marking information and package details.
“Product Identification System”
Added the definition for BG (121-lead 10x10x1.1 mm, XBGA).
Added the definition for Speed.
TABLE B-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
PIC32MX5XX/6XX/7XX
DS60001156J-page 422 2009-2016 Microchip Technology Inc.
Revision C (February 2010)
The revision includes the following updates, as
des cribed in Table B-2:
TABLE B-2: MAJOR SECTION UPDATES
Section Name Update Description
“High-Performance, USB, CAN
and Ethernet 32-bit Flash
Microcontrollers”
Added the following devices:
• PIC32MX675F256H
• PIC32MX775F256H
• PIC32MX775F512H
• PIC32MX675F256L
• PIC32MX775F256L
• PIC32MX775F512L
Added the following pins:
•EREFCLK
• ECRSDV
• AEREFCLK
• AECRSDV
Added the EREFCLK and ECRSDV pins to Table 5 and Table 6.
1.0 “Devi ce Ov er vie w”
Updated the pin number pinout I/O descriptions for the following pin names in
Table 1-1:
Added the following pins to the Pinout I/O Descriptions table (Table 1-1):
•EREFCLK
• ECRSDV
• AEREFCLK
• AECRSDV
4.0 “Memory Organization”
Added new devices and updated the virtual and physical memory map values in
Figure 4-4.
Added new devices to Figure 4-5.
Added new devices to the following register maps:
• Table 4-3, Table 4-4, Table 4-6 and Ta ble 4-7 (Interrupt Register Maps)
• Table 4-12 (I2C2 Register Map)
• Table 4-15 (SPI1 Register Map)
• Table 4-24 through Table 4-35 (PORTA-PORTG Register Maps)
• Table 4-36 and Table 4-37 (Change Notice and Pull-up Register Maps)
• Table 4-45 (CAN1 Register Map)
• Table 4-46 (CAN2 Register Map)
• Table 4-47 (Ethernet Controller Register Map)
Changed the bits named POSCMD to POSCMOD in Table 4-42 (Device
Configuration Word Summary).
1.0 “Special Features”
Changed all references of POSCMD to POSCMOD in the Device Configuration
Word 1 register (see Register 1-2).
Appendix A: “Migrating from
PIC32MX3XX/4XX to
PIC32MX5XX/6 XX/7XX
Devices”
Added the new section Appendix .
•SCL3 •SCL5 •RTCC •C1OUT
• SDA3 • SDA5 • CV
REF
-•C2IN-
• SCL2 • TMS • CV
REF
+•C2IN+
• SDA2 • TCK • CV
REFOUT
•C2OUT
• SCL4 • TDI • C1IN- • PMA0
• SDA4 • TDO • C1IN+ • PMA1
2009-2016 Microchip Technology Inc. DS60001156J- page 423
PIC32MX5XX/6XX/7XX
Revision D (May 2010)
The revision includes the following updates, as
des cribed in Table B-3:
TABLE B-3: MAJOR SECTION UPDATES
Section Name Update Description
“High-Performance, USB, CAN
and Ethernet 32-bit Flash
Microcontrollers”
Updated the initial Flash memory range to 64K.
Updated the initial SRAM memory range to 16K.
Added the following devices (see Table 1, Table 2, Table 3 and the Pin
Diagrams):
• PIC32MX534F064H
• PIC32MX564F064H
• PIC32MX664F064H
• PIC32MX564F128H
• PIC32MX664F128H
• PIC32MX764F128H
• PIC32MX534F064L
• PIC32MX564F064L
• PIC32MX664F064L
• PIC32MX564F128L
• PIC32MX664F128L
• PIC32MX764F128L
4.0 “Memory Organization”
Added new Memory Maps (Figure 4-1, Figure 4-2 and Figure 4-3).
The bit named I2CSIF was changed to I2C1SIF and the bit named I2CBIF was
changed to I2C1BIF in the Interrupt R egister Map tables (Table 4-2, Table 4-3,
Table 4-4, Table 4-5, Table 4-6 and Table 4-7)
Added the following devices to the Interrupt Register Map (Table 4-2):
• PIC32MX534F064H
• PIC32MX564F064H
• PIC32MX564F128H
Added the following devices to the Interrupt Register Map (Table 4-3):
• PIC32MX664F064H
• PIC32MX664F128H
Added the following device to the Interrupt Register Map (Table 4-4):
• PIC32MX764F128H
Added the following devices to the Interrupt Register Map (Table 4-5):
• PIC32MX534F064L
• PIC32MX564F064L
• PIC32MX564F128L
Added the following devices to the Interrupt Register Map (Table 4-6):
• PIC32MX664F064L
• PIC32MX664F128L
Added the following device to the Interrupt Register Map (Table 4-7):
• PIC32MX764F128L
PIC32MX5XX/6XX/7XX
DS60001156J-page 424 2009-2016 Microchip Technology Inc.
4.0 “Memory Organization”
(Continued)
Made the following bit name changes in the I2C1, I2C3, I2C4 and I2C5 Register
Map (Table 4-11):
• I2C3BRG SFR: I2C1BRG was changed to I2C3BRG
• I2C4BRG SFR: I2C1BRG was changed to I2C4BRG
• I2C5BRG SFR: I2C1BRG was changed to I2C5BRG
• I2C4TRN SFR: I2CT1DATA was changed to I2CT2ADATA
• I2C4RCV SFR: I2CR2DATA wa s changed to I2CR2ADATA
• I2C5TRN SFR: I2CT1DATA was changed to I2CT3ADATA
• I2C5RCV SFR: I2CR1DATA wa s changed to I2CR3ADATA
Added the RTSMD bit and UEN<1:0> bits to the UART1A, UART1B, UART2A,
UART2B, UART3A and UART3B Register Map (Table 4-13)
Added the SIDL bit to the DMA Global Register Map (Table 4-17).
Changed the CM bit to CMR in the System Control Register Map (Table 4-23).
Added the following devices to the I2C2, SPI1, PORTA, PORTC, PORTD,
PORTE, PORTF, PORTG, Change Notice and Pull-up Register Maps (Table 4-12,
Table 4-14, Table 4-24, Table 4-27, Table 4-29, Table 4-31, Table 4-33, Table 4-35
and Table 4-36):
• PIC32MX534F064L
• PIC32MX564F064L
• PIC32MX564F128L
• PIC32MX664F064L
• PIC32MX664F128L
• PIC32MX764F128L
Added the following devices to the PORTC, PORTD, PORTE, PORTF, PORTG,
Change Notice and Pull-up Register Maps (Table 4-26, Table 4-28, Table 4-30,
Table 4-32, Table 4-34 and Table 4-37):
• PIC32MX534F064H
• PIC32MX564F064H
• PIC32MX564F128H
• PIC32MX664F064H
• PIC32MX664F128H
• PIC32MX764F128H
Added the following devices to the CAN1 Register Map (Table 4-45):
• PIC32MX534F064H
• PIC32MX564F064H
• PIC32MX564F128H
• PIC32MX764F128H
• PIC32MX534F064L
• PIC32MX564F064L
• PIC32MX564F128L
• PIC32MX764F128L
Added the fo llow ing dev ices to the Ethernet C ontrol ler Regis ter Map (Table 4-47):
• PIC32MX664F064H
• PIC32MX664F128H
• PIC32MX764F128H
• PIC32MX664F064L
• PIC32MX664F128L
• PIC32MX764F128L
TABLE B-3: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
2009-2016 Microchip Technology Inc. DS60001156J- page 425
PIC32MX5XX/6XX/7XX
1.0 “Electrical Characteristics”
Update d the Typical a nd Max imum D C Cha racteris tics: O peratin g Curr ent (I
DD
) in
Table 1-5.
Updated the Typical and Maximum DC Characteristics: Idle Current (I
IDLE
) in
Table 1-6.
Update d the T ypic al and Maxi mum DC C haracteristic s: Power-Dow n Current (I
PD
)
in Table 1-7.
Added DC Characteristics: Program Memory parameters D130a and D132a in
Table 1-11.
Added the Internal Voltage Reference parameter (D305) to the Comparator
Specifications in Table 1-13.
TABLE B-3: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
PIC32MX5XX/6XX/7XX
DS60001156J-page 426 2009-2016 Microchip Technology Inc.
Revision E (July 2010)
Minor corrections were incorporated throughout the
document.
Revision F (December 2010)
The revision includes the following global update:
V
CAP
/V
DDCORE
has been changed to: V
CAP
/V
CORE
Other major changes are referenced by their respective
chapter/section in Table B-4:
TABLE B-4: SECTION UPDATES
Section Name Update Description
High-Performance, USB, CAN and
Ethernet 32-bit Flash Mic rocon trolle rs
Removed the following A nalog Fe ature: FV tol erant input pins
(digital pins only)
Updated the term LIN 1.2 support as LIN support for the peripheral
feature: Six UART modules with: RS-232, RS-485, and LIN support
1.0 “Devi ce Ov er vie w”
Updated the value of 64-pin QFN/TQFP pin number for the following pin
names: PMA0, PMA1 and ECRSDV
4.0 “Memory Organization”
The following register map tables were updated:
• Table 4-2:
- Changed bits 24/8 to I2C5BIF in IFS1
- Changed bits 24/8-24/10 to SRIPL<2:0> in INTSTAT
- Changed bits 25/9/-24/8 to U5IS<1:0> in IPC12
- Added note 2
• Table 4-3 through Table 4-7:
- Changed bits 24/8-24/10 to SRIPL<2:0> in INTSTAT
- Changed bits 25/9-24/8 to U5IS<1:0> in IPC12
• Table 4-3:
- Changed bits 24/8 to I2C5BIF in IFS1
- Added note 2
• Table 4-4:
- Changed bits 24/8 to I2C5BIF in IFS1
- Changed bits 24/8 to I2C5BIE in IEC1
- Added note 2 references
• Table 4-5:
- Changed bits 24/8 to I2C5BIF in IFS1
- Changed bits 24/8 to I2C5BIE in IEC1
- Added note 2 references
• Table 4-6:
- Changed bit 24/8 to I2C5BIF in IFS1
- Updated the bit value of bit 24/8 as I2C5BIE for the IEC1 register.
- Added note 2
• Table 4-7:
- Changed bit 25/9 to I2C5SIF in IFS1
- Changed bit 24/8 as I2C5BIF in IFS1
- Changed bit 25/9 as I2C5SIE in IEC1
- Changed bit 24/8 as I2C5BIE in IEC1
- Added note 2 references
• Added note 2 to Table 4-8
• Updated the All Resets values for the following registers in Table 4-11:
I2C3CON, I2C4CON, I2C5CON and I2C1CON.
• Updated the All Resets values for the I2C2CON register in Table 4-12
2009-2016 Microchip Technology Inc. DS60001156J- page 427
PIC32MX5XX/6XX/7XX
4.0 “Memory Organization”
(Continued) • Table 4-13:
- Changed register U4RG to U1BRG
- Changed register U5RG to U3BRG
- Changed register U6RG to U2BRG
• Table 4-14:
- Updated the All Resets values for the following registers: SPI3STAT,
SPI2STAT and SPI4STAT
• Table 4-15: Updated the All Resets values for the SPI1STAT register
• Table 4-17: Added note 2
• Table 4-19: Added note 2
• Table 4-20: Updated the All Resets values for the CM1CON and
CM2CON registers
• Table 4-21:
- Updated the All Resets values as 0000 for the CVRCON register
- Updated note 2
• Table 4-38: Updated the All Resets values for the PMSTAT register
• Table 4-40: Updated the All Resets values for the CHECON and
CHETAG registers
• Table 4-42: Updated the bit value of bit 29/13 as ‘—’ for the DEVCFG3
register
• Table 4-44:
- Updated the note references in the entire table
- Changed exis ting note 1 to note 4
- Added notes 1, 2 and 3
- Changed bits 23/7 in U1PWRC to UACTPND
- Changed register U1DDR to U1ADDR
- Changed register U4DTP1 to U1BDTP1
- Changed register U4DTP2 to U1BDTP2
- Changed register U4DTP3 to U1BDTP3
• Table 4-45:
- Updated the All Resets values for the C1CON and C1VEC registers
- Changed bits 30/14 in C1CON to FRZ
- Changed bits 27/11 in C1CON to CANBUSY
- Changed bits 22/6-16/0 in C1VEC to ICODE<6:0>
- Changed bits 22/6-16/0 in C1TREC to RERRCNT<7:0>
- Changed bits 31/15-24/8 in C1TREC to TERRC NT<7:0>
• Table 4-46:
- Updated the All Resets values for the C2CON and C2VEC registers
- Changed bits 30/14 in C1CON to FRZ
- Changed bits 27/11 in C1CON to CANBUSY
- Changed bits 22/6-16/0 in C1VEC register to ICODE<6:0>
- Changed bits 22/6-16/0 in C1TREC register to RERRCNT<7:0>
- Changed bits 31/15-24/8 in C1TREC to TERRC NT<7:0>
TABLE B-4: SECTION UPDATES (CONTINUED)
Section Name Update Description
PIC32MX5XX/6XX/7XX
DS60001156J-page 428 2009-2016 Microchip Technology Inc.
7.0 “Interrupt Controller”
• Updated the following Interrupt Sources in Table 7 -1:
- Changed IC2AM – I2C4 Master Event to: IC4M – I2C4 Master Event
- Changed IC3AM – I2C5 Master Event to: IC5M – I2C4 Master Event
- Changed U1E – UART1A Error to: U1 E – UART1 Error
- Changed U4E – UART1B Error to: U4 E – UART4 Error
- Changed U1RX – UART1A Receiver to: U1RX – UART1 Receiver
- Changed U4RX – UART1B Receiver to: U4RX – UART4 Receiver
- Changed U1TX – UART1A T ransmitter to: U1TX – UART1 Transmitter
- Changed U4TX – UART1B T ransmitter to: U4TX – UART4 Transmitter
- Changed U6E – UART2B Error to: U6 E – UART6 Error
- Changed U6RX – UART2B Receiver to: U6RX – UART6 Receiver
- Changed U6TX – UART2B T ransmitter to: U6TX – UART6 Transmitter
- Changed U5E – UART3B Error to: U5 E – UART5 Error
- Changed U5RX – UART3B Receiver to: U5RX – UART5 Receiver
- Changed U5TX – UART3B T ransmitter to: U5TX – UART5 Transmitter
1.0 “Oscillator Co nfigu ration”
Updated Figure 1-1
1.0 “Output Compare”
Updated Figure 1-1
1.0 “Ethernet Controller”
Added a note on using the Ethernet controller pins (see note above
Table 1-3)
1.0 “Comparator Voltage Refer ence
(CV
REF
)”
Updated the note in Figure 1-1
1.0 “Special Features”
Updated the bit descriptio n for bit 10 in Register 1-2
Added notes 1 and 2 to Register 1-4
1.0 “Electrical Characteristics”
Updated the Absolute Maxi mum Ratings:
• Voltage on any 5V tolerant pin with respect to V
SS
when V
DD
< 2.3V -
0.3V to +3.6V was updated
• Volta ge on V
BUS
with respect to V
SS
- 0.3V to +5.5V was added
Updated the maximum value of DC16 as 2.1 in Table 1-4
Updated the Typical values for the following parameters: DC20b, DC20c,
DC21c, DC22c and DC23c (see Table 1-5)
Updated Table 1-11:
• Removed the following DC Characteristics: Programming temperature
0°C TA +70° C (25°C recommended )
• Updated the Minimum value for the Parameter number D131 as 2.3
• Removed the Conditions for the following Parameter numbers: D130,
D131, D132, D135, D136 and D137
• Updated the condition for the parameter number D130a and D132a
Updated the Minimum, Typical and Maxi mum values for parameter D305
in Table 1-13
Added note 2 to Table 1-18
Updated the Minimum an d Maximu m values fo r parameter F20b (see
Table 1-19)
Updated the following figures:
• Figure 1-4
• Figure 1-9
• Figure 1-22
• Figure 1-23
Appendix A: “Migrating from
PIC32MX3XX/4XX to PIC32MX5XX/
6XX/7XX Devices”
Removed the A.3 Pin Assignments sub-section.
TABLE B-4: SECTION UPDATES (CONTINUED)
Section Name Update Description
2009-2016 Microchip Technology Inc. DS60001156J- page 429
PIC32MX5XX/6XX/7XX
Revision G (May 2011)
The revision includes the following global updates:
• All references to V
DDCORE
/V
CAP
have been
changed to: V
CORE
/V
CAP
• Added references to the new V-Temp temperature
range: -40ºC to +105ºC
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
Major updates are referenced by their respective
section in Table B-5.
TABLE B-5: MAJOR SECTION UPDATES
Section Name Update Description
High-Performance, USB, CAN and
Ethernet 32-bit Flash Mic rocon trolle rs
Removed the shading for all D- and D+ pi ns in all pin diagrams.
1.0 “Devi ce Ov er vie w”
Updated the V
BUS
description in Table 1-1.
1.0 “Guidelines for G etting St arted with
32-bit Microcon trolle rs ”
Added
“Alternativel y, input s can be reserved by conne cting the pin
to Vss through a 1k to 10k resistor and configuring the pin as an
input.”
.
4.0 “Memory Organization”
Added Not e 3 to the Interrupt Regi ster Map tabl es (see Table 4-2 through
Table 4-7.
22.0 “10-bit Analog-to-Digital Converter
(ADC)”
Updated the ADC Conversion Clock Period Block Diagram (see
Figure 22-2).
1.0 “Comparator Voltage Refer ence
(CV
REF
)”
Updated the Comparator Voltage Reference Block Diagram (see
Figure 1-1).
1.0 “Special Features”
Removed the second paragraph from
1.3.1 “On-Chip Regulator and
POR”
.
1.0 “Electrical Characteristics”
Added the new V-Temp temperature range (-40ºC to +105ºC) to the
heading of all specification tables.
Updated the Ambient temperature under bias, updated the Voltage on
any 5V tolerant pin with respect to V
SS
when V
DD
< 2.3V, and added
Voltage on V
BUS
with respect to Vss in Absolute Maximum Ratings.
Added the characteristic, DC5a to Operating MIPS vs. Voltage (see
Table 1-1).
Updated or added the following parameters to the Operating Current
(I
DD
) DC Char acteris tics : DC20, DC20b , DC23, and DC 23b (s ee Tab le 1-
5).
Added the following parameters to the Idle Current (I
IDLE
) DC
Characteristics: DC30b, DC33b, DC34c, DC35c, and DC36c (see
Table 1-6).
Added the following parameters to the Power-down Current (I
PD
) DC
Characteristics: DC40g, DC40h, DC40i, and DC41g, (see Table 1-7).
Added parameter IM51 and Note 3 to the I2Cx Bus Data Timing
Requirements (Master Mode) (see Table 1-32).
Updated the 10-bit ADC Conversion Rate Parameters (see Table 1-37).
Updated parameter AD57 (T
SAMP
) in the Analog-to-Digital Conversion
Timing Requirements (see Table 1-38).
1.0 “Packaging Information”
Updated the 64-Lead Plastic Quad Flat, No Lead Package (MR) –
9x9x0.9 mm Body [QFN] packing diagram.
Product Identification System
Added the new V-Temp (V) temperature information.
PIC32MX5XX/6XX/7XX
DS60001156J-page 430 2009-2016 Microchip Technology Inc.
Revision H (March 2013)
This revision includes the following global updates:
• Where applicable, control register tables have
been added to the document
• All references to V
CORE
were removed
• All occurrences of X BGA have b een updated to:
TFBGA
• All occurrences of V
USB
have been updated to:
V
USB
3
V
3
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
All other significant changes are referenced by their
respective section in Table B-6.
TABLE B-6: MAJOR SECTION UPDATES
Section Name Update Description
“32-bit Microcontrollers
(up to 512 KB Flash and 128
KB SRAM) with Graphics
Interface, USB, CAN, and
Ethernet”
Updated Core feat ures .
Added the VTLA to the Packages table.
Added Note 5 to the Feature tables (see Table 1, Table 2, and Table 3).
Section 2.0 “Guidelines for
Getting Started with 32-bit
MCUs”
The Recommended Minimum Connection was updated (see Figure 2-1).
Section 5.0 “Flas h Program
Memory”
A note regarding Flash page size and row size was added.
Section 8.0 “Oscillator
Configuration”
The R
P
resistor was added and Note 1 was updated in the Oscillator Diagram (see
Figure 8-1).
Section 31.0 “Electrical
Characteristics”
Added Note 1 to Operating MIPS vs. Voltage (see Table 31-1).
Added the VTLA package to Thermal Packaging Ch aracteristics (see Table 31-3).
Added Note 2 to DC Temperature and Voltage Specifications (see Table 31-4).
Updated Note 2 in the Operating Current DC Characteristics (see Table 31-5).
Updated Note 1 in the Idle C urrent DC Characteristics (see Table 31-6).
Updated Note 1 in the Power-Down Current DC Characteristics (see Table 31-7).
Updated the I/O Pin Output Specifications (see Table 31-9).
Added Note 2 to the BOR Electrical Characteristics (see Table 31-10).
Added Note 3 to the Comparator Specifications (see Table 31-13).
Parameter D320 (V
CORE
) was removed (see Table 31-15).
Updated the Minimum value for parameter OS50 (see Table 31-18).
Parameter SY01 (T
PWRT
) was removed (see Table 31-22).
Note 1 was added and the conditions for parameters ET3, ET4, ET7, and ET9 we re
updated in the Ethernet Module Specifications (see Table 31-35).
Added Note 6 to the ADC Module Specifications (see Table 31-36).
Added Note 3 to the 10-bit ADC Conversion Rate Parameter (see Table 31-37).
Added Note 4 to the Analog-to-Digital Conversion Timing Requirements (see
Table 31-38).
The following figures were added:
Figure 31-19: “MDIO Sourced by the PIC32 Device”
Figure 31-21: “Transmit Signal Timing Relationships at the MII”
Figure 31-22: “Receive Signal Timing Relationships at the MII”
Section 32.0 “DC and AC
Device Characteristics
Graphs”
This new chapter was added.
Section 33.0 “Packaging
Information”
Added the 124-lead VTLA package information (see
Section 33.1 “Package
Marking Information”
and
Section 33.2 “Package Details”
).
“Product Identification
System”
Added the TL definition for VTLA packages.
2009-2016 Microchip Technology Inc. DS60001156J- page 431
PIC32MX5XX/6XX/7XX
Revision J (September 2016)
This revision includes typographical and formatting
updates throughout the data sheet text. In addition, all
SFR Register maps were moved from the Memory
chapter to their respective peripheral chapters.
All other major updates are referenced by their
respective section in Table B-7.
TABLE B-7: MAJOR SECTION UPDATES
Section Name Update Description
“32-bit Microcontroll ers (up to 512
KB Flash and 128 KB SRAM) with
Graphics Interface, USB, CAN, and
Ethernet”
Updated Communication Interfaces for LIN support to 2.1.
Updated Qualification and Class B Support to AEC-Q100 REVH.
2.0 “Guidelines for Getting Started
with 32-bit MCUs”
The Recommended Minimum Connection diagram was updated (see
Figure 2-1).
The Example of MCLR Pin C onn ec tion s dia gram was upda ted (see Figure 2-
2).
2.11 “EMI/EMC/EFT (IEC 61000-4-4 and IEC 61000-4-2) Suppression
Considerations”
was added.
4.0 “Memory Organization”
The SFR Memory Map was added (see Table 4-1).
7.0 “Interrupt Controller”
The UART interrupt sources were updated in the Interrupt IRQ, Vector, and
Bit location table (see Table 7-1).
8.0 “Oscillator Configu ration ”
Updated the bit value definitions for the TUN<5:0> bits in the OCSTUN
register (s ee Register 8-2).
15.0 “Watchdog Timer (WDT)”
The content in this chapter was relocated from the Special Features chapter
to its own chapter.
18.0 “Serial Peripheral Interface
(SPI)”
The register map tables were combined (see Table 18-1).
19.0 “Inter-Integrated Circuit (I
2
C)”
The register map tables were combined (see Table 19-1).
The PMADDR register was updated (see Register 21-3).
21.0 “Parallel Master Port (PMP)”
The bit value definitions for the ADRMUX<1:0> and CSF<1:0> bits in the
PMCON register were updated (see Register 21-1).
29.0 “Special Features”
Removed the duplicate bit value definition for ‘010’ in the DEVCFG2 register
(see Register 29-3).
Note 1 was added to the Programming, Debugging, and Trace Ports block
diagr am (se e Figure 29-2).
The DDPCON register was relocated (see Register 29-6).
The Device ID, Revision, and Configuration Summary was updated (see
Table 29-2).
PIC32MX5XX/6XX/7XX
DS60001156J-page 432 2009-2016 Microchip Technology Inc.
32.0 “Electrical Characterist ics”
Note 4 in the Operating Current specification was updated (see Table 32-5).
Note 3 in the Idle Current specification was updated (see Table 32-6).
Note 6 references in the Power-Down Current specification were updated
(see Table 32-7).
The Program Memory parameters, D135, D136, and D137, and Note 4 were
updat ed (see Table 32-11).
The Voltage Reference Specifications were updated (see Table 32-14).
Parameter DO50 (Cosco) was added to the Capacitive Loading
Requirements on Output Pins (see Table 32-16).
The EJTAG Timing Characteristics were updated (see Figure 32-28).
The maximum value for parameters ET13 and ET14 were updated in the
Ethernet Module Specifications (see Table 32-35).
Parameter PM7 (T
DHOLD
) was update d (see Table 32-40).
34.0 “Packaging Information”
Packagi ng dia gram s were update d.
Product Identification System
The Speed and Program Memory Size were updated and Note 1 was added.
TABLE B-7: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
2009-2016 Microchip Technology Inc. DS60001156J- page 433
PIC32MX5XX/6XX/7XX
INDEX
A
AC Characteristics............................................................366
10-bit Conve rsion Rate Parameters..........................390
ADC Specifications...................................................388
Analog-to-Digital Conversion Requirements.............391
EJTAG Timing Requirements ...................................398
Ethernet ....................................................................386
Internal FRC Accuracy..............................................368
Internal RC Accuracy................................................369
OTG Electrical Specifications ...................................397
Parallel Master Port Read Requirements .................395
Paral l e l Master Port Write................................... ......396
Paral l e l Master Port Write Requirements..................396
Parallel Slave Port Requirements.............................394
PLL Clock Timing......................................................368
Analog-to-Digital Converter (ADC)....................................231
B
Block Diagrams
ADC1 Module............................................................231
Comparator I/O Operating Modes.............................323
Comparator Voltage Reference................................327
Connections for On-Chip Voltage Regulator. . ...........343
Core and Peripheral Modules.....................................25
DMA..........................................................................111
Ethern e t C o n troller.............. ........... .......... .................279
I2C Circuit.................................................................196
Input Capture......................................... .. .... ....... .... ..181
Inter rupt Controller.................. .............................. ......73
JTAG Programm ing, Debugging and Trace Ports ....343
MCU............................................................................41
Outpu t C o mpa re Module... ................... ........... ..........185
PIC32 CAN Module...................................................241
PMP Pinout and Connections to External Devices...211
Prefetch Module........................................................101
Reset System... ........... ................... ................... ..........69
RTCC........................................................................221
SPI Module ...............................................................189
Timer1.......................................................................167
Timer2 /3 /4/5 (16-Bit)............. ....................................171
Typical Multiplexed Port Struct ure............................157
UART........................................................................203
WDT and Power-up Timer .................................... ....177
Brown-out Reset (BOR)
and On-Chip Voltage Regulator................................343
C
C Compilers
MPLAB XC..... ................... ................... ................... ..348
Clock Diagram ....................................................................95
Comparator
Specifications............................................................364
Comparator Module ...................... .. ......... .... .. .... ....... .... ....323
Comparator Voltage Reference (CVref.............................327
Configuration Bits..............................................................333
Contro ller Area Networ k (CAN)...................... ...................241
CPU Module ........................................................................37
Customer Change Notification Service .............................437
Custom e r No tification Serv ice...........................................437
Customer Support.............................................................437
D
DC and AC Characteristics
Graphs and Tables................................................... 399
DC Characteristics............................................................ 352
I/O Pin Input Specifications ...................................... 360
I/O Pin Outpu t Specifications.......................... .......... 362
Idle Current (I
IDLE
).................................................... 356
Power-Down Current (I
PD
)........................................ 358
Program Memory...................................................... 363
Temperature and Voltage Specifications .................. 353
Development Support....................................................... 347
Direct Memory Access (DMA) Controller.......................... 111
E
Electrical Characteristics .................................................. 351
AC............................................................................. 366
Errata.................................................................................. 23
Ethern e t C o n troller...... ............................. ......................... 279
ETHPMM0 (Ethernet Controller Pattern Match Mask 0)... 289
ETHPMM1 (Ethernet Controller Pattern Match Mask 1)... 289
External Clock
Timer1 Timing Requirements. .................................. 372
Timer2, 3, 4, 5 Timing Requirements ....................... 373
Timing R equirements ................ ................... ............ 367
F
Flash Program Memory............... ..................................... .. 63
RTSP Opera tio n............. ............................................ 63
I
I/O Ports ....................... ................... .......... ................... .... 157
Parallel I/O (PIO) ...................................................... 158
Input Captur e.................................................................... 181
Instruction Set................................................................... 345
Inter-Integrated Circuit (I2C)............................................. 195
Internal Voltag e Reference Specifications........................ 365
Inter net Address.................................... ................... ........ 437
Interrupt Controller.............................................................. 73
IRG, Vector and Bit Location... ................................... 74
M
MCUArchitecture Overview ................................................ 42
Copro cessor 0 Registers.................................. .......... 43
Core Ex ception Types................................................ 44
EJTAG Debug Support............................................... 45
Power Management ................................................... 45
MCU Module...................................... .... .. .... ......... .... .... .. .... 41
Memory M ap....................................................................... 52
Memory M aps............................................. 48, 49, 50, 51, 53
Memory Organization ......................................................... 47
Layout......................................................................... 47
Microc h i p Internet Web Site................... ........... ................ 437
Migration
PIC32MX3XX /4XX to PIC32MX5XX/6XX/7XX......... 419
MPASM Assembler........................................................... 348
MPLAB Assembler, Linker, and Librarian......................... 348
MPLAB ICD 3 In-Circuit Debugger System...................... 349
MPLAB PM3 Device Programmer.................................... 349
MPLAB R EA L ICE In-Circuit Emul ator System........ ........ 349
MPLAB X Integrated Development Environment Software ....
347
MPLINK Object Linker/MPLIB Object Librarian................ 348
O
Open-Drain Configuration................................................. 158
PIC32MX5XX/6XX/7XX
DS60001156J-page 434 2009-2016 Microchip Technology Inc.
Oscillator Configuration. ......................................................95
Outpu t C o mpa re............... ................... ..............................185
P
Packaging .........................................................................401
Details.......................................................................403
Marking .....................................................................401
Paralle l Master Port (PMP) ......... .......... ........... .......... .......211
PIC32 Fa mily USB Interface Diagram...................... .........134
PICkit 3 In-Circuit Debugger/Programmer ........................349
Pinout I/O Descriptions (table). ...........................................26
Power-on Reset (POR)
and On-Chip Voltage Regulator................................343
Power-Saving Features.....................................................331
CPU Halted Methods ................................................331
Operation ..................................................................331
with CPU Running.....................................................331
Prefe tc h Cache ............................................ .....................101
Program Flash Memory
Wait State Characteristics.........................................363
R
Real-Time Clock and Calendar (RTCC). ...........................221
Register Maps............................................................ .55–283
Registers
AD1CHS (ADC In put Select) ....................................239
AD1CON1 (ADC Control 1) ......................................235
AD1CON2 (ADC Control 2) ......................................237
AD1CON3 (ADC Control 3) ......................................238
AD1CSSL (ADC Input Scan Select) .........................240
ALRMDA TE (Alarm Date Value )........................ .......230
ALRMTIME (Alarm Time Value) ...............................229
BMXB OO TSZ ( Bo ot Flash ( I FM) Size ) ....... .. ...... .. ..... .61
BMXCON (Bu s Matrix Con fig u ration) ............ .............56
BMXDKPB A (Data RAM Kernel Progr am
Base Add ress) ...................... ............................ ..57
BMXDRMSZ (Data RAM Size) ...................................60
BMXDUDBA (Data RAM User Data Base Address)...58
BMXDUPBA (Data RAM User Program
Base Add ress) ...................... ............................ ..59
BMXPFMSZ (Program Flash (PFM) Size)..................61
BMXPUPB A (Progr am Flas h (PF M) User Pr ogram
Base Add ress) ...................... ............................ ..60
CHEACC (Cache Access) ........................................104
CHECON (Cache Control)........................................103
CHEHIT (Cache Hit Statistics)..................................109
CHELRU ( Cac h e LRU)..... ................... .....................108
CHEMI S (Ca che Miss Statistics) .... ................... .......109
CHEMSK (Ca che TAG Mask).............. ................... ..106
CHETAG (Cache TAG).............................................105
CHEW0 (Cache Word 0)...........................................106
CHEW1 (Cache Word 1)...........................................107
CHEW2 (Cache Word 2)...........................................107
CHEW3 (Cache Word 3)...........................................108
CiCFG (CAN Baud Rate Configuration)....................248
CiCON (CAN Module Control) ..................................246
CiFIFOBA (CAN Message Buffer Base Address).....273
CiFIFOCINn (CAN Module Message Index Register ‘n’)
278
CiFIFOCONn (CAN FIFO Control R e g i ster ‘n’).........274
CiFIFO IN Tn (CAN FIFO Inte r rup t Register ‘n’).........276
CiFIFOUAn (CAN FIFO User Address Register ‘n’). .278
CiFLTCON0 (CAN Filter Control 0)...........................256
CiFLTCON1 (CAN Filter Control 1)...........................258
CiFLTCON2 (CAN Filter Control 2)...........................260
CiFLTCON3 (CAN Filter Control 3)...........................262
CiFLTCO N 4 (C AN Fi l te r C o n trol 4) .......... ..... .......... . 264
CiFLTCO N 5 (C AN Fi l te r C o n trol 5) .......... ..... .......... . 266
CiFLTCO N 6 (C AN Fi l te r C o n trol 6) .......... ..... .......... . 268
CiFLTCO N 7 (C AN Fi l te r C o n trol 7) .......... ..... .......... . 270
CiFSTAT (CAN FIFO Status).................................... 253
CiINT (CAN Interrupt)............................................... 250
CiRXFn (CAN Acceptance Filter ‘n’).........................272
CiRXMn (CAN Acce ptance Filt e r Mask ‘n’) .............. 255
CiRXOVF (CAN Receive FIFO Overflow Status) ..... 254
CiTMR (CAN Timer) ................................................. 254
CiTREC (CAN Transmit/Receive Error Count)......... 253
CiVEC (CA N In te rrupt Code)............................ ........ 252
CMSTAT (Comparator Control Register).................. 326
CMxCON (Comparator ’x’ Contro l)................. ..........325
CNCON (Change Notice Control)............................. 166
CVRCON (Comparator Voltage Reference Control) 329
DCHxCON (DMA Channel ’x’ Control) .....................124
DCHxCPTR (DMA Channel ’x’ Cell Pointer)............. 131
DCHxCSIZ (DMA Channel ’x’ Cell-Size) .................. 131
DCHxDAT (DMA Channel ’x’ Pattern Data).............. 132
DCHxDPTR (Channel ’x’ Destination Pointer).......... 130
DCHxDSA (DMA Channel ’x’ Destination
Start Ad d ress)..... ................... ................... ........ 128
DCHxDSIZ (DMA Channel ’x’ Destination Size)....... 129
DCHxECON (DMA Channel ’x’ Event Control)......... 125
DCHxINT (DMA Channel ’x’ Interrupt Control)......... 126
DCHxSPTR (DMA Channel ’x’ Source Pointer)........ 130
DCHxSSA (DMA Channel ’x’ Source Start Address) 128
DCHxSSIZ (DMA Channel ’x’ Source Size).............. 129
DCRCCON (DMA CRC Control)............................... 121
DCRCDATA (DMA CRC Data)................................. 123
DCRCXOR (DMA CRCXOR Enable) ....................... 123
DDPCON (Debug Data Port Control) .... ...................342
DEVCFG0 (Device Configuration Word 0................. 335
DEVCFG1 (Device Configuration Word 1................. 337
DEVCFG2 (Device Configuration Word 2................. 339
DEVCFG3 (Device Configuration Word 3................. 341
DEVI D (De vice and Revisi o n ID)............. ................. 342
DMAAD DR ( DMA Address )......................... ............. 120
DMACON (DMA Controller Contr ol)......................... 119
DMASTAT (DMA Status).......................................... 120
EMAC1CFG1 (Ethernet Controller MAC Configuration 1)
306
EMAC1CFG2 (Ethernet Controller MAC Configuration 2)
307
EMAC1CLRT (Ethernet Controller MAC Collision Win-
dow/Retry Limit)......................... ....................... 311
EMAC1IPGR (Ethernet Controller MAC Non-Back-to-
Back Interpacket Gap)...................................... 310
EMAC1IPGT (Ethernet Controller MAC Back-to-Back In-
terpacket Gap)............................................ ...... 309
EMAC1MADR (Ethernet Controller MAC MII Manage-
ment Address).................................................. 317
EMAC1MAXF (Ethernet Controller MAC Maximum
Frame Length)..................................................312
EMAC1MCFG (Ethernet Controller MAC MII Manage-
ment Configuration).......................................... 315
EMAC1MCMD (Ethernet Controller MAC MII Manage-
ment Command)............................................... 316
EMAC1MIND (Ethernet Controller MAC MII Manage-
ment Indicators)................................................ 319
EMAC1MRDD (Ethernet Controller MAC MII Manage-
ment Read Data).............................................. 318
EMAC1MWTD (Ethernet Controller MAC MII Manage-
ment Wr ite Data) ..............................................318
2009-2016 Microchip Technology Inc. DS60001156J- page 435
PIC32MX5XX/6XX/7XX
EMAC1SA0 (Ethernet Controller MAC Station Address
0).......................................................................320
EMAC1SA1 (Ethernet Controller MAC Station Address
1).......................................................................321
EMAC1SA2 (Ethernet Controller MAC Station Address
2).......................................................................322
EMAC1SUPP (Ethernet Controller MAC PHY Support) .
313
EMAC1TEST (Ethernet Controller MAC Test)..........314
ETHALGNERR (Ethernet Controller Alignment Errors
Statistics) ..........................................................305
ETHCON1 (Ethernet Controller Control 1)................284
ETHCON2 (Ethernet Controller Control 2)................286
ETHFCSERR (Ethernet Controller Frame Check Se-
quence Error Statistics) ....................................304
ETHFRMRXOK (Ethernet Controller Frames Received
OK Statistics)....................................................303
ETHFRMTXOK (Ethernet Controller Frames Transmit-
ted OK Statistics)..............................................300
ETHHT0 (Ethernet Controller Hash Table 0)............288
ETHHT1 (Ethernet Controller Hash Table 1)............288
ETHIEN (Ethernet Controller Interrupt Enable).........294
ETHIRQ (Ethernet Controller Interrup t Request). .....295
ETHMCOLFRM (Ethernet Controller Multiple Collision
Frame s Statistics)... ................... ................... ....302
ETHPM0 (Ethernet Controller Pattern Match Offset) 290
ETHPMCS (Ethernet Controller Pattern Match Check-
sum)..................................................................290
ETHRXFC (Ethernet Controller Receive Filter Configura-
tion)...................................................................291
ETHRXOVFLOW (Ethernet Controller Receive Overflow
Statistics) ..........................................................299
ETHRXST (Ethernet Controller RX Packet Descriptor
Start A ddress)........................ .......... .................287
ETHRXWM (Ethernet Controller Receive Watermarks) .
293
ETHSCOLFRM (Ethernet Controller Single Collision
Frame s Statistics)... ................... ................... ....301
ETHSTAT (Ethernet C ontroller Status).....................297
ETHTXST (Ethernet Controller TX Packet Descriptor
Start A ddress)........................ .......... .................287
I2CxCON (I2C Control)...................... .......................199
I2CxSTAT (I2C Status).............................................201
ICxCON (Input Capture ’x’ Control) ..........................183
IECx (Interrupt Enable Control)...................................91
IFSx (Interrupt Flag St a tu s)..... ................... ........... ......91
INTCON (Interrupt Control).........................................89
INTSTA T (Interr upt Status).........................................90
IPCx (Interrupt Priority Control)...................................92
NVMADDR (Fla sh Address) ... ........... .........................66
NVMCON (Pr o g ram ming Control) .................. .......... ..65
NVMDATA (Flash Program Data)...............................67
NVMKEY (Programming Unlock)................................66
NVMSRCADDR (Source Data Address).....................67
OCxCON (Output Compare ’x’ Control)....................187
OSCCON (Oscillator Control) .....................................97
OSCTUN (FRC Tuning)............................................100
PFABT (P refetch Cache Abort Statistics).................110
PMADDR (P arallel Port Address).............................217
PMAEN (Parallel Port Pin Enable)............................218
PMCON (Para lle l Po rt Control).................................213
PMMODE (Parallel Port Mode)...................... ...........215
PMSTAT (Parallel Port Status (Slave Mo des on ly)...219
RCON (Rese t C o n trol)................. .......... .....................71
RSWRST (So ftware Reset) ......................... ...............72
RTCCON (RT C Con trol).............. ........... .................. 223
RTCDATE (RTC Date Value)................................... 228
RTCTIME (RTC Time Value).................................... 227
SPIxCON ( SP I C o nt rol)............................................ 191
SPIxSTAT (SPI Status) ....................... ................... .. 193
T1CON (Ty p e A Timer Control)....... ........... .......... .... 169
TPTMR (Temporal Proximity Timer)........................... 90
TxCON (Typ e B Timer Control)................ .......... ...... 174
U1ADDR (US B A ddr e ss)........................ .......... ........ 150
U1BDTP1 (USB BDT Page 1).................................. 152
U1BDTP2 (USB BDT Page 2).................................. 153
U1BDTP3 (USB BDT Page 3).................................. 153
U1CNFG1 (US B Co n fig u ration 1)........ ........... .......... 154
U1CON (USB Control).............................................. 148
U1EIE (USB Error Interrupt Enable)......................... 146
U1EIR (USB Error Interrupt Status).......................... 145
U1EP0-U1EP15 (USB Endpoint Control)................. 155
U1FRMH (USB Fr ame Number High)...................... 151
U1FRML (USB Frame Number Low)........................ 150
U1IE (USB Interrupt Enable).................................... 144
U1IR (U SB Interrupt)......... .................. ................... .. 143
U1OTGCON (USB OTG Control)............................. 141
U1OTGIE (USB OTG Interrupt Enable).................... 139
U1OTGIR (USB OTG Interrupt Status) .................... 138
U1OTGSTAT (USB OTG Status)............................. 140
U1PWRC (USB Power Con trol) ................. .............. 142
U1SOF (USB SOF Threshold) ................................. 152
U1STAT (USB Status).............................................. 147
U1TOK (USB Token)................................................ 151
UxMODE (UAR Tx Mode) . ........................................ 207
UxSTA (UARTx Status and Control) ........................ 209
WDTCON (Watchdog Timer Contr ol)....................... 179
Resets ................................................................................ 69
Revision History................................................................ 420
RTCALR M (RT C ALARM Control)........... ................... ...... 225
S
Serial Peripheral Interface (SPI)....................................... 189
Software Simulator (MPL AB X SIM)............... .................. 349
Special Features............................................................... 333
T
Timer1 Module.................................................................. 167
Timer2/3, Timer4/5 Modules............................................. 171
Timing Diagrams
10-bit Analog-to-Digital Conversion (ASAM = 0, SS-
RC<2:0> = 000)......................... ..... .. .. .... .. .. .. .. .. 392
10-bit Analog-to-Digital Conversion (ASAM = 1, SS-
RC<2:0> = 111, SAMC<4:0> = 00001)............ 393
CAN I/O... ...................................... ........................... 385
EJTAG...................................................................... 398
External Clock .......................................................... 366
I/O Cha racteristics...... ...................................... ........ 369
I2Cx Bus Data (Master Mode).................................. 381
I2Cx Bus Data (Slave Mode).................................... 383
I2Cx Bus Start/Stop Bits (Maste r Mode)................... 381
I2Cx Bus Start/Stop Bits (Slave Mode).. ................... 383
Input Capture (CAPx)............................................... 374
OCx/PWM................................................................. 375
Outpu t Com p a re (OCx) .................................. .......... 374
Parallel Master Port Read ........................................ 395
Parallel Master Port Write......................................... 396
Parallel Slave Port.................................................... 394
SPIx Master Mode (CKE = 0)................................... 376
SPIx Master Mode (CKE = 1)................................... 377
SPIx Slave Mode (CKE = 0)............................. ...... .. 378
PIC32MX5XX/6XX/7XX
DS60001156J-page 436 2009-2016 Microchip Technology Inc.
SPIx Slave Mode (CKE = 1)......................................379
Timer1 , 2 , 3, 4, 5 External Cloc k...............................372
UART Reception.......................................................204
UART Transmission (8-bit or 9-bit Data)...................204
Timing Requirements
CLKO and I/O . ..........................................................369
Timing Specifications
CAN I/O Requirements .............................................385
I2Cx Bus Data Requirements (Master Mode)...........382
I2Cx Bus Data Requirements (Slave Mode).............384
Input Capture Requirements.................. .... .... .. .... .....374
Output Compare Requirements......................... .. .....374
Simple OCx/PWM Mode Requirements....................375
SPIx Master Mode (CKE = 0) Requirements............376
SPIx Master Mode (CKE = 1) Requirements............377
SPIx Slave Mode (CKE = 1) Requirements ..............379
SPIx Slave Mode Requirements (CKE = 0)..............378
U
UART ................................................................................203
USB On- Th e -Go (OTG) .............. .......... ................... .........133
V
V
CAP
pin............... .......... ................... ........... ................... ..343
Voltage Reference Specifications.............................. .......365
Voltage Regulator (On-Chip).............................................343
W
Watchdog Timer (WDT)....................................................177
WWW Address..................................................................437
WWW, On-Line Support ......................................................23
2009-2016 Microchip Technology Inc. DS60001156J- page 437
PIC32MX5XX/6XX/7XX
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchip.com. This web si te i s us ed as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•
Product Support
– Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•
General Technical Support
– Frequently Asked
Questions (FAQ), technical support requests,
online dis cu ss io n gr oups, Microchip con sul t an t
program member listing
•
Business of Microchip
– Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listin gs of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical suppo rt is a vailable through the web site
at: http://microchip.com/support
2009-2016 Microchip Technology Inc. DS60001156J- page 438
PIC32MX5XX/6XX/7XX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office
.
Architecture MX = 32-bit RISC MCU core
Product Groups 5XX = General purpose microcontroller family
6XX = General purpose microcontroller family
7XX = General purpose microcontroller family
Flash Memory Family F = Flash program memory
Pro g ram Me mory Si z e
64 = 64K
128 = 128K
256 = 256K
512 = 512K
Pin Count H = 64-pin
L = 100-pin, 121-pin, 124-pin
Speed (see
Note 1
) Blank or 80 = 80 MHz
Temperature Range I = -40°C to +85°C (Industrial)
V = -40°C to +105 °C (V -Temp)
Package PT = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)
PT = 100-Lead (12x12 x 1 mm) TQF P (Thi n Quad Flatpack)
PF = 100-Lead (14x14 x 1 mm) TQF P (Thi n Quad Flatpack)
MR = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)
BG = 121-Lead (10x10x1.1 mm) TFBGA (Plastic Thin Profile Ball Grid Array)
TL = 124-Lead (9x9x0.9 mm) VTLA (Very Thin Leadless Array)
Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)
ES = Engineering Sample
Example:
PIC32MX575F256H-80I/PT:
General purpose PIC32,
32-bit RISC MCU,
256 KB progr a m memor y,
64-pi n, I nd us trial te mp erature,
TQFP package.
Microchip Brand
Architecture
Flash Memory Family
Pin Count
Product Group s
Program Memory Size (KB)
PIC32 MX5XX F512 H T - 80 I / PT - XXX
Flash Memory Family
Speed (see Note 1)
Pattern
Package
Temperature Range
Tape and Reel Flag (if applicable)
Note 1: This option is not available for PIC32MX534/564/664/764 devices.
2009-2016 Microchip Technology Inc. DS60001156J- page 439
Information contained in this publication regarding device
appli ca tions and t he lik e is provid ed only f or yo ur conve nien ce
and may be supers eded by update s . I t is y our responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE
.
Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
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RightTouch, S pyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Spe ed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP , Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM , MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM .net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0958-8
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with t he customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are com mitted to continuously improving the c ode prot ecti on featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Mill ennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microch ip rece iv ed ISO/T S -16 94 9:20 09 certific at ion for i ts worldwid e
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPI C
®
DSCs, K
EE
L
OQ
®
code hoppi ng
devices, Serial EEPROMs, microperiph erals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949
==
DS60001156J-page 440 2009-2016 Microchip Technology Inc.
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Worldwide Sales and Service
06/23/16
