SY89851U
Low Power, 3GHz, 1:2 LV PECL Fanout
Buffer/Translator with Internal Termination
July 2005 M9999-071205
hbwhelp@micrel.com or (408) 955-1690
Precision Edge is a registered tradem ark of Micrel, Inc.
General Description
The SY89851U is a low jitter, low skew, high-speed
1:2 differential fanout buffer optimized for precision
telecom and enterprise server distribution
applications. The SY89851U distributes clock
frequencies from DC to >3GHz, and data rates to
2.5Gbps guaranteed over temperature and voltage.
The SY89851U differential input includes Micrel's
unique, 3-pin input termination architecture that
directly interfaces to any differential signal (AC- or
DC-coupled) as small as 100mV (200mVpp) without
any level shifting or termination resistor networks in
the signal path. The outputs are 800mV, 100K-
compatib le LVPECL with e xtremely fas t rise/fall tim e
guaranteed to be less than 180ps.
The SY89851U operates from a 2.5V ±5% or 3.3V
±10% supply and is guaranteed over the full
industria l temper ature range of –40°C to +85°C. T he
SY89851U is part of Micrel's high-speed, Precision
Edge® product line.
All support documentation can be found on Micrel's
web site at www.micrel.com.
Functional Block Diagram
Precision Edge®
Features
• Precision 1:2, 800mV LVPECL fanout buffer
• Low power consumption: 80mW typ. (2.5V)
• Guaranteed AC performance over temperature
and voltage:
– DC to >3GHz clock throughput
– <340ps propagation delay
– <180ps rise/fall time
– <20ps output-to-output skew
• Ultra-low jitter design:
– <1psRMS random jitter
– <10psPP deterministic jitter
– <10psPP total jitter (clock)
• Unique, patented input termination and VT pin
accepts DC- and AC-coupled inputs (CML,
LVPECL, LVDS)
• 100K LVPECL-c ompatible outp uts
• Power supply 2.5V ±5% or 3.3V ±10%
• –40°C to +85°C industrial temperature range
• Available in 16-pin (3mm x 3mm) QFN package
Applications
• All SONET and GigE clock distribution
• Fibre Channel applications
• Backplane dis tri but ion
• High-end, low skew, multiprocessor synchronous
clock distribution
Micrel, Inc. SY89851U
July 2005 M9999-071205
hbwhelp@micrel.com or (408) 955-1690
2
Ordering Information(1)
Part Number Package Type Operating Range Package Marking Lead Finish
SY89851UMG QFN-16 Industrial 851U with
Pb-Free bar-line ind icat or Pb-Free
NiPdAU
SY89851UMGTR(2) QFN-16 Industrial 851U with
Pb-Free bar-line ind icat or Pb-Free
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
16-Pin QFN
Micrel, Inc. SY89851U
July 2005 M9999-071205
hbwhelp@micrel.com or (408) 955-1690
3
Pin Description
Pin Number Pin Name Pin Function
1,4 IN, /IN Differential Inputs: This input pair is the differential signal input to the device.
Inputs accept AC- or DC-coupled signals as small as 100mV ( 200mV pp). Each
pin terminates to a VT pin through 50Ω. Note that these inputs will default to an
indeterminate state if left open. Please refer to the "Input Interface Applications"
section for more deta il s.
2 VT Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT pins provide a center-tap to a termination network for
maximum interface flexibility. See “Input Interface Applications” section for more
details.
3 VREF-AC Reference Voltage: This output biases to VCC–1.2V. It is used when AC-
coupling the inputs (IN, /IN). For AC-coupled applications, connect VREF-AC to the
VT pin and bypass with a 0.01µF low ESR capacitor to VCC. Maximum
sink/source current is ±1.5mA. See “Input Interface Applications” section for
more detail s.
5,8,13,16 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors and
place as close to each VCC pin as possible.
12,11
9,10 Q0, /Q0,
Q1, /Q1 Differential Outputs: These 100K LVPECL-compatible output pairs are the
precision, low skew copies of the inputs. Unused output pairs may be left open.
Terminate with 50Ω to VCC–2V. See “LVPECL Output Interface Application”
section for more deta il s.
6,7,14,15 GND,
Exposed Pad Ground. GND and exposed pad must both be connected to the same ground
plane.
Micrel, Inc. SY89851U
July 2005 M9999-071205
hbwhelp@micrel.com or (408) 955-1690
4
Absolute Maximum Ratings(1)
Supply Voltage (VCC) .......................... –0.5V to +4.0V
Input Voltage (IN, /IN) ............................. –0.5V to VCC
LVPECL Output Current (IOUT)
Continuous ............................................... ±50mA
Surge ...................................................... ±100mA
Termination Current
Source or sink current on VT .................. ±100mA
VREF-AC Current
Source or sink current ............................... ±2mA
Input Current
Source or sink current on IN, /IN .............. ±50mA
Lead Temperature (soldering, 20sec.) ........... +260°C
Storage Temperature (Ts) .................. –65°C to 150°C
Operating Ratings(2)
Supply Voltage (VCC).................. +2.375V to +2.625V
......................................................+3.0V to +3.6V
Ambient Temperature (TA) ................ –40°C to +85°C
Package Thermal Resistance(3)
QFN (θJA)
Still-Air ..................................................... 60°C/W
QFN (ψJB)
Junction-to-Board .................................... 33°C/W
DC Electrical Characteristics(4)
TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply 2.375 2.5 2.625 V
3.0 3.3 3.6 V
ICC Power Supply Current No load, max. VCC 32 45 mA
RIN Single-Ended Input Resistance
(IN-to-VT) 45 50 55 Ω
RDIFF_IN Differential Input Resistance
(IN-to-/IN) 90 100 110 Ω
VIH Input High Voltage
(IN, /IN) Note 5 VCC –1.6 VCC V
VIL Input Low Voltage
(IN, /IN) 0 VIH-0.1 V
VIN Input Voltage Swing
(IN, /IN) See Figure 1a. 0.1 1.7 V
VDIFF_IN Differential Input Voltage Swing
|IN-/IN| See Figure 1b. 0.2 V
VT_IN IN-to-VT
(IN, /IN) 1.28 V
VREF-AC Output Reference Voltage VCC –1.3 VCC –1.2 VCC –1.1 V
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. This is a stress rating only and
functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet.
Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the
PCB. θJA and ψJB values are for a 4-layer board in still air, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been
established.
5. VIH(min) not low er than 1.2V
Micrel, Inc. SY89851U
July 2005 M9999-071205
hbwhelp@micrel.com or (408) 955-1690
5
100K LVPECL Output DC Electrical Characteristics(6)
VCC = 2.5V ±5% or 3.3V ±10%; TA = –4 0°C to + 85°C; RL = 5 0Ω to VCC –2V, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VOH Output HIGH Voltage
(Q, /Q) VCC–1.145 VCC–0.895 V
VOL Output LOW Voltage
(Q, /Q) VCC–1.945 VCC–1.695 V
VOUT Output Voltage Swing
(Q, /Q) See Figure 1a. 550 800 mV
VDIFF_OUT Differential Output Voltage Swing
(Q, /Q) See Figure 1b. 1100 1600 mV
Note:
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been
established.
Micrel, Inc. SY89851U
July 2005 M9999-071205
hbwhelp@micrel.com or (408) 955-1690
6
AC Electrical Characteristics(7)
VCC = 2.5V ±5% or 3.3V ±10%, RL = 50Ω to VCC –2 V, VIN ≥ 100mV (200mVPP); TA = –40°C to + 85°C, unless
otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Operating Frequency NRZ Data 2.5 3.5 Gbps
Clock 3 4 GHz
tpd Differential Propagation Delay IN-to-Q 140 220 340 ps
tpd Tempco ∆tpd Temperature Coefficient 130 fs/°C
tSKEW Output-to-Output Skew
Part-to-Part Skew Note 8
Note 9 6 20
120 ps
ps
tJITTER
Data
Random Jitt er
Note 10
1
psRMS
Deter min ist ic Jitt e r Note 11 10 psPP
Clock
Cycle-to-Cycle Jitter
Note 12
1
psRMS
Total Jitter Note 13 10 psPP
tr, tf Output Rise/Fall Time (20% to 80%) At full output swing 50 100 180 ps
Notes:
7. High-frequency AC-parameters are guaranteed by design and characterization.
8. Output-to-output skew is measured between two different outputs under identical input transitions.
9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew
of the edges at the respectiv e i nput s.
10. Random jitter is measured with a K28.7 character pattern, measured at 2.5Gbps.
11. Deterministic jitter is measured at 2.5Gbps, with both K28.5 and 223 – 1 PRBS pattern.
12. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between
rising edges of the output signal.
13. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 1012 output edges will
deviate by more than the specified peak-to-peak jitter value.
Micrel, Inc. SY89851U
July 2005 M9999-071205
hbwhelp@micrel.com or (408) 955-1690
9
Single-Ended and Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
Timing Diagrams
Input and Output Stages
Figure 2a. Simplified Differential Input Stage
Figure 2b. Simplified LVPECL Output Stage
Micrel, Inc. SY89851U
July 2005 M9999-071205
hbwhelp@micrel.com or (408) 955-1690
10
Input Interface Applications
Figure 3a. LVPECL Interface
(DC-Coupled)
Figure 3b. LVPECL Interface
(AC-Coupled)
Optional: may connect VT to VCC
Figure 3c. CML Interface
(DC-Coupled)
Figure 3d. CML Interface
(AC-Coupled)
Figure 3e. LVDS Interface
Micrel, Inc. SY89851U
July 2005 M9999-071205
hbwhelp@micrel.com or (408) 955-1690
11
LVPECL Output Interface Applications
LVPECL has high input impedance, very low output
(open emitter) impedance, and small signal swing
which result in low EMI. LVPECL is ideal for driving
50Ω- and 100Ω-controlled impedance transmission
lines. There are several techniques for terminating
the LVPECL output including: Parallel Termination-
Thevenin Equivalent, Parallel Termination (3-
Resistor), and AC-Coupled Termination. Unused
output pairs may be left floating. However, single-
ended outputs must be terminated, or balanced.
Figure 4a. Parallel Thevenin-Equivalent
Termination
Figure 4b. Parallel Termination
(3-Resistor)
Related Product and Support Documentation
Part Number Function Data Sheet Link
SY58012U 5GHz, 1:2 LVPECL Fanout Buffer/Translator
with Internal Input Termination www.micrel.com/product-info/products/sy58012u.shtml
HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml
Micrel, Inc. SY89851U
July 2005 M9999-071205
hbwhelp@micrel.com or (408) 955-1690
12
Package Information
16-Pin QFN
Package Notes:
1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packaged before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-10 00 WEB http:/ww w. micrel.com
The information f urnished by Micrel in this data sheet is believed to be accurat e and reliable. However, no responsibil ity is
assumed by Mic rel
for its use. Micrel reserves the right t o change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where mal
fu nct ion of a
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xpected to result in personal injury. Life s upport devices or systems are devic es or syst ems that (a) are int ended
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result in a
significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or syst
ems is a
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© 2005 Micrel, Incorporated.
