List of figures
Figure 1. STM8S105xx access line block diagram ................................................................................10
Figure 2. Flash memory organisation ....................................................................................................13
Figure 3. LQFP 48-pin pinout .................................................................................................................21
Figure 4. LQFP 44-pin pinout .................................................................................................................22
Figure 5. LQFP/UFQFPN 32-pin pinout ................................................................................................23
Figure 6. SDIP 32-pin pinout ..................................................................................................................24
Figure 7. Memory map ...........................................................................................................................29
Figure 8. Supply current measurement conditions ................................................................................55
Figure 9. Pin loading conditions .............................................................................................................56
Figure 10. Pin input voltage ...................................................................................................................56
Figure 11. fCPUmax versus VDD ..............................................................................................................60
Figure 12. External capacitor CEXT .......................................................................................................61
Figure 13. Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz ...........................................70
Figure 14. Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V ..................................................71
Figure 15. Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz ..............................................................71
Figure 16. Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz ............................................72
Figure 17. Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V ....................................................72
Figure 18. Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz ................................................................73
Figure 19. HSE external clocksource .....................................................................................................74
Figure 20. HSE oscillator circuit diagram ...............................................................................................75
Figure 21. Typical HSI accuracy at VDD = 5 V vs 5 temperatures ..........................................................76
Figure 22. Typical HSI accuracy vs VDD @ 4 temperatures ..................................................................77
Figure 23. Typical LSI accuracy vs VDD @ 4 temperatures ...................................................................78
Figure 24. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................81
Figure 25. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................81
Figure 26. Typical pull-up current vs VDD @ 4 temperatures .................................................................82
Figure 27. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................84
Figure 28. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................84
Figure 29. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................85
Figure 30. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................85
Figure 31. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................86
Figure 32. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................86
Figure 33. Typ. VDD - VOH @ VDD = 5 V (standard ports) .......................................................................87
Figure 34. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ....................................................................87
Figure 35. Typ. VDD - VOH @ VDD = 5 V (high sink ports) ......................................................................88
Figure 36. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) ...................................................................88
Figure 37. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................89
Figure 38. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................90
Figure 39. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................90
Figure 40. Recommended reset pin protection ......................................................................................91
Figure 41. SPI timing diagram - slave mode and CPHA = 0 ..................................................................93
Figure 42. SPI timing diagram - slave mode and CPHA = 1(1) .............................................................93
Figure 43. SPI timing diagram - master mode(1) ...................................................................................94
Figure 44. Typical application with I2C bus and timing diagram (1) .......................................................95
Figure 45. ADC accuracy characteristics ...............................................................................................99
Figure 46. Typical application with ADC ................................................................................................99
Figure 47. 48-pin low profile quad flat package (7 x 7) ........................................................................103
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STM8S105xxList of figures