PIC18F4321 FAMILY
DS39689E-page 388 Preliminary © 2007 Microchip Technology Inc.
Resets ........................................................................ 41, 253
Brown-out Reset (BOR) ...........................................253
Oscillator Start-up Timer (OST) . ............. ...... ...... .....253
Power-on Res e t (POR) .............. ................... ...........253
Power-up Tim e r ( PWRT) ........... ........... .............. .....253
RETFIE ............................................................................304
RETLW .............................................................................304
RETURN ..........................................................................305
Return Add ress St a ck ........................ ....................... .........54
Associ a te d Re g i sters ............................ ................... ..54
Return Stack Pointer (STKP TR) ............ ................... .........55
Revision History ...............................................................377
RLCF ................................................................................305
RLNCF .............................................................................306
RRCF ...............................................................................306
RRNCF .............................................................................307
S
SCK ..................................................................................161
SDI ...................................................................................161
SDO .................................................................................161
SEC_IDLE Mode .............................. .. .... ......... .... .... .. .........38
SEC_RUN Mode ................................................................34
Serial Clock, SCK .............................................................161
Serial Data In (SDI) ..........................................................161
Serial Data Out (SDO) .....................................................161
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 307
Single-Supply ICSP Programming.
Slave Select (SS) ............................................................. 161
SLEEP ..............................................................................308
Sleep
OSC1 and OSC2 Pin States ................... .. .. .. .... .. ..... ..32
Softwa re Simulato r (MP L AB SIM) .... ............... .................324
Special Event Trigger. See Compare (CCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Speci a l Feat u res of the CPU ...... ............... .............. .........253
Special Function Registers ................................................62
Map ............................................................................62
Special ICPORT Features ................................................271
SPI Mode (MSSP )
Associ a te d Re g i sters ............................ ...................169
Bus Mode Compatibility ......... ............. .......... ...... .....169
Effects of a Reset .....................................................169
Enabling SPI I/O ......................................................165
Master Mode ............................................................166
Master/Slave Connection ....... .. .... .. ....... .. .... .. .... .. .....165
Operation .................................................................164
Operation in Power-Managed Modes ......................169
Serial Clock ..............................................................161
Serial Data In ...........................................................161
Serial Data Out ........................................................161
Slave Mode ..............................................................167
Slave Select .............................................................161
Slave Select Synchronization ..................................167
SPI Clock .................................................................166
Typica l Co nnec tion ........ .............. ............... .............165
SS ....................................................................................161
SSPOV .............................................................................195
SSPOV Status Flag ..........................................................195
SSPSTAT Register
R/W Bit .............................................................175, 177
Stack Full/Underflow Resets ..............................................56
SUBFSR ...........................................................................319
SUBFWB ..........................................................................308
SUBLW ............................................................................309
SUBULNK ........................................................................ 319
SUBWF ............................................................................ 309
SUBWFB ......................................................................... 310
SWAPF ............................................................................310
T
Table Reads/Table Writes ......... .... ..... .. .. .... .. .. .. .. ....... .. .. .... 56
TBLRD ............................................................................. 311
TBLWT ............................................................................. 312
Time - o ut in Vari o u s Si tuati o n s (tab l e) .. .. ...... ...... ..... .. ...... .. . 45
Timer0 ..............................................................................123
Associ a te d Re g i sters ...................... ................... ...... 12 5
Operation ................................................................. 124
Overflow In terrupt ........................... ......................... 125
Prescaler ................................................................. 125
Prescaler Assignment (PSA Bit) .............................. 125
Presca le r Select (T0 PS 2 :T0 PS0 Bi ts) ..................... 125
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 124
Source Edge Select (T0SE Bit) ............................... 124
Source Se le ct (T0CS Bit) .............. ....................... .... 124
Switching Prescaler Assignment ............................. 125
Timer1 ..............................................................................127
16-Bit Read/Write Mode ........................... ....... .. .. .... 129
Associ a te d Re g i sters .................. ............................. 131
Interrupt ................................................................... 130
Operation ................................................................. 128
Oscillator .......................................................... 127, 129
Layout Considera tions ...... .................. ............. 130
Low-Power Option ........................................... 129
Overflow In terrupt ..................... .................. ............. 127
Resetting, Using the CCP
Special Event Trigger ......................................130
Special Event Trigger (ECCP) ................................. 148
TMR1H Register ...................................................... 127
TMR1L Register ....................................................... 127
Use as a Rea l-Time Clock ....................................... 130
Timer2 ..............................................................................133
Associ a te d Re g i sters ...................... ................... ...... 13 4
Interrupt ................................................................... 134
Operation ................................................................. 133
Output ...................................................................... 134
PR2 Register ................................................... 144, 149
TMR2-to-PR2 Match Interrupt .................... ..... 144, 149
Timer3 ..............................................................................135
16-Bit Read/Write Mode ........................... ....... .. .. .... 137
Associ a te d Re g i sters .................. ............................. 137
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow Interrupt ................ ....... .... .. .. .... .. .. ..... 135, 137
Special Event Trigger (CCP) ................................... 137
TMR3H Register ...................................................... 135
TMR3L Register ....................................................... 135
Timing Diagrams
A/D Conver sion .... .............. ......................... ............. 364
Acknowledge Sequence .......................................... 198
Asynchronous Receptio n ......................................... 219
Asynchronous Tran smiss ion . ................................... 216
Asynchronous Tra nsmiss ion
(Back to Back) ................................................. 216
Automatic Baud Rate Calculation ............................ 214
Auto-Wake-up Bit (WUE) During
Normal Operation ........ ........... ................... ...... 220
Auto-Wake-up Bit (WUE) During Sleep . .................. 220
Baud Rate Generator with Clock Arbitration ............ 192
BRG Overflow Sequence ......................................... 214