858S011AKILFT - Integrated Device Technology

DATA SHEET

Low Skew, 1-To-2, Differential-To-CML

Fanout Buffer

ICS858S011I

General Description

The ICS858S011I is a high speed 1-to-2 Differential-to-CML Fanout

Buffer. The ICS858S011I is optimized for high speed and very low

output skew, making it suitable for use in demanding applications

such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre

Channel. The internally terminated differential input and VREF_AC

pin allow other differential signal families such as LVDS, LVPECL,

SSTL and CML to be easily interfaced to the input with minimal use

of external components. The ICS858S011I is packaged in a small

3mm x 3mm 16-pin VFQFN package which makes it ideal for use in

space-constrained applications.

Features

•Two differential CML outputs

•IN/nIN pair can accept the following differential input levels:

LVPECL, LVDS, CML, SSTL

•Maximum output frequency: 2GHz

•Output skew: 25ps (maximum)

•Part-to-part skew: 250ps (maximum)

•Additive phase jitter, RMS: 0.042ps (typical)

•Propagation delay: 525ps (maximum)

•Operating voltage supply range:

VCC = 2.375V to 3.63V, VEE = 0V

•-40°C to 85°C ambient operating temperature

•Available in lead-free (RoHS 6) package

ICS858S011I

16-Lead VFQFN

3mm x 3mm x 0.925mm package body

K Package

Top View

Pin Assignment

Block Diagram

nQ0

nQ1

nIN

VREF_AC

RIN

5 6 7 8

16 15 14 13

VREF_AC

nIN

nQ0

nQ1

VCC

VEE

VCC

VEE

Vcc

VCC

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

Table 1. Pin Descriptions

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 2A. Power Supply DC Characteristics, VCC = 2.375V to 3.63V, VEE = 0V, TA = -40°C to 85°C

Number Name Type Description

1 IN Input Non-inverting differential LVPECL clock input.

TInput Termination input.

REF_AC Output Reference voltage for AC-coupled applications.

4 nIN Input Inverting differential LVPECL clock input.

5, 8, 13, 16 VCC Power Power supply pins.

6, 7, 14, 15 VEE Power Negative supply pins.

9, 10 Q1, nQ1 Output Differential output pair. CML interface levels.

11, 12 nQ0, Q0 Output Differential output pair. CML interface levels.

Item Rating

Supply Voltage, VCC 4.6V (CML mode, VEE = 0V)

Inputs, VI-0.5V to VCC + 0.5V

Outputs, IO

Continuous Current

Surge Current

20mA

40mA

Input Current, IN/nIN +50mA

VT Current, IVT +100mA

Input Sink/Source, IREF_AC ±2mA

Operating Temperature Range, TA-40°C to 85°C

Storage Temperature, TSTG -65°C to 150°C

Package Thermal Impedance, θJA (Junction-to-Ambient) 74.7°C/W (0 mps)

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VCC Positive Supply Voltage 2.375 3.3 3.63 V

IEE Power Supply Current 57 mA

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

Table 2B. DC Characteristics, VCC = 2.375V to 3.63V, VEE = 0V, TA = -40°C to 85°C

NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram.

Table 2C. CML DC Characteristics, VCC = 2.375V to 3.63V, VEE = 0V, TA = -40°C to 85°C

NOTE 1: Outputs terminated with 50Ω to VCC.

AC Electrical Characteristics

Table 3. AC Characteristics, VCC = 2.375V to 3.63V, VEE = 0V, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has

been reached under these conditions.

All parameters characterized at ≤ 1.2GHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage, same temperature, same frequency and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using

the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

RIN Differential Input Resistance IN/nIN IN to VT

, nIN to VT40 50 60 Ω

VIH Input High Voltage IN/nIN 1.2 VCC V

VIL Input Low Voltage IN/nIN 0 VIH – 0.15 V

VIN Input Voltage Swing; NOTE 1 0.15 1.2 V

VDIFF_IN Differential Input Voltage Swing 0.3 V

IN to VTVoltage between IN and VTIN/nIN 1.28 V

VREF_AC Reference Voltage VCC – 1.4 VCC – 1.3 VCC – 1.2 V

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOH Output High Voltage; NOTE 1 VCC – 0.020 VCC – 0.010 VCC V

VOUT Output Voltage Swing 325 400 mV

VDIFF_OUT Differential Output Voltage Swing 650 800 mV

ROUT Output Source Impedance 40 50 60 Ω

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fOUT Output Frequency 2GHz

tPD

Propagation Delay, Differential;

NOTE 1 275 525 ps

tsk(o) Output Skew; NOTE 2, 4 25 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 ps

tjit Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

155.52MHz @ 3.3V, Integration

Range: 12kHz – 20MHz 0.042 ps

tR / tFOutput Rise/Fall Time 20% to 80% 60 200 ps

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

The source generator "Rohde & Schwarz SMA100A Low Noise

Signal Generator as external input to an Agilent 8133A 3GHz Pulse

Generator".

SSB Phase Noise dBc/Hz

Offset from Carrier Frequency (Hz)

Additive Phase Jitter @ 155.52MHz

12kHz to 20MHz = 0.042ps (typical)

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

Parameter Measurement Information

CML Output Load AC Test Circuit

Part-to-Part Skew

Single-ended & Differential Input Voltage Swing

Differential Input Level

Output Skew

Propagation Delay

SCOPE

Power

Supply

CML Driver

-2.375V to -3.63V

tsk(pp)

Part 1

Part 2

nQx

nQy

VIN, VOUT

400mV

(typical)

VDIFF_IN, VDIFF_OUT

800mV

(typical)

Cross Points

nIN

VCC

VEE

tsk(o)

nQx

nQy

tPD

nQ0, nQ1

Q0, Q1

nIN

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

Parameter Measurement Information, continued

Output Rise/Fall Time

Applications Information

Recommendations for Unused Output Pins

Outputs:

CML Outputs

All unused CML outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

20%

80% 80%

20%

SWING

nQ0, nQ1

Q0, Q1

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

3.3V LVPECL Input with Built-In 50Ω Termination Interface

The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL,

CML, SSTL and other differential signals. Both differential inputs

must meet the VPP and VCMR input requirements. Figures 1A to 1E

show interface examples for the IN /nIN input with built-in 50Ω

terminations driven by the most common driver types. The input

interfaces suggested here are examples only. If the driver is from

another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

Figure 1A. IN/nIN Input with Built-In 50Ω

Driven by an LVDS Driver

Figure 1C. IN/nIN Input with Built-In 50Ω

Driven by a CML Driver with Open Collector

Figure 1E. IN/nIN Input with Built-In 50Ω

Driven by an SSTL Driver

Figure 1B. IN/nIN Input with Built-In 50Ω

Driven by an LVPECL Driver

Figure 1D. IN/nIN Input with Built-In 50Ω

Driven by a CML Driver with Built-In 50Ω

Pullup

nIN

Receive

With

Built-In

50Ω

LVDS

3.3V 3.3V

Zo = 50Ω

nIN

CML – Open Collector

Receiver

With

Built-In

50Ω

3.3V3.3V

Zo = 50Ω

SSTL

R1 25

R2 25

nIN

Receive

With

Built-In

50Ω

3.3V 3.3V

Zo = 50Ω

nIN

Receiver

With

Built-In

50Ω

LVPECL

3.3V3.3V

Zo = 50Ω

CML – Built-in 50Ω Pull-up

nIN

Receiver

With

Built-In

50Ω

3.3V 3.3V

Zo = 50Ω

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

2.5V LVPECL Input with Built-In 50Ω Termination Interface

The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL,

CML, SSTL and other differential signals. Both differential inputs

must meet the VPP and VCMR input requirements. Figures 2A to 2E

show interface examples for the IN /nIN with built-in 50Ω termination

input driven by the most common driver types. The input interfaces

suggested here are examples only. If the driver is from another

vendor, use their termination recommendation. Please consult with

the vendor of the driver component to confirm the driver termination

requirements.

Figure 2A. IN/nIN Input with Built-In 50Ω

Driven by an LVDS Driver

Figure 2C. IN/nIN Input with Built-In 50Ω

Driven by a CML Driver

Figure 2E. IN/nIN Input with Built-In 50Ω

Driven by an SSTL Driver

Figure 2B. IN/nIN Input with Built-In 50Ω

Driven by an LVPECL Driver

Figure 2D. IN/nIN Input with Built-In 50Ω Driven by a

CML Driver with Built-In 50Ω Pullup

nIN

Receiver

With

Built-In

50Ω

LVDS

3.3V or 2.5V 2.5V

Zo = 50Ω

nIN

CML

Receive

With

Built-In

50Ω

2.5V2.5V

Zo = 50Ω

SSTL

R1 25Ω

R2 25Ω

nIN

Receiver

With

Built-In

50Ω

2.5V 2.5V

Zo = 50Ω

nIN

Receiver

With

Built-In

50Ω

18Ω

LVPECL

2.5V2.5V

Zo = 50Ω

CML - Built-in 50Ω Pull-up

nIN

Receive

With

Built-In

50Ω

2.5V 2.5V

Zo = 50Ω

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

Schematic Example

Figure 3 shows a schematic example of the ICS858S011I. This

schematic provides examples of input and output handling. The

ICS858S011I input has built-in 50Ω termination resistors. The input

can directly accept various types of differential signal without AC

couple. If AC couple termination is used, the ICS858S011I also

provides VREF_AC pin for proper offset level after AC couple. This

example shows the ICS858S011I input driven by a 3.3V LVPECL

driver. The ICS858S011I outputs are CML driver with built-in 50Ω

pullup resistors. In this example, we assume the traces are long

transmission line and the receiver is high input impedance without

built-in matched load. An external 100Ω resistor across the receiver

input is required.

Figure 3. ICS858S011I Application Schematic Example

Zo = 50

LVPECL

[U1,5]

Zo = 50

3.3V

0.1u

100 Ohm Dif f erential

Zo = 50

nQ1

[U1,8]

3.3V

0.1u

Alternativ e Termination Example f or

CML Driv er with Built-in Internal Pull

Up Resistor

3.3V

Zo = 50

0.1u

100

3.3V

[U1,13]

3.3V

[U1,16]

ICS858011

VREF_AC

nIN

VCC

VEE

VCC

nQ1

nQ0

VCC

VEE

VCC

150

3.3V

0.1u

nQ0

Zo = 50

3.3V

nQ0

150

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 4. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, please refer to the Application

Note on the Surface Mount Assembly of Amkor’s Thermally/

Electrically Enhance Leadframe Base Package, Amkor Technology.

Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

SOLDERSOLDER PINPIN EXPOSED HEAT SLUG

PIN PAD PIN PADGROUND PLANE LAND PATTERN

(GROUND PAD)

THERMAL VIA

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS858S011I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS858S011I is the sum of the core power plus the power dissipation in the load(s).

The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.

• Power (core)MAX = VDD_MAX * IDD = 3.63V * 57mA = 206.9mW

• Power Dissipation for internal termination RT

Power (RT)MAX = 4 * (VIN_MAX)2 / RT_MIN = (1.2V)2 / 80Ω = 72mW

Total Power_MAX = 206.9mW + 72mW = 278.9mW

•

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 74.7°C/W per Table 4 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.279W * 74.7°C/W = 105.8°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 4. Thermal Resistance θJA for 16 Lead VFQFN, Forced Convection

θJA by Velocity

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 74.7°C/W 65.3°C/W 58.5°C/W

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

Reliability Information

Table 5. θJA vs. Air Flow Table for a 16 Lead VFQFN

Transistor Count

The transistor count for ICS858S011I is: 216

Pin Compatible with 858011

θJA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 74.7°C/W 65.3°C/W 58.5°C/W

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

Package Outline and Package Dimensions

Package Outline - K Suffix for 16 Lead VFQFN

Table 6. K Package Dimensions for 16 Lead VFQFN

Reference Document: JEDEC Publication 95, MO-220

Top View

Index

rea

Chamfer 4x

0.6 x 0.6 max

OPTIONAL

0. 08 C

Seating Plan

-1)x e

(R ef.)

(Ref.)

N & N

Even

(Ref.)

N& N

Odd

(Typ.)

If N & N

are Even

(N -1)x e

(Re f.)

Thermal

Base

DDE

Anvil

Singulation

Sawn

Singulation

N-1N

CHAMFER

N-1

RADIUS

N-1

Bottom View w/Type B ID Bottom View w/Type C IDBottom View w/Type A ID

There are 3 methods of indicating pin 1 corner

at the back of the VFQFN package are:

1. Type A: Chamfer on the paddle (near pin 1)

2. Type B: Dummy pad between pin 1 and N.

3. Type C: Mouse bite on the paddle (near pin 1)

All Dimensions in Millimeters

Symbol Minimum Maximum

N16

A0.80 1.0

A1 00.05

A3 0.25 Reference

b0.18 0.30

e0.50 Basic

D, E 3.0

D2, E2 1.00 1.80

L0.30 0.50

ND NE4.0

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

Ordering Information

Table 7. Ordering Information

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Part/Order Number Marking Package Shipping Packaging Temperature

858S011AKILF 011A “Lead-Free” 16 Lead VFQFN Tube -40°C to 85°C

858S011AKILFT 011A “Lead-Free” 16 Lead VFQFN 2500 Tape & Reel -40°C to 85°C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without

additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support

devices or critical medical instruments.

ICS858S011I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

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