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April 1st, 2010
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Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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Rev.6.00 Jun. 02, 2004 page 1 of 15
HD74LV123A
Dual Retriggerable Monostable Multivibrators REJ03D0314–0600Z
(Previous ADE-20 5-258D (Z))
Rev.6.00
Jun. 02, 2004
Description
The HD74LV123A features output pulse-duration control by three methods. In the first method, the A input is low and
the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A
input is low, the B input is high, and the clear (CLR) input goes high.
The basic pulse duration is programmed by selecting external resistance and capacitance values.
The external timing capacitor must be connected be tween Cext and Rext/Cext (positive) and an external resistor
connected between Rext/Cext and Vcc
To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and Vcc.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-
active (B) input. Pulse duration can be reduced by taking CLR low.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
• Ordering Information
Part Name Package Type Package Code Package
Abbreviation Taping Abbreviation
(Quantity)
HD74LV123AFPEL SOP–16 pin(JEITA) FP–16DAV FP EL (2,000 pcs/reel)
HD74LV123ARPEL SOP–16 pin(JEDEC) FP–16DNV RP EL (2,500 pcs/reel)
HD74LV123ATELL TSSOP–16 pin TTP–16DAV T ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 2 of 15
Function Table
Inputs Outputs
CLR A BQQ
LXXLH
HHXLH
HXLLH
HL↑
H↓H
↑LH
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
: High level pulse
: Low level pulse
Pin Arrangement
V
CC
1Rext / Cext
1Cext
1Q
2B
2Q
2CLR
1A
1B
1CLR
1Q
2Q
2Cext
2Rext / Cext
2A
(Top view)
11
12
13
14
15
16
1
2
3
4
5
6
7
GND 89
10
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 3 of 15
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage range VCC –0.5 to 7.0 V
Input voltage range*1VI–0.5 to 7.0 V
–0.5 to VCC + 0.5 Output: H or LOutput voltage range*1, 2 VO–0.5 to 7.0 VVCC: OFF
Input clamp current IIK –20 mA VI < 0
Output clamp current IOK ±50 mA VO < 0 or VO > VCC
Continuous output current IO±25 mA VO = 0 to VCC
Continuous current through
VCC or GND ICC or IGND ±50 mA
785 SOPMaximum power dissipation at
Ta = 25°C (in still air)*3PT500 mW TSSOP
Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item Symbol Min Typ Max Unit Conditions
Supply voltage range VCC 2.0 — 5.5 V
Input voltage range VI0—5.5V
Output voltage range VO0—V
CC V
— — –50 µAV
CC = 2.0 V
——–2 V
CC = 2.3 to 2.7 V
——–6 V
CC = 3.0 to 3.6 V
IOH
— — –12
mA
VCC = 4.5 to 5.5 V
——50µAV
CC = 2.0 V
——2 V
CC = 2.3 to 2.7 V
——6 V
CC = 3.0 to 3.6 V
Output current
IOL
——12
mA
VCC = 4.5 to 5.5 V
0 — 200 VCC = 2.3 to 2.7 V
0 — 100 VCC = 3.0 to 3.6 V
Input transition rise or fall rate ∆t /∆v
0—20
ns/V
VCC = 4.5 to 5.5 V
5—— V
CC = 2.0 VExternal timing resistance Rext 1——
kΩVCC ≥ 2.3 V
External timing capacitance Cext — Unlimited — F
Power-up ramp rate ∆t /∆VCC 1 ——ms/
V
Operating free-air temperature Ta –40 — 85 °C
Note: Unused or floating inputs must be held high or low.
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 4 of 15
Logic Diagram
Q
Cext Rext/
Cext
Q
Q
Q
A
B
C
LR
CLR
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 5 of 15
DC Electrical Characteristics
Ta = –40 to 85°C
Item Symbol VCC (V)* Min Typ Max Unit Test Conditions
2.0 1.5 — —
2.3 to 2.7 VCC × 0.7 — —
3.0 to 3.6 VCC × 0.7 — —
VIH
4.5 to 5.5 VCC × 0.7 — —
2.0 — — 0.5
2.3 to 2.7 — — VCC × 0.3
3.0 to 3.6 — — VCC × 0.3
Input voltage
VIL
4.5 to 5.5 — — VCC × 0.3
V
Min to Max VCC – 0.1 — — IOH = –50 µA
2.3 2.0 — — IOH = –2 mA
3.0 2.48 — — IOH = –6 mA
VOH
4.5 3.8 — — IOH = –12 mA
Min to Max — — 0.1 IOL = 50 µA
2.3 — — 0.4 IOL = 2 mA
3.0 — — 0.44 IOL = 6 mA
Output voltage
VOL
4.5 — — 0.55
V
IOL = 12 mA
Input current IIN 0 to 5.5 — — ±1 µAV
IN = 5.5 V or GND
Input current
Rext / Cext IIN 5.5 — — ±2.5 µAV
IN = VCC or GND
Quiescent supply
current ICC 5.5 — — 20 µAV
IN = VCC or GND, IO = 0
2.3 — — 220
3.0 — — 280
4.5 — — 650
Active state supply
current
(per circuit)
∆ICC
5.5 — — 975
µAV
IN = VCC or GND
Rext/Cext = 0.5 VCC
Output leakage
current IOFF 0——5µAV
I or VO = 0 V to 5.5 V
Input capacitance CIN 3.3 — 4.0 — pF VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating con ditions.
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 6 of 15
Switching Characteristics
VCC = 2.5 ± 0.2 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test
Conditions FROM
(Input) TO
(Output)
— 13.5 31.4 1.0 37.0 CL = 15 pF
— 16.0 36.0 1.0 42.0 CL = 50 pF A or B Q or Q
— 11.0 25.0 1.0 29.5 CL = 15 pF
— 13.0 32.8 1.0 34.5 CL = 50 pF
CLR Q or Q
— 14.0 33.4 1.0 39.0 CL = 15 pF
Propagation
delay time tPLH
tPHL
— 16.0 38.0 1.0 44.0
ns
CL = 50 pF
CLR
(Trigger) Q or Q
— 170 260 — 320 ns CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ
90 100 110 90 110 µsCL = 50 pF,
Cext = 0.01 µF, Rext = 10 kΩ
twQ
0.9 1.0 1.1 0.9 1.1 ms CL = 50 pF,
Cext = 0.1 µF, Rext = 10 kΩ
Output pulse
width
∆twQ —±1———%C
L = 50 pF
Pulse width tw6.0 — — 6.5 — ns A, B or CLR
—40———ns
A, or B
(Rext = 1 kΩ, Cext = 100 pF)
Retrigger time trr
—1.5—— — µsA, or B
(Rext = 1 kΩ, Cext = 0.01 µF)
VCC = 3.3 ± 0.3 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test
Conditions FROM
(Input) TO
(Output)
— 9.7 20.6 1.0 24.0 CL = 15 pF
— 11.5 24.1 1.0 27.5 CL = 50 pF A or B Q or Q
— 8.0 15.8 1.0 18.5 CL = 15 pF
— 9.5 19.3 1.0 22.0 CL = 50 pF
CLR Q or Q
— 9.9 22.4 1.0 26.0 CL = 15 pF
Propagation
delay time tPLH
tPHL
— 11.5 25.9 1.0 29.5
ns
CL = 50 pF
CLR
(Trigger) Q or Q
— 150 240 — 300 ns CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ
90 100 110 90 110 µsCL = 50 pF,
Cext = 0.01 µF, Rext = 10 kΩ
twQ
0.9 1.0 1.1 0.9 1.1 ms CL = 50 pF,
Cext = 0.1 µF, Rext = 10 kΩ
Output pulse
width
∆twQ —±1—— — %C
L = 50 pF
Pulse width tw5.0 — — 5.0 — ns A, B or CLR
—30—— — nsA, or B
(Rext = 1 kΩ, Cext = 100 pF)
Retrigger time trr
—1.2—— — µsA, or B
(Rext = 1 kΩ, Cext = 0.01 µF)
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 7 of 15
Switching Characteristics (cont)
VCC = 5.0 ± 0.5 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test
Conditions FROM
(Input) TO
(Output)
— 7.3 12.0 1.0 14.0 CL = 15 pF
— 8.5 14.0 1.0 16.0 CL = 50 pF A or B Q or Q
— 5.9 9.4 1.0 11.0 CL = 15 pF
— 7.5 11.4 1.0 13.0 CL = 50 pF
CLR Q or Q
— 7.3 12.9 1.0 15.0 CL = 15 pF
Propagation
delay time tPLH
tPHL
— 8.7 14.9 1.0 17.0
ns
CL = 50 pF
CLR
(Trigger) Q or Q
— 140 200 — 240 ns CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ
90 100 110 90 110 µsCL = 50 pF,
Cext = 0.01 µF, Rext = 10 kΩ
twQ
0.9 1.0 1.1 0.9 1.1 ms CL = 50 pF,
Cext = 0.1 µF, Rext = 10 kΩ
Output pulse
width
∆twQ —±1—— — %C
L = 50 pF
Pulse width tw5.0 — — 5.0 — ns A, B or CLR
—20—— — nsA, or B
(Rext = 1 kΩ, Cext = 100 pF)
Retrigger time trr
—0.95—— — µsA, or B
(Rext = 1 kΩ, Cext = 0.01 µF)
Operating Characteristics
CL = 50 pF
Ta = 25°C
Item Symbol VCC (V) Min Typ Max Unit Test Conditions
3.3 — 74.0 —Power dissipation capacitance CPD 5.0 — 86.0 — pF f = 10 MHz
Test Circuit
L
C = 15 pF or 50 pF
L
C = 15 pF or 50 pF
Q
Cext
Cext = 28 pF or 100 pF or 0.01 µF or 0.1 µF
Rext = 1 kΩ or 2 kΩ or 10 kΩ
Cext Rext/
Cext
Rext
−+
Q
Output
A
CLR
B
CC
V
CC
V
Output
GND
Input
CC
V
Refer
to
Func-
tion
Table
Note : C includes the probe and jig capacitance.
L
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 8 of 15
Timing diagram
A
CLR
B
Q
Rext/
Cext
t
w
t
w
t
rr
t
w
+t
rr
Caution in use
In order to prevent any malfunctions due to noise, connect a high frequency
performance capacitor between Vcc and GND, and keep the wiring between the
External components and Cext, Rext/Cext pins as short as possible.
Large values of Cext may cause problems when powering down the HD74LV123A
because of the amount of energy stored in the capacitor. When a system containing
this device is powered down, the capacitor may discharge from Vcc through the protection
diodes at pin 7 or pin 15.
Current through the input protection diodes must be limited to 20 mA; therefore, the turn-off
time of the Vcc power supply must not be faster than t = Vcc • Cext/(20 mA). For example,
if Vcc = 5 V and Cext = 22 µF, the Vcc supply must turn off no faster than t = (5 V) • (22 µF)/
20 mA = 5.5 ms. This is usually not a problem because power supplies are heavily filtered
and cannot discharge at this rate.
When a more rapid decrease of Vcc to zero volts occurs, the HD74LV123A may sustain damage.
To avoid this possibility, use an external calmping diode.
The input pins for unused circuit should be used under conditions to fix the outputs to avoid
malfunction cased by noises. Also, it's recommended that Rext / Cext terminals are open and
external parts are not connected to.
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 9 of 15
GND
V
CC
GND
V
CC
GND
V
CC
10%
90%
50%
• Waveform − 1
Input A
Input CLR
Input B
Output Q
Output Q
t
f
t
r
10%
90%
50%
t
r
V
OH
V
OL
V
OH
V
OL
t
(trigger)
PLH
t
PHL
t
PLH
t
(L)
w
CC
50% V
10%
90%
50% 50%
t
r
90%
50%
10% 10%
90%
t
f
CC
50% V
CC
50% V
CC
50% V
t
(trigger)
PHL
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 10 of 15
1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t ≤ 3 ns, t ≤ 3 ns
2. The output are measured one at a time with one transition per measurement.
Notes:
r f
GND
V
CC
GND
V
CC
• Waveform − 2
Input A
Input B
Output Q
Output Q
V
OH
V
OL
V
OH
V
OL
t
(out)
w
t
r
t
f
t
(L)
w
t
(H)
w
t
(H)
w
t
(L)
w
10%
90%
50%
10% 10% 10%
90% 90% 90%
50% 50% 50%
50%
t
r
t
f
t
r
90%
50%
10% 10%
90%
t
f
CC
50% V
CC
50% V
CC
50% V
CC
50% V
• Waveform − 3
Input A
Input B
Output Q
Output Q
V
OH
V
OL
V
OH
V
OL
t
(out) +
t
w rr
t
rr
GND
V
CC
t
f
10% 10% 10%
90% 90% 90%
50% 50%
t
r
t
f
GND
V
CC
t
r
t
r
10%
90%
50% 90%
50%
10% 10%
90%
t
f
CC
50% V
CC
50% V
CC
50% V
CC
50% V
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 11 of 15
Application Data
10
1.0
10.0
100.0
1000.0
10000.0
0.1 2103104105106107
WQ
Timing capacitance Cext (pF)
Output pulse width t (µs)
Vcc = 2.5 V
1 kΩ
Rext
10 kΩ
100 kΩ
1 MΩ
10
1.0
10.0
100.0
1000.0
10000.0
0.1 2103104105106107
Vcc = 3.3 V
WQ
Timing capacitance Cext (pF)
Output pulse width t (µs)
1 kΩ
Rext
10 kΩ
100 kΩ
1 MΩ
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 12 of 15
10
1.0
10.0
100.0
1000.0
10000.0
0.1 2103104105106107
Vcc = 5.0 V
WQ
Timing capacitance Cext (pF)
Output pulse width t (µs)
1 kΩ
Rext
10 kΩ
100 kΩ
1 MΩ
2.0 2.5 3.0 3.5 4.0 4.5 5.0 6.05.5
0.8
0.9
1.0
1.1
1.2
1.3
1.4 Rext = 2 kΩ
CC
Supply voltage V (V)
Coefficient of output pulse width K
1000 pF
10000 pF
100000 pF
1000000 pF
Cext
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 13 of 15
2.0 2.5 3.0 3.5 4.0 4.5 5.0 6.05.5
0.8
0.9
1.0
1.1
1.2
1.3
1.4 Rext = 10 kΩ
CC
Supply voltage V (V)
Coefficient of output pulse width K
1000 pF
10000 pF
100000 pF
1000000 pF
Cext
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 14 of 15
Package Dimensions
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-16DAV
—
Conforms
0.24 g
*Ni/Pd/Au plating
*0.20 ± 0.05
*0.40 ± 0.06
0.12
0.15
M
2.20 Max 5.5
10.06
0.80 Max
16 9
18
10.5 Max
+ 0.20
– 0.30
7.80
0.70 ± 0.20
0˚ – 8˚
0.10 ± 0.10
1.15
1.27
As of January, 2003
Unit: mm
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
1.27
16 9
18
0.15
0.25
M
1.75 Max 3.95
*0.20 ± 0.05
9.9
0˚ – 8˚
10.3 Max
+ 0.10
– 0.30
6.10
+ 0.67
– 0.20
0.60
+ 0.11
– 0.04
0.14
*0.40 ± 0.06
0.635 Max 1.08
As of January, 2003
Unit: mm
HD74LV123A
Rev.6.00 Jun. 02, 2004 page 15 of 15
Package Code
JEDEC
JEITA
Mass
(reference value)
TTP-16DAV
—
—
0.05 g
*Ni/Pd/Au plating
0.50 ± 0.10
0˚ – 8˚
*0.15 ± 0.05
6.40 ± 0.20
0.10
1.10 Max
0.13 M
0.65
18
16 9
4.40
5.00
5.30 Max
0.07
+0.03
–0.04
0.65 Max
1.0
*0.20 ± 0.05
As of January, 2003
Unit: mm
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
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