Ele ctrical Specifications
QADC Electrical Charac teristics
MMC21 07 –Rev. 2.0 Technical Data
MOTO ROLA Electrical Specificatio ns 593
Table 22-8. QADC Conversion Specifications
(VDDH and VDDA = 5.0 Vdc ± 0.5 V, VDD = 2.7 to 3.6 V, VSS = VSSA = 0 Vdc,
VRH – VRL = 5 V ± 0.5 V, TA = TL to TH)
No. Parameter Symbol Min Max Unit
1QADC clock (QCLK) frequency(1) fQCLK 0.5 2.1 MHz
2 Conversion cycles CC 14 28 QCLK
cycles
3Conv ersion time, fQCLK = 2.0 MHz
Mi nimum = C C W / IS T =%00
Maximum = CCW/IST =%11 tCONV 7.0 14.0 µs
4 Stop mode recovery time tSR —10 µs
5Resolution(2) — 5 — mV
6Absolute (total unadjusted) error(3), (4), (5)
fQCLK = 2.0 MHz(2), two clock input samp le time AE –22Counts
7Di sru ptiv e in put injec tion curre nt (6), (7), (8) IINJ(9) –11mA
8Current coupling ratio(10)
PQA
PQB K —
—8x10 –5
8x10 –5 m
9
Increm enta l error due to injection current
All channels have same 10 kΩ < RS <100 kΩ
Channel unde r test has RS = 10 kΩ,
IINJ = I INJMAX, I INJMIN
EINJ —
—
—
+1.0
+1.0
+1.0
Counts
Counts
Counts
10 Source impedance at input(11) RS—100 kΩ
11 Incremental capacitance during sampling(12) CSAMP —5pF
1. Conversion characteristics vary wi th fQCLK rate. Re duced conversion accuracy occurs a t max fQCLK rate. Using the QADC
pins as GPIO functions during conversions may result in degraded results.
2. At VRH – VRL = 5.12 V, one count = 5 mV
3. Accuracy teste d and guaranteed at VRH – VRL = 5.0 V ± 0.5 V
4. Absolute error incl udes 1/ 2 c ount (~ 2.5 m V) of inheren t quanti zation error and ci rcui t (di ffer entia l, i ntegr al, an d offs et) error.
Specificati on assum es that adequate low-pass fi ltering is present on analog input pins — capacitive filter with 0.01 µF to
0.1 µF capaci tor between analog input and anal og ground, typical source isolation impedance o f 10 kΩ.
5. Input signals with large sle w rates or hi gh frequency noise com ponents cannot be conve rted accu rately. These signals may
affect the conver sion accuracy of ot her channels
6. Below di sruptive current conditi ons, the channel being stres sed has conversion values of $3FF for anal og inputs greater
than VRH an d $000 for values less than VRL. This assumes that VRH < VDDA and VRL > VSSA due to the pre sence of the
samp le amplifier. Other channels are not aff ected by non-di sruptiv e conditions.
7. Exceeding l imit may cau se conve rsion error on stress ed chann els and on unst res sed channel s. Trans itio ns withi n the limit
do not aff ect device reliability or cause permanent damage.
8. I nput m ust be c urrent limi ted to the value sp ecifi ed. To dete rmine t he va lue of the req uired c urrent -li mitin g resi stor, calculate
resi stance valu es using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, the n use the lar ger of t he calcul ated val ues.
9. Condition appli es to two adjacent pins.
10. Curr ent coupli ng rati o, K, is def ined as the ratio of the output current, IOut, measured on the pin under test to the injection
current, IINJ, when both adjacent pins are ov erstressed with the specified injection current. K = IOut/ IINJ The input volt age
error on the channel under test is calculated as VERR = IINJ x K x RS.— Continu ed —
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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