MMC2107CEHPU33 - Freescale Semiconductor / Motorola

MMC2107/D

REV 2

MMC2107

Technical Data

HCMOS

Mic ro c ontro ll er Uni t

M•CORE M•

ORE M•CO

RE M•CORE

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MMC2107 – Rev. 2.0 Technical Data

MOTOROLA 3

MMC2107

Technical Data

Motorola reserves the right to make changes without further notice to any products

herein. Motorola makes no warranty, representation or guarantee regarding the

suitability of its products for any particular purpose, nor does Motorola assume any

liab ility a rising out of the application or u se of any product or ci rcuit, a nd specifica lly

disclaims any and all liability, including without limitation consequential or incidental

damages. "Typical" parameters which may be provided in Motorola data sheets and/or

specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including "Typicals" must be validated for

each customer application by customer’s technical experts. Motorola does not convey

any license under its patent rights nor the rights of others. Motorola products are not

designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to supp ort or sustain life,

or for an y ot her app lication in which the failure o f the M otorola prod uct could crea te a

situation where personal injury or death may occur. Should Buyer purchase or use

Motorola products for any such unintended or unauthorized application, Buyer shall

indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of personal

injury or death associated with such unintended or unauthorized use, even if such claim

alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola and are registered trademarks of Motorola, Inc.

DigitalDNA is a trademark of Motorola, Inc. © Motorola, Inc., 2000

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Technical Data MMC2107 –Rev. 2.0

4MOTOROLA

Technical Data

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MMC21 07 –Rev. 2.0  Technical Data
MOTO ROLA List of S ect ions  5
Technical Data — MMC2107
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .43
Section 2. System Memory Map  . . . . . . . . . . . . . . . . . . .51
Section 3. Chip Configuration Module (CCM)  . . . . . . . .89
Section 4. Signal Description. . . . . . . . . . . . . . . . . . . . .107
Section 5. Reset Controller Module. . . . . . . . . . . . . . . .129
Section 6. M•CORE M210 Central Processor 
Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . .143
Section 7. Interrupt Controller Module . . . . . . . . . . . . .153
Section 8. Static Random-Access Memory 
(SRAM). . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Section 9. Non-Volatile Memory FLASH 
(CMFR). . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
Section 10. Clock Module. . . . . . . . . . . . . . . . . . . . . . . .221
Section 11. Ports Module . . . . . . . . . . . . . . . . . . . . . . . .247
Section 12. Edge Port Module (EPORT) . . . . . . . . . . . .261
Section 13. Watchdog Timer Module  . . . . . . . . . . . . . .271
Section 14 . Programmable Interrupt Timer 
Modules (PIT1 and PIT2)  . . . . . . . . . . . . . .281
Section 15. Timer Modules (TIM1 and TIM2). . . . . . . . .293
    
  
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Technical Data MMC2107 –Rev. 2.0
6 List of S ect ions MOTOROLA
Li st of  Sec ti o ns
Section 16. Serial Communications Interface 
Modules (SCI1 and SCI2) . . . . . . . . . . . . . .329
Section 17. Serial Peripheral Interface 
Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . .371
Section 18. Queued Analog-to-Digital 
Converter (QADC). . . . . . . . . . . . . . . . . . . .399
Section 19. External Bus Interface Module (EBI) . . . . .503
Section 20. Chip Select Module. . . . . . . . . . . . . . . . . . .521
Section 21. JTAG Test Access Port and OnCE . . . . . .533
Section 22. Electrical Specifications. . . . . . . . . . . . . . .585
Section 23. Mechanical Specifications . . . . . . . . . . . . .609
Section 24. Ordering Information  . . . . . . . . . . . . . . . . .615
    
  
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MMC21 07 –Rev. 2.0  Technical Data
MOTOROLA Table of Contents  7
Technical Data — MMC2107
Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
1.4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Section 2. System M emory Map
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.3 Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.4 Register Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Section 3. Chip Configuration Module (CCM)
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.4.1 Master Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.4.2 Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.4.3 Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.4.4 Factory Access Slave Test (FAST) Mode  . . . . . . . . . . . . . .91
3.5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
3.6 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
    
  
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Technical Data MMC2107 –Rev. 2.0
Table of Contents M OTOROLA
Table of Contents
7 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.1 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.2 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.3 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.3.1 Chip Configuration Register. . . . . . . . . . . . . . . . . . . . . . .94
7.3.2 Reset Configuration Register. . . . . . . . . . . . . . . . . . . . . .9 7
7.3.3 Chip Identification Register . . . . . . . . . . . . . . . . . . . . . . .99
7.3.4 Chip T est Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.2 Chip Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
8.3 Boot Device Selection  . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
8.4 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . .105
8.5 Clock Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
8.6 Internal FLASH Configuration  . . . . . . . . . . . . . . . . . . . . . .106
9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Section 4. Signal Description
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
3 Package Pinout Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .110
4 MMC2107 Specific Implementation Signal Issues . . . . . . . . .120
4.1 RSTOUT Signal Functions. . . . . . . . . . . . . . . . . . . . . . . . .120
4.2 INT Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
5 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
5.1 Reset Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
5.1.1 Reset In (RESET)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
5.1.2 Reset Out (RSTOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .121
5.2 Phase-Lock Loop (PLL) and Clock Signals . . . . . . . . . . . .122
5.2.1 External Clock In (EXTAL). . . . . . . . . . . . . . . . . . . . . . .122
5.2.2 Crystal (XTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
5.2.3 Clock Out (CLKOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . .122
5.2.4 Synthesizer Power (VDDSYN and VSSSYN). . . . . . . . . . .122
    
  
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Table of Contents
MMC21 07 –Rev. 2.0 Technical Data 
MOTOROLA Table of Contents  9
5.3 External Memory Interface Signals  . . . . . . . . . . . . . . . . . .122
5.3.1 Data Bus (D[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
5.3.2 Show Cycle Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . .123
5.3.3 Transfer Acknowledge (TA). . . . . . . . . . . . . . . . . . . . . .123
5.3.4 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . .123
5.3.5 Emulation Mode Chip Selects (CSE [1:0]) . . . . . . . . . . .123
5.3.6 Transfer Code (TC[2:0]). . . . . . . . . . . . . . . . . . . . . . . . .123
5.3.7 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
5.3.8 Address Bus (A[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .124
5.3.9 Enabl e Byte (EB[3:0])  . . . . . . . . . . . . . . . . . . . . . . . . . .124
5.3.10 Chip Sele ct (CS[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .124
5.3.11 Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
5.4 Edge P ort Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
5.4.1 External Interrupts (INT[7:6]) . . . . . . . . . . . . . . . . . . . . .124
5.4.2 External Interrupts (INT[5:2]) . . . . . . . . . . . . . . . . . . . . .124
5.4.3 External Interrupts (INT[1:0]) . . . . . . . . . . . . . . . . . . . . .125
5.5 Serial Peripheral Interface Module Signals . . . . . . . . . . . .125
5.5.1 Master Out/Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . .125
5.5.2 Master In/Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . .125
5.5.3 Serial Clock (SCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5.5.4 Slave Select (SS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5.6 Serial Communications Interface Module Signals . . . . . . .125
5.6.1 Receive Data (RXD1 and RXD2). . . . . . . . . . . . . . . . . .125
5.6.2 Transmit Data (TXD1 and TXD2). . . . . . . . . . . . . . . . . .126
5.7 Timer Signals (ICOC1[3:0] and ICOC2[3:0]) . . . . . . . . . . .126
5.8 Analog-to-Digital Converter Signals. . . . . . . . . . . . . . . . . .126
5.8.1 Analog Inputs (PQA[4:3], PQA[1:0], 
and PQB[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
5.8.2 Analog Reference (VRH and VRL)  . . . . . . . . . . . . . . . . .126
5.8.3 Analog Supply (VDDA and VSSA) . . . . . . . . . . . . . . . . . .126
5.8.4 Positive Supply (VDDH)  . . . . . . . . . . . . . . . . . . . . . . . . .126
5.9 Debug and Emulation Support Signals  . . . . . . . . . . . . . . .127
5.9.1 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.9.2 Test Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.9.3 Test Mode Select (TMS ) . . . . . . . . . . . . . . . . . . . . . . . .127
5.9.4 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.9.5 Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . .127
5.9.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
    
  
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Technical Data MMC2107 –Rev. 2.0
Table of Contents M OTOROLA
Table of Contents
5.10 Test Signal (TEST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
5.11 Power and Ground Signals  . . . . . . . . . . . . . . . . . . . . . . . .128
5.11.1 Power for FLASH Erase/Program (VPP) . . . . . . . . . . . .128
5.11.2 Power and Ground for FLASH Array 
(VDDF and VSSF) . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
5.11.3 Standby Power (VSTBY) . . . . . . . . . . . . . . . . . . . . . . . . .128
5.11.4 Positive Supply (VDD). . . . . . . . . . . . . . . . . . . . . . . . . . .128
5.11.5 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Section 5. Reset Controller Module
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
6 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .132
6.1 Reset Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .133
6.2 Reset Status Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
6.3 Reset Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
7.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
7.1.1 Power-On Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
7.1.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
7.1.3 Watchdog Timer Reset  . . . . . . . . . . . . . . . . . . . . . . . . .137
7.1.4 Loss of Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .137
7.1.5 Loss of Lock Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
7.1.6 Software Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
7.2 Reset Control Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
7.2.1 Synchronous Reset Requests . . . . . . . . . . . . . . . . . . . .138
7.2.2 Internal Reset Request . . . . . . . . . . . . . . . . . . . . . . . . .140
7.2.3 Power-On Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
7.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
7.3.1 Reset F low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
7.3.2 Reset Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
    
  
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Table of Contents
MMC21 07 –Rev. 2.0 Technical Data 
MOTOROLA Table of Contents  11
Section 6. M•CORE M 210 Central
Processor Unit (CPU)
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
4 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . .145
5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
6 Data F o rmat Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
7 Operand Addressing Capabilities. . . . . . . . . . . . . . . . . . . . . .150
8 Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Section 7. Interrupt Controller Module
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
4 Low-Power Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . .154
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
6 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
7 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .155
7.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
7.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
7.2.1 Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . .157
7.2.2 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . .159
7.2.3 Interrupt Force Registers . . . . . . . . . . . . . . . . . . . . . . . .160
7.2.4 Interrupt Pending Register. . . . . . . . . . . . . . . . . . . . . . .162
7.2.5 Normal Interrupt Enable Register. . . . . . . . . . . . . . . . . .163
7.2.6 Normal Interrupt Pending Register. . . . . . . . . . . . . . . . .164
7.2.7 Fast Interrupt Enable Register. . . . . . . . . . . . . . . . . . . .165
7.2.8 Fast Interrupt Pending Register. . . . . . . . . . . . . . . . . . .166
7.2.9 Priority Level Select Registers. . . . . . . . . . . . . . . . . . . .167
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
8.1 Interrupt Sources and Prioritization . . . . . . . . . . . . . . . . . .168
8.2 Fast and Normal Interrupt Requests . . . . . . . . . . . . . . . . .168
8.3 Autovectored and Vectored Interrupt Requests. . . . . . . . .169
    
  
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Technical Data MMC2107 –Rev. 2.0
Table of Contents M OTOROLA
Table of Contents
8.4 Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
8.4.1 M•CORE Processor Configuration. . . . . . . . . . . . . . . . .171
8.4.2 Interrupt Controller Configuration. . . . . . . . . . . . . . . . . .171
8.4.3 Interrupt Source Configuration. . . . . . . . . . . . . . . . . . . .172
8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
Section 8. Static Random-Access Memory (SRAM)
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
5 Standby Power Supply Pin (VSTBY) . . . . . . . . . . . . . . . . . . . .176
6 Standby Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
7 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
Section 9. Non-Volatile Memory FLASH (CMFR)
1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
4.2 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
6 Glossary of Terms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
7 Registers and Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .186
7.1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
7.1.1 CMFR Module Configuration Register. . . . . . . . . . . . . .188
7.1.2 CMFR Module Test Register . . . . . . . . . . . . . . . . . . . . .193
7.1.3 CMFR High-Voltage Control Register . . . . . . . . . . . . . .196
7.2 Array Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
7.2.1 Read Page Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
7.2.2 Program Page Buffers . . . . . . . . . . . . . . . . . . . . . . . . . .204
    
  
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Table of Contents
MMC21 07 –Rev. 2.0 Technical Data 
MOTOROLA Table of Contents  13
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
8.1 Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
8.2 Register Read and Write Operation. . . . . . . . . . . . . . . . . .205
8.3 Array Read Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
8.4 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
8.4.1 Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
8.4.2 Program Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . .211
8.4.3 Programming Shadow Information. . . . . . . . . . . . . . . . .212
8.4.4 Program Pulse-Width and Amplitude Modulation . . . . .213
8.4.5 Overprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
8.5 Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
8.5.1 Erase Sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
8.5.2 Erase Margin Reads  . . . . . . . . . . . . . . . . . . . . . . . . . . .218
8.5.3 Erasing Shadow Information Words. . . . . . . . . . . . . . . .219
8.6 Erase Pulse Amplitude and W idth Modulation. . . . . . . . . .219
8.7 Emulation Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
9 Master Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Section 10. Clock Module
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
4.1 Normal PLL Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
4.2 1:1 PLL Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
4.3 External Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
4.4 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
4.4.1 Wait and Doze Modes . . . . . . . . . . . . . . . . . . . . . . . . . .223
4.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
6 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
6.1 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
6.2 XTAL  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
6.3 CLKOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
    
  
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Technical Data MMC2107 –Rev. 2.0
Table of Contents M OTOROLA
Table of Contents
6.4 VDDSYN and VSSSYN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
6.5 RSTOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
7 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .226
7.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
7.2 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
7.2.1 Synthesizer Control Register. . . . . . . . . . . . . . . . . . . . .227
7.2.2 Synthesizer Status Register. . . . . . . . . . . . . . . . . . . . . .230
7.2.3 Synthesizer Test Register . . . . . . . . . . . . . . . . . . . . . . .233
7.2.4 Synthesizer Test Register 2. . . . . . . . . . . . . . . . . . . . . .234
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
8.1 System Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
8.2 System Clocks Generation. . . . . . . . . . . . . . . . . . . . . . . . .236
8.3 PLL Lock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
8.3.1 PLL Loss of Lock Conditions . . . . . . . . . . . . . . . . . . . . .238
8.3.2 PLL Loss of Lock Reset. . . . . . . . . . . . . . . . . . . . . . . . .238
8.4 Loss of Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .238
8.4.1 Alternate Clock Selection. . . . . . . . . . . . . . . . . . . . . . . .239
8.4.2 Loss-of-Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .242
8.5 Clock Operation During Reset . . . . . . . . . . . . . . . . . . . . . .243
8.6 PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
8.6.1 Phase and Frequency Detector (PFD). . . . . . . . . . . . . .245
8.6.2 Charge Pump/Loop Filter. . . . . . . . . . . . . . . . . . . . . . . .245
8.6.3 Voltage Control Output (VCO) . . . . . . . . . . . . . . . . . . . .246
8.6.4 Multiplication Factor Divider (MFD) . . . . . . . . . . . . . . . .246
9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
Section 11. Ports Module
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
3 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
4 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .249
4.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
4.2 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
4.2.1 Port Output Data Registers . . . . . . . . . . . . . . . . . . . . . .251
4.2.2 Port Data Direction Registers. . . . . . . . . . . . . . . . . . . . .252
    
  
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Table of Contents
MMC21 07 –Rev. 2.0 Technical Data 
MOTOROLA Table of Contents  15
4.2.3 Port Pin Data/Set Data Registers  . . . . . . . . . . . . . . . . .253
4.2.4 Port Clear Output Data Registers  . . . . . . . . . . . . . . . . .254
4.2.5 Port C/D Pin Assignment Register. . . . . . . . . . . . . . . . .255
4.2.6 Port E Pin Assignment Register. . . . . . . . . . . . . . . . . . .256
5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
5.1 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
5.2 Port Digital I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
Section 12. E dge Port Module (EPORT)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
3 Low-Power Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . .262
3.1 Wait and Doze Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
4 Interrupt/General -Purpose I/O Pin Descriptions. . . . . . . . . . .263
5 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .263
5.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
5.2.1 EPORT Pin Assignment Register  . . . . . . . . . . . . . . . . .264
5.2.2 EPORT Data Direction Register. . . . . . . . . . . . . . . . . . .266
5.2.3 Edge Port Interrupt Enable Register . . . . . . . . . . . . . . .267
5.2.4 Edge Port Data Register . . . . . . . . . . . . . . . . . . . . . . . .268
5.2.5 Edge Port Pin Data Register . . . . . . . . . . . . . . . . . . . . .268
5.2.6 Edge Port Flag Register. . . . . . . . . . . . . . . . . . . . . . . . .269
Section 13 . Watchdog Timer Module
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
3.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
3.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
3.4 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
    
  
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Technical Data MMC2107 –Rev. 2.0
Table of Contents M OTOROLA
Table of Contents
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
6 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .274
6.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
6.2.1 Watchdog Control Register . . . . . . . . . . . . . . . . . . . . . .275
6.2.2 Watchdog Modulus Register . . . . . . . . . . . . . . . . . . . . .277
6.2.3 Watchdog Count Register . . . . . . . . . . . . . . . . . . . . . . .278
6.2.4 Watchdog Servi ce Register . . . . . . . . . . . . . . . . . . . . . .279
Section 14. Programmable Interrupt Timer Modules
(PIT1 and PIT2)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
3 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
4.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
4.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
4.4 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
6 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .284
6.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
6.2.1 PIT Control and Status Register  . . . . . . . . . . . . . . . . . .285
6.2.2 PIT Modulus Register  . . . . . . . . . . . . . . . . . . . . . . . . . .288
6.2.3 PIT Count Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
7.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . .290
7.2 Free-Running Timer Operation  . . . . . . . . . . . . . . . . . . . . .291
7.3 Timeout Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
8 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
    
  
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Table of Contents
MMC21 07 –Rev. 2.0 Technical Data 
MOTOROLA Table of Contents  17
Section 15. Timer Modules (TIM1 and TIM2 )
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
5.1 Supervisor and User Modes. . . . . . . . . . . . . . . . . . . . . . . .297
5.2 Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
5.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
5.4 Wait, Doze, and Debug Modes  . . . . . . . . . . . . . . . . . . . . .297
5.5 Test Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
6.1 ICOC[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
6.2 ICOC3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
7 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .298
7.1 Timer Input Capture/Output Compare 
Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300
7.2 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . .301
7.3 Timer Output Compare 3 Mask Register . . . . . . . . . . . . . .302
7.4 Timer Output Compare 3 Data Register. . . . . . . . . . . . . . .303
7.5 Timer Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . .304
7.6 Timer System Control Register 1. . . . . . . . . . . . . . . . . . . .305
7.7 Timer Toggle-On-Overflow Register  . . . . . . . . . . . . . . . . .306
7.8 Timer Control Register 1  . . . . . . . . . . . . . . . . . . . . . . . . . .307
7.9 Timer Control Register 2  . . . . . . . . . . . . . . . . . . . . . . . . . .308
7.10 Timer Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . .309
7.11 Timer System Control Regi ster 2. . . . . . . . . . . . . . . . . . . .310
7.12 Timer Flag Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
7.13 Timer Flag Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
7.14 Timer Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .314
7.15 Pulse Accumulator Control Register  . . . . . . . . . . . . . . . . .315
7.16 Pulse Accumulator Flag Register. . . . . . . . . . . . . . . . . . . .317
7.17 Pulse Accumulator Counter Registers . . . . . . . . . . . . . . . .318
7.18 Timer Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . .319
7.19 Timer P ort Data Direction Register  . . . . . . . . . . . . . . . . . .320
7.20 Timer Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
    
  
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Technical Data MMC2107 –Rev. 2.0
Table of Contents M OTOROLA
Table of Contents
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
8.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
8.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
8.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
8.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
8.4.1 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .323
8.4.2 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . .324
8.5 General-Purpose I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . .325
9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326
10.1 Timer Channel Interrupts (CxF) . . . . . . . . . . . . . . . . . . . . .326
10.2 Pulse Accumulator Overfl ow (PAOVF). . . . . . . . . . . . . . . .327
10.3 Pulse Accumulator Input (PAIF). . . . . . . . . . . . . . . . . . . . .327
10.4 Timer Overflow (TOF)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
Section 16. Serial Co mmunications Interface Modules 
(SC I1 and SCI2)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
5.1 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
6.1 RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
6.2 TXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
7 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .334
7.1 SCI Baud Rate Registers. . . . . . . . . . . . . . . . . . . . . . . . . .336
7.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
7.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
7.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
7.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
7.6 SCI Data R egisters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
7.7 SCI Pullup and Reduced Drive Register . . . . . . . . . . . . . .346
    
  
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Table of Contents
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7.8 SCI Port Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .347
7.9 SCI Data D irection Register. . . . . . . . . . . . . . . . . . . . . . . .348
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
9 Data Form at . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
10 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
11 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
11.1 Frame Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
11.2 Transmitting a Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
11.3 Break Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
11.4 Idle Frames  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
12 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
12.1 Frame Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
12.2 Receiving a Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
12.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
12.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
12.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
12.5.1 Slow Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .363
12.5.2  Fast Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .364
12.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
12.6.1 Idle Input Line Wakeup (WAKE = 0)  . . . . . . . . . . . . . . .365
12.6.2 Address Mark Wakeup (WAKE = 1). . . . . . . . . . . . . . . .365
13 Single-Wire Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
14 Loop Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
15 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368
16 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
17 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
17.1 Transmit Data Register Empty. . . . . . . . . . . . . . . . . . . . . .369
17.2 Transmission Complete . . . . . . . . . . . . . . . . . . . . . . . . . . .369
17.3 Receive Data Register Full. . . . . . . . . . . . . . . . . . . . . . . . .370
17.4 Idle Receiver Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
17.5 Overrun  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
    
  
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Technical Data MMC2107 –Rev. 2.0
Table of Contents M OTOROLA
Table of Contents
Sect ion 17. Se rial Peripheral In terface Module (SPI)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
6 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
6.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . .374
6.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . .374
6.3 SCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
6.4 SS (Slave Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
7 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .375
7.1 SPI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
7.2 SPI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
7.3 SPI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . .379
7.4 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
7.5 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
7.6 SPI Pull up and Reduced Drive Register  . . . . . . . . . . . . . .383
7.7 SPI Port Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .384
7.8 SPI Port Data Direction Register . . . . . . . . . . . . . . . . . . . .385
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
8.1 Master Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
8.2 Slave Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
8.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
8.3.1 Transfer Format When CPHA = 1 . . . . . . . . . . . . . . . . .388
8.3.2 Transfer Format When CPHA = 0 . . . . . . . . . . . . . . . . .390
8.4 SPI Baud Rate Generation. . . . . . . . . . . . . . . . . . . . . . . . .393
8.5 Slave-Select Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393
8.6 Bidirectional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
8.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
8.7.1 Write Collision Error. . . . . . . . . . . . . . . . . . . . . . . . . . . .395
8.7.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
8.8 Low-Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . .396
8.8.1 Run Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
8.8.2 Doze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
8.8.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
    
  
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Table of Contents
MMC21 07 –Rev. 2.0 Technical Data 
MOTOROLA Table of Contents  21
9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
10.1 SPI Interrupt Flag (SPIF) . . . . . . . . . . . . . . . . . . . . . . . . . .397
10.2 Mode Fault (MODF) Fl ag . . . . . . . . . . . . . . . . . . . . . . . . . .397
Section 18. Queued Analog-to-Digital
Converter (QADC)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
5.1 Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
6 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
6.1 Port QA Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
6.1.1 Port QA Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . .406
6.1.2 Port QA Digital Input/Output Pins  . . . . . . . . . . . . . . . . .407
6.2 Port QB Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
6.2.1 Port QB Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . .407
6.2.2 Port QB Digital Input Pins  . . . . . . . . . . . . . . . . . . . . . . .407
6.3 External Trigger Input Pins. . . . . . . . . . . . . . . . . . . . . . . . .408
6.4 Multiplexed Address Output Pins. . . . . . . . . . . . . . . . . . . .408
6.5 Multiplexed Analog Input Pins . . . . . . . . . . . . . . . . . . . . . .409
6.6 Voltage Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .409
6.7 Dedicated Analog Supply Pins. . . . . . . . . . . . . . . . . . . . . .409
7 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
8 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
8.1 QADC Module Configuration Register . . . . . . . . . . . . . . . .411
8.2 QADC Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412
8.3 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412
8.4 Port QA Data Direction Register  . . . . . . . . . . . . . . . . . . . .414
    
  
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Technical Data MMC2107 –Rev. 2.0
Table of Contents M OTOROLA
Table of Contents
8.5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
8.5.1 Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
8.5.2 Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
8.5.3 QADC Control Register 2. . . . . . . . . . . . . . . . . . . . . . . .422
8.6 Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
8.6.1 QADC Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . .427
8.6.2 QADC Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . .436
8.7 Conversion Command Word Table . . . . . . . . . . . . . . . . . .437
8.8 Result Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441
8.8.1 Right-Justified Unsigned Result Register. . . . . . . . . . . .441
8.8.2 Left-Justified Signed Result Register. . . . . . . . . . . . . . .442
8.8.3 Left-Justified Unsigned Result Register. . . . . . . . . . . . .442
9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
9.1 QADC Bus Accessing  . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
9.2 External Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
9.2.1 External Multiplexing Operation. . . . . . . . . . . . . . . . . . .443
9.2.2 Module Version Options. . . . . . . . . . . . . . . . . . . . . . . . .444
9.2.3 External Multiplexed Address Configuration . . . . . . . . .446
9.3 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .446
9.3.1 Analog-to-Digital Converter Operation. . . . . . . . . . . . . .446
9.3.2 Conversion Cycle Times . . . . . . . . . . . . . . . . . . . . . . . .446
9.3.3 Channel Decode and Multiplexer. . . . . . . . . . . . . . . . . .448
9.3.4 Sample Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .448
9.3.5 Digital-to-Analog Converter (DAC) Array. . . . . . . . . . . .449
9.3.6 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .449
9.3.7 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .449
9.3.8 Successive-Approximation Register . . . . . . . . . . . . . . .449
9.3.9 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450
10 Digital Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450
10.1 Queue Priority  Timing Examples. . . . . . . . . . . . . . . . . . . .450
10.1.1 Queue Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451
10.1.2 Queue Priority Schemes . . . . . . . . . . . . . . . . . . . . . . . .453
10.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465
10.3 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .466
10.4 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467
10.5 Reserved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467
    
  
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Table of Contents
MMC21 07 –Rev. 2.0 Technical Data 
MOTOROLA Table of Contents  23
10.6 Single-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467
10.6.1 Software-Initiated Single-Scan Mode. . . . . . . . . . . . . . .468
10.6.2 External Trigger Single-Scan Mode. . . . . . . . . . . . . . . .469
10.6.3 External Gated Single-Scan Mode. . . . . . . . . . . . . . . . .470
10.6.4 Interval Timer Single-Scan Mode. . . . . . . . . . . . . . . . . .470
10.7 Continuous-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . .472
10.7.1 Software-Initiated Continuous-Scan Mode. . . . . . . . . . .473
10.7.2 External Trigger Continuous-Scan Mode. . . . . . . . . . . .474
10.7.3 External Gated Continuous-Scan Mode  . . . . . . . . . . . .474
10.7.4 Periodic Timer Continuous-Scan Mode . . . . . . . . . . . . .475
10.8 QADC Clock (QCLK) Generation. . . . . . . . . . . . . . . . . . . .476
10.9 Periodic/Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .480
10.10 Conversion Command Word Table . . . . . . . . . . . . . . . . . .481
10.11 Result Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .485
11 Pin Connection Considerations  . . . . . . . . . . . . . . . . . . . . . . .486
11.1 Analog Reference Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .486
11.2 Analog P ower Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .486
11.3 Conversion Timing Schemes . . . . . . . . . . . . . . . . . . . . . . .488
11.4 Analog Supply Filtering and Grounding . . . . . . . . . . . . . . .490
11.5 Accommodating Positive/Negative Stress Conditions . . . .494
11.6 Analog Input Considerations . . . . . . . . . . . . . . . . . . . . . . .495
11.7 Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .497
11.7.1 Settling Time for the External Circuit . . . . . . . . . . . . . . .498
11.7.2 Error Resulting from Leakage . . . . . . . . . . . . . . . . . . . .499
12 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500
12.1 Interrupt Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500
12.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .501
Section 19. External Bus Interface Module (EBI)
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .503
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .504
3 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .505
3.1 Data Bus (D[31:0])  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .506
3.2 Show Cycle Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . . . .506
3.3 Transfer Acknowledge (TA) . . . . . . . . . . . . . . . . . . . . . . . .506
3.4 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . . . .506
    
  
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Technical Data MMC2107 –Rev. 2.0
Table of Contents M OTOROLA
Table of Contents
3.5 Emulation Mode Chip Selects (CSE[1:0])  . . . . . . . . . . . . .506
3.6 Transfer Code (TC[2:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .506
3.7 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .507
3.8 Address Bus (A[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . .507
3.9 Enabl e Byte (EB[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . . . .507
3.10 Chip Sele cts (CS[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . .507
3.11 Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .507
3.12 Transfer Size (TSIZ[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .507
3.13 Processor Status (PSTAT[3:0]) . . . . . . . . . . . . . . . . . . . . .507
4 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .508
5 Operand Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .508
6 Enabl e Byte Pins (EB[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .510
7 Bus Master Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .510
7.1 Read Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511
7.1.1 State 1 (X1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .512
7.1.2 Optional Wait States (X2W). . . . . . . . . . . . . . . . . . . . . .512
7.1.3 State 2 (X2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .512
7.2 Write Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .513
7.2.1 State 1 (X1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .514
7.2.2 Optional Wait States (X2W). . . . . . . . . . . . . . . . . . . . . .514
7.2.3 State 2 (X2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .514
8 Bus Exception Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .516
8.1 Transfer Error Termination. . . . . . . . . . . . . . . . . . . . . . . . .516
8.2 Transfer Abort Termination  . . . . . . . . . . . . . . . . . . . . . . . .516
9 Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .516
9.1 Emulation Chip-Selects (CSE[1:0])  . . . . . . . . . . . . . . . . . .516
9.2 Internal Data Transfer Display (Show Cycles) . . . . . . . . . .517
9.3 Show Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .518
10 Bus Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .519
11 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .520
Section 20. Chip Select Module
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .521
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .521
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .522
    
  
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Table of Contents
MMC21 07 –Rev. 2.0 Technical Data 
MOTOROLA Table of Contents  25
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .523
5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524
6 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .524
6.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524
6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .525
7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530
8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531
Section 21. JTAG Test Access Port and OnCE
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535
3 Top-Level Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . .537
3.1 Test Clock (T CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
3.2 Test Mode Select (TMS)  . . . . . . . . . . . . . . . . . . . . . . . . . .538
3.3 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
3.4 Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . . . .538
3.5 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
3.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538
4 Top-Level TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . .540
5 Instruction Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .541
5.1 EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .541
5.2 IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542
5.3 SAMPLE/P RELOAD Instruction. . . . . . . . . . . . . . . . . . . . .543
5.4 ENABLE_MCU _ONCE Instruction. . . . . . . . . . . . . . . . . . .543
5.5 HIGHZ Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544
5.6 CLAMP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544
5.7 BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544
6 IDCODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545
7 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .546
8 Boundary SCAN Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .546
9 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .546
10 Non-Scan Chain Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .547
11 Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547
12 Low-Level TAP (OnCE) Module . . . . . . . . . . . . . . . . . . . . . . .553
    
  
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Technical Data MMC2107 –Rev. 2.0
Table of Contents M OTOROLA
Table of Contents
13 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555
13.1 Debug Serial Input (TDI)  . . . . . . . . . . . . . . . . . . . . . . . . . .555
13.2 Debug Serial Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . .555
13.3 Debug Serial Output (TDO) . . . . . . . . . . . . . . . . . . . . . . . .555
13.4 Debug Mode Select (TMS). . . . . . . . . . . . . . . . . . . . . . . . .556
13.5 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
13.6 Debug Event (DE ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
14 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
14.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
14.2 OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . .558
14.3 OnCE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .559
14.3 . 1 In terna l Debug Request Input (IDR)  . . . . . . . . . . . . . . .559
14.3.2 CPU Debug Request (DBGRQ). . . . . . . . . . . . . . . . . . .560
14.3.3 CPU Debug Acknowledge (DBGACK). . . . . . . . . . . . . .560
14.3.4 CPU B reakpoint Request (BRKRQ). . . . . . . . . . . . . . . .560
14.3.5 CPU A ddress, Attributes (ADDR, ATTR). . . . . . . . . . . .560
14.3.6 CPU Status (PSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . .560
14.3.7 OnCE Debug Output (DEBUG) . . . . . . . . . . . . . . . . . . .560
14.4 OnCE Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . .561
14.4.1 OnCE Command Register . . . . . . . . . . . . . . . . . . . . . . .561
14.4.2 OnCE Control Register . . . . . . . . . . . . . . . . . . . . . . . . .564
14.4.3 OnCE Status Register . . . . . . . . . . . . . . . . . . . . . . . . . .568
14.5 OnCE Decoder (ODEC). . . . . . . . . . . . . . . . . . . . . . . . . . .570
14.6 Memory Breakpoint Logic. . . . . . . . . . . . . . . . . . . . . . . . . .570
14.6.1 Memory Address Latch (MAL). . . . . . . . . . . . . . . . . . . .571
14.6.2 Breakpoint Address Base Registers  . . . . . . . . . . . . . . .571
14.7 Breakpoint Address Mask Registers . . . . . . . . . . . . . . . . .571
14.7.1 Breakpoint Address Comparators . . . . . . . . . . . . . . . . .572
14.7.2 Memory Breakpoint Counters  . . . . . . . . . . . . . . . . . . . .572
14.8 OnCE Trace Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572
14.8.1 OnCE Trace Counter. . . . . . . . . . . . . . . . . . . . . . . . . . .573
14.8.2 Trace Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .574
14.9 Methods of Entering Debug Mode . . . . . . . . . . . . . . . . . . .574
14.9.1 Debug Request During RESET . . . . . . . . . . . . . . . . . . .574
14.9.2 Debug Request During Normal Activity . . . . . . . . . . . . .575
14.9.3 Debug Request During Stop, Doze, or Wait Mode  . . . .575
14.9.4 Software Request During Normal Activity . . . . . . . . . . .575
    
  
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Table of Contents
MMC21 07 –Rev. 2.0 Technical Data 
MOTOROLA Table of Contents  27
14.10 Enabling OnCE Trace Mode  . . . . . . . . . . . . . . . . . . . . . . .575
14.11 Enabling OnCE Memory Breakpoints. . . . . . . . . . . . . . . . .576
14.12 Pipeline Information and Write-Back Bus Register  . . . . . .576
14.12.1 Program Counter Register. . . . . . . . . . . . . . . . . . . . . . .577
14.12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .577
14.12.3 Control State Register . . . . . . . . . . . . . . . . . . . . . . . . . .577
14.12.4 Writeback Bus Register . . . . . . . . . . . . . . . . . . . . . . . . .579
14.12.5 Processor Status Register. . . . . . . . . . . . . . . . . . . . . . .579
14.13 Instruction Address FIFO Buffer (PC FIFO). . . . . . . . . . . .580
14.14 Reserved Test Control Registers. . . . . . . . . . . . . . . . . . . .581
14.15 Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581
14.16 OnCE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582
14.17 Target Site Debug System Requirements . . . . . . . . . . . . .582
14.18 Interface Connector for JTAG/OnCE Serial Port . . . . . . . .582
Section 22. Electrical Specifications
1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .585
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .585
3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .586
4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .587
5 Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .587
6 Electrostatic Discharge (ESD) Protection. . . . . . . . . . . . . . . .587
7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .588
8 PLL Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .590
9 QADC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . .591
10 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .594
11 External Interface T iming Characteristics. . . . . . . . . . . . . . . .596
12 Reset and Configuration Override Timing  . . . . . . . . . . . . . . .601
13 SPI Timi ng Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .602
14 OnCE, JTAG, and Boundary Scan Timing . . . . . . . . . . . . . . .605
    
  
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Technical Data MMC2107 –Rev. 2.0
28 Table of Contents M OTOROLA
Table of Contents
Section 23. Mechanical  Specifications
23.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609
23.3 Bond Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610
23.4 Package Information for the 144-Pin LQFP . . . . . . . . . . . . . .611
23.5 Package Information for the 100-Pin LQFP . . . . . . . . . . . . . .611
23.6 144-Pin LQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . .612
23.7 100-Pin LQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . .613
Section 24. Ordering Information
24.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .615
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .615
24.3 MC Order Numbers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .615
    
  
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MMC21 07 –Rev. 2.0  Technical Data
MOTO ROLA List of Figures  29
Technical Data — MMC2107
List of Figures
Figure Title Page
1-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2-1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2-2 Register Summary  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3-1 Chip C onfiguration Module Block Diagram  . . . . . . . . . . . . .92
3-2 Chip Configuratio n Register (CCR) . . . . . . . . . . . . . . . . . . .94
3-3 Reset Configuration Register (RCON) . . . . . . . . . . . . . . . . .97
3-4 Chip Identification Register (CIR). . . . . . . . . . . . . . . . . . . . .99
3-5 Chip Te st Register (CTR). . . . . . . . . . . . . . . . . . . . . . . . . .100
4-1 144-Pin LQFP Assignments. . . . . . . . . . . . . . . . . . . . . . . .115
4-2 100-Pin LQFP Assignments. . . . . . . . . . . . . . . . . . . . . . . .116
5-1 Reset Controller Block Diagram. . . . . . . . . . . . . . . . . . . . .131
5-2 Reset Control Reg ister (RCR) . . . . . . . . . . . . . . . . . . . . . .133
5-3 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . .134
5-4 Reset T e st Register (RTR). . . . . . . . . . . . . . . . . . . . . . . . .135
5-5 Reset Control Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
6-1 M•CORE Processor Block Diagram. . . . . . . . . . . . . . . . . .145
6-2 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
6-3 Data Organization in Memory. . . . . . . . . . . . . . . . . . . . . . .149
6-4 Data Organization in Registers  . . . . . . . . . . . . . . . . . . . . .149
7-1 Interrupt Controller Block Diagram. . . . . . . . . . . . . . . . . . .155
7-2 Interrupt Control Register (ICR) . . . . . . . . . . . . . . . . . . . . .157
7-3 Interrupt Status Register (ISR). . . . . . . . . . . . . . . . . . . . . .159
7-4 Interrupt Force Register High (IFRH). . . . . . . . . . . . . . . . .160
7-5 Interrupt Force Register Low (IFRL). . . . . . . . . . . . . . . . . .161
    
  
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Technical Data MMC2107 –Rev. 2.0
30 List of Figures MOTOROLA
Li st of  Figu r e s
Figure Title Page
7-6 Interrupt Pending Register (IPR) . . . . . . . . . . . . . . . . . . . .162
7-7 Normal Interrupt Enable Register (NIER). . . . . . . . . . . . . .163
7-8 Normal Interrupt Pending Register (NIPR). . . . . . . . . . . . .164
7-9 Fast Interrupt Enable Register (FIER) . . . . . . . . . . . . . . . .165
7-10 Fast Interrupt Pending Register (FIPR) . . . . . . . . . . . . . . .166
7-11 Priority Level Select Registers (PLSR0–PLSR39) . . . . . . .167
9-1 CMFR 128-Kbyte Block Diagram. . . . . . . . . . . . . . . . . . . .183
9-2 CMF R Array and Control Register Addressing  . . . . . . . . .186
9-3 CMFR Module Configuration Register (CMFRMCR ) . . . . .188
9-4 CMFR Module Test Register (CMFRMTR) . . . . . . . . . . . .193
9-5 CMFR High-Voltage Control Register (CMFRCTL) . . . . . .196
9-6 Pulse Status Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
9-7 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . .209
9-8 Program State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .210
9-9 FLASH Erasi ng Flowchart . . . . . . . . . . . . . . . . . . . . . . . . .216
9-10 Erase State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
10-1 Clock Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . .224
10-2 Synthesizer Control Register (SYNCR) . . . . . . . . . . . . . . .227
10-3 Synthesizer Status Register (SYNSR) . . . . . . . . . . . . . . . .230
10-4 Synthesizer Test Register (SYNTR). . . . . . . . . . . . . . . . . .233
10-5 Synthesizer Test Register 2 (SYNTR2) . . . . . . . . . . . . . . .234
10-6 Lock Detect Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . .237
10-7 PLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
10-8 Crystal Oscillator Exam p le . . . . . . . . . . . . . . . . . . . . . . . . .244
11-1 Ports Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . .248
11-2 Port Output Data Registers (PORTx). . . . . . . . . . . . . . . . .251
11-3 Port Data Direction Regi sters (DDRx) . . . . . . . . . . . . . . . .252
11-4 Port Pin Data/Set Data Registers (PORTxP/SETx) . . . . . .253
11-5 Port Clear Output Data Registers (CLRx) . . . . . . . . . . . . .254
11-6 Port C, D, I7, and I6 Pin Assignment
Register (PCDPAR). . . . . . . . . . . . . . . . . . . . . . . . . . . .255
11-7 Port E Pin Assignment Register (PEPAR) . . . . . . . . . . . . .256
    
  
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List of Figures
MMC21 07 –Rev. 2.0 Technical Data 
MOTO ROLA List of Figures  31
Figure Title Page
11-8 Digital Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
11-9 Digital Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
12-1 EPORT Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .262
12-2 EPORT  Pin Assignm ent Regi ster (EPPAR). . . . . . . . . . . .264
12-3 EPORT Data Direction Register (EPDDR). . . . . . . . . . . . .266
12-4 EPORT  Port Interrupt Enable Register (EPIER) . . . . . . . .267
12-5 EPORT Port Data Register (E PDR). . . . . . . . . . . . . . . . . .268
12-6 EPORT Port Pin Data Register (EPPDR)  . . . . . . . . . . . . .268
12-7 EPORT  Port Flag Register (EPFR) . . . . . . . . . . . . . . . . . .269
13-1 Watchdog Timer Block Diagram. . . . . . . . . . . . . . . . . . . . .273
13-2 Watchdog Control Register (WCR)  . . . . . . . . . . . . . . . . . .275
13-3 Watchdog Modulus Register (WMR) . . . . . . . . . . . . . . . . .277
13-4 Watchdog Count Register (WCNTR) . . . . . . . . . . . . . . . . .278
13-5 Watchdog Service Register (WSR) . . . . . . . . . . . . . . . . . .279
14-1 PIT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
14-2 PIT Control and Status Register (PCSR). . . . . . . . . . . . . .285
14-3 PIT Modulus Register (PMR) . . . . . . . . . . . . . . . . . . . . . . .288
14-4 PIT Count Register (PCNTR). . . . . . . . . . . . . . . . . . . . . . .289
14-5 Counter Reloading from the Modulus Latch. . . . . . . . . . . .290
14-6 Counter in Free-Running Mode . . . . . . . . . . . . . . . . . . . . .291
15-1 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
15-2 Timer Input Capture/Output Compare
Select Register (TIMIOS) . . . . . . . . . . . . . . . . . . . . . . .300
15-3 Timer Compare Force Register (TIMCFORC) . . . . . . . . . .301
15-4 Timer Output Compare 3 Mask Register (TIMOC3M) . . . .302
15-5 Timer Output Compare 3 Data Register (TIMOC3D). . . . .303
15-6 Timer Counter Register High (TIMCNTH) . . . . . . . . . . . . .304
15-7 Timer Counter Register Low (TIMCNTL) . . . . . . . . . . . . . .304
15-8 Timer System Control Register (TIMSCR1). . . . . . . . . . . .305
15-9 Fast Clear Flag Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
15-10 Timer Toggle-On-Overflow Register (TIMTOV) . . . . . . . . .306
15-11 Timer Control Register 1 (TIMCTL1) . . . . . . . . . . . . . . . . .307
    
  
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Technical Data MMC2107 –Rev. 2.0
32 List of Figures MOTOROLA
Li st of  Figu r e s
Figure Title Page
15-12 Timer Control Register 2 (TIMCTL2) . . . . . . . . . . . . . . . . .308
15-13 Timer Interr upt Enable Register (TIMIE) . . . . . . . . . . . . . .309
15-14 Timer System Control Register 2 (TIMSCR2) . . . . . . . . . .310
15-15 Timer Flag Register 1 (TIMFLG1)  . . . . . . . . . . . . . . . . . . .312
15-16 Timer Flag Register 2 (TIMFLG2)  . . . . . . . . . . . . . . . . . . .313
15-17 Timer Channel [0:3] Register High (TIMCxH)  . . . . . . . . . .314
15-18 Timer Channel [0:3] Register Low (TIMCxL) . . . . . . . . . . .314
15-19 Pulse Accumulator Control Register (TIMPACTL). . . . . . .315
15-20 Pulse Accumulator Flag Register (TIMPAFLG) . . . . . . . . .317
15-21 Pulse Accumulator Counter Register High
(TIMPACNTH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
15-22 Pulse Accumulator Counter Register Low
(TIMPACNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
15-23 Timer Port Data Register (TIMPORT) . . . . . . . . . . . . . . . .319
15-24 Timer Port Data Direction Register (TIMDDR). . . . . . . . . .32 0
15-25 Timer Test Register (TIMTST) . . . . . . . . . . . . . . . . . . . . . .321
15-26 Channel 3 Output Compare/Pulse Accumulator Logic. . . .324
16-1 SCI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
16-2 SCI Baud Rate Register High (SCIBDH) . . . . . . . . . . . . . .336
16-3 SCI Baud Rate Register Low (SCIBDL). . . . . . . . . . . . . . .336
16-4 SCI Control Register 1 (SCICR1). . . . . . . . . . . . . . . . . . . .337
16-5 SCI Control Register 2 (SCICR2). . . . . . . . . . . . . . . . . . . .340
16-6 SCI Status Register 1 (SCISR1)  . . . . . . . . . . . . . . . . . . . .342
16-7 SCI Status Register 2 (SCISR2)  . . . . . . . . . . . . . . . . . . . .344
16-8 SCI Data Register High (SCIDRH). . . . . . . . . . . . . . . . . . .345
16-9 SCI Data Register Low (SCIDRL)  . . . . . . . . . . . . . . . . . . .345
16-10 SCI Pullup and Reduced Drive Register (SCIPURD). . . . .346
16-11 SCI Port Data Register (SCIPORT) . . . . . . . . . . . . . . . . . .347
16-12 SCI Data Direction Register (SCIDDR) . . . . . . . . . . . . . . .348
16-13 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
16-14 Transmitter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .351
16-15 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .356
16-16 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .357
16-17 Start Bit Sear ch Example 1 . . . . . . . . . . . . . . . . . . . . . . . .359
16-18 Start Bit Sear ch Example 2 . . . . . . . . . . . . . . . . . . . . . . . .360
    
  
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List of Figures
MMC21 07 –Rev. 2.0 Technical Data 
MOTO ROLA List of Figures  33
Figure Title Page
16-19 Start Bit Sear ch Example 3 . . . . . . . . . . . . . . . . . . . . . . . .360
16-20 Start Bit Sear ch Example 4 . . . . . . . . . . . . . . . . . . . . . . . .361
16-21 Start Bit Sear ch Example 5 . . . . . . . . . . . . . . . . . . . . . . . .361
16-22 Start Bit Sear ch Example 6 . . . . . . . . . . . . . . . . . . . . . . . .362
16-23 Slow Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
16-24 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
16-25 Single-Wire Operation (LOOPS = 1, RSRC = 1) . . . . . . . .366
16-26 Loop Operation (LOOPS = 1, RSRC = 0)  . . . . . . . . . . . . .367
17-1 SPI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
17-2 SPI Control Register 1 (SPICR1). . . . . . . . . . . . . . . . . . . .376
17-3 SPI Control Register 2 (SPICR2). . . . . . . . . . . . . . . . . . . .378
17-4 SPI Baud Rate Register (SPIBR). . . . . . . . . . . . . . . . . . . .379
17-5 SPI Status Register (SPISR) . . . . . . . . . . . . . . . . . . . . . . .381
17-6 SPI Data Register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . .382
17-7 SPI Pullup and Reduced Drive Register (SPIPURD). . . . .383
17-8 SPI Port Data Register (SPIPORT) . . . . . . . . . . . . . . . . . .384
17-9 SPI Port Data Direction Register (SPIDDR). . . . . . . . . . . .385
17-10 Full-Duplex Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
17-11 SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . .389
17-12 SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . .391
17-13 Transmission Error Due to Master/Slave Clock Skew . . . .392
18-1 QADC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
18-2 QADC Input and Output Signals  . . . . . . . . . . . . . . . . . . . .406
18-3 QADC Module Configuration Register (QADCMCR) . . . . .411
18-4 QADC Test Register (QADCTEST) . . . . . . . . . . . . . . . . . .412
18-5 QADC Port QA Data Register (PORTQA) . . . . . . . . . . . . .413
18-6 QADC Port QB Data Register (PORTQB) . . . . . . . . . . . . .413
18-7 QADC Port QA Data Direction Register (DDRQA). . . . . . .415
18-8 QADC Control Register 0 (QACR0). . . . . . . . . . . . . . . . . .416
18-9 QADC Control Register 1 (QACR1). . . . . . . . . . . . . . . . . .419
18-10 QADC Control Register 2 (QACR2). . . . . . . . . . . . . . . . . .422
18-11 QADC Status Register 0 (QASR0). . . . . . . . . . . . . . . . . . .427
18-12 Queue Status Transition. . . . . . . . . . . . . . . . . . . . . . . . . . .435
18-13 QADC Status Register 1 (QASR1). . . . . . . . . . . . . . . . . . .436
    
  
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Technical Data MMC2107 –Rev. 2.0
34 List of Figures MOTOROLA
Li st of  Figu r e s
Figure Title Page
18-14 Conversion Command Word T able (CCW) . . . . . . . . . . . .437
18-15 Right-Justified Unsigned Result Register (RJURR). . . . . .441
18-16 L eft-Justified Signed Result Register (LJS RR)  . . . . . . . . .442
18-17 Left-Justified Unsigned Result Register ( LJURR) . . . . . . .4 42
18-18 External Multiplexing Configuration . . . . . . . . . . . . . . . . . .445
18-19 QADC Analog Subsystem Block Diagram . . . . . . . . . . . . .447
18-20 Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447
18-21 Bypass Mode Conversion Timing. . . . . . . . . . . . . . . . . . . .448
18-22 QADC Queue Operation with Pause . . . . . . . . . . . . . . . . .452
18-23 CCW Priority Situation 1. . . . . . . . . . . . . . . . . . . . . . . . . . .455
18-24 CCW Priority Situation 2. . . . . . . . . . . . . . . . . . . . . . . . . . .456
18-25 CCW Priority Situation 3. . . . . . . . . . . . . . . . . . . . . . . . . . .457
18-26 CCW Priority Situation 4. . . . . . . . . . . . . . . . . . . . . . . . . . .457
18-27 CCW Priority Situation 5. . . . . . . . . . . . . . . . . . . . . . . . . . .458
18-28 CCW Priority Situation 6. . . . . . . . . . . . . . . . . . . . . . . . . . .459
18-29 CCW Priority Situation 7. . . . . . . . . . . . . . . . . . . . . . . . . . .459
18-30 CCW Priority Situation 8. . . . . . . . . . . . . . . . . . . . . . . . . . .460
18-31 CCW Priority Situation 9. . . . . . . . . . . . . . . . . . . . . . . . . . .460
18-32 CCW Priority Situation 10. . . . . . . . . . . . . . . . . . . . . . . . . .461
18-33 CCW Priority Situation 11. . . . . . . . . . . . . . . . . . . . . . . . . .461
18-34 CCW Freeze Situation 12. . . . . . . . . . . . . . . . . . . . . . . . . .462
18-35 CCW Freeze Situation 13. . . . . . . . . . . . . . . . . . . . . . . . . .462
18-36 CCW Freeze Situation 14. . . . . . . . . . . . . . . . . . . . . . . . . .463
18-37 CCW Freeze Situation 15. . . . . . . . . . . . . . . . . . . . . . . . . .463
18-38 CCW Freeze Situation 16. . . . . . . . . . . . . . . . . . . . . . . . . .463
18-39 CCW Freeze Situation 17. . . . . . . . . . . . . . . . . . . . . . . . . .464
18-40 CCW Freeze Situation 18. . . . . . . . . . . . . . . . . . . . . . . . . .464
18-41 CCW Freeze Situation 19. . . . . . . . . . . . . . . . . . . . . . . . . .464
18-42 QADC Clock Subsystem Functions . . . . . . . . . . . . . . . . . .477
18-43 QADC Clock Pro grammability Examples . . . . . . . . . . . . . .479
18-44 QADC Conversion Queue Operation. . . . . . . . . . . . . . . . .482
18-45 Equivalent Analog Input Circuitry. . . . . . . . . . . . . . . . . . . .487
18-46 Errors Resulting from Clipping . . . . . . . . . . . . . . . . . . . . . .488
18-47 External Positive Edge Trigger Mode 
Timing With Pause . . . . . . . . . . . . . . . . . . . . . . . . . . . .489
18-48 Gated Mode, Single Scan Timing. . . . . . . . . . . . . . . . . . . .491
    
  
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List of Figures
MMC21 07 –Rev. 2.0 Technical Data 
MOTO ROLA List of Figures  35
Figure Title Page
18-49 Gated Mode, Continuous S can Timing  . . . . . . . . . . . . . . .491
18-50 Star-Ground at the Point of Power Supply Origin. . . . . . . .493
18-51 Input Pin Subjected to Negative Stress . . . . . . . . . . . . . . .494
18-52 Input Pin Subjected to Positive Stress . . . . . . . . . . . . . . . .494
18-53 External Multiplexing of Analog Signal Sources. . . . . . . . .496
18-54 Electrical Model of an A/D Input Pin. . . . . . . . . . . . . . . . . .497
19-1 Read Cycle Fl owchart . . . . . . . . . . . . . . . . . . . . . . . . . . . .511
19-2 Write Cycle Flowchart  . . . . . . . . . . . . . . . . . . . . . . . . . . . .513
19-3 M aster Mode  — 1-Clock Read and Write Cycle. . . . . . . . .515
19-4 M aster Mode  — 2-Clock Read and Write Cycle. . . . . . . . .515
19-5 Internal (Show) Cycle Followed . . . . . . . . . . . . . . . . . . . . . . . .
by External 1-Clock Read . . . . . . . . . . . . . . . . . . . . . . .518
19-6 Internal (Show) Cycle Followed 
by External 1-Clock Write . . . . . . . . . . . . . . . . . . . . . . .519
20-1 Chip Select Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .523
20-2 Chip Select Control Register 0 (CSCR0) . . . . . . . . . . . . . .525
20-3 Chip Select Control Register 1 (CSCR1) . . . . . . . . . . . . . .526
20-4 Chip Select Control Register 2 (CSCR2) . . . . . . . . . . . . . .526
20-5 Chip Select Control Register 3 (CSCR3) . . . . . . . . . . . . . .527
21-1 Top-Level Tap Module and Low-Level (OnCE) 
TAP Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536
21-2 Top-Level TAP Controller State Machine. . . . . . . . . . . . . .540
21-3 IDCODE Register Bit Specification  . . . . . . . . . . . . . . . . . .545
21-4 OnCE Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .553
21-5 Low-Level (OnCE) Tap Module Data Registers (DRs). . . .554
21-6 OnCE Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
21-7 OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . .559
21-8 OnCE Command Register (OCMR). . . . . . . . . . . . . . . . . .562
21-9 OnCE Control Register (OCR) . . . . . . . . . . . . . . . . . . . . . .564
21-10 OnCE Status Register (OSR). . . . . . . . . . . . . . . . . . . . . . .568
21-11 OnCE Memory Breakpoint Logic . . . . . . . . . . . . . . . . . . . .570
21-12 OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . .573
21-13 CPU Scan Chain Register (CPUSCR). . . . . . . . . . . . . . . .576
    
  
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Technical Data MMC2107 –Rev. 2.0
36 List of Figures MOTOROLA
Li st of  Figu r e s
Figure Title Page
21-14 Control State Register (CTL) . . . . . . . . . . . . . . . . . . . . . . .578
21-15 OnC E PC FIFO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .580
21-16 Recommended Connector Interface 
to JTAG/OnCE Port. . . . . . . . . . . . . . . . . . . . . . . . . . . .583
22-1 VPP versus Programming Time . . . . . . . . . . . . . . . . . . . . .595
22-2 VPP versus Programming Pulses. . . . . . . . . . . . . . . . . . . .595
22-3 CLKOUT Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .597
22-4 Clock Read/Write Cycle Timing . . . . . . . . . . . . . . . . . . . . .598
22-5 Read/Write Cycle Timing with Wait States. . . . . . . . . . . . .599
22-6 Show Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600
22-7 RESET and Configuration Override Timing . . . . . . . . . . . .601
22-8 SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .603
22-9 Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .605
22-10 Boundary Scan (JTAG) Timing  . . . . . . . . . . . . . . . . . . . . .606
22-11 Test Access Port Timing  . . . . . . . . . . . . . . . . . . . . . . . . . .606
22-12 TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606
22-13 Debug Event Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .607
    
  
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MMC21 07 –Rev. 2.0  Technical Data
MOTO ROLA List of Tables  37
Technical Data — MMC2107
List of Tables
Table Title Page
2-1 Register Address Location Map . . . . . . . . . . . . . . . . . . . . . . .53
3-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
3-2 Write-Once Bits Read/Write Accessibility. . . . . . . . . . . . . . . .93
3-3 Chip C onfiguration Module Memory Map. . . . . . . . . . . . . . . .94
3-4 Chip Configuration Mode Selection . . . . . . . . . . . . . . . . . . . .95
3-5 Bus Monitor Timeout Values  . . . . . . . . . . . . . . . . . . . . . . . . .97
3-6 Reset Configuration Pin States During Reset  . . . . . . . . . . .101
3-7 Configuration During Reset . . . . . . . . . . . . . . . . . . . . . . . . .102
3-8 Chip Configuration Mode Selection . . . . . . . . . . . . . . . . . . .103
3-9 Chip Sele ct CS0 Configuration Encoding. . . . . . . . . . . . . . .104
3-10 Boot Device Selection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
3-11 Output Pad Driver Strength Selection  . . . . . . . . . . . . . . . . .105
3-12 Clock Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
3-13 Internal FLASH Configuration. . . . . . . . . . . . . . . . . . . . . . . .106
4-1 Package Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
4-2 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
5-1 Reset Controller Signal Properties. . . . . . . . . . . . . . . . . . . .131
5-2 Reset Controller Module Memory Map. . . . . . . . . . . . . . . . .132
5-3 Reset Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
6-1 M•CORE Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . .150
7-1 Interrupt Controller Module Memory Map. . . . . . . . . . . . . . .156
7-2 MASK Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
7-3 Priority Select Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
7-4 Fast Interrupt Vector Number. . . . . . . . . . . . . . . . . . . . . . . .170
    
  
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Technical Data MMC2107 –Rev. 2.0
38 List of Tables MOTOROLA
Li st of  Tab les
Table Title Page
7-5 Vector Table Mapping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
7-6 Interrupt Source Assignment . . . . . . . . . . . . . . . . . . . . . . . .172
9-1 Non-Volatile Memory FLASH Memory Map . . . . . . . . . . . . .187
9-2 Negative Voltage Modulation . . . . . . . . . . . . . . . . . . . . . . . .194
9-3 Drain Amplitude Modulation (GDB = 0) . . . . . . . . . . . . . . . .195
9-4 System Clock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
9-5 Clock Period Exponent and Pulse Width Range  . . . . . . . . .199
9-6 Determining SCLKR[2:0], CLKPE[1:0],
and CLKPM[6:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
9-7 Program Interlock State Descriptions. . . . . . . . . . . . . . . . . .210
9-8 Results of Programming Margin Read . . . . . . . . . . . . . . . . .212
9-9 Required Programming Algorithm . . . . . . . . . . . . . . . . . . . .213
9-10 Erase Interlock State Descriptions . . . . . . . . . . . . . . . . . . . .217
9-11 Required Erase Algorithm  . . . . . . . . . . . . . . . . . . . . . . . . . .219
10-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
10-2 Clock Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . .226
10-3 System Frequency Multiplier of the Reference 
Frequency in Normal PLL Mode . . . . . . . . . . . . . . . . . . .228
10-4 STPMD[1:0] Operation in Stop Mode. . . . . . . . . . . . . . . . . .230
10-5 System Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
10-6 Clock-Out and Clock-In Relationships . . . . . . . . . . . . . . . . .235
10-7 Loss of Clock Summ ary . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
10-8 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
10-9 Charge Pump Current and MFD
in Normal Mode Operation  . . . . . . . . . . . . . . . . . . . . . . .245
11-1 I/O Port Module Memory Map  . . . . . . . . . . . . . . . . . . . . . . .250
11-2 PEPAR Reset Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
11-3 Ports A–I Supported Pin Functions  . . . . . . . . . . . . . . . . . . .258
12-1 Edge P ort Module Memory Map. . . . . . . . . . . . . . . . . . . . . .263
12-2 EPPAx Fiel d Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
13-1 Watchdog Timer Module Memory Map  . . . . . . . . . . . . . . . .274
    
  
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List of Tables
MMC21 07 –Rev. 2.0 Technical Data 
MOTO ROLA List of Tables  39
Table Title Page
14-1 Programmable Interrupt Timer Modules Memory Map. . . . .284
14-2 Prescaler Select Encoding . . . . . . . . . . . . . . . . . . . . . . . . . .286
14-3 PIT Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
15-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298
15-2 Timer Modules Memory Map . . . . . . . . . . . . . . . . . . . . . . . .299
15-3 Output Compare Action Selection . . . . . . . . . . . . . . . . . . . .307
15-4 Input Capture Edge Selection. . . . . . . . . . . . . . . . . . . . . . . .308
15-5 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
15-6 Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
15-7 TIMPORT I/O Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
15-8 Timer Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . .326
16-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334
16-2 Seria l Commu nicati ons Inter face Module 
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
16-3 SCI Normal, Loop, and Single-Wire Mode 
Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
16-4 Example Baud Rates (System Clock = 33 MHz) . . . . . . . . .350
16-5 Example 10-Bit and 11-Bit Frames. . . . . . . . . . . . . . . . . . . .352
16-6 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
16-7 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
16-8 Stop B it Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359
16-9 SCI Port Control Summary. . . . . . . . . . . . . . . . . . . . . . . . . .368
16-10 SCI Interrupt Request Sources. . . . . . . . . . . . . . . . . . . . . . .369
17-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
17-2 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
17-3 SS P in I/O Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . .377
17-4 Bidirectional Pin Configurations . . . . . . . . . . . . . . . . . . . . . .378
17-5 SPI Baud Rate Selection (33-MHz Module Clock). . . . . . . .380
17-6 SPI Port Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384
17-7 Normal Mode and Bidirectional Mode  . . . . . . . . . . . . . . . . .394
17-8 SPI Interrupt Request Sources. . . . . . . . . . . . . . . . . . . . . . .397
    
  
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Technical Data MMC2107 –Rev. 2.0
40 List of Tables MOTOROLA
Li st of  Tab les
Table Title Page
18-1 Multiplexed Analog Input Channels . . . . . . . . . . . . . . . . . . .409
18-2 QADC Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
18-3 Prescaler Clock High Times. . . . . . . . . . . . . . . . . . . . . . . . .417
18-4 Prescaler Clock Low Times . . . . . . . . . . . . . . . . . . . . . . . . .418
18-5 Queue 1 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . .420
18-6 Queue 2 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . .423
18-7 Pause Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
18-8 Queue Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433
18-9 Input Sample Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .439
18-10 Non-Multiplexed Channel Assignments
and Pin Designations. . . . . . . . . . . . . . . . . . . . . . . . . . . .440
18-11 M ul tiplexed C hanne l Assignment s
and Pin Designations. . . . . . . . . . . . . . . . . . . . . . . . . . . .440
18-12 Analog Input Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . .444
18-13 Trigger Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454
18-14 Status Bits  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454
18-15 QADC Clock Programmability . . . . . . . . . . . . . . . . . . . . . . .479
18-16 External Circuit Settling Time to 1/2 LSB
(10-Bit Conversions) . . . . . . . . . . . . . . . . . . . . . . . . . . . .499
18-17 Error Resulting From Input Leakage (IOff) . . . . . . . . . . . . . .500
18-18 QADC Status Flags and Interrupt Sources. . . . . . . . . . . . . .500
19-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .505
19-2 Data Transfer Cases  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .509
19-3 EB[3:0] Assertion Encoding . . . . . . . . . . . . . . . . . . . . . . . . .510
19-4 Emulation Mode Chip-Select Summary . . . . . . . . . . . . . . . .517
20-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524
20-2 Chip Select Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . .524
20-3 Chip Select Wait States Encoding . . . . . . . . . . . . . . . . . . . .529
20-4 Chip Select Address Range Encoding . . . . . . . . . . . . . . . . .531
21-1 JTAG Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542
21-2 List of Pins Not Scanned in JTAG Mode . . . . . . . . . . . . . . .548
21-3 Boundary-Scan Register Definition  . . . . . . . . . . . . . . . . . . .549
21-4 OnCE Register Addressing  . . . . . . . . . . . . . . . . . . . . . . . . .563
    
  
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List of Tables
MMC21 07 –Rev. 2.0 Technical Data 
MOTO ROLA List of Tables  41
Table Title Page
21-5 Sequential Control Field Settings. . . . . . . . . . . . . . . . . . . . .565
21-6 Memory Breakpoint Control Field Settings. . . . . . . . . . . . . .567
21-7 Processor Mode Field Settings. . . . . . . . . . . . . . . . . . . . . . .569
22-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .586
22-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .587
22-3 ESD Protection Characteristics . . . . . . . . . . . . . . . . . . . . . .587
22-4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . .588
22-5 PLL Electrical Specifications  . . . . . . . . . . . . . . . . . . . . . . . .590
22-6 QADC Absolute Maximum Ratings  . . . . . . . . . . . . . . . . . . .591
22-7 QADC Electrical Specifications  . . . . . . . . . . . . . . . . . . . . . .592
22-8 QADC Conversion Specifications. . . . . . . . . . . . . . . . . . . . .593
22-9 FLASH Program and Erase Characteristics. . . . . . . . . . . . .594
22-10 FLASH EEPROM Module Life Characteristics. . . . . . . . . . .594
22-11 External Interface Timing Characteristics. . . . . . . . . . . . . . .596
22-12 Reset and Configuration Override Timing . . . . . . . . . . . . . .601
22-13 SPI Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .602
22-14 OnCE, JTA G, and Boundary Scan Timing. . . . . . . . . . . . . .605
24-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .615
    
  
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Technical Data MMC2107 –Rev. 2.0

42 List of Tables MOTOROLA

Li st of Tab les

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MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA General Description 43

Technical Data — MMC2107

Section 1. General Descrip tion

1.1 Contents

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

1.2 Introduction

The MMC2107 is the first member of a family of general-purpose

microcontrollers (MCU) based on the M •CORE™ M210 central

processor unit (CPU).

As a low-voltage part, the MMC2107 operates at voltages between

2. 7 volts and 3.6 volts. It is particul arly suited fo r use in bat tery-pow ered

applications. The operating frequency is up to a maximum of 33 MHz

over a temperature range of –40°C to 85°C.

Available packages are 100-pin low-profile quad flat pack (LQFP)

or a 144-pin LQFP for applications requiring the full external memory

interface support or a large number of general-purpose inputs/outputs

(GPIO).

™M•CORE is a trademark of Mot orola, Inc.

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Technical Data MMC2107 –Rev. 2.0

44 Gen eral D es cri ptio n MOTOR OLA

General Description

1.3 Featur es

Features of the MMC2107 include:

• M•CORE M210 integer processor:

–32-bit reduced instruction set computer (RISC) architecture

–Low power and high performance

•OnCE™ debug support

•On-chip 128-Kbyte FLASH:

–Motorola’s one transistor, CDR MoneT(1) FLASH bit cell

–Page mode (2111) read access

–External VPP required for programming

–16-K block size

•On-chip, 8-Kbyte static random-access memory (SRAM):

–One cl ock per access (i n cluding bytes, half- words, a nd wor ds)

–Byte, half-word (16 bits), and word (32 bits) read/write

accesses

–Standby power supply support

•Serial peripheral interface (SPI):

–Master mode and slave mode

–Wired-OR mode

–Slave sel ect output

–Mode fault error flag with CPU interrupt capability

–Double-buffered operation

–Serial clock with programmable polarity and phase

–Control of SPI operation during wait mode

–Reduc ed dri ve control

™OnCE is a trademar k of Motorola, Inc.

1. CDR MoneT desig nates the Motorola one-transi stor bitcell.

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General Description

Features

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA General Description 45

•Two serial communications interfaces (SCI):

–Full-duplex operation

–Standard mark/space non-return-to- zero (NRZ) format

–13-bit baud rate selection

–Programmable 8-bit or 9-bit data format

–Separately enabled transmitter and receiver

–Separate receiver and transmitter CPU interrupt requests

–Programmable transmitter output polarity

–Two receiver wakeup methods (idle line and address mark)

–Interrupt-driven operation with eight flags

–Receiver framing error detection

–Hardware parity checking

–1/16 bit-time noise detection

–General-purpose input/output port

•Two timers:

–Four 16-bit input capture/output compare channels

–16-bit architecture

–16-bit pulse accumulator

–Pulse widths variable from microseconds to seconds

–Prescaler

–Toggle-on-overflow feature for pulse-width modulator (PWM)

generation

–Timer port pullups enabled on reset

•Queued analog-to-digital converter (QADC):

–Eight analog input channels

–10-bit resolution ±2 counts accuracy

–Minimum 7 µs conversion time

–Internal sample and hold

–Programmable input sample time for various source

impedances

–Two conversion command queues with a total of 64 entries

–Subqueues possible using pause mechanism

–Queue complete and pause software interrupts available on

both queues

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Technical Data MMC2107 –Rev. 2.0

46 Gen eral D es cri ptio n MOTOR OLA

General Description

–Queue po inters indicate current location for each queue

–Automated queue modes initiated by:

External edge trigger and gated trigger

Periodic/interval timer, within queued analog-to-digital

converter (QADC) module {queue1 and queue2}

Software command

–Single-scan or continuous-scan of queues

–Output da ta readable in three formats:

Right-justified unsigned

Left-justified signed

Left-justified unsigned

–Unused analog channels can be used as digital input/output

(I/O)

–Minimum pin set configuration implemented

•Interrupt controller:

–Up to 40 interrupt sources

–32 unique programmable priority levels for each interrupt

source

–Independent enable/disable of pending interrupts based on

priority level

–Select normal or fast interrupt request for each priority level

–Fast interrupt requests always have priority over normal

interrupts.

–Ability to mask interrupts at and below a defined priority level

–Ability to select between autovectored or vectored interrupt

requests

–Vectored interrupts generated based on priority level

–Ability to generate a separate vector number for normal and

fast interrupts

–Ability for software to self-schedule interrupts

–Softwar e visibility of pending inte rrupts an d interr upt signals t o

core

–Asynchronous operation to support wakeup from low-power

modes

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General Description

Features

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA General Description 47

•External interrupts supported:

–Rising/falling edge select

–Low-level sensitive

–Ability for software generation of external interrupt event

–General-purpose input/output support

•Periodic interval timer:

–16-bit counter

–Selectable as free running or count down

•Watchdog timer:

–16-bit counter

–Low-power mode support

•Phase-lock loop (PLL):

–Reference crystal from 2 to 10 MHz

–Low-power modes supported

–Separate clock-out signal

• Reset:

–Sepa rate reset in and reset out sign als

–Six sources of reset:

Power- on re set (P OR )

External

Software

Watchdog

Loss of clock

Loss of lock

–Status flag indication of source of last reset

•Chip configur ations:

–Support for single-chip, master, emulation, and test modes

–System configuration during reset

–Bus monitor

–Configurable output pad drive strength control

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Technical Data MMC2107 –Rev. 2.0

48 Gen eral D es cri ptio n MOTOR OLA

General Description

•General-purpose input/output (GPIO):

–Up to 72 bits of GPIO

–Coherent 32-bit control

–Bit manipulation supported via set/clear functions

–Unused peripheral pins may be used as extra GPIO.

–Reduc ed dri ve control

• M•CORE to IPbus interface:

–Complete interfacing between the M•CORE bus and the IPbus

peripheral bus

–Mi nimum of three clocks for peripheral bus access

–Data alignment and data width conversion between the

M•CORE 32-bit data bus and the IPbus peripheral data buses

•External interface:

–Provides for direct support of asynchronous random-access

memory (RAM), read-only memory (ROM), and FLAS H

–Support interfacing to 16-bit and 32-bit data buses

–32-bit external bidirectional data bus

–23-bit address bus

–Four chip selects

–Byte/write enables

–Ability to boot from internal or external memories

–Internal bus activity is visible via show-cycle mode

–Special chip selects support replacement of GPIO with

external logic (port replacement logic)

–Emulation of internal page mode FLASH support

•Joint Test Action Gr oup (JTAG) support for system -l evel board

testing

1.4 Block Diagram

The basic structure of the MMC2107 is shown in Figure 1-1.

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General Description

Block Diagram

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA General Description 49

Figure 1-1. Block Diagram

FLASH

CONTR OLL E R OSC/PLL

RESET

SPI

SRAM

SCI1 SCI2

INTERRUPT

IPBUS

INTERFACE

TMS

TDI

TDO

TCLK

TRST

INT[7:0]

MISO

TXD2

RXD2

TIM1 TIM2

ICOC1[3:0]

PQB[3:0]

VRL, VRH

VDDA, VSSA

EXTAL

XTAL

VDDSYN

VSSSYN

CLKOUT

RESET

RSTOUT

D[31:0]

VPP

VDDF, VSSF

VSS x 8

VDD x 8

PORTS

128-KBYTE

8-KBYTE

VSTBY

ICOC2[3:0]

TXD1

RXD1

POR

PROGRAMMABLE

INTERVAL

TIMER 2

WATCHDOG

TIMER

ADC

MOSI

SCK

TEST

PROGRAMMABLE

INTERVAL

TIMER 1

EDGE

PORT

PSTAT[3:0]

M•CORE

(M210)

A[22:0]

R/W

EB[3:0]

CS[3:0]

TC[2:0]

SHS

CSE[1:0]

TEA

TEST

PQA[4:3]

PQA[1:0]

VDDH

M•CORE BUS

EXTERNAL MEMORY INTERFACE

IPBUS

OnCE

JTAG

TAP

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Technical Data MMC2107 –Rev. 2.0

50 Gen eral D es cri ptio n MOTOR OLA

General Description

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MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 51

Technical Data — MMC2107

Section 2. System Memory Map

2.1 Contents

2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

2.3 Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

2.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.2 Introduction

The address map, shown in Figure 2- 1, includes:

•128 Kbytes of internal FLASH

•8 Kbytes of internal static random-access memory (SRAM)

•Internal memory mapped registers

•External address space

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Technical Data MMC2107 –Rev. 2.0

52 System Memory Map MOTOR OLA

System Memory Map

2.3 Address Map

Figure 2-1. Address Map

INTERNAL FLASH

INTERNAL SRAM

EXTERNAL MEMORY

0x00c0_0000

8 KBYTES

128

BYTES

0x0080_0000

REGISTERS

SEE 2.4 Register Map

0x8000_0000

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System Memory Map

Address Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 53

Table 2-1. Register Address Location Map(1)

1. See modul e se ction s for d etail s of h ow much of each blo ck is being dec oded. Access es t o

addresses outsi de the mod ule memory maps (and also the reserved are a

0x00d1_0000–0x7fff_ffff) wi ll not be responded to and will result in a bus moni tor transfer

error exception.

Base Address (Hex) Usage

0x00c0_0000 Ports(2) (PORTS)

2. The port register space is mir rored/re peated in the 64-Kbyte block. This all ows the f ull

64-Kbyte block to be decoded and used to execute an external access to a port

replacement uni t i n emu lat ion mode.

0x00c1_0000 Chip configuration (CCM)

0x00c2_0000 Chip selects (CS)

0x00c3_0000 Clocks (CLOCK)

0x00c4_0000 Reset (RESET )

0x00c5_0000 Interrupt controller (INTC)

0x00c6_0000 Edge port (EPORT)

0x00c7_0000 Watchdog timer (WDT)

0x00c8_0000 Programmable interrupt timer 1 (PIT1)

0x00c9_0000 Programmable interrupt timer 2 (PIT2)

0x00ca_0000 Queued analog-to-digital converter (QADC)

0x00cb_0000 Serial peripheral interface (SPI)

0x00cc_0000 Serial communications interface 1 (SCI1)

0x00cd_0000 Serial communications interface 2 (SCI2)

0x00ce_0000 Timer 1 (TIM1)

0x00cf_0000 Timer 2 (TIM2)

0x00 d0_000 0 FLASH reg isters (C MF R)

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Technical Data MMC2107 –Rev. 2.0

54 System Memory Map MOTOR OLA

System Memory Map

2.4 Register Map

Address Register Name Bit Number

Po r ts (PORTS)

Bit 7654321Bit 0

0x00c0_0000 Port A Output Data

See page 251.

Read: PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0_0001 Port B Output Data

See page 251.

Read: PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0_0002 Port C Output Data

See page 251.

Read: PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0_0003 Port D Output Data

See page 251.

Read: PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0_0004 Port E Output Data

See page 251.

Read: PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0_0005 Port F Output Data

See page 251.

Read: PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0_0006 Port G Outp u t Da ta

See page 251.

Read: PORTG7 PORTG6 PORTG5 PORTG4 PORTG3 PORTG2 PORTG1 PORTG0

Write:

Reset:11111111

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 1 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 55

Bit 7654321Bit 0

0x00c0_0007 Port H Output Data

See page 251.

Read: PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0_0008 Po r t I Ou tp u t D a ta

See page 251.

Read: PORTI7 PORTI6 PORTI5 PORTI4 PORTI3 PORTI2 PORTI1 PORTI0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c0_0009

↓

0x00c0_000b Reserved Writes have no effect, reads ret urn 0s, and the ac cess terminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00c0_000c Port A Data Direc tion

See page 252.

Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0_000d Port B Data Direction

See page 252.

Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0_000e Port C Data Direc tion

See page 252.

Read: DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0_000f Port D Data Direction

See page 252.

Read: DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0_0010 Port E Data Direction

See page 252.

Read: DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 2 of 34)

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Technical Data MMC2107 –Rev. 2.0

56 System Memory Map MOTOR OLA

System Memory Map

Bit 7654321Bit 0

0x00c0_0011 Port F Data Direction

See page 252.

Read: DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0_0012 Port G Data Direction

See page 252.

Read: DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0_0013 Port H Data Direc tion

See page 252.

Read: DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0_0014 Port I Data Direction

See page 252.

Read: DDRI7 DDRI6 DDRI5 DDRI4 DDRI3 DDRI2 DDRI1 DDRI0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c0_0015

↓

0x00c0_0017 Reserved Writes have no effect, reads ret urn 0s, and the ac cess terminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00c0_0018

Por t A Pi n D a ta/ Set

Data Register

(PORTAP/SETA)

See page 253.

Read: PORTAP7 PORTAP6 PORTAP5 PORTAP4 PORTAP3 PORTAP2 PORTAP1 PORTAP0

Write: SETA7 SETA6 SETA5 SETA4 SETA3 SETA2 SETA1 SETA0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0_0019

Por t B Pi n D a ta/ Set

Data Register

(PORTBP/SETB)

See page 253.

Read: PORTBP7 PORTBP6 PORTBP5 PORTBP4 PORTBP3 PORTBP2 PORTBP1 PORTBP0

Write: SETB7 SETB6 SETB5 SETB4 SETB3 SETB2 SETB1 SETB0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0_001a

Port C Pin Data/Set

Data Register

(PORTCP/SETC)

See page 253.

Read: PORTCP7 PORTCP6 PORTCP5 PORTCP4 PORTCP3 PORTCP2 PORTCP1 PORTCP0

Write: SETC7 SETC6 SETC5 SETC4 SETC3 SETC2 SETC1 SETC0

Reset:PPPPPPPP

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 3 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 57

Bit 7654321Bit 0

0x00c0_001b

Port D Pin Data/Set

Data Register

(PORTDP/SETD)

See page 253.

Read: PORTDP7 PORTDP6 PORTDP5 PORTDP4 PORTDP3 PORTDP2 PORTDP1 PORTDP0

Write: SETD7 SETD6 SETD5 SETD4 SETD3 SETD2 SETD1 SETD0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0_001c

Por t E Pi n D a ta/ Set

Data Register

(PORTEP/SETE)

See page 253.

Read: PORTEP7 PORTEP6 PORTEP5 PORTEP4 PORTEP3 PORTEP2 PORTEP1 PORTEP0

Write: SETE7 SETE6 SETE5 SETE4 SETE3 SETE2 SETE1 SETE0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0_001d

Port F Pin Data/Set

Data Register

(PORTFP/SETF)

See page 253.

Read: PORTFP7 PORTFP6 PORTFP5 PORTFP4 PORTFP3 PORTFP2 PORTFP1 PORTFP0

Write: SETF7 SETF6 SETF5 SETF4 SETF3 SETF2 SETF1 SETF0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0_001e

Port G Pin Data/Set

Data Register

(PORTGP/SETG)

See page 253.

Read: PORTGP7 PORTGP6 PORTGP5 PORTGP4 PORTGP3 PORTGP2 PORTGP1 PORTGP0

Write: SETG7 SETG6 SETG5 SETG4 SETG3 SETG2 SETG1 SETG0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0_001f

Port H Pin Data/Set

Data Register

(PORTHP/SETH)

See page 253.

Read: PORTHP7 PORTHP6 PORTHP5 PORTHP4 PORTHP3 PORTHP2 PORTHP1 PORTHP0

Write: SETH7 SETH6 SETH5 SETH4 SETH3 SETH2 SETH1 SETH0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0_0020

Por t I Pi n D ata / Set

Data Register

(PORTIP/SETI)

See page 253.

Read: PORTIP7 PORTIP6 PORTIP5 PORTIP4 PORTIP3 PORTIP2 PORTIP1 PORTIP0

Write: SETI7 SETI6 SETI5 SETI4 SETI3 SETI2 SETI1 SETI0

Reset:PPPPPPPP

Bit 7654321Bit 0

0x00c0_0021

↓

0x00c0_0023 Reserved Writes have no effect, reads ret urn 0s, and the ac cess terminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00c0_0024 Port A Clear Outpu t

Data Register (CLRA)

See page 254.

Write: CLRA7 CLRA6 CLRA5 CLRA4 CLRA3 CLRA2 CLRA1 CLRA0

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 4 of 34)

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Technical Data MMC2107 –Rev. 2.0

58 System Memory Map MOTOR OLA

System Memory Map

Bit 7654321Bit 0

0x00c0_0025 Port B Clear Outpu t

Data Register (CLRB)

See page 254.

Write: CLRB7 CLRB6 CLRB5 CLRB4 CLRB3 CLRB2 CLRB1 CLRB0

Reset:00000000

Bit 7654321Bit 0

0x00c0_0026 Port C Clear Output

Data Register (CLRC)

See page 254.

Write: CLRC7 CLRC6 CLRC5 CLRC4 CLRC3 CLRC2 CLRC1 CLRC0

Reset:00000000

Bit 7654321Bit 0

0x00c0_0027 Port D Clear Output

Data Register (CLRD)

See page 254.

Write: CLRD7 CLRD6 CLRD5 CLRD4 CLRD3 CLRD2 CLRD1 CLRD0

Reset:00000000

Bit 7654321Bit 0

0x00c0_0028 Port E Clear Outpu t

Data Register (CLRE)

See page 254.

Write: CLRE7 CLRE6 CLRE5 CLRE4 CLRE3 CLRE2 CLRE1 CLRE0

Reset:00000000

Bit 7654321Bit 0

0x00c0_0029 Port F Clear Outpu t

Dat a Register (CLRF)

See page 254.

Write: CLRF7 CLRF6 CLRF5 CLRF4 CLRF3 CLRF2 CLRF1 CLRF0

Reset:00000000

Bit 7654321Bit 0

0x00c0_002a Port G Clear Outpu t

Data Register (CLRG)

See page 254.

Write: CLRG7 CLRG6 CLRG5 CLRG4 CLRG3 CLRG2 CLRG1 CLRG0

Reset:00000000

Bit 7654321Bit 0

0x00c0_002b Port H Clear Output

Data Register (CLRH)

See page 254.

Write: CLRH7 CLRH6 CLRH5 CLRH4 CLRH3 CLRH2 CLRH1 CLRH0

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 5 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 59

Bit 7654321Bit 0

0x00c0_002c P o r t I C l e a r O u tp ut

Data Register (CLRI)

See page 254.

Write: CLRI7 CLRI6 CLRI5 CLRI4 CLRI3 CLRI2 CLRI1 CLRI0

Reset:00000000

Bit 7654321Bit 0

0x00c0_002d

↓

0x00c0_002f Reserved Writes have no effect, reads ret urn 0s, and the access t erminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00c0_0030

Port C/D Pin

Assignment Register

(PCDPAR)

See page 255.

Read: PCDPA 0000000

Write:

Reset: See note 0 0 0 0 0 0 0

Note: Reset state determined during reset configuration. PCDPA = 1 except in single-chip

mode or when an external boot device is selected with a 16-bit port size in master mode.

Bit 7654321Bit 0

0x00c0_0031

Por t E Pi n

Assignment Register

(PEPAR)

See page 256.

Read: PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0

Write:

Reset: Reset state determined during reset configuration as shown in Table 11-2. PEPAR Reset Valu es.

Bit 7654321Bit 0

0x00c0_0032

↓

0x00c0_003f Reserved Writes have no effect, reads ret urn 0s, and the access t erminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00c0_0040

↓

0x00c0_ffff Reserved Ports register space (block of 0x00c0_0000 through 0x00c0_oo3f) is mirrored/repeated.

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 6 of 34)

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Technical Data MMC2107 –Rev. 2.0

60 System Memory Map MOTOR OLA

System Memory Map

Chip Configuration Module (CCM)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c1_0000

0x00c1_0001 Chip Configuration

(CCR)

See page 94.

Read: LOAD 0SHEN EMINT 0 MODE2 MODE1 MODE0

Write:

Reset: Note 1 0 Note 2 Note 2 0 Note 1 Note 1 Note 1

Bit 7654321Bit 0

Read: 0 SZEN PSTEN SHINT BME BMD BMT1 BMT0

Write:

Reset: 0 Note 3 Note 2 0 1 0 0 0

Notes:

1. Determined during reset configuration

2. 0 for all configurations except emulation mode, 1 for emulation mode

3. 0 for all configurations except emulation and master modes, 1 for emulation and master modes

Bit 7654321Bit 0

0x00c1_0002 Reserved Writes have no effect, reads return 0s, and the access t erminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00c1_0003 Reserved Writes have no effect, reads ret urn 0s, and the ac cess terminates

without a transfer er ror exception.

Bit 15 14 13 12 11 10 9 Bit 8

0x00c1_0004

0x00c1_0005 Reset Configuration

See page 97.

Write:

Reset:00000000

Bit 7654321Bit 0

RPLLSEL 1

RPLLREF 0

RLOAD 01

BOOTPS 0

BOOTSEL 00

MODE

Write:

Reset:11001000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 7 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 61

Bit 15 14 13 12 11 10 9 Bit 8

0x00c1_0006

0x00c1_0007 Chip Identifica tion

See page 99.

PIN7 0

PIN6 0

PIN5 1

PIN4 0

PIN3 1

PIN2 1

PIN1 1

PIN0

Write:

Reset:00010111

Bit 7654321Bit 0

PRN7 0

PRN6 0

PRN5 0

PRN4 0

PRN3 0

PRN2 0

PRN1 0

PRN0

Write:

Reset: 00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00c1_0008

0x00c1_0009 Chip T es t Register

(CTR)

See page 100.

Write:

Reset:00000000

Bit 7654321Bit 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c1_000a

0x00c1_000b Reserved Writes have no effect, reads ret urn 0s, and the ac cess terminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00c1_000c

↓

0x00c1_000f Unimplemented Access results in the module generating an access termination transfer error .

Bit 7654321Bit 0

0x00c1_0010

↓

0x00c1_ffff Unimplemented Access results in a bus monitor timeout generating an access t ermination transfer error.

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 8 of 34)

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Technical Data MMC2107 –Rev. 2.0

62 System Memory Map MOTOR OLA

System Memory Map

Chip Selects (CS)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c2_0000

0x00c2_0001 Chip Select Control

See page 525.

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset: 0 0 See note 1 1 1 1 1

Bit 7654321Bit 0

Read: 0 0 0 0 0 0 TAEN CSEN

Write:

Reset:0000001See note

Note: Reset state determined during reset configuration.

Bit 15 14 13 12 11 10 9 Bit 8

0x00c2_0002

0x00c2_0003 Chip Select Control

See page 526.

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset:00111111

Bit 7654321Bit 0

TAEN CSEN

Write:

Reset:0000001See note

Note: Reset state determined during reset configuration

Bit 15 14 13 12 11 10 9 Bit 8

0x00c2_0004

0x00c2_0005 Chip Select Control

See page 526.

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset:00111111

Bit 7654321Bit 0

Read: 0 0 0 0 0 0 TAEN CSEN

Write:

Reset:00000010

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 9 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 63

Bit 15 14 13 12 11 10 9 Bit 8

0x00c2_0006

0x00c2_0007 Chip Select Control

See page 527.

Read: SO RO PS WWS WE WS2 WS1 WS0

Write:

Reset:00111111

Bit 7654321Bit 0

Read: 0 0 0 0 0 0 TAEN CSEN

Write:

Reset:00000010

Bit 7654321Bit 0

0x00c2_0008

↓

0x00c2_ffff Unimplemented Access results in a bus monitor timeout generating an access t ermination transfer error.

Clocks (CLOCK)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c3_0000

0x00c3_0001 Synthesizer Control

See page 227.

Read: LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0

Write:

Reset:00100001

Bit 76 54 321Bit 0

Read: LOCEN DISCLK FWKUP RSVD4 STMPD1 STMPD0 RSVD1 RSVD0

Write:

Reset:00000000

Bit 76 54 321Bit 0

0x00c3_00 02 S ynthesizer Status

See page 230.

Read: PLLMODE PLLSEL PLLREF LOCKS LOCK LOCS 0 0

Write:

Reset: Note 1 Note 1 Note 1 Note 2 Note 2 0 0 0

Notes:

1. Reset state determined during reset configuration

2. See the LOCKS and LOCK bit descriptions.

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 10 of 34)

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Technical Data MMC2107 –Rev. 2.0

64 System Memory Map MOTOR OLA

System Memory Map

Bit 7654321Bit 0

0x00c3_0003 Synthesizer Test Register

(SYNTR)

See page 233.

Write:

Reset:00000000

Bit 31 30 29 28 27 26 25 B it 24

0x00c3_0004

0x00c3_0005

0x00c3_0006

0x00c3_0007

Synthesizer Test

See page 234.

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 B it 16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: 0 0 0 0 0 0 RSVD9 RSVD8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD2 RSVD0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c3_0008

↓

0x00c3_ffff Unimplemented Access results in a bus monitor timeout generating an access t ermination transfer error.

Reset (RESET)

Bit 7654321Bit 0

0x00c4_0000 Reset Control Register

(RCR)

See page 133.

Read: SOFTRST FRC-

RSTOUT 000000

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 11 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 65

Bit 7654321Bit 0

0x00c4_0001 Reset Status Register

(RSR)

See page 134.

Read: 0 0 SOFT WDR POR EXT LOC LOL

Write:

Reset: 0 0 Reset dependent

Bit 7654321Bit 0

0x00c4_0002 Reset Test Register

(RTR)

See page 135.

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c4_0003 Reserved Writes have no effect, reads ret urn 0s, and the ac cess terminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00c4_0004

↓

0x00c4_ffff Unimplemented Access results in a bus monitor timeout generating an access t ermination transfer error.

Interrupt Controller (INTC)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c5_0000

0x00c5_0001 Interrupt Control Register

(ICR)

See page 157.

Read: AE FVE ME MFI 0000

Write:

Reset:10000000

Bit 7654321Bit 0

Read: 0 0 0 MASK4 MASK3 MASK2 MASK1 MASK0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00c5_0002

0x00c5_0003 Interrupt Status Register

(ISR)

See page 159.

Read: 0 0 0 0 0 0 INT FINT

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 VEC6 VEC5 VEC4 VEC3 VEC2 VEC1 VEC0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 12 of 34)

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Technical Data MMC2107 –Rev. 2.0

66 System Memory Map MOTOR OLA

System Memory Map

Bit 31 30 29 28 27 26 25 Bit 24

0x00c5_0004

0x00c5_0005

0x00c5_0006

0x00c5_0007

Interrupt Force Register

High (IFRH)

See page 160.

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: IF39 IF38 IF37 IF36 IF35 IF34 IF33 IF32

Write:

Reset:00000000

Bit 31 30 29 28 27 26 25 Bit 24

0x00c5_0008

0x00c5_0009

0x00c5_000a

0x00c5_000b

Interrupt Force Register

Low (IFRL)

See page 161.

Read: IF31 IF30 IF29 IF28 IF27 IF26 IF25 IF24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: IF7IF6IF5IF4IF3IF2IF1IF0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 13 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 67

Bit 31 30 29 28 27 26 25 Bit 24

0x00c5_000c

0x00c5_000d

0x00c5_000e

0x00c5_000f

Interrupt Pending

See page 162.

Read: IP31 IP30 IP29 IP28 IP27 IP26 IP25 IP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: IP23 IP22 IP21 IP20 IP19 IP18 IP17 IP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: IP15 IP14 IP13 IP12 IP11 IP10 IP9 IP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0

Write:

Reset:00000000

Bit 31 30 29 28 27 26 25 Bit 24

0x00c5_0010

0x00c5_0011

0x00c5_0012

0x00c5_0013

Normal Interrupt Enable

See page 163.

Read: NIE31 NIE30 NIE29 NIE28 NIE27 NIE26 NIE25 NIE24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: NIE23 NIE22 NIE21 NIE20 NIE19 NIE18 NIE17 NIE16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: NIE15 NIE14 NIE13 NIE12 NIE11 NIE10 NIE9 NIE8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: NIE7 NIE6 NIE5 NIE4 NIE3 NIE2 NIE1 NIE0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 14 of 34)

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Technical Data MMC2107 –Rev. 2.0

68 System Memory Map MOTOR OLA

System Memory Map

Bit 31 30 29 28 27 26 25 Bit 24

0x00c5_0014

0x00c5_0015

0x00c5_0016

0x00c5_0017

Normal Interrupt Pending

See page 164.

Read: NIP31 NIP30 NIP29 NIP28 NIP27 NIP26 NIP25 NIP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: NIP23 NIP22 NIP21 NIP20 NIP19 NIP18 NIP17 NIP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: NIP15 NIP14 NIP13 NIP12 NIP11 NIP10 NIP9 NIP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: NIP7 NIP6 NIP5 NIP4 NIP3 NIP2 NIP1 NIP0

Write:

Reset:00000000

Bit 31 30 29 28 27 26 25 Bit 24

0x00c5_0018

0x00c5_0019

0x00c5_001a

0x00c5_001b

Fast Interrupt Enable

See page 165.

Read: FIE31 FIE30 FIE29 FIE28 FIE27 FIE26 FIE25 FIE24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: FIE23 FIE22 FIE21 FIE20 FIE19 FIE18 FIE17 FIE16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: FIE15 FIE14 FIE13 FIE12 FIE11 FIE10 FIE9 FIE8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: FIE7 FIE6 FIE5 FIE4 FIE3 FIE2 FIE1 FIE0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 15 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 69

Bit 31 30 29 28 27 26 25 Bit 24

0x00c5_001c

0x00c5_001d

0x00c5_001e

0x00c5_001f

Fast Interrupt Pending

See page 166.

Read: FIP31 FIP30 FIP29 FIP28 FIP27 FIP26 FIP25 FIP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: FIP23 FIP22 FIP21 FIP20 FIP19 FIP18 FIP17 FIP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: FIP15 FIP14 FIP13 FIP12 FIP11 FIP10 FIP9 FIP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: FIP7 FIP6 FIP5 FIP4 FIP3 FIP2 FIP1 FIP0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c5_0040

through

0x00c5_0067

Priority Level Select

Registers

(PLSR39—PLSR0)

See page 167.

Read: 0 0 0 PLS4 PLS3 PLS2 PLS1 PLS0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c5_0068

↓

0x00c5_007f Unimplemented Access results in the module generating an access termination transfer error .

Bit 7654321Bit 0

0x00c5_0080

↓

0x00c5_ffff Unimplemented Access results in a bus monitor timeout generating an access t ermination transfer error.

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 16 of 34)

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Technical Data MMC2107 –Rev. 2.0

70 System Memory Map MOTOR OLA

System Memory Map

Edge Port (EPORT)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c6_0000

0x00c6_0001 EPORT Pin Assignmen t

See page 264.

Read: EPPA7 EPPA6 EPPA5 EPPA4

Write:

Reset:00000000

Bit 7654321Bit 0

Read: EPPA3 EPPA2 EPPA1 EPPA0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c6_0002 EPORT Data Direction

See page 266.

Read: EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 EPDD0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c6_0003 EPORT Port Inte rru pt

Enable Register (EPIER)

See page 267.

Read: EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 EPIE0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c6_0004 EPORT Port Data

See page 268.

Read: EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 EPD0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c6_0005 EP ORT Port Pin Data

See page 268.

Read: EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1 EPPD0

Write:

Reset: P PPPPPPP

Bit 7654321Bit 0

0x00c6_0006 EPORT Port Flag Regiser

(EPFR)

See page 269.

Read: EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 EPF0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c6_0007 Reserved Writes have no effect, reads ret urn 0s, and the ac cess terminates

without a transfer er ror exception.

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 17 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 71

Bit 7654321Bit 0

0x00c6_0008

↓

0x00c6_ffff Unimplemented Access results in a bus monitor timeout generating an access t ermination transfer error.

Watc hdog Timer (WDT)

Bit 15 14 13 12 11 10 9 Bit 8

0x00c7_0000

0x00c7_0001 Watchdog Control

See page 275.

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 0 0 0 WAIT DOZE DBG EN

Write:

Reset:00001111

Bit 15 14 13 12 11 10 9 Bit 8

0x00c7_0002

0x00c7_0003 Watchdog Modulus

See page 277.

Read: WM15 WM14 WM13 WM12 WM11 WM10 WM9 WM8

Write:

Reset:11111111

Bit 7654321Bit 0

Read: WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0

Write:

Reset:11111111

Bit 15 14 13 12 11 10 9 Bit 8

0x00c7_0004

0x00c7_0005 Watchdog Count Register

(WCNTR)

See page 278.

Read: WC15 WC14 WC13 WC12 WC11 WC10 WC9 WC8

Write:

Reset:11111111

Bit 7654321Bit 0

Read: WC7 WC6 WC5 WC4 WC3 WC2 WC1 WC0

Write:

Reset:11111111

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 18 of 34)

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Technical Data MMC2107 –Rev. 2.0

72 System Memory Map MOTOR OLA

System Memory Map

Bit 15 14 13 12 11 10 9 Bit 8

0x00c7_0006

0x00c7_0007 Watchdog Service

See page 279.

Read: WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00c7_0008

↓

0x00c7_ffff Unimplemented Access results in a bus monitor timeout generating an access t ermination transfer error.

Progr a m mable Inter rupt Timer 1 (PI T1 ) and Programmi ng Interrupt Timer 2 (PIT2 )

Note: Addresses for PIT1 are at 0x00c8_#### and addresses for PIT2 are at 0x00c9_####.

Bit 15 14 13 12 11 10 9 Bit 8

0x00c8_0000

0x00c8_0001

0x00c9_0000

0x00c9_0001

PIT Control and Status

See page 285.

Read: 0 0 0 0 PRE3 PRE2 PRE1 PRE0

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 PDOZE PDBG OVW PIE PIF RLD EN

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00c8_0002

0x00c8_0003

0x00c9_0002

0x00c9_0003

PIT Modulus Register

(PMR)

See page 288.

Read: PM15 PM14 PM13 PM12 PM11 PM10 PM9 PM8

Write:

Reset:11111111

Bit 7654321Bit 0

Read: PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

Write:

Reset:11111111

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 19 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 73

Bit 15 14 13 12 11 10 9 Bit 8

0x00c8_0004

0x00c8_0005

0x00c9_0004

0x00c9_0005

PIT Count Register

(PCNTR)

See page 289.

Read: PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8

Write:

Reset:11111111

Bit 7654321Bit 0

Read: PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Write:

Reset:11111111

Bit 7654321Bit 0

0x00c8_0006

↓

0x00c8_0007 Unimplemented Access results in the mo dule generating an a ccess termination transfer error.

Bit 7654321Bit 0

0x00ca_0008

↓

0x00ca_ffff Unimplemented Access results in a bus monitor timeout generating an access t ermination transfer error.

Queued Analog-to-D igital Converter (QADC)

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0000

0x00ca_0001 QADC Module

Configuration Register

(QADCMCR)

See page 411.

Read: QSTOP QDBG 000000

Write:

Reset:00000000

Bit 7654321Bit 0

Read: SUPV 0000000

Write:

Reset:10000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0002

0x00ca_0003 QADC Test Register

(QADCTEST)

See page 412.

Access results in the module generating an access termination transfer error if not in test mode.

Bit 7654321Bit 0

Access results in the module generating an access termination transfer error if not in test mode.

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 20 of 34)

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Technical Data MMC2107 –Rev. 2.0

74 System Memory Map MOTOR OLA

System Memory Map

0x00ca_0004

0x00ca_0005 Reser ved Writes have no effect, reads ret urn 0s, and the access t erminates

without a transfer er ror exception.

Bit 7654321Bit 0

Writes have no effect, reads return 0s, and the access t erminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00ca_0006 QA DC Port A D ata

See page 413.

Read: 0 0 0 PQA4 PQA3 0PQA1 PQA0

Write:

Reset: 0 0 0 P P 0 P P

Bit 7654321Bit 0

0x00ca_0007 QA DC Port B D ata

See page 413.

Read: 0 0 0 0 PQB3 PQB2 PQB1 PQB0

Write:

Reset:0000PPPP

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0008

0x00ca_0009 QA DC Port A D ata

Direction Register

(DDRQA)

See page 415.

Read: 0 0 0 DDQA4 DDQA3 0DDQA1 DDQA0

Write:

Reset:00000000

Bit 7654321Bit 0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_000a

0x00ca_000b QADC Control Regis ter 0

(QACR0)

See page 416.

Read: MUX 00

TRG 000

PSH8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: PSH7 PSH6 PSH5 PSH4 PSA PSL2 PSL1 PSL0

Write:

Reset:00110111

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 21 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 75

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_000c

0x00ca_000d QADC Control Regis ter 1

(QACR1)

See page 419.

Read: CIE1 PIE1 0MQ112 MQ111 MQ110 MQ19 MQ18

Write: SSE1

Reset:00000000

Bit 7654321Bit 0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_000e

0x00ca_000f QA DC Control Regis ter 2

(QACR2)

See page 422.

Read: CIE2 PIE2 0MQ212 MQ211 MQ210 MQ29 MQ28

Write: SSE2

Reset:00000000

Bit 7654321Bit 0

Read: RESUME BQ26 BQ25 BQ24 BQ23 BQ22 BQ21 BQ20

Write:

Reset:01111111

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0010

0x00ca_0011 QADC Status Register 0

(QASR0)

See page 427.

Read: CF1 PF1 CF2 PF2 TOR1 TOR2 QS9 QS8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: QS7 QS6 CWP5 CWP4 CWP3 CWP2 CWP1 CWP0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 22 of 34)

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Technical Data MMC2107 –Rev. 2.0

76 System Memory Map MOTOR OLA

System Memory Map

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0012

0x00ca_0013 QADC Status Register 1

(QASR1)

See page 436.

Read: 0 0 CWPQ15 CWPQ14 CWPQ13 CWPQ12 CWPQ11 CWPQ10

Write:

Reset:00111111

Bit 7654321Bit 0

Read: 0 0 CWPQ25 CWPQ24 CWPQ23 CWPQ22 CWPQ21 CWPQ20

Write:

Reset:00111111

Bit 7654321Bit 0

0x00ca_0014

↓

0x00ca_01ff Reserved Writes have no e ffect, reads return 0s, and t he access terminates

without a transfer er ror exception.

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0200

0x00ca_027e Conversion Command

Word Register

(CCW)

See page 437.

Read: 0 0 0 0 0 0 PBYP

Write:

Reset:000000UU

Bit 7654321Bit 0

Read: IST1 IST0 CHAN5 CHAN4 CHAN3 CHAN2 CHAN1 CHAN0

Write:

Reset:UUUUUUUU

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0280

0x00ca_02fe Right-Justified Unsigned

Result Register (RJURR)

See page 441.

Read: 0 0 0 0 0 0 RESULT

Write:

Reset:000000

Bit 7654321Bit 0

Read: RESULT

Write:

Reset:

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 23 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 77

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0300

0x00ca_037e Left-Justified Signed

Result Register (LJSRR)

See page 442.

Read: SRESULT

Write:

Reset:

Bit 7654321Bit 0

Read: RESULT 000000

Write:

Reset: 000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ca_0380

0x00ca_03fe Left-Justified Unsigned

Result Register (LJURR)

See page 442.

Read: RESULT

Write:

Reset:

Bit 7654321Bit 0

Read: RESULT 000000

Write:

Reset: 000000

Bit 7654321Bit 0

0x00ca_0400

↓

0x00ca_ffff Unimplemented Access results in a bus monitor timeout generating an access t ermination transfer error.

Serial Peripheral Interface (SPI)

Bit 7654321Bit 0

0x00cb_0000 SPI Control Regis ter 1

(SPICR1)

See page 376.

Read: SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBFE

Write:

Reset:00000100

Bit 7654321Bit 0

0x00cb_0001 SPI Control Regis ter 2

(SPICR2)

See page 378.

Read: 0 0 0 0 0 0 SPISDOZ SPC0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 24 of 34)

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Technical Data MMC2107 –Rev. 2.0

78 System Memory Map MOTOR OLA

System Memory Map

Bit 7654321Bit 0

0x00cb_0002 SPI Baud Rate Register

(SPIBR)

See page 379.

Read: 0 SPPR6 SPPR5 SPPR4 0SPR2 SPR1 SPR0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb_0003 SPI Status Register

(SPISR)

See page 381.

Read: SPIF WCOL 0 MODF 0 0 0 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb_0004 Reserved Writes have no effect, reads return 0s, and the access terminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00cb_0005 SPI Data Register

(SPIDR)

See page 382.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb_0006

SPI Pullup and Reduced

Drive Register

(SPIPURD)

See page 383.

Read: 0 0 RSVD5 RDPSP 00

RSVD1 PUPSP

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb_0007 SPI Port Data Register

(SPIPORT)

See page 384.

Read: RSVD7 RSVD6 RSVD5 RSVD4 PORTSP3 PORTSP2 PORTSP1 PORTSP0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb_0008 SPI Port Data D i rectio n

See page 385.

Read: RSVD7 RSVD6 RSVD5 RSVD4 DDRSP3 DDRSP2 DDRSP1 DDRSP0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cb_0009

↓

0x00cb_000f Reserved Writes have no effect, reads ret urn 0s, and the access t erminates

without a transfer er ror exception.

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 25 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 79

Bit 7654321Bit 0

0x00cb_0010

↓

0x00cb_ffff Unimplemented Access results in a bus monitor timeout generating an access t ermination transfer error.

Serial Communications Interface 1 (SCI1) and Serial Communications Interface 2 (SCI2)

Note: Addresses for SCI1 are at 0x00c c_### # and addresses for S CI 2 are at 0x 00cd_# ###.

Bit 7654321Bit 0

0x00cc_0000

0x00cd_0000

SCI Baud Rate

See page 336.

Read: 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_0001

0x00cd_0001

SCI Baud Rate

See page 336.

Read: SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

Write:

Reset:00000100

Bit 7654321Bit 0

0x00cc_0002

0x00cd_0002

SCI Control Register 1

(SCICR1)

See page 337.

Read: LOOPS WOMS RSRC M WAKE ILT PE PT

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_0003

0x00cd_0003

SCI Control Register 2

(SCICR2)

See page 340.

Read: TIE TCIE RIE ILIE TE RE RWU SBK

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_0004

0x00cd_0004

SCI Status Register 1

(SCISR1)

See page 342.

Read: TDRE TC RDRF IDLE OR NF FE PF

Write:

Reset:11000000

Bit 7654321Bit 0

0x00cc_0005

0x00cd_0005

SCI Status Register 2

(SCISR2)

See page 344.

Read: 0 0 0 0 0 0 0 RAF

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 26 of 34)

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Technical Data MMC2107 –Rev. 2.0

80 System Memory Map MOTOR OLA

System Memory Map

Bit 7654321Bit 0

0x00cc_0006

0x00cd_0006

SCI Data Register High

(SCIDRH)

See page 345.

Read: R8 T8 000000

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_0007

0x00cd_0007

SCI Data Register Low

(SCIDRL)

See page 345.

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset:00000000

Bit 7654321Bit 0

0x00cc_0008

0x00cd_0008

SCI Pullup and Reduced

Drive Register

(SCIPURD)

See page 346.

Read: SCISDOZ 0RSVD5 RDPSCI 00

RSVD1 PUPSCI

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_0009

0x00cd_0009

SCI Port Data Register

(SCIPORT)

See page 347.

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 PORTSC1 PORTSC0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_000a

0x00cd_000a

SCI Data Direction

See page 348.

Read: RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 DDRSC1 DDRSC0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00cc_000b

↓

0x00cc_000f

0x00cd_000b

↓

0x00cd_000f

Reserved Writes have no effect, reads return 0s, and the access t erminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00cc_0010

↓

0x00cc_ffff

0x00cd_0010

↓

0x00cd_ffff

Unimplemented A ccess results in a bus monitor timeout generating an access t ermination transfer error.

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 27 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 81

Timer 1 (TIM1) and Tim er 2 (TIM2)

Note: Addresses for TIM1 are at 0x00ce_#### and addresses for TIM2 ar e at 0x00cf_####.

Bit 7654321Bit 0

0x00ce_0000

0x00cf_0000

Timer Input Capture/

Output Compare Select

See page 300.

Read: 0 0 0 0 IOS3 IOS2 IOS1 IOS0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0001

0x00cf_0001

Timer Compare Force

See page 301.

Write: FOC3 FOC2 FOC1 FOC0

Reset:00000000

Bit 7654321Bit 0

0x00ce_0002

0x00cf_0002

Timer Output Compare 3

Mask Register

(TIMOC3M)

See page 302.

Read: 0 0 0 0 OC3M3 OC3M2 OC3M1 OC3M0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0003

0x00cf_0003

Timer Output Compare 3

Data Register (TIMOC3D)

See page 303.

Read: 0 0 0 0 OC3D3 OC3D2 OC3D1 OC3D0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0004

0x00cf_0004

Timer Counter Register

High (TIMCNTH)

See page 304.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0005

0x00cf_0005

Timer Counter Register

Low (TIMCNTL)

See page 304.

Read: Bit 7 6 5 4 3 2 1 Bit 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0006

0x00cf_0006

Timer System Control

See page 305.

Read: TIMEN 00

TFFCA 0000

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 28 of 34)

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Technical Data MMC2107 –Rev. 2.0

82 System Memory Map MOTOR OLA

System Memory Map

Bit 7654321Bit 0

0x00ce_0007

0x00cf_0007 Reserved Writes have no effect, reads return 0s, and the access t erminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00ce_0008

0x00cf_0008

Timer Toggle on Overf low

See page 306.

Read: 0 0 0 0 TOV3 TOV2 TOV1 TOV0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0009

0x00cf_0009

Timer Control

See page 307.

Read: OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_000a

0x00cf_000a Reserved Writes have no effect, reads return 0s, and the access t erminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00ce_000b

0x00cf_000b

Timer Control

See page 308.

Read: EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG10

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_000c

0x00cf_000c

Timer Interrupt Enable

See page 309.

Read: 0 0 0 0 C3I C2I C1I C0I

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_000d

0x00cf_000d

Timer System Control

See page 310.

Read: TOI 0PUPT RDPT TCRE PR2 PR1 PR0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_000e

0x00cf_000e

Timer Flag Register 1

(TIMFLG1)

See page 312.

Read: 0 0 0 0 C3F C2F C1F C0F

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 29 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 83

Bit 7654321Bit 0

0x00ce_000f

0x00cf_000f

Timer Flag Register 2

(TIMFLG2)

See page 313.

Read: TOF 0000000

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ce_0010

0x00cf_0010

Timer Channel 0 Register

High (TIMC0H)

See page 314.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0011

0x00cf_0011

Timer Channel 0 Register

Low (TIMC0L)

See page 314.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ce_0012

0x00cf_0012

Timer Channel 1 Register

High (TIMC1H)

See page 314.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0013

0x00cf_0013

Timer Channel 1 Register

Low (TIMC1L)

See page 314.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ce_0014

0x00cf_0014

Timer Channel 2 Register

High (TIMC2H)

See page 314.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0015

0x00cf_0015

Timer Channel 2 Register

Low (TIMC2L)

See page 314.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ce_0016

0x00cf_0016

Timer Channel 3 Register

High (TIMC3H)

See page 314.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 30 of 34)

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Technical Data MMC2107 –Rev. 2.0

84 System Memory Map MOTOR OLA

System Memory Map

Bit 7654321Bit 0

0x00ce_0017

0x00cf_0017

Timer Channel 3 Register

Low (TIMC3L)

See page 314.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0018

0x00cf_0018

Pulse Accu mulat o r

Control Register

(TIMPACTL)

See page 315.

Read: 0 PAE PAMOD PEDGE CLK1 CLK0 PAOVI PAI

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0019

0x00cf_0019

Pulse Accumulator Flag

See page 317.

Read: 0 0 0 0 0 0 PAOVF PAIF

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

0x00ce_001a

0x00cf_001a

Pulse Accu mulat o r

Counter Register High

(TIMPACNTH)

See page 318.

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_001b

0x00cf_001b

Pulse Accu mulat o r

Counter Register Low

(TIMPACNTL)

See page 318.

Read: Bit 7654321Bit 0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_001c

0x00cf_001c Reserved Writes have no e ffect, reads return 0s, and t he access terminates

without a transfer er ror exception.

Bit 7654321Bit 0

0x00ce_001d

0x00cf_001d

Timer Port Data Register

(TIMPORT)

See page 319.

Read: 0 0 0 0 PORTT3 PORTT2 PORTT1 PORTT0

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_001e

0x00cf_001e

Time r Port D ata D ire ction

See page 320.

Read: 0 0 0 0 DDRT3 DDRT2 DDRT1 DDRT0

Write:

Reset:00000000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 31 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 85

Bit 7654321Bit 0

0x00ce_001f

0x00cf_001f

Timer Test Register

(TIMTST)

See page 321.

Write:

Reset:00000000

Bit 7654321Bit 0

0x00ce_0020

↓

0x00ce_ffff

0x00cf_0030

↓

0x00cf_ffff

Unimplemented Access re sults in the mo dule generating an access termination transf er error.

Non-Volatile Mem ory FLASH (CMFR)

Bit 31 30 29 28 27 26 25 Bit 24

0x00d0_0000

0x00d0_0001

0x00d0_0002

0x00d0_0003

CMFR Module

Configuration Register

(CMFRMCR)

See page 188.

Read: FSTOP FDBG 0EME SIE LOCKCTL DIS RSVD24

Write:

Reset: 0 0 0 Note 1 0 0 Note 1 0

Bit 23 22 21 20 19 18 17 Bit 16

Read: SUPV7 SUPV6 SUPV5 SUPV4 SUPV3 SUPV2 SUPV1 SUPV0

Write:

Reset:11111111

Bit 15 14 13 12 11 10 9 Bit 8

Read: DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

Write:

Reset:00000000

Bit 7654321Bit 0

Read: PROTECT7 PROTECT6 PROTECT5 PROTECT4 PROTECT3 PROTECT2 PROTECT1 PROTECT0

Write:

Reset:11111111

Notes:

1. Reset state is defined by reset override.

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 32 of 34)

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Technical Data MMC2107 –Rev. 2.0

86 System Memory Map MOTOR OLA

System Memory Map

Bit 31 30 29 28 27 26 25 Bit 24

0x00d0_0004

0x00d0_0005

0x00d0_0006

0x00d0_0007

CMFR Module Test

See page 193.

Write:

Reset:

Bit 23 22 21 20 19 18 17 Bit 16

Write:

Reset:

Bit 15 14 13 12 11 10 9 Bit 8

Read: 0 0 0 0 NVR PAWS2 PAWS1 PAWS0

Write:

Reset: 0000

Bit 7654321Bit 0

Read: 0 RSVD6 GDB 00000

Write:

Reset:00000000

Bit 31 30 29 28 27 26 25 Bit 24

0x00d0_0008

0x00d0_0009

0x00d0_000a

0x00d0_000b

CMFR High-Voltage

Control Register

(CMFRCTL)

See page 196.

Read: HVS 0SCLKR2 SCLKR1 SCLKR0 0CLKPE1 CLKPE0

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: 0 CLKPM6 CLKPM5 CLKPM4 CLKPM3 CLKPM2 CLKPM1 CLKPM0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: BLOCK7 BLOCK6 BLOCK5 BLOCK4 BLOCK3 BLOCK2 BLOCK1 BLOCK0

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 RSVD6 100

ERASE SES EHV

Write:

Reset:00100000

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 33 of 34)

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System Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA System Mem ory Map 87

Bit 7654321Bit 0

0x00d0_000c

↓

0x00d0_001c Unim plemented Access results in the mo dule generating an a ccess termination transfer error.

Bit 7654321Bit 0

0x00d0_001d

↓

0x7fff_ffff Unimplemented Access results in a bus monitor timeout generating an access termination tra nsfer error.

Address Register Name Bit Number

P = Current pin state U = Unaf fected = Writes have no effect and the access terminates without a transfer error exception.

Figure 2-2. Register Summary (Sheet 34 of 34)

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Technical Data MMC2107 –Rev. 2.0

88 System Memory Map MOTOR OLA

System Memory Map

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MMC21 07 –Rev. 2.0  Technical Data
MOTOROLA Chip Configurat ion Module (CCM)  89
Technical Data — MMC2107
Section 3.   Chip Configuration Module (CCM)
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
4.1 Master Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
4.2 Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
4.3 Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
4.4 Factory Access Slave Test (FAST) Mode  . . . . . . . . . . . . . .91
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.1 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.2 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.3 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
7.3.1 Chip Configuration Register. . . . . . . . . . . . . . . . . . . . . . .94
7.3.2 Reset Configuration Register. . . . . . . . . . . . . . . . . . . . . .9 7
7.3.3 Chip Identification Register . . . . . . . . . . . . . . . . . . . . . . .99
7.3.4 Chip T est Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.2 Chip Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
8.3 Boot Device Selection  . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
8.4 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . .105
8.5 Clock Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
8.6 Internal FLASH Configuration  . . . . . . . . . . . . . . . . . . . . . .106
9 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
    
  
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Technical Data MMC2107 –Rev. 2.0

90 Chi p C onfiguration Mo dule (CCM) MOTOROLA

Chip Configuration Module (CC M)

3.2 Introduction

The chip configuration module (CCM) controls the chip configuration and

mode of operation.

3.3 Featur es

The CCM performs these operations.

•Selects the chip operating mode:

–Master mode

–Single-chip mode

–Emulation mode

–Factory access slave test (FAST) mode for factory test only

•Selects external clock or phase-lock loop (PLL) mode with internal

or external reference

•Selects output pad strength

•Selects boot device

•Selects module configuration

•Selects bus monitor configuration

3.4 Mo des of Operation

The CCM configures the chip for four modes of operation:

•Master mode

•Single-chip mode

•Emulation mode

•FAST mode for factory test only

The operating mode is determined at reset and cannot be changed

thereafter.

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Chip Configuration Module (CCM)

Modes of Op eration

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Chip Configurat ion Module (CCM) 91

3.4.1 Master Mode

In master mode, the internal central processor unit (CPU) can access

external memories and peripherals. Full master mode functionality

requires the bonding out of the optional pins. The external bus consists

of a 32-bit data bus and 23 address lines. Available bus control signals

include R/W, TC[2:0], TSIZ[1:0], TA, TEA, OE, and EB[3:0]. Up to four

chip selects can be programmed to select and control external de vices

and to provide bus cycle termination. When interfacing to 16-bit ports,

the ports C and D pins and EB[3:2] can be configured as

general-purpose input/output (I/O).

3.4.2 Single-Chip Mode

In si ngle-chip m ode, all memory is internal to the chip . External bus pins

are configured as digital I/O.

3.4.3 Emulation Mode

Emulation mode supports external port replacement logic. All ports are

emulated and all primary pin functions are enabled. Since the full

external bus must be visible to support the external port replacement

logic, the emulation mode pin configuration resembles master mode.

Full emulation mod e functionality requires bonding out the optional pins.

Emula tion mode chi p selects are provide d to give addition al informati on

about the bus cycle. Also, the signal SHS is provided as a strobe for

capturing addresses and data during show cycles.

3.4.4 Factory Access Slave Test (FAST) Mode

FAST mode is for factory test only.

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Technical Data MMC2107 –Rev. 2.0

92 Chi p C onfiguration Mo dule (CCM) MOTOROLA

Chip Configuration Module (CC M)

3.5 Block Diagram

Figure 3-1. Ch ip Configuration Module Block Diagram

3.6 Signal Descriptions

Table 3-1 provides an overview of the CCM signals. For more detailed

information, refer to Section 4. Signal Description.

RESET

CHIP MODE

SELECTION

BOOT DEVICE

SELECTION

OU T PUT PAD

STRENGTH SELE CTI ON

CLOCK MO DE

SELECTION

MODULE

CONFIGURATION

RESET CONFIGURATION REGISTER

CHIP CO NFIGURA TIO N RE G IS TE R

CHIP IDENTIFICATION REGISTER

CHIP TEST R EGI STER

Table 3-1. Signal Properties

Name Function Reset State

RCON Reset configuration select Internal weak pullup device

VDDSYN Clock mode select —

D[31:16] Res et configuration overrides —

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Chip Configuration Module (CCM)

Mem ory Map and Registers

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Chip Configurat ion Module (CCM) 93

3.7 Memory Map and Registers

This subsection provides a description of the memory map and registers.

3.7.1 Programming Model

The CCM programming model consists of these registers:

•The chip configuration register (CCR) controls the main chip

configuration.

•The reset configuration register (RCON) indicates the default chip

configuration.

•The chip identification register (CIR) contains a unique part

number.

•The chip test register (CTR) contains chip-specific test functions.

Some control register bits are implemented as write-once bits. These

bits are always readable, but once the bit has been w ritten, additional

writes have no effect, except during debug mode and test operations.

Some write-once bits and test bits can be read and written while in debug

mode or test mode. When debug or test mode is exited, the chip

configuration module resumes operation based on the current register

valu es. If a write to a wr ite-once r egister bit occurs whi le in debug or test

mode, the re gister bit rem ains writable on exit from debug or t est mode.

Table 3-2 sho ws th e accessibility of write-once bits.

Table 3-2. Write-Once Bits Read/Write Accessibility

Configuration Read/Write Access

All configurations Read-always

Debug operation (all modes) Write-alway s

Test operation (all modes) Write-always

Master mode Write-once

Single-chip mode Write-once

FAST mode Write-once

Emulation mode Write-once

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Technical Data MMC2107 –Rev. 2.0

94 Chi p C onfiguration Mo dule (CCM) MOTOROLA

Chip Configuration Module (CC M)

3.7.2 Memory Map

3.7.3 Register Descriptions

The following subsection describes the CCM registers.

3.7.3.1 Chip Configuration Register

Table 3-3. Chip Configur ation Module Memory Map

Address Bits 31–16 Bi ts 15–0 Access(1)

0x00c1_0000 Chip configuration register (CCR) Reserved(2) S

0x0 0 c1 _0004 Reset configuration register (RCON) Chip identification register (CIR ) S

0x00c1_0008 Chip test register (CTR) Reserved(2) S

0x00c1_000c Unimplemented(3) —

1. S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a

cycle termina ti on transfer error.

2. Writing to reserved addresses has no effect; reading ret urns 0s.

3. Accessi ng an unimplemented address has no effect and causes a cycle terminati on transfer error.

Address: 0x00 c1_0000 and 0x00c1_0001

Bit 15 14 13 12 11 10 9 Bit 8

Read: LOAD 0SHEN EMINT 0 MODE2 MODE1 MODE0

Write:

Reset: Note 1 0 Note 2 Note 2 0 Note 1 Note 1 Note 1

Bit 7654321Bit 0

Read: 0 SZEN PSTEN SHINT BME BMD BMT1 BMT0

Write:

Reset:0Note 3Note 201000

= Writes have no effect and the access terminates without a transfer error exception.

Notes:

1. Determined during reset configuration

2. 0 for all configurati ons e xcept emulation m ode, 1 for emul ation mode

3. 0 for all configurati ons e xcept emulation and m aster modes, 1 for em ulation and master

modes

Figure 3-2. Chip Configuration Register (CCR)

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Chip Configuration Module (CCM)

Mem ory Map and Registers

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Chip Configurat ion Module (CCM) 95

LOAD — Pad Driver Load Bit

The LOAD bit selects full or default drive strength for selected pad

output drivers. For maximum capacitive load, set the LOAD bit to

select full drive strength. For reduced power consumption, clear the

LOAD bit to select default drive strength.

1 = Full drive strength

0 = Default drive strength

Table 3-2 shows th e read/write accessibility of this write-once bit.

SHEN — Show Cycle Enable Bit

The SHEN bit enables the external memory interface to drive the

external bus during internal transfer operations.

1 = Show cycles enabled

0 = Show cycles disabled

In emul ation mod e, the SHE N bit is rea d-only. In all other mo des, it is

a read/w rite bit.

EMINT — Emulate Internal Address Space Bit

The EMINT bit enables chip select 1 (CS1) to decode the internal

memory address space.

1 = CS1 decodes internal memory address space.

0 = CS1 decodes external memory address space.

The EMINT bit is read-always but can be wr itten only in emulation

mode.

MODE[2:0] — Chip Configuration Mode Field

This read-onl y field refl ects the chip configuration mode, as shown in

Table 3-4.

Table 3-4. Chip Configuration Mode Selection

MODE[2:0] Chip Configuration Mode

111 Master mode

110 Sing le-chip mode

10X FAST mode

0XX Em ulation mode

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Technical Data MMC2107 –Rev. 2.0

96 Chi p C onfiguration Mo dule (CCM) MOTOROLA

Chip Configuration Module (CC M)

SZEN — TSIZ[1:0] Enable Bits

This rea d/write bit ena bles the TSIZ[1:0] f u nction o f the e xterna l pins.

1 = TSIZ[1:0] function enabled

0 = TSIZ[1:0] function disabled

PSTEN — PSTAT[3:0] Signal Enable Bits

This read/write bit enables the PSTAT[3:0] function of the external

pins.

1 = PSTAT[3:0] function enabled

0 = PSTAT[3:0] function disabled

SHINT — Show Interrupt Bit

The SHINT bit allows visibility to any active interrupt request to the

processor. If the SHINT bit i s set, the RSTOUT pin is the OR of the

fast and normal interrupt signals.

1 = Internal requests reflected on RSTOUT pin

0 = Normal RSTOUT pin function

The SHINT bit is read/write always.

NOTE: The FRCRSTOUT function in the reset controller has a higher priority

than the SHINT function.

BME — Bus Monitor External Enable Bit

The BME bit enables the bus monitor to operate during external bus

cycles.

1 = Bus monitor enabled on external bus cycles

0 = Bus monitor disabled on external bus cycles

Table 3-2 shows th e read/write accessibility of this write-once bit.

BMD — Bus Monitor Debug Mode Bit

The BMD bit controls how the bus monitor responds during debug

mode.

1 = Bus monitor enabled in debug mode

0 = Bus monitor disabled in debug mode

This bit is read/write always.

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Chip Configuration Module (CCM)

Mem ory Map and Registers

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Chip Configurat ion Module (CCM) 97

BMT[1:0] — Bus Monitor Timing Field

The BM T field sele cts the timeout time for the bus monito r as shown

in Table 3-5.

Table 3-2 shows th e read/write accessibility of these write-once bits.

3.7.3.2 Reset Configuration Register

The reset configuration register (RCON) is a read-only register; writing

to RCON has no effect. At reset, RCON determines the default operation

of certain chip functions. All default functions defined by the RCON

valu es may be overr idden du ri ng re set config uratio n onl y if the exte rnal

RCON pin is asserted.

Table 3-5. Bus Monitor Timeout Values

BMT[1:0] Timeout Period

(in Sy stem C locks)

00 64

01 32

10 16

11 8

Address: 0x00c1_0004 and 0x00c1_0005

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

RPLLSEL 1

RPLLREF 0

RLOAD 01

BOOTPS 0

BOOTSEL 00

MODE

Write:

Reset:11001000

= Writes have no effect and the access terminates without a transfer error exception.

Figu re 3-3. Re set Conf igu ra tio n Regi ste r (RCO N)

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Technical Data MMC2107 –Rev. 2.0

98 Chi p C onfiguration Mo dule (CCM) MOTOROLA

Chip Configuration Module (CC M)

RPLLSEL — PLL Mode Select Bit

When the PLL is enabled, the read-only RPLLSEL bit reflects the

default PLL mode.

1 = No rma l PLL mode

0 = 1:1 PLL mode

The default PLL mode can be overridden during reset configuration.

If the default mod e is o verr id den, the PLLSEL b i t in t he clock mod ul e

SYNSR reflects the PLL mode.

RPLLREF — PLL Reference Bit

When the PLL is enabled in normal PLL mode, the read-only

RPLLREF bit reflects the default PLL reference.

1 = Crystal oscillator is PLL reference.

0 = External clock is PLL reference .

The default PLL reference can be overridden during reset

configuration. If the default mode is overridden, the PLLREF bit in the

clock module SYNSR reflects the PLL reference.

RLOAD — Pad Driver Load Bit

The read-only RLOAD bit reflects the pad driver strength

configuration.

1 = Full drive strength

0 = Default drive strength

The default function of the pad driver strength can be overridden

during reset configuration. If the default mode is overridden, the

LOAD bit i n CCR reflects the pad driver strength configuration.

BOOTPS — Boot Port Size Bit

If the boot device is co nfigured to be external, the read-only BOOTPS

bit reflects the default selection for the boot port size.

1 = Boot device uses 32-bit port.

0 = Boot device uses 16-bit port.

The default function of the boot port size can be overridden during

reset configuration. If the default mode is overridden, the PS bit in

CSCR0 reflects the boot device port size configuration.

BOOTSEL — Boot Select Bit

This read-only bit reflects the default selection for the boot device.

1 = Boot from external boot device

0 = Boot from internal boot device

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Chip Configuration Module (CCM)

Mem ory Map and Registers

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Chip Configurat ion Module (CCM) 99

The de fault functi on of the b oot select can b e overridde n during r eset

configuration. If the default mode is overridden, the CSEN bit in

CSCR0 bit reflects the boot device configuration.

MODE — Chip Conf iguration Mode Bit

The read -onl y MODE bi t reflects the de fault chip confi gur ation mo de.

1 = Master mode

0 = Single-chip mode

The defa ult mode can be over ridden during reset con figura tion. If the

default mode is ov errid den, the MODE0 bit in CCR reflects the mode

configuration.

3.7.3.3 Chip Identification Register

The chip identification register (CIR) is a read-only register; writing to

CIR has no effect.

PIN[7:0] — Part Identification Number Field

This read-only field contains a unique identification number for the

part.

PRN[7:0] — Part Revision Number Fi eld

This read-only field contains the full-layer mask revision number. This

number is increased by one for each new full-layer mask set of this

part. The revision numbers are assigned in chronological order.

Address: 0x00 c1_0006 and 0x00c1_0007

Bit 15 14 13 12 11 10 9 Bit 8

PIN7 0

PIN6 0

PIN5 1

PIN4 0

PIN3 1

PIN2 1

PIN1 1

PIN0

Write:

Reset:00010111

Bit 7654321Bit 0

PRN7 0

PRN6 0

PRN5 0

PRN4 0

PRN3 0

PRN2 0

PRN1 0

PRN0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 3-4. Chip Identification Register (CIR)

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Technical Data MMC2107 –Rev. 2.0

100 Chip Configurat ion Module (CCM ) MOTOR OLA

Chip Configuration Module (CC M)

3.7.3.4 Chip Test Register

The chip test register (CTR) is reserved for factory testing.

NOTE: To safeg uard agai nst uninte ntionally ac tivating te st logic, write $0000 to

the lock-out test features. Setting any bit in CTR may lead to

unpredictable results.

3.8 Functional D escription

Six functions are defined within the chip configuration module:

1. Reset configuration

2. Chip mode selection

3. Boot devi ce selection

4. Output pad strength configuration

5. Clock mode selection

6. Module configuration

These functions are described here.

Address: 0x00 c1_0008 and 0x00c1_0009

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 3-5. Chip Test Register (CTR)

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Chip Configuration Module (CCM)

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Chip Configurat ion Module (CCM) 101

3.8.1 Reset Configuration

During reset, the pins for the reset override functions are immediately

configured to known states, even if the clock source is not present.

Table 3-6 shows the states of the external pins while in reset.

If the RCON pin is not asse rted du ri ng re set, the chip con fi gura tion and

the reset configuration pin functions after reset are determined by RCON

or fixed defaults, regardless of the states of the external data pins. The

internal configurat ion signals are driven to levels specified by the RCON

If the external RCON pin is asserted during reset, then various chip

functi ons, includi n g the reset configura ti on pin functio ns after re set, are

configured according to the levels driven onto the external data pins.

(See Table 3-7.) The internal configurati on signals are driven to reflect

the levels on the external configuration pins to allow for module

configuration.

Table 3-6. Reset Configuration Pin Stat es During Reset

Pin Pin

Function(1)

1. If the external RCON pin is not asser ted duri ng reset, pin functions are deter m ined by th e

default operation mode defined in the RCON register. If the external RCON pin is asserted,

pin functions are determine d by the chi p operation mode defi ned by the override values

driven on the external data bus pins.

I/O Output

State Input

State

D[28, 26, 23:21, 19:16],

PA[4 , 2], PB[7:5, 3:0] Digital I/O or prim ary

function Input —Mus t be driven

by external logic

RCON RCON function for all

modes(2)

2. Dur ing res et, the ex ternal RCON pin ass umes its RCON p in func tion, but th is pin chang es

to t he funct ion def ined by the chip oper atio n mode i mmediate ly aft er res et. See Table 3-7.

Input —Internal weak

pullup device

VDDSYN Not affected Input —Must be driven by

external logic

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Technical Data MMC2107 –Rev. 2.0

102 Chip Configurat ion Module (CCM ) MOTOR OLA

Chip Configuration Module (CC M)

Table 3 -7. Configuration During Reset(1)

Pin(s) Affected Default

Configuration Override Pin s

in Reset(2),(3) Function

D[31:0], SHS, TA, TEA,

CSE[1:0], TC[2:0], OE,

A[22:0], EB[3:0] , CS[3:0 ]

VDD, VDD,

RCON0

D[26,17:16] Chip Mode Selected

111 Master mode

110 Sin gle-chip mode

10X FAST mode

0XX Emulation mode

CS[1:0] RCON[3:2]

D [19:18] Boot Device

X0 Internal with 32-bit po rt

01 External with 16-bit port

11 External with 32-bit port

All output pins RCON5

D21 Ou tput P ad D ri v e Strengt h

0 D efault strength

1 Full strength

Clock mode VDDSYN,

RCON[7:6]

VDDSYN, D[23:22] Clock Mode

0XX Ext ernal clock mode (PLL disabled )

10X 1:1 PLL mod e

110 N ormal PLL mode with external clock reference

111 N ormal PLL mode w/crystal oscillator reference

Internal FLASH

configuration VDD

D28 Modul e Confi gu r at i on

1 Internal FL ASH enabled

0 Internal FL ASH disabled

1. Modif ying the defa ult configura ti ons is possible only if the exter nal RCON pin is asserted.

2. The D[31:29, 27, 25:24 , 20, 15:0] pins do not af fect reset configuration.

3. The external reset override circuitry drives the data bus pins wit h the override values while RSTOUT is asserted. It must

stop dr iving t he data bu s p ins wi thin one CLKO UT cyc le after RST OUT is negat ed. To preven t content ion wi th t he exter nal

reset override circuitry, the reset override pins are for ced to inputs duri ng reset and do not beco me outputs until at least

one CLKOUT cycle after RSTOUT is negated.

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Chip Configuration Module (CCM)

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Chip Configurat ion Module (CCM) 103

3.8.2 Chip Mo de Selection

The chip mode is selected dur ing reset and refl ected in the MODE field

of the chip configuration register (CCR). Once reset is exited, the

operating mode cannot be changed. Tab le 3-8 shows the mode

selection during reset configuration.

During reset, certain module configurations depend on whether

emulation mode is active as determined by the state of the internal

emulation signal.

3.8.3 Boot Device Selection

During reset configuration, the CS0 chip select pin is optionally

configured to select an external boot device. In this case, the CSEN bit

in CSCR0 is set, enabling CS0 after reset. CS0 will be asserted for the

initial boot fetch accessed from address 0x0. It is assumed that the reset

vect or loaded fro m address 0x0 causes the CPU to start exe cuting fr om

ext erna l memor y space deco ded by CS 0. Also, the P S bit is configu red

for either a 16-bit or 32-bit port size depending on the external boot

device. See Tab le 3-9.

In emulation mode, the CS1 chip select pin is optionally configured for

emulating an internal memory. In emulation mode and booting from

internal memory, the CSEN bit in CSCR1 is set, enabling CS1 after

reset.

Table 3-8. Chip Configuration Mode Selection(1)

1. Modifying the default configurations i s possible only if the external RCON pi n is asserted.

Chip Configuration

Mode CCR Register MODE Field

MODE2 MODE1 MODE0

Mast er mode D26 driven high D17 driven high D16 driven high

Single-chip m ode D26 driven high D17 driven high D16 driven low

FAST mode D26 driven high D17 driven low D16 don’t c a re

Em ulation mode D26 driven low D17 don’t care D16 don’t ca re

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Technical Data MMC2107 –Rev. 2.0

104 Chip Configurat ion Module (CCM ) MOTOR OLA

Chip Configuration Module (CC M)

Once r eset i s exited, the state s of the CSEN an d P S bits in CS CR 0 an d

the CSEN bit in CSCR1 remain, but can be modified by software.

NOTE: When booting exter nall y, the D28 pi n should be dr iven lo w during reset

configuration to disable the internal FLASH located at address 0x0 so

that no conflict exists with the external boot device.

The boot device selection during reset configuration is summarized in

Table 3-10.

Table 3-9. Chip Select CS0 Config uration Encoding

Chip Select CS0 Control

CSCR0

CSEN Bit PS Bit CSEN Bit

Chip select disabled (32-bit port size) 0 1 1(1)

1. CSCR1 CSEN is initially set only in emulation mode when booting from internal memory

and is cl eared otherwi se.

Chip select enabled with 16-bit port size 1 0 0

Chip select enabled with 32-bit port size 1 1 0

Table 3-10. Boot Device Selection(1)

1. Modifying the default configurations i s possible only if the external RCON pi n is asserted.

Boot Device Selection

CSCR0

CSEN Bit PS Bit CSEN Bit

Internal boot device;

default 32-bit port D18 driven low D19 don’t care D18 driven low

Exte rnal boot device

with 16-bit port D18 driven high D19 driven low D18 driven high

Exte rnal boot device

with 32-bit port D18 driven high D19 driven high D18 driven high

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Chip Configuration Module (CCM)

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Chip Configurat ion Module (CCM) 105

3.8.4 Output Pad Strength Configuration

Output pad strength is determined during reset configuration as shown

in Table 3-11. Once reset is exited, the output pad strength configuration

can be changed by programming the L O AD bi t of the ch ip conf ig urat ion

3.8.5 Clock Mo de Selection

The clock mode i s selected dur ing reset a nd reflected in the PL LMODE,

PLLSEL, and PLLREF bits of SYNSR. Once reset i s exited, the clock

mode cannot be changed.

Table 3-12 summarizes clock mode selection during reset configuration.

Table 3-11. Output Pad Driver Strength Selection(1)

1. Modifying the default configurations is possible only if the external RCON pin is asserted

low.

Optional Pin Function Selection CC R Register LOAD Bit

Outp ut pads configured for default strength D 2 1 driven low

Outp ut pads configured for full strength D2 driven high

Table 3-12. Clock Mode Selection(1)

Clock Mode Syn thesizer Statu s Register (SYNS R)

MODE Bit PLLSEL Bit PLLREF Bit

Exte rnal clock mode; PLL disab led VDDSYN driv en low D23 don’t care D22 don’t care

1:1 PLL mode VDDSYN dr iven hig h D23 driven low D22 don’t care

Normal PLL mo de; external clock reference VDDSYN driven high D23 driven high D22 driven low

Nor mal P L L mode; cry sta l os c illato r r e fe renc e VDDSYN driven hig h D23 driven high D22 dri ven high

1. Modifying the default configurations is possible only if the exter nal RCON pin is asser ted l ow.

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Technical Data MMC2107 –Rev. 2.0

106 Chip Configurat ion Module (CCM ) MOTOR OLA

Chip Configuration Module (CC M)

3.8.6 Internal FLASH Configuration

During reset configuration, the D28 pin controls whether or not the

internal FLASH is enabled or disabled as shown in Table 3-13.

3.9 Reset

Rese t initial izes CC M reg i sters to a known sta rtup state as de scribed in

3. 7 Memor y Ma p an d R eg ister s. T he CCM con trol s chip co nfigur ation

at reset as described in 3.8 Functional Description.

3.10 Interrupts

The CCM does not generate interrupt requests.

Table 3-13. Internal FLASH Configuration(1)

1. Modifying the default configurations is possible only if the external RCON pin is asserted

low.

Internal FLASH Configuration External D28 State

Internal FLASH enabled D28 pin driven high

Internal FLASH disabled D28 pin driven low

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MMC21 07 –Rev. 2.0  Technical Data
MOTOROLA Signal Description  107
Technical Data — MMC2107
Section 4.   Signal Description
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
3 Package Pinout Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .110
4 MMC2107 Specific Implementation Signal Issues . . . . . . . . .120
4.1 RSTOUT Signal Functions. . . . . . . . . . . . . . . . . . . . . . . . .120
4.2 INT Signal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
5 Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
5.1 Reset Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
5.1.1 Reset In (RESET)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
5.1.2 Reset Out (RSTOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .121
5.2 Phase-Lock Loop (PLL) and Clock Signals . . . . . . . . . . . .122
5.2.1 External Clock In (EXTAL). . . . . . . . . . . . . . . . . . . . . . .122
5.2.2 Crystal (XTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
5.2.3 Clock Out (CLKOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . .122
5.2.4 Synthesizer Power (VDDSYN and VSSSYN). . . . . . . . . . .122
5.3 External Memory Interface Signals  . . . . . . . . . . . . . . . . . .122
5.3.1 Data Bus (D[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
5.3.2 Show Cycle Strobe (SHS) . . . . . . . . . . . . . . . . . . . . . . .123
5.3.3 Transfer Acknowledge (TA). . . . . . . . . . . . . . . . . . . . . .123
5.3.4 Transfer Error Acknowledge (TEA) . . . . . . . . . . . . . . . .123
5.3.5 Emulation Mode Chip Selects (CSE [1:0]) . . . . . . . . . . .123
5.3.6 Transfer Code (TC[2:0]). . . . . . . . . . . . . . . . . . . . . . . . .123
5.3.7 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
5.3.8 Address Bus (A[22:0]) . . . . . . . . . . . . . . . . . . . . . . . . . .124
5.3.9 Enabl e Byte (EB[3:0])  . . . . . . . . . . . . . . . . . . . . . . . . . .124
5.3.10 Chip Sele ct (CS[3:0]). . . . . . . . . . . . . . . . . . . . . . . . . . .124
5.3.11 Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
    
  
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Technical Data MMC2107 –Rev. 2.0
Signal Description MOTOROLA
Signal Descri ption
5.4 Edge P ort Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
5.4.1 External Interrupts (INT[7:6]) . . . . . . . . . . . . . . . . . . . . .124
5.4.2 External Interrupts (INT[5:2]) . . . . . . . . . . . . . . . . . . . . .124
5.4.3 External Interrupts (INT[1:0]) . . . . . . . . . . . . . . . . . . . . .125
5.5 Serial Peripheral Interface Module Signals . . . . . . . . . . . .125
5.5.1 Master Out/Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . .125
5.5.2 Master In/Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . .125
5.5.3 Serial Clock (SCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5.5.4 Slave Select (SS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5.6 Serial Communications Interface Module Signals . . . . . . .125
5.6.1 Receive Data (RXD1 and RXD2). . . . . . . . . . . . . . . . . .125
5.6.2 Transmit Data (TXD1 and TXD2). . . . . . . . . . . . . . . . . .126
5.7 Timer Signals (ICOC1[3:0] and ICOC2[3:0]) . . . . . . . . . . .126
5.8 Analog-to-Digital Converter Signals. . . . . . . . . . . . . . . . . .126
5.8.1 Analog Inputs (PQA[4:3], PQA[1:0],  . . . . . . . . . . . . . . . . . .
and PQB[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
5.8.2 Analog Reference (VRH and VRL)  . . . . . . . . . . . . . . . . .126
5.8.3 Analog Supply (VDDA and VSSA) . . . . . . . . . . . . . . . . . .126
5.8.4 Positive Supply (VDDH)  . . . . . . . . . . . . . . . . . . . . . . . . .126
5.9 Debug and Emulation Support Signals  . . . . . . . . . . . . . . .127
5.9.1 Test Reset (TRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.9.2 Test Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.9.3 Test Mode Select (TMS ) . . . . . . . . . . . . . . . . . . . . . . . .127
5.9.4 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.9.5 Test Data Output (TDO). . . . . . . . . . . . . . . . . . . . . . . . .127
5.9.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
5.10 Test Signal (TEST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
5.11 Power and Ground Signals  . . . . . . . . . . . . . . . . . . . . . . . .128
5.11.1 Power for FLASH Erase/Program (VPP) . . . . . . . . . . . .128
5.11.2 Power and Ground for FLASH Array 
(VDDF and VSSF) . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
5.11.3 Standby Power (VSTBY) . . . . . . . . . . . . . . . . . . . . . . . . .128
5.11.4 Positive Supply (VDD). . . . . . . . . . . . . . . . . . . . . . . . . . .128
5.11.5 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
    
  
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Signal Description

Introduction

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Signal Description 109

4.2 Introduction

The MMC2107 is available in two packages:

•100-pin Joint-Electron Device Engineering Council (JEDEC)

low-profile quad flat pack (LQFP) — The 100-pin device is a

minimum pin set for single-chip mode implementation.

•144-pin JEDEC LQFP — The 144-pin implementation includes 44

optional pins as a bond-out option to:

–Accommodate an expanded set of features

–Allow expansion of the number of general-purpose

input/output (I/O)

–Utilize off-chip memory

–Provide enhanced support for development purposes

The optional group of pins includes:

•23 address output lines

•Four chip selects

•Two emulation chip selects

•Four byte/wr it e enables

•Read/write (R/W) signal

•Output enable signal

•Three transfer code signals

•Six power/ground pins

NOTE: The optional pins are either all present or none of them are present.

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Technical Data MMC2107 –Rev. 2.0

110 Signal Description MOTOROLA

Signal Descri ption

4.3 Package Pinout Summary

Refer to:

•Table 4-1 for a summary of the pinouts for both packages

•Figure 4-1 and Figure 4-2 for a pictorial view of the pinouts

•Table 4-2 for a brief description of each signal

Table 4-1. Package Pinouts (Sheet 1 of 5)

Pin N u mber Pin Name

144-Pin Package 100-Pi n Package

1 1 D30 / PA6

2 2 D29 / PA5

3 3 D28 / PA4

4 4 D27 / PA3

5 5 D26 / PA2

6 — A11

7 6 D25 / PA1

8 — VSS

9 — VDD

10 7 D24 / PA0

11 —A10

12 8 D23 / PB7

13 —A9

14 —A8

15 9 D22 / PB6

16 10 D21 / PB5

17 11 D20 / PB4

18 12 VSS

19 13 VDD

20 14 D19 / PB3

21 15 D18 / PB2

22 16 D17 / PB1

23 —A7

24 —A6

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Signal Description

Package P inou t Summary

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Signal Description 111

25 17 D16 / PB0

26 —A5

27 18 D15 / PC7

28 —A4

29 —A3

30 19 D14 / PC6

31 20 D13 / PC5

32 21 VSS

33 22 VDD

34 23 D12 / PC4

35 24 D11 / PC3

36 25 D10 / PC2

37 26 D 9 / PC1

38 27 D 8 / PC0

39 28 D 7 / PD7

40 29 D 6 / PD6

41 30 D 5 / PD5

42 31 D 4 / PD4

43 32 D 3 / PD3

44 —VSS

45 —VDD

46 33 D 2 / PD2

47 —A2

48 34 D 1 / PD1

49 —A1

50 —A0

51 35 D 0 / PD0

52 36 ICOC23

53 37 ICOC22

54 38 ICOC21

55 39 ICOC20

Table 4-1. Package Pinouts (Sheet 2 of 5)

Pin N u mber Pin Name

144-Pin Package 100-Pi n Package

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Technical Data MMC2107 –Rev. 2.0

112 Signal Description MOTOROLA

Signal Descri ption

56 40 ICOC13

57 41 ICOC12

58 42 ICOC11

59 —R/W

60 —CSE1

61 43 ICOC10

62 —CSE0

63 44 TEST

64 —VSS

65 —VDD

66 45 TXD2

67 —TC2

68 46 RXD2

69 47 TXD1

70 48 RXD1

71 49 INT0

72 50 INT1

73 51 VSSF

74 52 VDDF

75 53 INT2

76 54 VSS

77 55 VDD

78 —TC1

79 56 INT3

80 —TC0

81 —CS3

82 57 INT4

83 —CS2

84 58 INT5

85 —CS1

Table 4-1. Package Pinouts (Sheet 3 of 5)

Pin N u mber Pin Name

144-Pin Package 100-Pi n Package

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Signal Description

Package P inou t Summary

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Signal Description 113

86 —CS0

87 59 VPP

88 60 INT6

89 61 INT7

90 62 MOSI

91 63 MISO

92 64 VSTBY

93 65 SCK

94 66 SS

95 —OE

96 —EB3

97 67 SHS / PE7

98 —EB2

99 68 TA / PE6

100 —EB1

101 —EB0

102 69 TEA / PE5

103 70 VDDH

104 71 PQB3

105 72 PQB2

106 73 PQB1

107 74 PQB0

108 75 PQA4

109 76 PQA3

110 77 PQA1

111 78 PQA0

112 79 VRL

113 80 VRH

114 81 VSSA

115 82 VDDA

Table 4-1. Package Pinouts (Sheet 4 of 5)

Pin N u mber Pin Name

144-Pin Package 100-Pi n Package

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Technical Data MMC2107 –Rev. 2.0

114 Signal Description MOTOROLA

Signal Descri ption

116 —A22

117 —A21

118 83 RESET

119 —A20

120 84 RSTOUT

121 —A19

122 —A18

123 85 VDDSYN

124 86 XTAL

125 87 EXTAL

126 88 VSSSYN

127 89 VSS

128 90 CLKOUT

129 91 VDD

130 92 TCLK

131 —A17

132 —A16

133 93 TDI

134 —A15

135 94 TDO

136 —A14

137 —A13

138 95 TMS

139 —A12

140 96 VSS

141 97 VDD

142 98 TRST

143 99 DE

144 100 D31 / PA7

Table 4-1. Package Pinouts (Sheet 5 of 5)

Pin N u mber Pin Name

144-Pin Package 100-Pi n Package

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Signal Description

Package P inou t Summary

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Signal Description 115

Figure 4-1. 144-Pin LQFP Assignments

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

PQA4

PQB0

PQB1

PQB2

PQB3

VDDH

TEA

EB0

EB1

EB2

SHS

EB3

SCK

VSTBY

MISO

MOSI

INT7

INT6

VPP

CS0

CS1

INT5

CS2

INT4

CS3

TC0

INT3

TC1

VDD

VSS

INT2

VDDF

VSSF

D30

D29

D28

D27

D26

A11

D25

VSS

VDD

D24

A10

D23

D22

D21

D20

VSS

VDD

D19

D18

D17

D16

D15

D14

D13

VSS

VDD

D12

D11

D10

ICOC23

ICOC22

ICOC21

ICOC20

ICOC13

ICOC12

ICOC11

R/W

CSE1

ICOC10

CSE0

TEST

TXD2

TC2

RXD2

TXD1

RXD1

INT0

INT1

D31

TRST

A12

TMS

A13

A14

TDO

A15

TDI

A16

A17

TCLK

CLKOUT

SSSYN

EXTAL

XTAL

DDSYN

A18

A19

RSTOUT

A20

RESET

A21

A22

DDA

SSA

PQA0

PQA1

PQA3

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Technical Data MMC2107 –Rev. 2.0

116 Signal Description MOTOROLA

Signal Descri ption

Figure 4-2. 100-Pin LQFP Assignments

100

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PB7

PB6

PB5

PB4

VSS

VDD

PB3

PB2

PB1

PB0

PC7

PC6

PC5

VSS

VDD

PC4

PC3

PC2

PC1

PC0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

ICOC23

ICOC22

ICOC21

ICOC20

ICOC13

ICOC12

ICOC11

ICOC10

TEST

TXD2

RXD2

TXD1

RXD1

INT0

INT1PQA3

PQA1

PQA0

SSA

DDA

RESET

RSTOUT

DDSYN

XTAL

EXTAL

SSSYN

CLKOUT

TCLK

TDI

TDO

TMS

TRST

PA7

VSSF

VDDF

INT2

VSS

VDD

INT3

INT4

INT5

VPP

INT6

INT7

MOSI

MISO

VSTBY

SCK

PE7

PE6

PE5

VDDH

PQB3

PQB2

PQB1

PQB0

PQA4

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Signal Description

Package P inou t Summary

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Signal Description 117

Table 4-2. Signal Descriptions (Sheet 1 of 3)

Name(1) Alternate Qty. Dir. Input

Hyst. Input

Sync.(2)

Drive

Strength

Control(3) Pullup(4) Output

Driver

(ST/OD/SP)(5)

Reset

RESET — 1 I/O(6) YY —Pullup —

RSTOUT SHOWINT 1I/O(6) — — LOAD —ST

Clock

EXTAL — 1 I N N — — SP

XTAL — 1 O — — — — SP

CLKOUT — 1 I/O(6) — — LOAD —ST

VDDSYN — 1 I — — — — —

VSSSYN — 1 I — — — — —

External Memory Interface an d Ports

D[31:0] PA[7:0], PB[7:0 ]

PC[7:0], PD[7:0] 32 I/O Y Y LOAD —ST

SHS RCON / PE7 1I/O Y Y LOAD Pullup ST

TA PE6 1I/O Y Y LOAD Pullup ST

TEA PE5 1I/O Y Y LOAD Pullup ST

CSE[1:0] PE[4:3] 2I/O Y Y LOAD Pullup ST

TC[2:0] PE[2:0] 3I/O Y Y LOAD Pullup ST

R/W PF7 1I/O Y Y LOAD Pullup ST

A[22:0] PF[6:0], PG[7:0 ]

PH[7:0] 23 I/O Y Y LOAD Pullup ST

EB[3:0] PI[7:4] 4I/O Y Y LOAD Pullup ST

CS[3:0] PI[3:0] 4I/O Y Y LOAD Pullup ST

OE — 1 I/O(6) — — LOAD —ST

Edge Port

INT[7:6] TSIZ[1:0] / GPIO 2I/O Y Y LOAD — —

INT[5:2] PSTA T[3:0] / GPIO 4I/O Y Y LOAD — —

INT[1:0] GPIO 2I/O Y Y LOAD — —

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Technical Data MMC2107 –Rev. 2.0
118 Signal Description MOTOROLA
Signal Descri ption
Serial Peripher al Interface (SPI)
MOSI GPIO 1I/O Y Y RDPSP0 Pullup(4) ST / OD(7)
MISO GPIO 1I/O Y Y RDPSP0 Pullup(4) ST / OD(7)
SCK GPIO 1I/O Y Y RDPSP0 Pullup(4) ST / OD (7)
SS GPIO 1I/O Y Y RDPSP0 Pullup(4) ST / OD(7)
Serial Communication Interface (SCI1 and SCI2)
TXD1 GPIO 1I/O Y Y RDPSCI0 Pullup(4) ST / OD(7)
RXD1 GPIO 1I/O Y Y RDPSCI0 Pullup(4) ST / OD (7)
TXD2 GPIO 1I/O Y Y RDPSCI0 Pullup(4) ST / OD(7)
RXD2 GPIO 1I/O Y Y RDPSCI0 Pullup(4) ST / OD (7)
Timer 1 and Timer 2
ICOC13 IC / OC / PAI / GPIO 1I/O Y Y RDPT Pullup(4) ST
ICOC1[2:0] IC / OC / GPIO 3I/O Y Y RDPT Pullup(4) ST
ICOC23 IC / OC / PAI / GPIO 1I/O Y Y RDPT Pullup(4) ST
ICOC2[2:0] IC / OC / GPIO 3I/O Y Y RDPT Pullup(4) ST
Queued Analog-to- Digital Converter (QADC)
PQA4–PQA3, 
PQA1–PQA0 GPIO 4I/O Y Y — — ST
PQB[3:0] GPI 4 I Y Y — — —
VRH — 1 I — — — — —
VRL — 1 I — — — — —
VDDA — 1 I — — — — —
VSSA — 1 I — — — — —
VDDH — 1 I — — — — —
Table 4-2. Signal Descriptions (Sheet 2 of 3)
Name(1) Alternate Qty. Dir. Input
Hyst. Input
Sync.(2)
Drive
Strength
Control(3) Pullup(4) Output
Driver
(ST/OD/SP)(5)
    
  
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Signal Description

Package P inou t Summary

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Signal Description 119

Debug and JTAG Test Port Control

TRST — 1 I Y N — Pullup —

TCLK — 1 I Y N — Pullup —

TMS — 1 I Y N — Pullup —

TDI — 1 I Y N — Pullup —

TDO — 1 O(8) — — LOAD —ST

DE — 1 I/O Y N LOAD Pullup OD

Test

TEST — 1 I Y N — — —

Pow er Sup plies

VPP — 1 I — — — — —

VDDF — 1 I — — — — —

VSSF — 1 I — — — — —

VSTBY — 1 I — — — — —

VDD — 5 I — — — — —

VSS — 5 I — — — — —

VDD — 3 I — — — — —

VSS — 3 I — — — — —

Total 100

Total with optional pins 144

1. Shaded signals are for optional bond-out for 144-pin package.

2. Synchronize d input used only if signal configured a s a digital I/O. RESET signal is always synchronized, except in low-

power stop mode.

3. LOAD (chip configuratio n register bit), R DPSP0 (SPIPURD register bit in SPI), RDPSCI0 (SCIPURD register bit in both

SC Is ), RDP T (T IMSCR 2 re g is te r bit in both ti m e rs )

4. All pullups are disconnected when t he signal is programmed as an output.

5. Output driver ty pe: ST = standar d, OD = standard driver with open-drain pulldown option sel ected, SP = special

6. Di gital i nput f uncti on for RST OUT, CLKOUT, OE, and digital output functi on for RESET used onl y for JTAG bo undary s can

7. Open-drain and pullup function selectable via pr ogrammer’s model in mo dule configuration registers

8. Three-state output with no input function

Table 4-2. Signal Descriptions (Sheet 3 of 3)

Name(1) Alternate Qty. Dir. Input

Hyst. Input

Sync.(2)

Drive

Strength

Control(3) Pullup(4) Output

Driver

(ST/OD/SP)(5)

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Technical Data MMC2107 –Rev. 2.0

120 Signal Description MOTOROLA

Signal Descri ption

4.4 MMC2107 Specific Implementation Signal Issues

Most modules are designed to allow expanded capabilities if all the

module signals to the pads are implemented. This subsection discusses

how these modules are implemented on the MMC2107.

4.4.1 RSTOUT Signal Func tions

The RSTOUT signal has these multiple functions:

•Whenever the internal system reset is asserted, the RSTOUT

signal will always be asserted to indicate the reset condition to the

system.

•If the internal reset is not asserted, then setting the FRCRSTOUT

bit in the reset control register will assert the RSTOUT signal for

as long as the FRCRSTOUT bit is set.

•If the intern al reset is not asserted a nd the FR CRST OUT bit i s not

set, then setting the SHOWINT bit in the chip configuration

signal.

•If the intern al reset is not asserted a nd the FR CRST OUT bit i s not

set and the SHOWINT bit is not set, then the RSTOUT signal will

be negated to indicate to the system that there is no reset

condition.

CAUTION: External logic used to drive reset configuration data during reset needs

to be considered when using the RSTOUT signal for a function other

than an indication of reset.

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Signal Description

Sig nal Descriptions

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Signal Description 121

4.4.2 INT Signal Functions

The INT signals have these multiple functions:

•If the SZEN bit in the chip configuration register is set, then

INT[7:6] will be used to reflect the state of the TSIZ[1:0] sig n als

from the M•CORE.

•If the PSTEN bit in the chip configuration register is set, then

INT[5:2] will be used to reflect the state of the PSTAT[3:0] signals

from the M•CORE.

NOTE: If the SZEN or PSTEN bits are set during emulation mode, then the

corresp onding edge por t INT functions are lost and will not be emulated

externally.

The d efault reset values for PUP SCI1 and PUPSCI0 will be 0. Thus, th e

pullup function is disabled by default.

4.5 Signal Descriptions

This subsection provides a brief description of the signals. For more

detailed information, reference the module section.

4.5.1 Reset Signals

These signals are used to either reset the chip or as a reset indication.

4.5.1.1 Reset In (RESET)

This active-low input signal is used as an external reset request.

4.5.1.2 Reset Out (RSTOUT)

This active-low output signal is an indication that the internal reset

controller has reset the chip. When RSTOUT is active, the user may

drive override options on the data bus. RSTOUT is three-stated in

phase-lock loop (P LL) test mode.

RSTOUT may also be used to reflect an indication of an internal interrupt

request.

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Technical Data MMC2107 –Rev. 2.0

122 Signal Description MOTOROLA

Signal Descri ption

4.5.2 Phase-Lock Loop (PLL) and Clock Signals

These sign als are used to support the on-chip clock generation circuitry.

4.5.2.1 External Clock In (EXTAL)

This input signal is always driven by an external clock input except when

used as a connection to the exter nal crystal when the inter nal oscillator

circuit is used. The clock source is configured during reset.

4.5.2.2 Crystal (XTAL)

This outpu t signal is used as a connection to the external crystal when

the internal oscillator circuit is used. XTAL should be grounded when

using an external clock input.

4.5.2.3 Clock Out (CLKOUT)

This output signal reflects the internal system clock.

4.5.2.4 Synthesizer Power (VDDSYN and VSSSYN)

These are dedicated quiet power and ground supply signals for the

frequency synthesizer circuit.

4.5.3 External Memory Interface Signals

In addition to the function stated here, these signals can be configured

as discrete I/O signals also.

4.5.3.1 Data Bus (D[31:0])

These three-state bidirectional signals provide the general-purpose data

path between the microcontroller unit (MCU) and all other devices.

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Sig nal Descriptions

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Signal Description 123

4.5.3.2 Show Cycle Strobe (SHS)

This output signal is used in emulation mode as a strobe for capturing

addresses, controls, and data during show cycles. This signal is also

used as RCON.

NOTE: This input signal, used only during reset, indicates whether the states on

the external signals affect the chip configuration.

4.5.3.3 Transfer Acknowledge (TA)

This signal indicates that the external data transfer is complete. During

a read cycle, when t he processor recognize s TA, it lat ches the data and

then t ermin ates the bus cycle. Dur ing a write cycle, when the pr ocessor

recognizes TA, the bus cycle is ter minated. This signal is an input in

master and emulation modes.

4.5.3.4 Transfer Error A cknowledge (TEA)

This signal indicates an error condition exists for the bus transfer. The

bus cycle is terminated and the central processor unit (CPU) begins

execution of the access error exception. This signal is an input in ma ster

and emulation modes.

4.5.3.5 Emulation Mode Chip Selects (CSE[1:0])

These output signals provide information for development support.

4.5.3.6 Transfer Code (TC[2:0])

These outp ut signal s indicate the dat a transfe r code for the current bus

cycle.

4.5.3.7 Read/Write (R/W)

This output signal indi cates the direct io n of the data tran sfer on the bus.

A logic 1 indicates a read from a slave device and a logic 0 indicates a

write to a slave device.

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Technical Data MMC2107 –Rev. 2.0

124 Signal Description MOTOROLA

Signal Descri ption

4.5.3.8 Address Bus (A[22:0])

These output signals provide the address for the current bus transfer.

4.5.3.9 Enable Byte (EB[3:0])

These outpu t signals indicate w hich byt e of data is valid during exter nal

cycles.

4.5.3.10 Chip Select (CS[3:0])

These output signals select external devices for external bus

transactions.

4.5.3.11 Output Enable (OE)

This outpu t signal indicates when an external device can drive data

during external read cycles.

4.5.4 Edge Port Signals

These signals are used by the edge port module.

4.5.4.1 External Interrupts (INT[7:6])

These bidirectional signals function as either external interrupt sources

or GPIO. Also, these signals may be used to reflect the internal TSIZ[1:0]

signals and externally to provide an indication of the M•CORE transfer

size.

4.5.4.2 External Interrupts (INT[5:2])

These bidirectional signals function as either external interrupt sources

or GPIO. Also, these signals may be used to reflect the internal

PSTAT[3:0] signals and externally to provide an indication of the

M•CORE processor status.

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MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Signal Description 125

4.5.4.3 External Interrupts (INT[1:0])

These bidirectional signals function as either external interrupt sources

or GPIO.

4.5.5 Serial Peripheral Interface Module Signals

These signals are used by the SPI module and may also be configured

to be discrete I/O signals.

4.5.5.1 Master Out/Slave In (MOSI)

This signal is the serial data output from the SPI in master mode and the

serial data input i n slave mode.

4.5.5.2 Master In/Slave Out (MISO)

This signal is the serial data input to the SPI in master mode and the

serial data output in slave mode.

4.5.5.3 Serial Clock (SCK)

The serial clock synchronizes data transmissions between master and

slave devices. SCK is an output if the S PI is co nfigured as a m aster and

SCK is an input if the SPI is configured as a slave.

4.5.5.4 Slave Select (SS)

This I/O sign al is the periph eral chip select sign al in master m ode and is

an active-low slave select in slave mode.

4.5.6 Serial Communications Interface Module Signals

These signals are used by the two SCI modules.

4.5.6.1 Receive Data (RXD1 and RXD2)

These signals are used for the SCI receiver data input and are also

available for GPIO when not configured for receiver operation.

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Technical Data MMC2107 –Rev. 2.0

126 Signal Description MOTOROLA

Signal Descri ption

4.5.6.2 Transmit Data (TXD1 and TXD2)

These signals are used for the SCI transmitter data output and ar e also

available for GPIO when not configured for transmitter operation.

4.5.7 Timer Signals (ICOC1[3:0] and ICOC2[3:0])

These sig nals provi de the exter nal interface to the timer functions. T hey

may be configu red as ge nera l-pur pose I/O if t he tim er o utput functio n is

not needed. The default state at reset is general-purpose input.

4.5.8 Analog-to-Digital Converter Signals

These signals are used by the analog-to-digital converter (QADC)

module.

4.5.8.1 Analog Inputs (PQA[4:3], PQA[1:0], and PQB[3:0])

These signa ls provide the analog i nputs to the QADC. T he PQA signa ls

may also be used as general -pu rpose digital I/O. The PQB signa ls may

also be used as general-purpose digital inputs.

4.5.8.2 Analog Reference (VRH and VRL)

These signals serve as the high (VRH) and low (VRL) reference potentials

for the analog converter.

4.5.8.3 Analog Supply (VDDA and VSSA)

These dedicated power supply signals isolate the sensitive analog

circuitry from the normal levels of noise present on the digital power

supply.

4.5.8.4 Positive Supply (VDDH)

This signal supplies positive power to the ESD structures in the QADC

pads.

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Signal Description

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MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Signal Description 127

4.5.9 Debug and Emulation Support Signals

These signal s are used as the interface to the on-chi p JTAG (Joint Test

Action Gr oup) controller and also to interface to the OnCE logic.

4. 5.9.1 Test Reset (TRS T)

This a ctive-low input signal is used to initialize the JTAG and OnCE logic

asynchronously.

4. 5.9.2 Test Clock (TCLK)

This input signal is the test clock used to synchronize the JTAG and

OnCE logic.

4.5.9.3 Test Mode Select (TMS)

This input signal is used to sequence the JTAG state machine. TMS is

sampled on the rising edge of TCLK.

4.5.9.4 Test Data Input (TDI)

This input signal is the serial input for test instructions and data. TDI is

sampled on the rising edge of TCLK.

4.5.9.5 Test Data Output (TDO)

This output signal is the seria l output for te st instru ctions and data . TDO

is three-stateable and is actively driven in the shift-IR and shift-DR

controller states. TDO changes on the falling edge of TCLK.

4. 5.9.6 Debug Event (DE)

This is a bidire ctional, act ive-low signa l. As an output , this signal will be

asserted for three system clocks, synchronous to the rising CLKOUT

edge, to acknowledge that the CPU has entered debug mode as a result

of a debug request or a breakpoint condition. As an input, this signal

provides multiple functions.

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Technical Data MMC2107 –Rev. 2.0

128 Signal Description MOTOROLA

Signal Descri ption

4.5.10 Test Signal (TEST)

This input signal (TEST) is reserved for factory testing only and should

be con nected to V SS to prevent u nintentional activati on of test fun ctions.

4.5.11 Power and Ground Signals

These signals provide system power and ground to the chip. Multiple

signals are provided for adequate current capability. All power supply

signals must have adequate bypass capacitance for high-frequency

noise suppression.

4.5.11.1 Power for FLASH Erase/Program (VPP)

This signal supplies an isolated power for FLASH program and erase

operations.

4.5.11.2 Power and Ground for FLASH Array (VDDF and VSSF)

These sign als supply an isol ated power and ground to the FLASH arr ay.

4.5.11.3 Standby Power (VSTBY)

This signal is used to provide standby volta ge to the RAM array i f VDD is

lost.

4.5.11.4 Positive Supply (VDD)

This signal supplies positive power to the core logic and I/O pads.

4.5.11.5 Ground (VSS)

This signal is the negative supply (ground) to the chip.

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MMC21 07 –Rev. 2.0  Technical Data
MOTOROLA Re set Controller Module  129
Technical Data — MMC2107
Section 5.   Reset Controller Module
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
4 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
5 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
6 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .132
6.1 Reset Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .133
6.2 Reset Status Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
6.3 Reset Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
7.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
7.1.1 Power-On Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
7.1.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
7.1.3 Watchdog Timer Reset  . . . . . . . . . . . . . . . . . . . . . . . . .137
7.1.4 Loss of Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .137
7.1.5 Loss of Lock Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
7.1.6 Software Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
7.2 Reset Control Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
7.2.1 Synchronous Reset Requests . . . . . . . . . . . . . . . . . . . .138
7.2.2 Internal Reset Request . . . . . . . . . . . . . . . . . . . . . . . . .140
7.2.3 Power-On Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
7.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
7.3.1 Reset F low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
7.3.2 Reset Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
    
  
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Technical Data MMC2107 –Rev. 2.0

130 Rese t Controller Module MOTOR OLA

Reset Controller Module

5.2 Introduction

The reset controller is provided to:

•Determine the cause of reset

•Assert the appropriate reset signals to the system

•Keep a history of what caused the reset

5.3 Featur es

Features of the reset controller module include:

•Six sources of reset:

–External

–Power- on re set (P OR )

–Watchdog timer

–Phase-lock loop (PLL) loss of lock

–PLL loss of clock

–Software

•Software can assert external RSTOUT pin independent of chip

reset state.

•Software readable status flags indicating the cause of the last

reset

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Reset Controller Module

Block Diagram

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Re set Controller Module 131

5.4 Block Diagram

Figure 5-1 shows the structure of the reset controller.

Figure 5-1. Reset Controller Block Diagram

5.5 Signals

See Table 5-1 for an overview of the reset controller signal properties.

For additional information, refer to Section 4. Signal Description.

POWER-ON

RESET

WATCHDOG

TIMER TIMEOUT

PLL

LOSS OF LOCK

PLL

LOSS OF CLOCK

RESET

CONTROLLER

RESET

RSTOUT

TO INTERNAL RESETS

SOFTWARE

RESET

Table 5- 1. Reset Controller Signal Properties

Name Alternate Direction Input

Hysteresis Input

Synchronization Pullup(1)

1. Pullups are disconnected from pins configured as outputs.

RESET pin —IY Y(2)

2. RESET is al ways synchroni zed except when in lo w-power stop mode.

RSTOUT pin SHOW INT O———

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Technical Data MMC2107 –Rev. 2.0

132 Rese t Controller Module MOTOR OLA

Reset Controller Module

5.6 Memory Map and Registers

The reset controller programming model consists of the following

registers:

•Reset control register (RCR) — Selects interrupt controlle r

functions

•Reset status register (RSR) — Refl ects the state of the last reset

source

•Reset test register (RTR) — Used only for factory test

Table 5-2. Reset Controller Module Memory Map

Address Bits 7–0 Access(1)

1. S/U = CPU superv isor or us er mode access. User mode acc esses to supervi sor only

ad dresses have no effect and result in a a cycle te rm ination tran sfer error.

0x000c4_0000 Reset control register (RCR) S/U

0x000c4_0001 Reset status register (RSR) S/U

0x000c4_0002 Reset test register (RTR) S/U

0x000c4_0003 Reserved(2)

2. Within the specified module memory map, accessing r eserved addresses does not

generate a bus error exception. Reads of reserved addres ses return 0s and writ es have

no effect.

—

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Reset Controller Module

Mem ory Map and Registers

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Re set Controller Module 133

5.6.1 Reset Control Register

The reset control register (RCR) allows software control for requesting a

reset or for independently asserting the external RSTOUT pin. RCR is

read/write always.

SOFTRST — Software Reset Request Bit

The SOFTRST bit allows software to request a reset. Note that the

reset caused by setting this bit clears this bit.

1 = Request software reset

0 = No software reset request

FRCRSTOUT — Force RSTO UT Pin Bit

The FRCRSTOUT bit allows software to assert or negate the external

RSTOUT pin.

1 = Assert the RSTOUT pin.

0 = Do not assert the RSTOUT pin.

CAUTION: External logic driving reset configuration data during reset needs to be

considered when asserting the RSTOUT pin when setting

FRCRSTOUT.

Address: 0x000c4_0000

Bit 7654321Bit 0

Read: SOFTRST FRC-

RSTOUT 000000

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 5-2. Reset Control Register (RCR)

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Technical Data MMC2107 –Rev. 2.0

134 Rese t Controller Module MOTOR OLA

Reset Controller Module

5.6.2 Reset Status Register

The reset status register (RSR) contains a status bit for every reset

source. When reset is entered, the cause of the reset condition is latched

alo ng with a valu e of 0 for the o ther reset sou rces that were not pending

at the tim e of th e re set cond iti on. These va l ues ar e the n ref lected i n the

RSR. One or more status bits may be set at the same time. The cause

of any subsequent reset is also recorded in the register, overwriting

status from the previous reset condition.

RSR can be read at any time. Writing to RSR has no effect.

SOFT— Software Reset Flag

SOFT indicates that the last reset was caused by software.

1 = Last reset caused by software

0 = No software reset

WDR — Watchdog Timer Reset Flag

WDR indicates that the last reset was caused by a watchdog timer

timeout.

1 = Last reset caused by watchdog timer timeout

0 = No watchdog timer timeout reset

POR — Power-On Reset Flag

POR indicates that the last reset was caused by a power-on reset.

1 = Last reset caused by power-on reset

0 = Last reset not caused by power-on reset

Address: 0x000c4_0001

Bit 7654321Bit 0

Read: 0 0 SOFT WDR POR EXT LOC LOL

Write:

Reset: 0 0 Reset dependent

= Writes have no effect and the access terminates without a transfer error exception.

Figure 5-3. Reset Status Register (RSR)

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Reset Controller Module

Mem ory Map and Registers

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Re set Controller Module 135

EXT — External Reset Flag

EXT indicates that the last reset was caused by an external device

asserting the external R ESET pin.

1 = Last reset state caused by external device asserting the

external RESET pin

0 = No external reset

LOC — Loss of Clock Reset Flag

LOC indicates that the last reset state was caused by a loss of clock

detected by the loss of clock circuit.

1 = Last reset caused by loss of clock

0 = No loss of clock reset

LOL — Loss of Lock Reset Flag

LOL indicates that the last reset state was caused by a loss of lock

detected by the PLL circuit.

1 = Last r eset caused by loss of lock

0 = No loss of lock

5.6.3 Reset Test Register

The reset test regi ster (RTR) is used only for factory testing.

This register is read-only when not in test mode.

Address: 0x000c4_0002

Bit 7654321Bit 0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 5-4. Reset Test Register (RTR)

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Technical Data MMC2107 –Rev. 2.0

136 Rese t Controller Module MOTOR OLA

Reset Controller Module

5.7 Functional D escription

This subsection provides a function al description of the MM C2107 reset

controller module.

5.7.1 Reset Sources

Table 5-3 defines the sources of reset and the signals driven by the reset

controller.

To protect data integrity, a synchronous reset source is not acted upon

by the reset control logic until the end of the current bus cycle. Reset is

then asser ted on the next r ising edge of the system clock after the cycle

is terminated. Whenever the reset control logic must synchronize reset

to the end of the bus cycle, the internal bus monitor is automatically

enabled regardless of the BME bit setting in the chip configuration

the bus monitor terminates the cycle based on the length of time

programmed in the BMT field of CCR.

Internal single-byte, half-word, or word writes are guaranteed to

complete without data corruption when a synchronous reset occurs.

External writes, including word writes to 16-bit ports, are also

guaran teed to compl ete.

Asynchronous reset sources usually indicate a catastrophic failure.

There fore , the reset contr ol logic do es not wait for the curr ent bu s cycle

to complete. Reset is asserted immediately to the system.

Table 5-3. Reset Source Summary

Source Type

Power on Asynchronous

External RESET pin (not stop mode) Synchronous

External RESET pin (during stop mode) Asynchron ous

Watchdog timer Synchronous

Loss of clock Asynchronous

Loss of lock Asyn ch ronous

Software Synchronous

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Reset Controller Module

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Re set Controller Module 137

5.7.1.1 Power-On Reset

At power -up, the reset cont roll er asse rts RSTOU T. RSTOUT continues

to be asserted until VDD has reached a minimum acceptable level and,

if a PLL clock mode is selected, until the PLL achieves phase lock. Then

after approximately another 512 cycles, RSTOUT is negated and the

part begins operation.

5.7.1.2 External Reset

Asserting the external RESET pin for at least four rising CLKOUT edges

causes the external reset request to be recognized and latched. The bus

monitor is enabled and the current bus cycle is completed. The reset

controller asserts RS TOUT for approximately 512 cycles after the

RESET pin is negated and the PLL has acquired lock. The part then exits

reset and begins operation.

In low-power stop mode, the system clocks are stopped. Asserting the

external RESET pin during stop mode causes an external reset to be

recognized.

5.7.1.3 Watchdog Timer Reset

A watchdog timer timeout causes the watchdog timer reset request to be

recognized and latched. The bus monitor is enabled and the current bus

cycle is completed. If the RESET pin is negated and the PLL has

acquired lock, the reset controller asserts RSTOUT for approximately

512 cycles. Then the part exits reset and begins operation.

5.7.1.4 Loss of Clock Reset

This reset condition occurs in PLL clock mode when the LOCRE bit in

SYNCR is set and either the PLL reference or the PLL fails. The reset

controller asserts RS TOUT for approximately 512 cycles after the PLL

has acquired lock. The part then exits reset and begins operation.

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Technical Data MMC2107 –Rev. 2.0

138 Rese t Controller Module MOTOR OLA

Reset Controller Module

5.7.1.5 Loss of Lock Reset

This reset condition occurs in PLL clock mode when the LOLRE bit in

SYNCR is set and the PLL loses lock. The reset controller asserts

RSTOUT for approximately 512 cycles after th e PLL has acqu ired lock.

The part then exits reset and begins operation.

5. 7.1.6 Softw are Reset

A software reset occurs when the SOFT RST bit is set. If the RESET pin

is negated and the PLL has acquired lock, the reset controller asserts

RSTOUT for approximately 512 cycles. Then the part exits reset and

begins operation.

5.7.2 Reset Control Flow

Figure 5-5 shows the reset logic control flow. In the flow description that

follows, there are references in parentheses to the control state box

numbers in the figure. All cycle counts given are approximate.

5.7.2.1 Synchronous Reset Requests

If eit her th e exter nal RESE T pin is asse rted b y an external device fo r at

lea st fou r r ising CLK OUT edg es ( 3), or the watchdog time r tim es ou t, or

software requests a reset, the reset control logic latches the reset

request internally and enables the bus monitor (5). When the current bus

cycle is completed (6), RSTOUT is asserted (7). The reset control logic

waits until the RESET pin is negated (8) and for the PLL to attain lock

(9, 9A) before waiting 512 CLKOUT cycles (10) . The reset control logic

may latch the configuration according to the RCON pin level (11, 11A)

before negating RSTOUT (12).

If the external RESET pin is asserted by an external device for at least

four rising CLKOUT edges during the 512 count (10) or during the wait

for P LL lock (9 A), the re set flow swit ches to (8 ) and waits for the RES ET

pin to be negated before continuing.

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Reset Controller Module

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Re set Controller Module 139

Fi gure 5-5. Re set Cont ro l Flow

ASSERT RSTOUT AND

LATCH RESET STATUS

RESET

PIN OR WD TIMEOUT

OR SW RESET?

LOSS OF CLOCK?

LOSS OF LOCK?

BUS CYCLE

ENABLE BUS MONITOR

COMPLETE?

RESET NEGATED?

PLL MODE?

WAIT 512 CLKOUT CYCLES

RCON ASSERTED? LATCH CONFIGURA TION

PLL LOCKED?

POR

ASSERT RSTOUT AND

LATCH R ESET STATUS

NEGATE RSTOUT

12 11

11A

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Technical Data MMC2107 –Rev. 2.0

140 Rese t Controller Module MOTOR OLA

Reset Controller Module

5.7.2.2 Internal Reset Request

If reset i s asserted by an asynchronous internal reset source, such as

loss of clock (1) or loss of lock (2), the reset control logic asserts

RSTOUT (4). The reset control logic waits for the PLL to attain lock

(9, 9A) before waiting 512 CLKOUT cycles (10). Then the reset control

logic may latch the configuration according to the RCON pin level (11,

11A) before negating RSTOUT (12).

If a l oss of lo ck occurs dur ing the 5 12 count ( 10), the reset flow sw itches

to (9A) and waits for the PLL to lock before continuing.

5.7.2.3 Power-On Reset

When the reset sequence is initiated by power-on reset (0), the same

reset sequ ence is followed as for the other asynchr onous reset sources.

5.7.3 Concurrent Resets

This subsection describes the concurrent resets.

5.7.3.1 Reset Flow

If a pow er-o n reset cond ition is d etected dur in g any rese t sequence, t he

power-on reset sequence starts immediately (0).

If the external RESET pin is asserted for at least four rising CLKOUT

edges while waiting for PLL lock or the 512 cycles, the exter nal reset is

recognized. Reset processing switches to wait for the external RESET

pin to negate (8).

If a l oss of clock or loss of lock condition is detected while wa iting fo r the

current bus cycle to complete (5, 6) for an external reset request, the

cycle is terminated. T h e reset status bits are latched (7) and reset

processing waits for the external RESET pin to negate (8).

If a loss of clock or loss of lock condition is detected during the 512-cycle

wait, the reset sequence continues after a PLL lock (9, 9A).

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Reset Controller Module

Interrupts

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Re set Controller Module 141

5.7.3.2 Reset Status Flags

For a power-on reset, the POR bit in RSR is set, and the SOFT, WDR,

EXT, LOC, and LOL bits are cleared even if another type of reset

condition is detected during the reset sequence for the POR.

If a l oss of clock or loss of lock condition is detected while wa iting fo r the

current bus cycle to complete (5, 6) for an external reset request, the

EXT bit along with the LOC and/or LOL bits are set.

5.8 Interrupts

The reset controller does not generate interrupt requests.

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Technical Data MMC2107 –Rev. 2.0

142 Rese t Controller Module MOTOR OLA

Reset Controller Module

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MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA M•CORE M210 Central Processo r Unit (CPU) 143

Technical Data — MMC2107

Section 6. M•CORE M210 Central Processor Unit (CPU)

6.1 Contents

6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

6.4 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . .145

6.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

6.6 Data F o rmat Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

6.7 Operand Addressing Capabilities. . . . . . . . . . . . . . . . . . . . . .150

6.8 Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

6.2 Introduction

The M•CORE M210 central processor unit (CPU) architecture is one of

the most compact, full 32-bit core implementations available. The

pipelined reduced instruction set computer (RISC) execution unit uses

16-bit instructions to achieve maximum speed and code efficiency, while

conserving on-chip memory resources. The instruction set is designed

to suppor t high-le vel language i mplementat ion. A non-i ntrusive re sident

debugging system supports product development and in-situ testing.

The M•CORE technology library also encompasses a full complement of

on-chip peripheral modules designed specifically for embedded control

applications.

Total system power consumption is determined by all the system

components, rather than the processor core alone. In particular, memory

power consumption (both on-chip and external) is a dominant factor in

total power consumption of the core plus memory subsystem. With this

in mind, the M•CORE instruction set architecture trades absolute

performance capability for reduced total energy consumption. This is

accomplished while maintaining an acceptably high level of performance

at a given clock frequency.

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Technical Data MMC2107 –Rev. 2.0

144 M•CORE M210 Central Processo r Unit (CPU) MO TOR OLA

M•CORE M210 Central Processor Unit (CPU)

The stream lined execut ion engi ne uses many of the same perfor mance

enhance ments a nd i mplem enta tion techn iques i ncor porated i n de sktop

RISC processors. A strictly defined load/store architecture minimizes

control complexity. Use of a fixed, 16-bit instruction encoding

significantly lowers the memory bandwidth needed to sustain a high ra te

of instruction execution, and careful selection of the instruction set

allows the code density and overall memory efficiency of the M•CORE

architecture to surpass those of complex instruction set computer

(CISC) architectures.

These factor s re duce system ener gy con sumption sign ifica ntly, a nd th e

fully static M •CORE design uses other techniques to reduce it even

more. The core uses dynamic clock management to automatically

power-down internal functions that are not in use on a clock-by-clock

basis. It also incorporates three power-conservation operating modes,

which are invoked via dedicated instructions.

6.3 Featur es

The main features of the M•CORE are:

•32-bit load/store RISC architecture

•Fixed 16-bit instruction length

•16 entry, 32-bit general-purpose register file

•Efficient 4-stage execution pipeline, hidden from application

software

•Single-cycle execution for most instructions, 2-cycle branches and

memory accesses

•Support for byte/half-word/word memory access

•Fast interrupt support, with 16 entry user-controlled alternate

•Vectored and autovectored interrupt support

•On-chip emulation support

•Full static design for minimal power consumption

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M•CO RE M210 Central Processor Unit (CPU)

Microarchitecture Summary

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA M•CORE M210 Central Processo r Unit (CPU) 145

6.4 Microarchitecture Summary

Figure 6-1 is a block di agram of the M•CORE processor.

The processor utilizes a 4-stage pipeline for instruction execution. The

instruction fetch, instruction decode/register file read, execute, and

regi ster file writeb ack stages oper ate in an over lapped fashi on, allow ing

single clock instruction execution for most instructions.

The execution unit consists of a 32-bit arithmetic/logic un it, a 32-bit

barrel shifter, a find-first-one unit, result feed-forward hardware, and

miscellaneous support hardware for multiplication, division, and

multiple-register loads and stores.

Figure 6-1. M•CORE Processor Block Diagram

SCALE

ADDRESS GENERATION

ADDRESS MUX

GENERAL-PURPOSE

32 BITS X 16

ALTERNATE

32 BITS X 16

CONTROL

RE G ISTER FIL E

32 BITS X 13

IMMEDIATE

MUX

SIGN EXT.

MUX

BARREL SHIFTER

MULTIPLIER

DIVIDER

ADDER/LOGICAL PRIORITY ENCODER/

ZERO DETECT RESULT MUX

DAT A CAL CUL AT ION

INCREMENT BRANCH

ADDER

INSTR UCT IO N PIPELI N E

INSTRUCTION DECODE

ADDRESS

BUS

DATA

X PORT Y PORT

MUX

WRITEBACK BUS

H/W ACCELERATOR INTERFACE BUS BUS

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Technical Data MMC2107 –Rev. 2.0

146 M•CORE M210 Central Processo r Unit (CPU) MO TOR OLA

M•CORE M210 Central Processor Unit (CPU)

Arithmetic and logical operations are executed in a single cycle.

Multiplication is implemented with a 2-bit per clock, overlapped-scan,

modified Booth algorithm with early-out capability, to reduce execution

time for operations with small multipliers. Divide is implemented with a

1-bit per clock early-in algorithm. The find-first-one unit operates in a

single clock cycle.

The program counter unit incorporates a dedicated branch address

adder to minimize delays during change of flow operations. Branch

target addresses are calculated in parallel with branch instruction

decode. Taken branches and jumps require only two clocks; branches

which are not taken execute in a single clock.

Memory load and store operations are provided for 8-bit (byte), 16-bit

(half-word), and 32-bit (word) data, with automatic zero extension for

byte and half-word load operations. These instructions can execute in as

few as two clock cycles. Load and store multiple register instructions

allow low overhead context save and restore operations. These

instructions can execute in (N+1) clock cycles, where N is the number of

registers to transfer.

A condition code/carry (C) bit is provided for condition testing and for use

in imp lemen ti ng arith metic and log ical opera ti ons with oper ands/ resul ts

greate r than 32 bits. The C bit is typi cally set by explicit test /compa rison

operations, not as a side-effect of normal instruction operation.

Exceptions to this rule occur for specialized operations where it is

desirable to combine condition setting with actual computation.

The processor uses autovectors for both normal and fast interrupt

requests. Fast interrupts take precedence over normal interrupts. Both

types ha ve de di cated exceptio n sha dow r egi sters. F or se rvic e requests

of either kind, an automatic vector is generated when the request is

made.

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M•CO RE M210 Central Processor Unit (CPU)

Programming Model

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA M•CORE M210 Central Processo r Unit (CPU) 147

6.5 Programming Model

Figure 6-2 shows the M•CORE programming model. The model is

defined differently for supervisor and user privilege modes. By

conv ention, in both mod es R15 ser ves as the link r egister for sub routine

calls. R0 is typically used as stack pointer.

Figure 6-2. Programming Model

The user programming model consists of 16 general-purpose 32-bit

registers (R[15:0]), the 32-bit PC, and the C bit. The C bit is implemented

as bit 0 of the pr ocessor status regi ste r (PSR) and is the only portion of

the PSR accessible in the user model.

R0’

R12

R13

R14

R15

R11

R10

US ER PROGRAMMER’S

MODEL

ALTER NATE FILE

SUPER VISOR PROGRAMM E R’S

MODEL

PC PC

C* BIT 0 OF PSR

PSR

VBR

EPSR

FPSR

EPC

FPC

SS0

SS1

SS2

CR0

CR1

CR2

CR3

CR4

CR5

CR6

CR7

CR8

CR9

SS4 CR10

GCR CR11

SS3

GSR CR12

R15

R12

R13

R14

R11

R10

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Technical Data MMC2107 –Rev. 2.0

148 M•CORE M210 Central Processo r Unit (CPU) MO TOR OLA

M•CORE M210 Central Processor Unit (CPU)

The supervisor programming model consists of the user model plus 16

additional 32-bit general-purpose registers (R[15:0]’, or the alternate

file), the entire PSR, and a set of status/control registers (CR[12:0]).

Setting the S bit i n the PSR enables supervisor mode operation.

The alternate file allows very low overhead context switching for

real-time event handling. While the alternate file is enabled,

general-purpose operands are accessed from it.

The vector base register (VBR) determines the base address of the

excepti on vector ta ble. E xcep tion s hadow reg isters EPC a nd E P SR are

used to save the states of the program counter and PSR, respectively,

when an exception occurs. Shadow registers FPC and FPSR save the

states of the program counter and PSR, respectively, when an exception

occurs.

Scratch registers (SS[4:0]) are used to handle exception events.

The global control (GCR) and status (GSR) registers can be used for a

variety of system monitoring tasks.

The supervisor programming model includes the PSR, which contains

operation control and status information. In addition, a set of exception

shadow registers is provided to save the state of the PSR and the

program counter at the time an exception occurs. A separate set of

shadow registers is provided for fast interrupt support to minimize

context saving overhead.

Five scratch registers are provided for supervisor software use in

handling exception events. A single register is provided to alter the base

address of the exception vector table. Two registers are provided for

global control and status.

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M•CO RE M210 Central Processor Unit (CPU)

Data Format Summary

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA M•CORE M210 Central Processo r Unit (CPU) 149

6.6 Data Format S ummary

The operand data formats supported by the integer unit are standard

two’s-complement dat a formats. The operand size for each instruction is

either explicitly encoded in the instruction (load/store instructions) or

implicitly defined by the instruction operation (index operations, byte

extr action). Typically, instructions operate on all 32 bits of the source

operand(s) and generate a 32-bit result.

Memory is viewed from a big-endian byte ordering perspective. The

most sign ificant byte (byte 0) of word 0 is located at address 0. Bits are

numbered within a word starting with bit 31 as the most significant bit.

Figur e 6-3. Data Organization in Memo ry

Figure 6-4. Data Or ganization in Registers

BYTE 0 BYTE 1 BYTE 2 BYTE 3 WORD AT 0X00 00 000 0

31 0

BYTE 4 BYTE 5 BYTE 6 BYTE 7 WORD AT 0X0000 000 4

BYTE 8 BYTE 9 BYTE A BYTE B WORD AT 0X0000 000 8

BYTE C BYTE D BYTE E BYTE F WORD AT 0X00 00 000 C

BYTE SIGNED BYTE

S S S S SS SSSSSSSSSSSSSSS S S S

8 7

BYTE UNS IGNED B Y TE

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

8 7

HALF-WORD SIGNED

S S S S S S S S S S S S S S S S

016 1531

HALF-WORD

HALF-WORD UNSIGNED

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

016 1531

HALF-WORD

WORD

BYTE 3 BYTE 2 BYTE 1 BYTE 0

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Technical Data MMC2107 –Rev. 2.0

150 M•CORE M210 Central Processo r Unit (CPU) MO TOR OLA

M•CORE M210 Central Processor Unit (CPU)

6.7 Operand Addressing Capabilities

M•CORE accesses all memory operands through load and store

instructions, transferring data between the general-purpose registers

and memory. Register-plus-four-bit scaled displacement addressing

mode i s used for load a nd store instruct ions addressi ng byte, half-wo rd,

and word data.

Load and store multiple instructions allow a subset of the 16

general-purpose registers to be transferred to or from a base address

pointed to by register R0 (the default stack pointer by convention).

Load and store register quadrant instructions use register indirect

addressing to transfer a register quadrant to or from memory.

6.8 Instruction Set Overview

The instruction set is tailored to support high-level languages and is

optimized for those instructions most commonly executed. A standard

set of arithmetic and logical instructions is provided, as well as

instruction support for bit operations, byte extraction, data movement,

control flow modification, and a small set of conditionally executed

instructions which can be useful in eliminating short conditional

branches.

Table 6-1 is an alphabetized listing of the M•CORE instruction set. Refer

to the M•CORE Reference Manual (Motorol a document order number

MCORERM/AD) for more details on instruction operation.

Table 6-1. M•CORE Instruction Set (Sheet 1 of 3)

Mnemonic Description

ABS

ADDC

ADDI

ADDU

AND

ANDI

ANDN

ASR

ASRC

Ab s olu t e Value

Add with C B it

Add Imm ediate

Add Unsigned

Logical AND

Logical AND Immedi ate

AND NOT

Ar it hmetic S h if t Rig ht

Arithmetic Shift Right, Update C Bit

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M•CO RE M210 Central Processor Unit (CPU)

In stru ction Set Overview

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA M•CORE M210 Central Processo r Unit (CPU) 151

BCLRI

BGENI

BGENR

BKPT

BMASKI

BREV

BSETI

BSR

BTSTI

Bit Clear Immediate

Branch on C ondition False

Bit Generate Immediate

Bit Generate Register

Breakpoint

Bit Mask Imm e dia te

Branch

Bit Re ve r se

Bit Se t Imm e di a te

Branch to Subroutine

Branch on C ondition True

Bit Test Immediate

CLRF

CLRT

CMPHS

CMPLT

CMPLTI

CMPNE

CMPNEI

Clear Register on Condition False

Clear Register on Condition True

Compare High er or Same

Compare Less Than

Compare Less Than Immedia te

Compare Not Equa l

Compare Not Equal Immediate

DECF

DECGT

DECLT

DECNE

DECT

DIVS

DIVU

DOZE

Decrement on Condition False

Decrement Register and Set Condition if Result Greater T han Zero

Decrement Register and Set Condition if Result Less Than Zero

Decrement Register and Set Condition if Result Not E qual to Zero

Decrement on Condition True

Divide Signed Integer

Divide Unsigned Integer

Doze

FF1 F ind First One

INCF

INCT

IXH

IXW

Incremen t on Condition False

Incremen t on Condition True

Index Half-Word

Index Word

JMP

JMPI

JSR

JSRI

Jump

Jump Indirect

Jump to Subroutine

Jump to Subroutine Indirect

LD.[BHW]

LDM

LDQ

LOOPT

LRW

LSL, LSR

LSLC, LS RC

LSLI, LSRI

Load

Load Multiple Registers

Load Register Quadrant

Decrement with C-Bit Update and Branch if Condition True

Load Relative Word

Logical Shift Left and Right

Logical Shift Left and Right, Update C Bit

Logical Shift Left and Right by Im m edia te

Table 6-1. M•CORE Instruction Set (Sheet 2 of 3)

Mnemonic Description

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Technical Data MMC2107 –Rev. 2.0

152 M•CORE M210 Central Processo r Unit (CPU) MO TOR OLA

M•CORE M210 Central Processor Unit (CPU)

MFCR

MOV

MOVI

MOVF

MOVT

MTCR

MULT

MVC

MVCV

Move from Control Register

Move

Move Immediate

Move on Condition False

Move on Condition True

Move to Control Register

Multiply

Move C Bit to Regi ster

Move Inverted C Bit to Register

NOT Logical Complement

OR Logical Inclu sive-OR

ROTLI

RSUB

RSUBI

RTE

RFI

Rotate Lef t by Immediate

Reverse Subtract

Reverse Subtract Immed iate

Return from Exception

Return from Interrupt

SEXTB

SEXTH

ST.[BHW]

STM

STQ

STOP

SUBC

SUBU

SUBI

SYNC

Sign-Extend Byte

Sign-Extend Half-Word

Store

Store Multiple Registers

Stor e Register Quadrant

Stop

Subtract with C B it

Subtract

Subtrac t Immediate

Synchronize

TRAP

TST

TSTNBZ

Trap

Test Operan ds

Test for No Byte Equ al Zero

WAIT Wait

XOR

XSR

XTRB0

XTRB1

XTRB2

XTRB3

Exclus ive OR

Extended Sh ift Right

Extract Byte 0

Extract Byte 1

Extract Byte 2

Extract Byte 3

ZEXTB

ZEXTH Zero-Extend B yte

Zero-Extend Half-Word

Table 6-1. M•CORE Instruction Set (Sheet 3 of 3)

Mnemonic Description

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MMC21 07 –Rev. 2.0  Technical Data
MOTOROLA Interrupt Controller Module  153
Technical Data — MMC2107
Section 7.   Interrupt Controlle r Module
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
4 L ow-Power Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . .154
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
6 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
7 Memory Map and R egisters . . . . . . . . . . . . . . . . . . . . . . . . . .155
7.1 Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
7.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
7.2.1 Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . .157
7.2.2 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . .159
7.2.3 Interrupt Force Registers . . . . . . . . . . . . . . . . . . . . . . . .160
7.2.4 Interrupt Pending Register. . . . . . . . . . . . . . . . . . . . . . .162
7.2.5 Normal Interrupt Enable Register. . . . . . . . . . . . . . . . . .163
7.2.6 Normal Interrupt Pending Register. . . . . . . . . . . . . . . . .164
7.2.7 Fast Interrupt Enable Register. . . . . . . . . . . . . . . . . . . .165
7.2.8 Fast Interrupt Pending Register. . . . . . . . . . . . . . . . . . .166
7.2.9 Priority Level Select Registers. . . . . . . . . . . . . . . . . . . .167
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
8.1 Interrupt Sources and Prioritization . . . . . . . . . . . . . . . . . .168
8.2 Fast and Normal Interrupt Requests . . . . . . . . . . . . . . . . .168
8.3 Autovectored and Vectored Interrupt Requests. . . . . . . . .169
8.4 Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
8.4.1 M•CORE Processor Configuration. . . . . . . . . . . . . . . . .171
8.4.2 Interrupt Controller Configuration. . . . . . . . . . . . . . . . . .171
8.4.3 Interrupt Source Configuration. . . . . . . . . . . . . . . . . . . .172
8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
    
  
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Technical Data MMC2107 –Rev. 2.0

154 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

7.2 Introduction

The inter rupt controll er collects requests fr om multiple interru pt sources

and provides an interface to the processor core interrupt logic.

7.3 Featur es

Features of the interrupt controller module include:

•Up to 40 interrupt sources

•32 unique programmable priority levels for each interrupt source

•Independent enable/disable of pending interrupts based on

priority level

•Select normal or fast interrupt request for each priority level

•Fast interr upt requests al ways have priority over normal interr upts

•Ability to mask interrupts at and below a defined priority level

•Ability to select between autovectored or vectored interrupt

requests

•Vectored interrupts generated based on priority level

•Ability to generate a separate vector number for normal and fast

interrupts

•Ability for software to self-schedule interrupts

•Software visibility of pending interrupts and interrupt signals to

core

•Asynchronous operation to support wakeup from low-power

modes

7.4 Low-Power Mode Operation

The interrupt controller is not affected by any low-power modes. All logic

between the input sources and generating the raw interrupt to the

M•CORE processor i s combinational. This allows the M•CORE

processor to wake up during low-power stop mode when all system

clocks are stopped.

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Interrupt Controller Module

Block Diagram

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Interrupt Controller Module 155

7.5 Block Diagram

Figure 7-1. Interrupt Controller Block Diagram

7.6 External Signals

No interrupt controller signals connect off-chip.

7.7 Memory Map and Registers

This subsection describes the memory map (see Table 7-1) and

registers.

INTERRUPT

SOURCES

ICR

VECTOR

32-TO-5

PRIORITY

ENCODER

FVE

NORMAL

40 32

40 x 5 BITS 32

PLSR

AUTOVECTOR

OR PRIORITY

LEVEL

SELECT

ISR

5DECODE

MASK

MFI

32 32

FMASK

NMASK

NMASK &

FMASK

PLSR

SELECT

AND FAST

INTERRUPTS

NUMBER

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Technical Data MMC2107 –Rev. 2.0

156 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

7.7.1 Memory Map

Table 7-1. Interrupt Controller Module Memory Map

A ddres s B i ts 31–24 Bits 23–16 Bits 15–8Bits 7–0 Access(1)

0x00c5_000 0 I nterrupt control register (ICR) Interrupt status register (ISR) S/U

0x00c5_000 4 I nterrupt force register high (I FR H) S/U

0x00c5_000 8 IInterrupt force register low (IFRL) S/U

0x00c5_00 0c Interrupt pending register (IPR) S/U

0x00c5_001 0 Norm al interrupt enable register (NIER) S/U

0x00c5_0014 Norm al interrupt pending register (NIPR) S /U

0x00c5_001 8 Fast interrupt enable register (FIE R) S/U

0x00c5_00 1c Fast int errupt pending register (FIPR) S/ U

0x00c5_0020

through

0x00c5_003c Unimplemented(2) —

Priority level sele ct re gisters (PLSR0–PLSR39)

0x00c5_0040 PLSR0 PLSR1 PLSR2 PLSR3 S

0x00c5_0044 PLSR4 PLSR5 PLSR6 PLSR7 S

0x00c5_0048 PLSR8 PLSR9 PLSR10 PLSR11 S

0x00c5_004c PLSR12 PLSR13 PLSR14 PLSR15 S

0x00c5_0050 PLSR16 PLSR17 PLSR18 PLSR19 S

0x00c5_0054 PLSR20 PLSR21 PLSR22 PLSR23 S

0x00c5_0058 PLSR24 PLSR25 PLSR26 PLSR27 S

0x00c5_005c PLSR28 PLSR29 PLSR30 PLSR31 S

0x00c5_0060 PLSR32 PLSR33 PLSR34 PLSR35 S

0x00c5_0064 PLSR36 PLSR37 PLSR38 PLSR39 S

0x00c5_0068

through

0x00c5_007c Unimplemented(2) —

1. S = CPU supervisor mode access onl y. S/U = CPU supervisor or us er mode access. User mode accesses to super visor

only addresses have no effect and result in a cycle termination transfer error.

2. Accesses to unimpl em ented address locations have no effect and res ult in a cycle termination transfer error.

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Interrupt Controller Module

Mem ory Map and Registers

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Interrupt Controller Module 157

7.7.2 Registers

This subsection contains a des cription of the interr upt control ler module

registers.

7.7.2.1 Interrupt Control Register

The 16-bit interrupt control register (ICR) selects whether interrupt

requests are autovectored or vectored, and if vectored, whether fast

interrupts generate a different vector number than normal interrupts.

This register also controls the masking functions.

AE — Autovector Enable Bit

The r ead/write A E bit enab les autovector ed interru pt requests. Reset

sets AE.

1 = Autovectored interrupt requests

0 = Vecto red interrupt reque sts

FVE — Fast Vector Enable Bit

The read/write FVE bit enables fast vectored interrupt requests to

have vector numbers separate from normal vectored interrupt

requests. Reset clears FVE.

1 = Uni que vector numbers for fast vectored interrupt requests

0 = Same vector number for fast and normal vectored interrupt

requests

Address: 0x00 c5_0000 and 0x00c5_0001

Bit 15 14 13 12 11 10 9 Bit 8

Read: AE FVE ME MFI 0000

Write:

Reset:10000000

Bit 7654321Bit 0

Read: 0 0 0 MASK4 MASK3 MASK2 MASK1 MASK0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 7-2. Interrupt Control Register (ICR)

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Technical Data MMC2107 –Rev. 2.0

158 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

ME — Mask Enable Bit

The read/write ME bit enables interrupt masking. Reset clears ME.

1 = Interrupt masking enabled

0 = Interrupt masking disabled

MFI — Mask Fast Interrupts Bit

The read/write MFI bit enables masking of fast interrupt requests.

Reset clears MFI.

1 = Fast interrupt requests masked by MASK value. All normal

interrupt requests are masked.

0 = Fast interrupt requests are not masked regardless of the MASK

value. The MASK only applies to normal interrupts. Reset

clears MFI.

MASK[4:0] — Interrupt Mask Fi eld

The read/write MASK[4:0] field determines which interrupt priority

levels are masked. When the ME bit is set, all pending interrupt

requests at priority levels at and below the current MASK value are

masked. To mask all normal interrupts without masking any fast

interrupts, set the MASK value to 31 with the MFI bit cleared. See

Table 7-2. Reset clears MASK[4:0].

Table 7-2. MASK Encoding

MASK[4:0] Masked Priority

Levels

Decimal Binary

0 00000 0

1 00001 1–0

2 00010 2–0

3 00011 3–0

•

31 11111 31–0

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Interrupt Controller Module

Mem ory Map and Registers

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Interrupt Controller Module 159

7.7.2.2 Interrupt Status Register

The 16-bit, read-only interrupt status register (ISR) reflects the state of

the i nterr upt co ntroller outpu ts to the M •CORE processor. Writes to this

INT — Normal Interrupt Request Flag

The read-only INT flag indicates whether the normal interrupt request

signal to the M•CORE processor is asserted or negated. Reset clears

INT.

1 = Normal interrupt request asserted

0 = Normal interrupt request negated

FINT — Fast Interrupt Request Flag

The read-only FINT flag indicates whether the fast interrupt request

signal to the M•CORE processor is asserted or negated. Reset clears

FINT.

1 = Fast interrupt request asserted

0 = Fast interrupt request negated

VEC[6:0] — Interrupt Vector Number Field

The read-only VEC[6:0] field reflects the state of the 7-bit interrupt

vector number. Reset clears VEC[6:0].

Address: 0x00 c5_0002 and 0x00c5_0003

Bit 15 14 13 12 11 10 9 Bit 8

Read: 0 0 0000INTFINT

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 VEC6 VEC5 VEC4 VEC3 VEC2 VEC1 VEC0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 7-3. Int errupt Status Register (ISR)

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Technical Data MMC2107 –Rev. 2.0

160 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

7.7.2.3 Interrupt Force Registers

The two 32-bit read/write interrupt force registers (IFRH and IFRL)

individually force interrupt source requests.

Address: 0x00 c5_0004 through 0x00c5_0007

Bit 31 30 29 28 27 26 25 Bit 24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: IF39 IF38 IF37 IF36 IF35 IF34 IF33 IF32

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 7-4. Interrupt Force Register High (IFRH)

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Interrupt Controller Module

Mem ory Map and Registers

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Interrupt Controller Module 161

IF[39:0] — Interrupt Force Field

This read/write field forces interrupt requests at the corresponding

source numbers. IFRH and IFRL allow software generation of

inte rrupt r equests for functional o r debug purposes. W riting 0 to an IF

bit negates the interrupt request. Reset clears the IF[39:0] field.

1 = Force interrupt request

0 = Interrupt source not forced

Address: 0x00 c5_0008 through 0x00c5_000b

Bit 31 30 29 28 27 26 25 Bit 24

Read: IF31 IF30 IF29 IF28 IF27 IF26 IF25 IF24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: IF23 IF22 IF21 IF20 IF19 IF18 IF17 IF16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: IF7 IF6 IF5 IF4 IF3 IF2 IF1 IF0

Write:

Reset:00000000

Figure 7-5. Interrupt Force Register Low (IFRL)

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Technical Data MMC2107 –Rev. 2.0

162 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

7.7.2.4 Interrupt Pending Register

The 32-bit, read-only interrupt pending register (IPR) reflects any

currently pending interrupts which are assigned to each priority level.

Writes to this register have no effect and are terminated normally.

IP[31:0] — Interrupt Pending Field

A read-only IPx bit is set when at least one interrupt request is

asserted at priority level x. Reset clears IP[31:0].

1 = At least one interrupt request asserted at priority level x

0 = All interrupt requests at level x negated

Address: 0x0 0c5_000c through 0x00c5_000f

Bit 31 30 29 28 27 26 25 Bit 24

Read: IP31 IP30 IP29 IP28 IP27 IP26 IP25 IP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: IP23 IP22 IP21 IP20 IP19 IP18 IP17 IP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: IP15 IP14 IP13 IP12 IP11 IP10 IP9 IP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 7-6. Interrupt Pending Register (IPR)

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Interrupt Controller Module

Mem ory Map and Registers

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Interrupt Controller Module 163

7.7.2.5 Normal Interrupt Enable Register

The read/write, 32-bit normal interrupt enable register (NIER)

individually enables any current pending interrupts which are assigned

to each pri ori ty level as a norm al i nter rupt source. E nabling an i nterrupt

source which has an asserted request causes that request to become

pending, and a request to the M•CORE processor is asserted if not

already outstanding.

NIE[31:0] — Normal Interrupt Enable Field

The read/write NIE[31:0] field enables interrupt requests from sources

at the corresponding priority level as normal interrupt requests. Reset

clears NIE[31:0].

1 = Normal interrupt request enabled

0 = Normal interrupt request disabled

Address: 0x00 c5_0010 through 0x00c5_0013

Bit 31 30 29 28 27 26 25 Bit 24

Read: NIE31 NIE30 NIE29 NIE28 NIE27 NIE26 NIE25 NIE24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: NIE23 NIE22 NIE21 NIE20 NIE19 NIE18 NIE17 NIE16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: NIE15 NIE14 NIE13 NIE12 NIE11 NIE10 NIE9 NIE8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: NIE7 NIE6 NIE5 NIE4 NIE3 NIE2 NIE1 NIE0

Write:

Reset:00000000

Figure 7-7. Normal Inter rupt Enable Register (NIER)

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Technical Data MMC2107 –Rev. 2.0

164 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

7.7.2.6 Normal Interrupt Pending Register

The read-only, 32-bit normal interrupt pending register (NIPR) reflects

any currently pending normal interrupts which are assigned to each

priority level. Writes to this register have no effect and are terminated

normally.

NIP[31:0] — Normal Interrupt Pending Field

A rea d-only NIPx bi t is set when at l east one nor mal interru pt request

is asserted at priority level x. Reset clears NIP[31:0].

1 = At least one norma l inte rrupt requ est asserted at prior it y level x

0 = All normal interrupt requests at priority level x negated

Address: 0x00 c5_0014 through 0x00c5_0017

Bit 31 30 29 28 27 26 25 Bit 24

Read: NIP31 NIP30 NIP29 NIP28 NIP27 NIP26 NIP25 NIP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: NIP23 NIP22 NIP21 NIP20 NIP19 NIP18 NIP17 NIP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: NIP15 NIP14 NIP13 NIP12 NIP11 NIP10 NIP9 NIP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: NIP7 NIP6 NIP5 NIP4 NIP3 NIP2 NIP1 NIP0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 7-8. Normal Interrupt Pending Register (NIPR)

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Interrupt Controller Module

Mem ory Map and Registers

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Interrupt Controller Module 165

7. 7.2.7 Fast Interrupt Enable Register

The read/write, 32-bit fast interrupt enable register (FIER) enables any

curren t pe nding interrupts w hich are assign ed at each prior it y level as a

fast interrupt source. Enabling an interrupt source which has an asserted

request causes that interrupt to become pending, and a request to the

M•CORE processor is asserted if not already outstanding.

FIE[31:0] — Fast Interrupt Enable Fiel d

The read/write FIE[31:0] field enables interrupt requests from sources

at the corresponding priority level as fast interrupts. Reset clears

FIE[31:0].

1 = Fast interrupt enabled

0 = Fast interrupt disabled

Address: 0x00 c5_0018 through 0x00c5_001b

Bit 31 30 29 28 27 26 25 Bit 24

Read: FIE31 FIE30 FIE29 FIE28 FIE27 FIE26 FIE25 FIE24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: FIE23 FIE22 FIE21 FIE20 FIE19 FIE18 FIE17 FIE16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: FIE15 FIE14 FIE13 FIE12 FIE11 FIE10 FIE9 FIE8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: FIE7 FIE6 FIE5 FIE4 FIE3 FIE2 FIE1 FIE0

Write:

Reset:00000000

Figure 7-9. Fast Inter rupt En able Register (FIER)

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166 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

7. 7.2.8 Fast Interrupt Pending Register

The read-only, 32-bit fast interrupt pending register (FIPR) reflects any

currently pending fast interrupts which are assigned to each priority

level. Writes to this register have no effect and are terminated normally.

FIP[31:0] — Fast Interrupt Pending Fiel d

A read-only FIP[x] bit is set when at least one interrupt request at

priority level x is pending and enabled as a fast interrupt. Reset clears

FIP[31:0].

1 = At least one fast interrupt request asserted at priority level x

0 = Any fast interrupt requests at priority level x negated

Address: 0x0 0c5_001c through 0x00c5_001f

Bit 31 30 29 28 27 26 25 Bit 24

Read: FIP31 FIP30 FIP29 FIP28 FIP27 FIP26 FIP25 FIP24

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: FIP23 FIP22 FIP21 FIP20 FIP19 FIP18 FIP17 FIP16

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: FIP15 FIP14 FIP13 FIP12 FIP11 FIP10 FIP9 FIP8

Write:

Reset:00000000

Bit 7654321Bit 0

Read: FIP7 FIP6 FIP5 FIP4 FIP3 FIP2 FIP1 FIP0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figur e 7-10. Fast Interrupt Pending Register (FIPR)

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Interrupt Controller Module

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Interrupt Controller Module 167

7.7.2.9 Priority Level Select Registers

There are 40 read/write, 8-bit priority level select registers

PLSR0–PLSR39, one for every interrupt source. The PLSRx register

assigns a priority level to interrupt source x.

PLS[4:0] — Priority Level Select Field

The PLS[4:0] field assigns a priority level from 0 to 31 to the

corresponding interrupt source. Reset clears PLS[4:0].

7.8 Functional D escription

The interrupt controller collects interrupt requests from multiple interrupt

sources and provides an interface to the processor core interrupt logic.

Interrupt controller functions include:

•Interrupt source prioritization

•Fast and normal interrupt requests

•Autovectored and vectored interrupt requests

•Interrupt configuration

Address: 0x00 c5_0040 through 0x00c5_0067

Bit 7654321Bit 0

Read: 0 0 0 PLS4 PLS3 PLS2 PLS1 PLS0

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfer error exception.

Figure 7-11. Priority Level Select Registers (PLSR0–PLSR39)

Table 7-3. Priority Select Encoding

PLS[4:0] Priority Level Vector Numbe r

00000 0 (lowest) 00000

00001–11110 1–30 00001–11110

11111 31 (highest) 11111

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Technical Data MMC2107 –Rev. 2.0

168 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

7.8.1 Interrupt Sources and Prioritization

Each interrupt source in the system sends a unique signal to the interrupt

controller. Up to 40 interrupt sources are supported. Each interrupt

source can be programmed to one of 32 priority levels using PLSR in the

interrupt controller. The highest priority level is 31 and l owest priority

level is 0. By default, each interrupt source is assigned to the priority

level 0. Each interrupt source is associated with a 5-bit priority level

select value tha t selects one of 32 priority levels. The inte rrupt controller

uses the priority levels as the basis for the generation of all interrupt

signals to the M•CORE processor.

Interrupt requests may be forced by software by writing to IFRH and

IFRL. Each bit of IFRH and IFRL is logically ORed with the

corresponding interrupt source signal before the priority level select

logic. To negate the forced interrupt request, the interrupt handler can

clea r the app ropr iate IF R bit. IPR ref l ects the state of each pr iority level .

7.8.2 Fast and Normal Interrupt Requests

FIER allows individual enabling or masking of pending fast interrupt

requests. FIER is logically ANDed with IPR, and the result is stored in

FIPR. FIPR bits are bit-wise ORed together and inverted to form the fast

interrupt signal routed to the M•COR E processor. The FIP R allows

sof tware to quickly determine the highest pr iority pend i ng fast inter rupt.

The output of FIPR also feeds into a 32-to-5 priority encoder to generate

the vector number to present to the M•CORE processor if vectored

interrupts are required.

NIER allows individual enabling or masking of pending normal inter rupt

requests. NIER is l ogically ANDed with IPR, and the result is stored in

NIPR. NIPR bits are bit-wise ORed together and inverted to form the

normal interrupt signal routed to the M•CORE processor. The normal

interrupt signal is only asserted if the fast interrupt signal is negated. The

NIPR allows software to quickly determine the highest priority pending

normal interrupt. The output of NIPR also feeds into a 32-to-5 priority

encoder to generate the vector number to present to the M•CORE

processor if vectored interrupts are required. If the fast interrupt signal is

asserted, then the vector number is determined by the highest priority

fast interrupt.

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Interrupt Controller Module

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Interrupt Controller Module 169

If an interrupt is pending at a given priority level and both the

corresp onding FIE R and N IER b its are set, th en both the correspond ing

FIPR and NIPR bits are set, assuming these bits are not masked.

Fast interrupt requests always have priority over normal interrupt

request s , even if the norm al i nter rup t req uest is a t a hi g her prior ity level

than the highest fast interrupt request.

If the fast interr upt signal i s asser ted wh en th e n orma l inter rup t signa l i s

already asserted, then the normal interrupt signal is negated.

IPR, NIPR, and FIPR are read-only. To clear a pending interrupt, the

interrupt must be cleared at the source using a special clearing

sequence defined by each source. All interrupt sources to the interrupt

controller are to be held until recognized and cleared by the interrupt

service routine. The interrupt controller does not have any edge-detect

logic. Edge-triggered interrupt sources are handled at the source

module.

In ICR, the MASK[4:0] bits can mask interrupt sources at and below a

selected priority level. The MFI bit determines whether the mask applies

only to normal interrupts or to fast interrupts with all normal interrupts

being masked. The ME bit enables interrupt masking.

ISR reflects the current vector number and the states of the signals to

the M•CORE processor.

The vector number and fast/normal interrupt sources are synchronized

before being sent to the M•CORE processor. Thus, the interrupt

controller adds one clock of latency to the interrupt sequence. The fast

and normal interrupt raw sources are not synchronized to allow these

signals to be used to wake up the M•CORE processor during stop mode

when all system clocks are stopped.

7.8.3 Autovectored and Vectored Interrupt Requests

The AE bit in ICR enables autovectored interrupt requests to the

M•CORE processor. AE is set by defau lt, and all interrupt requests are

autovecto red. An interr upt handler may read FIPR or NIPR to determine

the pri ority of the interr upt source. If m ultiple inte rrupt sour ces share the

same priority level, then it is up to the interrupt service routine to

determine the correct source of the interrupt.

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Technical Data MMC2107 –Rev. 2.0

170 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

If the AE bit is 0, then each interrupt request is presented with a vector

number. The low five bits of the vector number (4–0) are determined

based on the highest pending priority, with active fast interrupts having

pri ority over ac tive normal interru pts. The re maining tw o bits (vector bits

5 and 6) are deter mined base d on whethe r the i nterrup t request is a f ast

inte rrupt an d the set ting of the FVE bi t. If FVE is set, then a fa st interrup t

request has a vector number different from that of a normal interrupt

request as shown in Table 7-4.

If FV E is 0, bo th nor mal and fast interrupt s requests assigned t o prio ri ty

levels 0–31 are mapped to vector numbers 32–63 in the vector table. If

FVE is 1, normal interrupt requests assigned to priority levels 0–31 are

mapped to vector numbers 32–63 in the vector table.

If FVE is 1, then fast interrupt requests assigned to priority levels 0–31

are m apped to vector n umbers 6 4–95 in the vector table. See Table 7-5.

Table 7-4. Fast Inter ru pt Vecto r Number

Fast Inte rrup t FVE Interru pt Ve c tor

Bits 6:5

No X 01

X0 01

Yes 1 10

Table 7-5. Vector Table Mapping

Vector

Number Usage Inte rru pt Vector

Bits 6:5

0–31 Fixed exceptions (including autovectors) 00

32–63 Vectored interrupts

32 = l owest priority

63 = highest priority 01

64–95 Vectored interrupts

64 = l owest priority

95 = highest priority 10

96–127 Vect ored interrupts (not used) 11

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Interrupt Controller Module

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Interrupt Controller Module 171

7.8.4 Interrupt Configuration

After reset, all interrupts are disabled by default. To properly configure

the system to handle interrupt requests, configuration must be

performed at three levels:

• M•CORE processor

•Interrupt controller

•Local interrupt sources

Configure the M•CORE first, the interrupt controller second, and the

local interrupt sources last.

7. 8.4.1 M•CORE Processor Configuration

For fast interrupts, set the FIE[x] bit in FIER in the M•CORE processor.

For normal i nterr upts, set the NIE[x] bit. Both FIE and NIE are cleared a t

reset. To allow long latency, multicycle instr uctions to be interrupted

before completion, set the IC bit.

VBR in the M•CORE processor defines the base address of the

exception vector table. If autovectors are to be used, then initialize the

INT and FINT autovectors (vector numbers 10 and 11, respectively). If

vect ored inter rup ts are to be used, then initialize t he ve ctore d inte rrup t s

(v ector numb ers 32–63 and/or 64–95). Whether 32 or 64 vectors are

required depends on whether the fast interrupts share vectors with the

normal interr upt sou rces ba sed on the F VE bit i n th e inter rup t contr oller

ICR.

For each vector number, create an interrupt service routine to service

the interrupt, clear the local interrupt flag, and return from the interrupt

routine.

7.8.4.2 Interrupt Controller Configuration

By defau lt, each interrupt sou rce to the interru pt controll er is assigned a

priority level of 0 and disabled. Each interrupt source can be

programmed to one of 32 priority levels and enabled as either a fast or

normal interrupt source. Also, the FVE and AE bits in ICR can be

programmed to select autovectored/vectored interrupts and also

determine if the fast interrupt vector number is to be separate from the

normal interrupt vector.

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Technical Data MMC2107 –Rev. 2.0

172 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

7.8.4.3 Interrupt Source Configuration

Each module that is capable of generati ng an interrupt request has an

interrupt request enable/disable bit. To allow the interrupt source to be

asserted, set the local interrupt enable bit.

Once an interrupt request is asserted, the module keeps the source

asserted unti l the inte rru pt servi ce routine perf orms a speci al sequ ence

to cl ear the inte rrupt flag. Clearing the fla g negates th e interrupt request.

7.8.5 Interrupts

The interrupt controller assigns a number to each interrupt source, as

Table 7-6 shows.

Table 7-6. Interrupt Source Assignment

Source Mod ule Flag Source Desc ription Flag Clear ing Mechan ism

ADC

PF1 Queue 1 conversion pause Write PF1 = 0 after reading PF1 = 1

1 CF1 Queue 1 conver sion complete Write CF1 = 0 after reading CF1 = 1

2 PF2 Queue 2 conversion pause Write PF2 = 0 after reading PF2 = 1

3 CF2 Queue 2 conversion complete Write CF2 = 0 after reading CF2 = 1

4SPI MODF M ode fa ult Write to SPICR1 after re ading MODF = 1

5 SPIF Transfer complete Access SPIDR after reading SPIF = 1

SCI1

TDRE T ransmit data register empty Write SCIDRL after re ading TD RE = 1

7 TC T ransmit complete Write SCIDRL after re ading TC = 1

8 RDRF Receive data regist er full Read S CIDRL after reading RDRF = 1

9 OR Rec ei ver overrun Read SCIDRL after reading OR = 1

10 IDLE Receiver line idle Read SCIDRL after reading ID LE = 1

SCI2

TDRE T ransmit data register empty Write SCIDRL after re ading TD RE = 1

12 TC T ransmit complete Write S CIDRL after reading TC = 1

13 RDRF Receive data regist er full Read S CIDRL after reading RDRF = 1

14 OR Recei ver overrun Read SCIDRL after reading OR = 1

15 IDLE Receiver line idle Read SCIDRL after reading ID LE = 1

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MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Interrupt Controller Module 173

TIM1

C0F Timer channel 0 Write C0F = 1 or access IC/OC if TFFCA = 1

17 C1F Timer channel 1 Write 1 to C1F or access IC/OC if TFFCA = 1

18 C2F Timer channel 2 Write 1 to C2F or access IC/OC if TFFCA = 1

19 C3F Timer channel 3 Write 1 to C3F or access IC/OC if TFFCA = 1

20 TOF Timer overflow Write TOF = 1 or access TIMCNTH/L if TFFCA = 1

21 PAIF Pulse accumulator input Wri te PAIF = 1 or access PAC if TFFCA = 1

22 PAOVF Pulse accumu lator overflow Write P AOV F = 1 or access PAC if T FFC A = 1

TIM2

C0F Timer channel 0 Write C0F = 1 or access IC/OC if TFFCA = 1

24 C1F Timer channel 1 Write C1F = 1 or access IC/OC if TFFCA = 1

25 C2F Timer channel 2 Write C2F = 1 or access IC/OC if TFFCA = 1

26 C3F Timer channel 3 Write C3F = 1 or access IC/OC if TFFCA = 1

27 TOF Timer overflow Write TOF = 1 or access TIMCNTH/L if TFFCA = 1

28 PAIF Pulse accumulator input Wri te PAIF = 1 or access PAC if TFFCA = 1

29 PAOVF Pulse accumu lator overflow Write P AOV F = 1 or access PAC if T FFC A = 1

30 PIT1 PIF PIT interrupt flag Write PIF = 1 or write PMR

31 PIT2 PIF PIT interrupt flag Write PIF = 1 or write PMR

EPORT

EPF0 Edge port flag 0 Write EPF0 = 1

33 EPF1 E dge port flag 1 Write E P F1 = 1

34 EPF2 E dge port flag 2 Write E P F2 = 1

35 EPF3 E dge port flag 3 Write E P F3 = 1

36 EPF4 E dge port flag 4 Write EPF4 = 1

37 EPF5 Edge port flag 5 Wri te EPF5 = 1

38 EPF6 E dge port flag 6 Write E P F6 = 1

39 EPF7 E dge port flag 7 Write E P F7 = 1

Table 7-6. Interrupt Source Assignment (Continued)

Source Mod ule Flag Source Desc ription Flag Clear ing Mechan ism

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Technical Data MMC2107 –Rev. 2.0

174 Interrupt Controller Module MOTOROLA

Inter rup t Contro lle r Module

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MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Static Random-Access Memory (SRAM) 175

Technical Data — MMC2107

Section 8. Static Random-Access Memory (SRAM)

8.1 Contents

8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

8.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

8.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

8.5 Standby Power Supply Pin (VSTBY) . . . . . . . . . . . . . . . . . . . .176

8.6 Standby Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

8.7 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

8.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

8.2 Introduction

Features of the static random-access memory (SRAM) include:

•On-chip, 8-Kbyte static random-access memory (SRAM)

•Fixed address space

•Byte, half-word (16-bit), or word (32-bit) read/write accesses

•One clock per access (including bytes, half-words, and words)

•Supervisor or user mode access

•Stand by powe r sup pl y switch to support an external p ower supply

8.3 Mo des of Operation

Access to the SRAM is not restricted in any way. The array can be

accessed in all supervisor and user modes.

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Technical Data MMC2107 –Rev. 2.0

176 Static Random- Access Memory (SRAM) MOTOROLA

Static Random- Access Memory (SRAM)

8.4 Low-Power Modes

In wait, doze, and stop modes, clocks to the SRAM are disabled. No

recovery time is required when exiting any low-power mode.

8.5 Standby Power Supply Pin (VSTBY)

The standby power supply pin (VSTBY) provides standby voltage to the

RAM array if VDD is lost. VSTBY is isolated from all other VDD nodes.

8.6 Standby Operation

When the chip is powered down, the contents of the SRAM array are

maintained by the standby power supply, VSTBY. If the standby voltage

falls below the minimum required voltage, the SRAM contents may be

corrupted. The SRAM automatically switches to standby operation with

no l oss o f dat a when the vol tage on VDD is below the voltage on V STBY.

In standby mode, the SRAM does not respond to any bus cycles.

Unexpected operation may occur if the central processor unit (CPU)

requests data from the SRAM in standby mode. If standby operation is

not needed, then the VSTBY pin should be connected to VDD.

The current on VSTBY may exceed its specified maximum value at some

time during the transition time during which VDD is at or below the

volta ge switch threshold to a thr eshold abo ve V SS. If the sta ndby power

supply cannot provide enough current to maintain VSTBY above the

requi red minimu m value, th en a capacitor must be provi ded from V STBY

to VSS. The value of the capacitor, C, can be calculated as:

where:

I is the differe nce between the transition current req ui rement a nd th e

maximum power supply current,

t is the duration of the VDD transition near the voltage switch

threshold, a nd

V is the difference between the minimum available supply voltage and

the required minimum VSTBY voltage.

----

×=

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Static Random-Acce ss Memory (SRAM)

Reset Operation

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Static Random-Access Memory (SRAM) 177

8.7 Reset Op eration

The SRAM contents are undefined immediately following a power-on

reset. SRAM contents are unaffected by system reset.

If a synchronous reset occurs during a read or write access, then the

access completes normally and any pipelined access in progress is

stopped without corruption of the SRAM contents.

8.8 Interrupts

The SRAM module does not generate interrupt requests.

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Technical Data MMC2107 –Rev. 2.0

178 Static Random- Access Memory (SRAM) MOTOROLA

Static Random- Access Memory (SRAM)

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MMC21 07 –Rev. 2.0  Technical Data
MOTOROLA Non-Volatile Memory FLASH (CMFR)  179
Technical Data — MMC2107
Section 9.   Non-Volatile Memory FLASH (CMFR)
1  Contents
2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
4.2 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
5 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
6 Glossary of Terms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
7 Registers and Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .186
7.1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
7.1.1 CMFR Module Configuration Register. . . . . . . . . . . . . .188
7.1.2 CMFR Module Test Register . . . . . . . . . . . . . . . . . . . . .193
7.1.3 CMFR High-Voltage Control Register . . . . . . . . . . . . . .196
7.2 Array Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
7.2.1 Read Page Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
7.2.2 Program Page Buffers . . . . . . . . . . . . . . . . . . . . . . . . . .204
8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
8.1 Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
8.2 Register Read and Write Operation. . . . . . . . . . . . . . . . . .205
8.3 Array Read Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
8.4 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
8.4.1 Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
8.4.2 Program Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . .211
8.4.3 Programming Shadow Information. . . . . . . . . . . . . . . . .212
8.4.4 Program Pulse-Width and Amplitude Modulation . . . . .213
8.4.5 Overprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
    
  
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Technical Data MMC2107 –Rev. 2.0
180 Non-Volatile Memory FLASH (CMF R) MOTOROLA
Non-Volatile Memory FLASH (CMFR)
9.8.5 Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
9.8.5.1 Erase Sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
9.8.5.2 Erase Margin Reads  . . . . . . . . . . . . . . . . . . . . . . . . . . .218
9.8.5.3 Erasing Shadow Information Words. . . . . . . . . . . . . . . .219
9.8.6 Erase Pulse Amplitude and W idth Modulation. . . . . . . . . .219
9.8.7 Emulation Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
9.9 Master Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
9.10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
9.2  Introduction
This  section  descr ibes th e ope ration  of the embedded F LASH m emor y. 
The FLASH memory can be read, programmed, and erased from a 
single external programming voltage suppl y, VPP. The program and 
erase operations are enabled through the use of an internal charge 
pump.
The CDR MoneT FLASH uses the Motorola one-transistor bitcell 
(MoneT). The 128-Kbyte CMFR array is divided into 16-Kbyte 
(16,384 bytes) array blocks. The CMFR array size is created by using 
eight array blocks.
The primary function of the CMFR is to serve as electrically 
programmable and erasable NVM to store program instructions and/or 
data. It is a class of nonvolatile solid state silicon memory device 
consisting of an array of isolated elements, a means for selectively 
adding and removing charge to the elements electrically and a me ans of 
selectively sensing the stored charge in the elements. When power is 
removed from the device, the stored charge of the isolated elements are 
retained.
The CM FR  is ar ran ged i nt o two m ajor se cti ons a s shown i n  Figur e 9- 1 . 
The first section is the MoneT array used to store system program and 
data. The second section is the bus interface unit (BIU) that controls 
access and operation of the CMFR array. 
    
  
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Non -Vola t ile Memor y FLASH ( C MFR)

Features

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 181

9.3 Featur es

Features of the CMFR module include:

•MoneT FLASH bitcell

•128-Kbyte array size using 16-Kbyte blocks

•Array block restriction control:

–Array block erasing

–Array protection for program and erase operations

–Supervisor space and supervisor/unrestricted space selection

–Data space and instruction/data spaces selection.

•32-bit word length

•Page mode read:

–Retains two separate pages

–Read page size of 32 bytes (8 words)

–Off-page read access time of two clocks

–On-page read access time of one clock

•Programming:

–Program up to 512 bytes at a time

–Simultaneously program up to eight 64-byte pages located at

the same block offset address

•External VPP program and erase power supply

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Technical Data MMC2107 –Rev. 2.0

182 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

9.4 Mo des of Operation

This subsection describes the two modes of operation:

1. S top mode

2. Disabled mode

9.4.1 Stop Mode

When the FSTOP bit in the CMFR module configuration register

(CMFRMCR) register is set, the CMFR enters a low-power operation

mode. Write to FSTOP bit is allowed only when SES = 0 in the CMFR

high-voltage control register (no high-voltage operations). When the

FSTOP bit is set, only CMFRMCR can be accessed, accesses to the

array are ignored, and accesses to other registers are terminated with

bus errors. To prevent unpredictable behavior it is recommended to

change this bit separately. The CMFR requires a recovery time of 16

clocks after exiting stop mode. This means that if a read access to the

array is done immediately after writing FSTOP = 0, the access is

completed after 16 clocks.

9.4.2 Disabled Mode

When the DI S bit in CMF RMCR is set, the arr ay is di sabled and the BIU

does not respond to array accesses. Write to DIS bit is allowed only

when SES = 0 (no high-voltage operations). Disabling the CMFR does

not place the module in the lowest power consumption mode like stop

mode, b ut does pl ace the CMFR in a safe state and preven ts the CMFR

from conflicting on the internal bus during an external boot. There is no

recovery time required when re-enabling the CMFR.

For details of the CMFR module configuration register (CMFRMCR) see

9.7.1.1 CMFR Module Configuration Register and 9.7.1.3 CMFR

High-Voltage Co ntrol Reg ister.

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Non -Vola t ile Memor y FLASH ( C MFR)

Block Diagram

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 183

9.5 Block Diagram

Figure 9-1. CMFR 128-Kbyte Block Diagram

The CMFR is divided into array blocks to allow for independent erase,

address attributes restriction, and protection from program and erase for

each array block. The size of an array b lock in the CMFR module is fixed

at 16 Kbytes. The total CMF R array is distributed into eight blocks. F or

a detailed description of the read page buffer operation see 9.7.2.1 Read

Page Buffers and 9.8.3 Array Read Operation.

BUS INTERFACE UNIT (BIU)

0x0001_c000—0x0001_ffff

0x0001_8000—0x0001_bfff

0x0001_4000—0x0001_7fff

0x0000_c000—0x0000_ffff

0x0000_8000—0x0000_bfff

0x0000_4000—0x0000_7fff

0x0000_0000—0x0000_3fff

0x0001_0000—0x0001_3fff

16-KBYTE ARRA Y BLOC K 0

16-KBYTE ARRA Y BLOC K 1

16-KBYTE ARRA Y BLOC K 2

16-KBYTE ARRA Y BLOC K 3

16-KBYTE ARRA Y BLOC K 4

16-KBYTE ARRA Y BLOC K 5

16-KBYTE ARRA Y BLOC K 6

16-KBYTE ARRA Y BLOC K 7

AND SHAD O W INFO RMA TION

64-BYTE PROGR AM PAGE BU FFER 0

64-BYTE PROGR AM PAGE BU FFER 1

32-BYTE READ PAG E BUFF ER 0

64-BYTE PROGR AM PAGE BU FFER 2

64-BYTE PROGR AM PAGE BU FFER 3

64-BYTE PROGR AM PAGE BU FFER 4

64-BYTE PROGR AM PAGE BU FFER 5

32-BYTE READ PAG E BUFF ER 1

64-BYTE PROGR AM PAGE BU FFER 6

64-BYTE PROGR AM PAGE BU FFER 7

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Technical Data MMC2107 –Rev. 2.0

184 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

To improve system performance, the BIU accesses information in the

array at 32 bytes per access. These 32 b ytes ar e cop ie d in a rea d pa ge

buffer aligned to the low-order addresses. A CMFR array contains two

non-over lapping read page buffers. The first read page buffer is

associated to the lower array blocks. The second r ead page buffer is

associated to the higher array blocks. Read access time of the data in

the cur rent r ead page buffers is one syste m clock, while the time to read

a new page into a page buffer and access the required information is two

system clocks. These accesses are known as an on-page read and an

off-page read, respectively. To prevent the BIU from accessing an

unnecessary page from the array, the CMFR monitors the address to

determine if the required information is in one of the two current read

page buffe rs and the access is valid for the module. This strategy allows

the CMFR to have a two-clock read for an off-page access and one-clock

for an on-p age access. In normal operation write accesses to the CMFR

array are not allowed, a write access causes a bus error.

The CMFR requires an external program or erase voltage, VPP, to

progr am or erase the arra y. Special contro l logic is includ ed to requi re a

specific series of read and write accesses.

To improve program performance, the CMFR programs up to eight

unique 64-byte pages simultaneously in eight separate array blocks.

These 64 bytes are aligned to the low-order addresses to form a

program page buffer.

Each of the page s being pr ogrammed si multaneously are located at the

same block offset address. Erasing is performed on one or more of the

selected array blocks simultaneously.

An extra row (256 bytes) of the CMFR array is used to provide reset

configuration information and is called shadow information. This row

may be accessed by setting the SIE bit in the CMFR module

configuration register and accessing the CMFR array. The shadow

information is in the lowest array block 0 of the CMFR array. Note that

the shadow row is erased with block 0.

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Non -Vola t ile Memor y FLASH ( C MFR)

Glossary of Terms

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 185

9.6 Glossary of Terms

Array block – CMFR array subdivision is a 16-Kbyte contiguous block

of information. Each array block can be erased independently.

BIU – Bus inter face unit that controls access and o peration of the CMFR

CMFR – CDR MoneT FLASH ARray

Erase interlock write – A write to any CMFR array address after

initializing the erase sequence

Era se margin r ead – Special o ff-page re ad of the C MFR array i n which

the CMFR hardware adjusts the reference of the sense amplifier to

check for correct erase operation. All CMFR off-page reads between the

erase interlock write and clearing the SES bit are erase margin reads.

Initialize program/erase sequence – The write to the high-voltage

control register that changes the SES bit from a 0 to a 1

MoneT – The Motorola one-transistor bitcell

Off-page read – Array read operation that requires two clocks and

updates a page buffer

On-page read – Array read operation that accesses inform ati on in one

of the read page buffers and requires one clock.

Overprogrammed – By exceeding the specified programming time

and/or voltage, a CMFR bit can be overprogrammed. This causes

erased bits in the same column in the same array block to read as

programmed.

Programm ing write – A write to a CMFR array address to transfer

information into a program page buffer. The CMFR accepts

programming writes after initializing the program sequence until the EHV

bit is changed from a 0 to a 1.

Program m argin read – Special off-page read of the CMFR array in

which the CMFR hardware adjusts the reference of the sense amplifier

to check for correct program operation. All CMFR array off-page reads

between the first programming write and clearing the SES bit are

program margin reads.

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Technical Data MMC2107 –Rev. 2.0

186 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

Pr ogram p age buffe r – 64 bytes of information used to program the

CMFR. This information is aligned to a 64-byte boundary within the

CMFR. The CMFR module has eight program page buffers, one per

array block.

Read page buffer – 32-byte block of information that is read from the

CMFR array. This information is aligned to a 32-byte boundary within the

CMFR. The CMFR module has two read page buffers.

Shad ow information – An extra row (256 bytes) of the CMFR array

used to provide Motorola internal use data and also possibly user

defi ned infor mat ion. This row may be accessed by setting the S IE bit in

the CMFR module configuration register and accessing the CMFR array.

The shadow information is the lowest array block 0 of the CMFR array.

9.7 Registers an d Memory Map

The CMFR module consists of two addressed sections. The first is the

32-byte control registers used to configure, program, era se, and test the

array while, the second is the array. See Figure 9-2.

Figure 9-2. CMFR Array and Control Register Addressing

0x00d0_0020

0x00d0_0000

0x0001_ffff

0x0000_0000

FLAS H CO NTRO L

32 BYTES

CMFR FLASH

128 KBYTE S

0x00d0_001f

0x00d0_000c

0x00d0_000b

0x00d0_0008

0x00d0_0007

0x00d0_0004

0x00d0_0003

0x00d0_0000

UNIMPLEMENTED

CMFR HIGH- V OL TAGE CONT RO L

CMFR MO DULE TEST REGIS TER

(CMFRMTR)

CMFR MO DULE CONFIGURATION

REGIS TE R ( CMFRMCR)

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Non -Vola t ile Memor y FLASH ( C MFR)

Registe rs and Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 187

9.7.1 Contr ol Registers

The control registers control CMFR operation. On reset, the registers are

loaded with default reset information.

The access time of a CMFR register is one system clock for both read

and write accesses. Accesses to unimplemented registers cause the

BIU to generate a transfer error exception.

Table 9- 1. Non-Volatile Memory FLASH Me mory M ap

Address Control Register

Located in Supervisor Data Space

0x00d0_ 0000 Module configuration register (CMFR MCR)

0x00d0_ 0004 Module test register (CMFRMTR)

0x00d0_0008 High-voltage control register (CMFRCTL)

0x00d0_000c

through

0x00d0_001f Unimplemented

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Technical Data MMC2107 –Rev. 2.0

188 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

9.7.1.1 CMFR Module Configuration Register

The CMFR module configuration register (CMFRMCR) controls

operation of the CMFR array and BIU.

Address: 0x00d0_0000 through 0x00d0_0003

Bit 31 30 29 28 27 26 25 Bit 24

Read: FSTOP FDBG 0EME SIE LOCKCTL DIS RSVD24

Write:

Reset: 0 0 0 Note 1 0 0 Note 1 0

Bit 23 22 21 20 19 18 17 Bit 16

Read: SUPV7 SUPV6 SUPV5 SUPV4 SUPV3 SUPV2 SUPV1 SUPV0

Write:

Reset:11111111

Bit 15 14 13 12 11 10 9 Bit 8

Read: DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

Write:

Reset:00000000

Bit 765 4321Bit 0

Read: PROTECT7 PROTECT6 PROTECT5 PROTECT4 PROTECT3 PROTECT2 PROTECT1 PROTECT0

Write:

Reset:11111111

= Writ es have no effect and the access terminates without a transfer error exception.

Notes:

1. Reset state is determined during reset configurati on.

Figure 9-3. CMFR Module Configuration Register (CMFRMCR)

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Non -Vola t ile Memor y FLASH ( C MFR)

Registe rs and Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 189

FSTOP — FLASH Stop Enable Bit

The read-always FSTOP bit causes the CMFR to enter a low-power

stop m ode. W riting ha s n o e ffect if S ES = 1. W he n FS TOP is set, the

BIU continues to operate to allow accesses to CMFRMCR. Accesses

to other registers are terminated with bus error. Accesses to the array

are ignored. To prevent unpredictable behavior, change the FSTOP

bit in a separate write operation.

1 = CMFR in low-power stop mode

0 = CMFR in normal mode

FDBG — FLASH Debug Enable Bit

The read/write FDBG bit determines whether the set-once LOCKCTL

bit is writable when the chip is in deb ug mode. Writing to the FDBG bit

must occur before the LOCKCTL bit is writable.

1 = Debug mode enabled

0 = Debug mode disabled

EME — Emulation Enable Bit

The read-always EME bit enables the CMFR to enter emulation

mode. EME is writable when the LOCKCTL and DIS bits are set.

During emulation mode the CMFR terminates array access cycles,

but does not drive data. Array data can be emulated by reading an

external memory, and on-page/off-page timing is the same as in

non-emulation mode. Note that write accesses to the array space are

the same as normal mode.

1 = Emulation mode enabled

0 = Emulation mode disabled

For more information about emulation operation see 9.8.7 Emulation

Operation.

SIE — Shadow Information E nable Bit

The read-always SIE bit selects the shadow information row. SIE is

write-protected when the ERASE bit is clear and the SES bit is set.

When SIE is set and an array location is read using supervisor data,

the shadow information is read from a location determined by the

column, 32 byte read page select, and word addresses of the access.

Accessing the control block registers accesses the registers and not

the shadow information.

1 = Shadow information enabled; normal array access disabled

0 = Shadow information disabl ed; normal array access enabled

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Technical Data MMC2107 –Rev. 2.0

190 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

The address range of the shadow information is the entire address

range of the array, but the high order array addresses, are not used

to encode the location.

NOTE: When SI E = 1, only the p rogr am p age buffer assoc ia ted with the lowest

block can be programmed. The other program page buffers cannot be

accessed and do not apply any programming voltages to their array

blocks while programming the shadow information. The shadow

information is in block 0.

LOCKCTL — Lock Control Bit

The read-always, set-once LOCKCTL bit controls the write-lock

function. Once the LOCKCTL bit is set in normal operation, the

write-lock can only be disabled again by a master reset. The

LOCKCTL bit is writable if the device is in debug mode.

1 = Write-locked registers protected

0 = Write-lock disabled

Setting the LOCKCTL bit locks the SUPV[7:0], DATA[7:0] and

PROTECT[7:0] bits. Writing to these bits has no effect; the cycle ends

normally and the bits do not change.

NOTE: If LOCKCTL is set before PROTECT[7:0] is cleared, the device must use

debug mode to program or erase the CMFR.

The default reset state of LOCKCTL is 0. It can be set once after

master reset to allow protecti on of the write-locked register bits after

initialization.

If the LOCKCTL bit and write-locked register bits are written

simultaneously, the new value does not affect the current cycle.

DIS — Disable Bit

The read-always DIS bit disables array information. Writing to DIS has

no effect if the SES bit is set. When DIS is set, the array is disabled

and the CMFR BIU does not respond to array accesses.

The reset value is defined during reset configuration by the external

D28 pin.

1 = Array information disabled

0 = Array information enabled

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Non -Vola t ile Memor y FLASH ( C MFR)

Registe rs and Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 191

RSVD24 — Re served

Writing to this read/write bit updates the va lue but has no effect on

functionality.

SUPV[7:0] — Supervisor Space Field

The read-always SUPV[7:0] field controls supervisor/unrestricted

address sp ace assignmen t of array blocks. The field is writable when

the LOCKCTL bit is clear.

Arr ay blocks that correspon d to 1s in SUPV[7:0] are sel ected for da ta

address space.

Each array block can be mapped into supervisor or unrestricted

address space. When an array block is mapped into supervisor

address space (SUPV [M] = 1) only supervisor a ccesses are allo wed.

A user access to a location in supervisor address space causes a

data error exception. When an array block is mapped into unrestricted

address space (SUPV[M] = 0) both supervisor and user accesses are

allowed.

The default reset state of SUPV[7:0] bits are supervisor address

space (SUPV[M] = 1).

1 = Array block in supervisor address space

0 = Array block in unrestricted address space

DATA[7:0] — Data Space Fiel d

The read-always DATA[7:0] field controls data/program address

space assignment of array blocks. When LOCKCTL = 1, the

DATA[7:0] field is write-protected, and writing to it has no effe ct.

Array blocks th at correspo nd to 1s in DATA[7:0 ] are selected for data

address space.

Each array block can be mapped into data address space or both data

and program address space. When an array block is mapped into

data address space (DATA[M] = 1) only data accesses are allowed.

A pr ogra m access to a loca tion in d ata ad dress space cau s es a d ata

error exception. When an array block is mapped into both data and

program address space (DATA[M] = 0) both data and program

accesses are allowed.

The default reset state of DATA[7:0] bits are data and prog ram

address space (D ATA[ M] = 0).

1 = Array block in data address space

0 = Array block is both data and program address space

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Technical Data MMC2107 –Rev. 2.0

192 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

PROTECT[7:0] — Block Protect Field

The read-always PROTECT[7:0] field protects array blocks from

program and erase operations. If LOCKCTL = 1 or SES = 1, writing to

PROTECT[7:0] has no effect.

Array blocks that cor respond to 1s in PRO TECT[7:0 ] are selected for

data address space.

Each array block can be protected from program and erase operation

by setting its PROTECT bit. The CMFR BIU performs all programming

and era s e interl ocks excep t that th e pro gram and e rase vo ltages a re

not applied to locations within the protected array block(s).

The default reset state of PROTE CT[7:0] bits are protected

(PROTECT[M] = 1).

1 = Array block protected

0 = Array block not protected

CAUTION: If the LOCKCTL bit is set before PROTECT[7:0] is cleared, the device

must use debug mode to program or erase the CMFR.

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Non -Vola t ile Memor y FLASH ( C MFR)

Registe rs and Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 193

9.7.1.2 CMFR Module Test Register

The CMFR module test register (CMFRMTR) controls the CMFR array

and BIU.

Address: 0x00d0_0004 through 0x00d0_0007

Bit 31 30 29 28 27 26 25 Bit 24

Write:

Reset:

Bit 23 22 21 20 19 18 17 Bit 16

Write:

Reset:

Bit 15 14 13 12 11 10 9 Bit 8

Read: 0 0 0 0 NVR PAWS2 PAWS1 PAWS0

Write:

Reset: 0000

Bit 7654321Bit 0

Read: 0 RSVD6 GDB 00000

Write:

Reset:00000000

= Writes have no effect and the access terminates without a transfe r error exception.

Figure 9-4. CMFR Module Test Register (CMFRMTR)

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Technical Data MMC2107 –Rev. 2.0

194 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

NVR — Negative Voltage Range Select Bit

The read-always NVR bit modulates the negative pump output to

select the negative voltage range in program and erase modes as

shown in Table 9-2. NVR is writable when the HVS bit is clear but has

no effect when the GDB bit is clear.

1 = Negative voltage low range

0 = Negative voltage high range

PAWS[2:0] — Pulse Amplitude/Width Select Field

The read-always PAWS[2:0] field selects the pulse drain amplitude

and width for program or erase operations. PAWS[2:0] is writable

when the HVS bit is clear. PAWS[2] must be set for all program and

erase o pera ti ons. If G DB = 1, the gate/source volta ge app lied dur ing

program/erase is determined by PAWS[1:0] and NVR and shown in

Table 9-2.

NOTE: The program pulse time is equal to the value selected by the pulse width

timing control. When SES = 1, write to SCLKR[2:0], CLKPE[1:0], and

CLKP M[6:0 ] only whe n P AWS[2] = 1. Do not wr ite to P A WS[2: 0] dur ing

high-voltage operations.

RSVD6 — Reserved

Reserved for factory test and must remain clear at all times

Table 9-2. Negative Voltage Modulation

PAWS[2:0] NVR = 0 NVR = 1

100 –6 V –2 V

101 –7 V –3 V

110 –8 V –4 V

111 –9 V –5 V

0XX Reserved(1)

1. When PAWS[2] = 0 and PAWS[1:0] have no ef fec t.

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Non -Vola t ile Memor y FLASH ( C MFR)

Registe rs and Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 195

GDB — Gate or Drain/Source Select Bit

The read-always GDB bit selects gate, source, or drain for voltage

modulation. GDB is writable when the SES bit is clear.

GDB selects the ga te, source, or drain. In programming , GDB selects

gate ( GD B = 1) or dra in (GD B = 0) voltage for amp litu de m odulat io n.

When PAWS[2] = 0, mask plugs control amplitude modulation. When

PAWS[2] = 1, the PAWS[1:0] bits control amplitude modulation.

1 = Gate selected

0 = Drain/source selected

Table 9-3. Drain Amplitude Modulation (GDB = 0)

PAWS[2:0] Drain Voltage

100 60% VPP

101 70% VPP

110 80% VPP

111 VPP

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Technical Data MMC2107 –Rev. 2.0

196 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

9.7.1.3 CMFR High-Voltage Control Register

The CMFR high-voltage control register (CMFRCTL) controls the

program and erase operations of the CMFR.

HVS — High Voltage Status Bit

The re ad-only HVS bit reflects th e status of the program/e rase pul se.

Writing to HVS has no effect. HVS is set when a pulse is active and

during recovery. While HVS = 1, accesses to the array cause a bus

error , and S ES cannot b e chan ged. T he pu lse becom es acti ve when

the EHV bit is set and is terminated by clearing EHV or by the pulse

width timing control. See Figure 9-6.

1 = Pulse applied to array or CMFR in recovery

0 = Pulse not applied to array

Address: 0x00d0_0008 through 0x00d0_000b

Bit 31 30 29 28 27 26 25 Bit 24

Read: HVS 0SCLKR2 SCLKR1 SCLKR0 0CLKPE1 CLKPE0

Write:

Reset:00000000

Bit 23 22 21 20 19 18 17 Bit 16

Read: 0 CLKPM6 CLKPM5 CLKPM4 CLKPM3 CLKPM2 CLKPM1 CLKPM0

Write:

Reset:00000000

Bit 15 14 13 12 11 10 9 Bit 8

Read: BLOCK7 BLOCK6 BLOCK5 BLOCK4 BLOCK3 BLOCK2 BLOCK1 BLOCK0

Write:

Reset:00000000

Bit 7654321Bit 0

Read: 0 RSVD6 100

ERASE SES EHV

Write:

Reset:00100000

= Writes have no effect and the access terminates without a transfe r error exception.

Figure 9-5. CMFR High-Voltage Control Register (CMFRCTL)

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Non -Vola t ile Memor y FLASH ( C MFR)

Registe rs and Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 197

Figure 9-6. Pulse Status Timing

The recovery time is the time that the CMFR requires to remove the

program or erase voltage from the array before sw itching to another

mode of operation. The recovery time is determined by the

SCLKR[2:0] field and the ERASE bit. If SCLKR is not 000, the

recovery time is 48 of the scaled clock periods. If SCLKR = 000 the

recovery time is 128 clocks.

Once reset is completed HVS indicates no program or erase pulse

(HVS = 0).

SCLKR[2:0] — System Clock Range Field

The read/write SCLKR[2:0] field selects the system clock range for

program/erase pulse timing.

NOTE: The SCLKR[2:0] bits are not write protected by the SES bit. Unless the

PAWS[2] bit is set, writes to SCLKR[2:0] in software should not be

changed if SES = 1.

To control the pulse widths for program and erase operations, the CMFR

uses the system clock and the timing control in CMFRCT L. The total

pulse time is defined by:

pulse width = system clock period × R × 2N × M

Where:

R = clock scaling (see Table 9-4)

N = 5 + CLKPE[1:0] + ( (ERASE) × 10)

M = 1 + CLKPM[6:0]

EHV

HVS

Recovery = 48 scaled clocks or 128 clocks

RECOVERY

PULSE WID T H

RECOVERY

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198 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

The control of the program/erase pulse timing is divided into three

functions.

The first term of the timing con trol is the clock scaling, R. T he value of R

is determined by the system clock range (SCLKR[2:0]). SCLKR[2:0]

defines the base clock of the pulse timer. Use Table 9-4 to set

SCLKR[2:0] based on the system clock frequency.

CAUTION: If the correct value for SCLKR[2:0] is not selected from the table, the

pulse timer may run too fast and cause damage to the device.

The system clock period is mu ltiplied by the clock scaling value to

generate a 83.3-ns to 125-ns scaled clock. This scaled clock is used to

run the charge pump submodule and the next functional block of the

timing control.

NOTE: The mi nimum specified system clock frequency for program and erase

operations is 8.0 MHz. The C M FR does not h ave any m eans to m onitor

the system clock frequency and cannot prevent program or erase

operation at frequencies below 8.0 MHz. Attempting to program or erase

the CMFR at system clock frequencies lower than 8.0 MHz does not

damage the device if the maximum pulse times and total times are not

exceeded. While some bits in the CMFR array may change state if

progr ammed or era sed at sys tem clock frequencies bel ow 8.0 MHz, the

full program or erase transition is not assured.

Table 9-4. System Clock Range

SCLKR[2:0] System Clock Frequency (MHz) Clock Scaling (R)

Minimum Maximum(1)

1. The ma ximu m system clock frequency is 33 MHz.

000 Reserved

001 8 12 1

010 12 18 3/2

011 18 24 2

100 24 36 3

101 36 40 4

110 and 111 Reserved by Motorola for future use

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Non -Vola t ile Memor y FLASH ( C MFR)

Registe rs and Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 199

CAUTION: Never stop or alter the system clock frequency during a program or

erase operation. Changin g the clock fr equency du ring program or eras e

results in inaccurate pulse widths and variations in the charge pump

output.

The default reset state of SCLKR[2:0] is 000, giving a clock scaling

of 1, and the program or erase pulse is not terminated until EHV is

cleared by a softw are write.

CLKPE[1:0] — Clock Period Exponent Field

The read/write CLKPE[1:0] field selects the clock period exponent for

progr am/er ase pulse timi ng. Th e second ter m of the timing contr ol is

the clock multiplier, 2N. The program pulse number (pulse), clock

peri od expo nent bits (CLK P E[1:0]), an d ERA SE define the exponent

in the 2N multiply of the clock period. The exponent, N, is defined by

the equation: N = 5 + CLKPE[1:0] + [(ERASE) × 10]

All of the exponents are shown in Table 9-5.

NOTE: The CLKPE[1:0] bits are not write protected by the SES bit. Unless the

PAWS[2] bit is set, writes to CLKPE[1:0] in software should not be

changed if SES = 1.

The default reset state of CLKPE[1:0] is 00 .

Table 9-5. Clock Period Exponent a nd Pulse Width Range

ERASE CLKPE[1:0] Exponent (N)

Pulse Width Range for all System Clock

Frequ encies from 8. 0 MHz to 3 3.0 MH z

Minimum

2N × 1.25E – 7 Maximum(1)

2N × 128 × 8.33E – 8

1. The ma ximu m system clock frequency is 33 MHz.

00 5 4.00 µs 0.34 ms

01 6 8.00 µs 0.68 ms

10 7 16.00 µs 1.36 ms

11 8 32.0 µs 2.73 ms

00 15 4.096 ms 349.5 ms

01 16 8.192 ms 699.0 ms

10 17 16.39 ms 1.398 s

11 18 32.77 ms 2.796 s

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Technical Data MMC2107 –Rev. 2.0

200 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

CLKPM[6:0] — Clock Period Multiplier Field

The third term of the timing control is the linear clock multiplier, M. The

clock period multiplier, CLKPM[6:0], defines a linear multiplier for the

program or erase pulse. M is defined by:

M = 1 + (CLKPM[6:0])

This allows the program/erase pulse to be from 1 to 128 times the

pulse set by the system clock period, SCLKR[2:0] and CLKPE[1:0].

The default reset state of CLKPM[6:0] is binary 000 0000, which gives

a multiplier of 1.

NOTE: The C LKPM[ 6:0] bits are not write pro t ected by the SES bi t. Unless the

PAWS[2] bit is set, writes to CLKPM[6:0] in software should not be

changed if SES = 1.

Table 9-6 shows an example of calculating the values of SCLKR[2:0],

CLKP E[1:0] and CLKPM[6:0] f or a 1 -ms p rogr am p ulse, E RASE = 0,

in a system with a 33.0-MHz system clock ha ving a per iod of 30.3 ns.

Table 9-6. Determining SCLKR[2:0], CLKPE[1:0],

and CLKPM[6:0]

No. Example Calculation

1Determine SCLKR[2:0] — Table 9-4 shows that a SCLKR[2: 0] value of 100

and an R value of 3 gives a system clock frequency from 24 MHz to 36 MHz.

Determi n e CLKPE[1:0] — 9.7.1 Control Registers shows that when

ERASE = 0, a 1-ms program pulse can be generated by an N value of 7

(CLKPE[1:0] = 10) or 8 (C LKPE [ 1:0] = 11). An N value of 8 is used in this

example.

Determin e CLKPM[6:0] — Using the selected values of N and R in the pulse

width equation, pulse width = system clock period × R × 2N × M and solving

for M yield s 42.97. Rounding M to 43 and using the M equation,

M = 1 + (CLKPM[6:0]) and solving for CLKPM[6:0] yields 42.

4Check the results — pulse width = 30.3 ns × 3 × 28 × 43 = 1.00 ms where

SCLKR[2:0] = 100, CLKPE[1:0 ] = 11, CLKPM[6:0] = 0101010, ERAS E = 0,

system clock frequency = 33.0 MHz

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Non -Vola t ile Memor y FLASH ( C MFR)

Registe rs and Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 201

BLOCK[7:0] — Block Program and Erase Field

The read/write BLOCK[7:0] field selects array blocks for program or

erase operation. BLOCK[7:0] is writable when the SES bit is clear. If

SES is written in the same cycle with BLOCK[7:0] bits, the write

permission to BLOCK[7:0] bits depends on the previous value of SES.

Up to eight blocks at once can be selected for program operation.

Array blocks that correspond to 1s in BLOCK[7:0] are selected for

program or erase operation. The BLOCK[7:0] default state is $00, not

selected for program or erase.

1 = Array block selected for program or erase

0 = Array block not selected for program or erase

RSVD6 — Reserved

Rese rved for test purposes. Writing to this read /write bi t updates the

values and could affect functionality if set to 1.

ERASE — Program or Erase Select Bit

The read-always ERASE bit selects program or erase operations.

ERASE is wri table when the SES bit is clea r. If S ES and ER ASE are

written in the same cycle, the write permission to ERASE bit depends

on the previous value of SES.

When ERASE = 0, the array is configured for programming, and if

SES = 1 the SIE bit is write locked. When ERASE = 1, the array is

configured for erasing, and SES does not write lock the SIE bit.

1 = Erase operation

0 = Program operation

SES — Start/End Sequence Bit

The read-always SES bit signals the start and end of a program or

erase sequence. SES is writable when the HVS and EHV bits are

clear. If SES and EHV are written in the same cycle, the write

permission to SES depends on the previous value of EHV. At the start

of a program or erase sequence, SES is set, locking PROT ECT[7:0] ,

BLOCK[7:0], and ERASE.

1 = CMFR configured for program or erase operation

0 = CMFR not configured for program or erase operation

NOTE: SES does not lock the SCLKR[2:0], CLKPE[1:0], and CLKPM[6:0] bits.

Do not change these bits in software when SES = 1 unless

PAWS[2] = 1.

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Technical Data MMC2107 –Rev. 2.0

202 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

At this point the CMFR is ready to receive the programming writes, the

erase interlock write, or a write to CMFRMCR for programming the

reset values of the DIS bit, or a write to CMF RRC.

NOTE: The erase interlock write is a write to any CMFR array location after SES

is set and ERASE = 1.

If the ERASE bit is a 0, the CMFR BIU accepts programming writes to

the CMFR array address for programming. The first programming

write selects the program page offset address to be programmed

along with the data for the programming buffers at the location written.

All programming writes after the first write update the program buffers

usin g the lower a ddre s s and the b lock addr ess to select th e pr ogra m

page buffers to receive the data. See 9.7.2 .2 Prog ram Pag e Buff ers

for fur ther i nformation. After th e data has be en writt en to the pr ogram

buffers the EHV bit is set (written to a 1) to start the programming

pulse and lock out further programming writes.

If the ERASE bit is a 1, the CMFR BIU accepts writes to the CMFR

array address for erase. An erase interlock write is required before the

EHV bit can be set.

At the end of the program or erase operation, the SES bit must be

cleared (written to a 0) to return to normal operation and release the

program buffers and the locked bits. The CMFR requires a recovery

time of 16 clocks after negating SES. This means that if a read access

to the CMFR array is done immediately after writing SES = 0, the

access is completed after 16 clocks. Also, the FSTOP bit should not

be asserted during this recovery time.

The d efaul t reset state of S ES is not confi gu red for pro gram or era se

operation (SES = 0).

EHV — Enable High-Voltage Bit

The read-always EHV bit controls the application of the program or

erase voltage to the CMFR. High-voltage operations to the array,

spec ial shadow l ocations or NV M registers can occu r only if EHV = 1.

EHV can be assert ed only after the SES bit has been asser ted and a

valid programming write(s) or erase hardware interlock write has

occurred. Attempts to assert EHV when SES is negated (including the

cycle which writes 0 to SES), or when a valid programming write or

erase hardware interlock write has not occurred since SES was

asserted have no effect.

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Non -Vola t ile Memor y FLASH ( C MFR)

Registe rs and Memory Map

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 203

Once EHV is set, SES cannot be changed; attempts to read or write

the array or CMFRRC cause bus errors.

The default reset state of EHV disables program or erase pulses

(EHV = 0). A m aster rese t while EHV = 1 terminates the high-vol tage

operat ion an d the CMFR generates the requi red sequence to disa ble

the high voltage without damage to the high-voltage circuits.

1 = Program/erase pulse enabled

0 = Program/erase pulse disabled

9.7.2 Array Addressing

Information in the array is accessed in 32-byte pages. Two read page

buffers are aligned to the low order addresses. The first page buffer is

for the lower array blocks. The second page buffer is for the higher array

blocks. Access time of information in the read page buffers is one system

clock. Access time for an off-page read is two system clocks. To prevent

the B IU from accessing an unne cessary page from the arra y, the CMFR

monitors the address to determine if the required information is wi thin

one o f th e t wo r ead pag e b uffer s an d t he access is valid for the m odule.

This strategy allow s the CMFR to have a 2-clock read for an off-page

access and a 1-clock read for an on-page access.

Writing to the array while not in a program/erase sequence causes a bus

error.

9.7.2.1 Read Page Buffers

The two 32-byte read page buffers are fully independent and are locate d

in two separate read sections of the array. The BIU monitors the status

and address of e ach page b uffer. The status of the read page buffers are

usually valid, but are made invalid by these operations:

•Reset

•Programming write

•Erase interlock write

•Setting the EHV bit

•Clearing the SE S bit

•Setting or clearing the SIE bit

•Exiting stop mode

•Exiting disable mode

•Exiting boot mode

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Technical Data MMC2107 –Rev. 2.0

204 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

Each access to the array determines if the requested location is within

the current pages. If the requested location is not within the read page

buffers, the appropriate read page buffer is made invalid and a new page

of information is fetched from the array. The page buffer address is

updated and status is made valid. If the req uested locat ion is within one

of the current page buffers or has been fetched from the array, the

selected bytes are transferred to the CPU, completing the access. Array

accesses that make the page buffer(s) invalid are off-page reads that

require two system clocks. Array accesses that do not make the page

buffer(s) invalid are on-page reads that require one system clock.

9. 7.2.2 Program Page Buffers

The CMFR can program up to eight 64-byte pages at one time. Each

program page buffer is associated with one array block. A ll program

page buffers share the same block offset address, stored in the BIU. The

block offset address is extracted from the address of the first

programming write. To select the array block to be programmed, the

program page buffers use BLOCK[7:0]. The data programmed in each

array block is determined by the programming writes to the program

buffer for each block. A ll program buffer data is unique whereas the

program page offset address is shared by all blocks.

An a rray block is selecte d for pr ogramm ing i f the c orrespond in g BLOCK

bit is a 1. If BLOCK[M] = 1, then array block[M] is programmed. If

BLOCK[M] = 0, then array block[M] is not programmed. The program

page buffers are written regardless of the state of the BLOCK bits, but

high-voltage is not applied to blocks for which BLOCK[M] = 0.

Bits in the program page buffers select the non-programmed state if

SES = 0. During a program margin read, the program buffers update bits

to the non-programmed state for bits that correspond to array bits that

the program margin read has determined are programmed.

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Non -Vola t ile Memor y FLASH ( C MFR)

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 205

9.8 Functional D escription

The CMFR is an electrically erasable and programmable non-volatile

memor y. Thi s subse ction de scri bes the fu nctioning of the CMFR dur i ng

various operational modes.

9.8.1 Master Reset

The device signals a master reset to the CMFR when a full reset is

required. A master reset is the highest priority operation for the CMFR

and terminates all other operations. The CMFR uses master reset to

initialize all register bits to their default reset value. If the CMFR is in

progr am o r er ase o pera ti on ( EHV = 1) and a master reset i s gene rate d,

the module performs the needed interlocks to disable the high voltage

without damage to the high voltage circuits. Master reset terminates any

other mode of operation and forces the CMFR BIU to a state ready to

receive accesses.

9.8.2 Register Read and Write Operation

The CMFR control re gisters are accessib le for read or wri te opera tion at

all times while the device is powered up except during master reset.

The access time of a CMFR register is one system clock for both read

and write accesses. Accesses to unimplemented registers causes the

BIU to generate a data error exception.

9.8.3 Array Read Operation

The CMFR array is available for read operation under most conditions

while the device is powered up. Reads of the array are ignored (no

response) during master reset or while the CMFR is disabled or in stop

mode. During programming and erase operation while the high voltage

is applied to the array (EHV = 1 or HVS = 1) the BIU generates data

errors for all array accesses. At certain points, as defined in the program

or erase sequence, reading the array results in a margin read. These

margin reads return the status of the program or erase operation and not

the data in the array.

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Technical Data MMC2107 –Rev. 2.0

206 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

The type of array read is determined by comparing the address of the

requested information with the address of the read page buffers. If the

requested address is not in one of the read page buffers or if the read

page buffer has been made invalid, an off-page read results. This read

updates the sele cted array b lock’s read pag e buffer a ddress, copi es the

information from the array into the read page buffer, and drives a

word/half-word onto the data bus. The off-page read requires a minimum

of two clocks; margin off-page reads require additional clocks (see

9.8.4.2 Program Margin Reads and 9.8.5.2 Erase Margin Reads). If

the add ress of the requ ested inform ation is withi n the addr ess ranges of

either of the read page buffers, the second type of read is performed.

This read is an on-page read and requires one clock to transfer

information from the read page buffer onto the data bus.

NOTE: After reset, programming writes, erase interlock w rite, setting EHV ,

clearing SES, setting/clearing SIE and exiting stop mode or disable

mode, the page buffers do not contain valid information and the CMFR

must do an off-page read before an on-page read can be done.

9.8.4 Programming

To modify the charge stored in the isolated element of the CMFR bit from

a l ogic 1 stat e to a l o gic 0 state, a p rogr amm ing oper ati on is req ui red. A

programmed bit reads as logic 0. This programming operation applies

the required voltages to change the charge state of the selected bits

without changing the logic state of any other bits in the array. The

program operation cannot chan ge the logic 0 state to a logic 1 state; this

transition must be done by the erase operation. An erased bit reads as

log ic 1. Programmi ng uses a set of e ight pr ogra m buffe rs of 64 bytes to

store the required data, an address offset buffer to store the starting

address of the block(s) to be programmed, and a block select buffer that

stores information on which block(s) are to be programmed. From one to

eight of the program page buffers may be programmed at one time.

CAUTION: Do not program any page more than once after a successful erase

operation. Whil e this doe s not physi cally d amag e the arr ay it causes a n

increased partial disturb time for the unselected bits on the row and

columns that are not programmed. A full er ase of all blocks being

programmed must be done before the CMFR can be used reliably.

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Non -Vola t ile Memor y FLASH ( C MFR)

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 207

Blocks of the CMFR that are protected (PROTECT[block] = 1) are not

programmed.

The program sequence is outlined in 9.8.4.1 Program Sequence and

depicted in the flowchart form in Figure 9-7.

9.8.4.1 Program Sequence

Use this sequence to enable the high voltage to the array or shadow

information for program operation:

1. Make sure the CMFRMTR and CMFRCTL are in their reset states.

2. Set PAWS[2] = 1 and GDB = 1 in CMFRMTR.

3. In CMFRMCR, write PROTECT[7:0] to disable protection of

blocks to be programmed.

4. Use the procedure in Table 9-6 to write the pulse width timing

control fields for a prog ram pulse.

5. In CMFRCTL, clea r the ERASE bi t, and write BLOCK[7:0] to

select the array blocks to be programmed.

6. In CMFRCTL, set the SES bit.

7. P rog ram ming write — A successful write to the array locations to

be programmed. This updates the programming page buffer(s)

with the information to be programmed. All accesses to the array

after the first write are to the same block offset address regardless

of the address provided. Thus the locations accessed after the first

programming write are limited to the page locations to be

programmed. Off-page read accesses of the array after the first

programming write are program margin reads.

NOTE: All program pa ge buff ers shar e the sam e block offset addre ss stored in

the BIU. The block offset address is extracted from the address of the

fir st pr ogra mming w rite . To select the array bl ock( s) to be pr ogra mme d,

the pro gram pag e buffers use BL OCK[7:0]. S ubse quen t writes fill in the

programming page buffers using the block address to select the program

page buffer and the page word address to select the word in the page

buffer.

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Technical Data MMC2107 –Rev. 2.0

208 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

8. In CMFRCTL, set the EHV bit.

NOTE: If a program page buffer word has not received a programming write, no

programming voltages are applied to the drain of the corresponding

word in the array. At this point, writing to the program page buffers is

disabled and causes a bus error until SES has been cleared and set.

9. Read CMFRCTL until HVS = 0.

10. In CMFRCTL, clear the EHV bit.

11. Verify the program by reading the words of the pages that are

being programmed. These are program margin reads. A bit that

was successfully programme d retur ns a 0 durin g a ma rgin rea d. It

returns a 1 if it has been unsuccessfully programmed. If any bit

intended to be programmed does not return a 0 after reading all

the locations, the margin read has failed. If the margin read is

successful continue to step 12, otherwise do the following:

a. Write new pulse wi dth para meter s (if re quired, see Table 9- 9

for the required pro gram ming algorithm) C LKPE and CLKPM.

b. Write new values for P AWS and NVR (if required, see

Table 9-9)

c. Go back to step 8 to apply additional pulses.

To reduce the time for verification, read two locations in each array

block that is being programmed after reading a non-programmed

bit. After a locati on has bee n verified (all bits are prog ramm ed) , it

is not necessary to reverify the location, as no further

programming voltages are applied to the drain of the

corresponding bits.

CAUTION: After a program pulse, read at least one location with address bit 5 = 0

and one location with address bit 5 = 1 on each programmed page.

Failure to do so ma y result in the loss of information in the CMFR array,

and a full erase of all blocks being programmed must be done before the

CMFR can be used reliably.

12. In CMFRCTL, clear the SES bit.

13. If more information needs to be programmed, go to step 3.

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Non -Vola t ile Memor y FLASH ( C MFR)

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 209

Fi gu re 9-7. FLAS H Progr am min g Flow c har t

DISABLE PROTEC TION OF THE BLOCKS

TO BE PROGRAMM ED

PROTECT[7:0] IN CMFRMCR

WRIT E THE PU LSE W IDT H TIMI NG CONT RO L FIELDS

FO R A PROGRAM PULSE (SEE TABLE 9 -8)

SCLKR[2:], CLKPE[1:], CLKPM[6:0] IN CMFRCTL

SELECT PROGRAM OPERATION AND SELECT

THE ARR AY BLOCK TO BE PROGR AM M ED

ERA SE = 0, BLOCK[ 7: 0] IN CMF R C TL

CONFIGURE C MFR FOR PR OGR AM OPERAT IO N

SES = 1 IN CMF RCTL

WRITE 64 BYTES OF DATA TO THE LOCATION

TO BE PROGRAMM ED

ENABLE HIGH-VOLTAGE PULSE FOR PROGRAMMING

EHV = 1 IN CMFRCTL

DISABLE HI GH -VOLTAGE PU LSE

EHV = 0 IN CMFRCTL

VERIFI CA TION PR OCE SS

END OF THE PR OGR AM M ING SEQUENCE

SES = 0 IN CMF RCTL

PULSE APP LIED TO THE

CMFR AR RA Y BLOCK ?

HVS = 0 IN CMFRCTL

YES

FAILED

YES PROGR AM NEX T PAGE? FINISH

10.

11.

12.

13.

Notes:

1. This page program algorithm assu mes the blocks to be programmed are in itially er ased.

2. Make sure that CMFRMT R is in its reset state at the beginning of the progr am ming process and afterwards.

SET PAWS [2] = 1 AND GDB = 1 IN THE CMFRM T R

UPDATE CLKPE,

CLKPM, PAW S,

AND NVR IF NEEDE D

MAKE S URE CMFRM TR A ND CMFRCTL

AR E I N T H EI R R ESET STATES

11a.

11b.

11c.

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Technical Data MMC2107 –Rev. 2.0

210 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

Figu re 9-8. Pr ogra m Stat e Diagram

S2 S3

S1 S4

T6T1 T2 T4

RESET

Table 9-7. Program Interlock State Descriptions

State Mode Next

State Tr ansition Req uiremen t

Normal operatio n: Normal array reads and

and pulse width timing control can be

modified.

S2 T2 Write ERASE = 0 an d SES = 1

First pro gram hardw a re int erlo ck wri te:

Normal read operation. Array accepts

programming writes. Normal register

accesses. CMFRCTL write cannot change

EHV. If write is to a register other than

CMFRMCR, no data is stored i n program

page buffers; CMFR remains in S2.

S1 T1 Write SES = 0 or master reset

S3 T3

Hardware interlock: Successful programming

write to any array location. Latches selected

data word into programming page buffer;

addres s latched to select location to

progra m. Bit that has been written remains

in program buffer until another write to i t, or

SES is cle a r e d , or a progr a m ma r g in r e a d

determines bit needs no modification by

progra m operation. If write is to a register

(except CMFRMCR), no data is stored in

program page buffe rs, and CMFR remains

in S2. Writing to CMFRMCR does not allow

array to be programmed.

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Non -Vola t ile Memor y FLASH ( C MFR)

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 211

9. 8.4.2 Progra m Margin Re ads

The CMFR provides a program margin read with electrical margin for the

program state. Program margin reads provide sufficient margin to

assure specified data retention. The program margin read is enabled

when SE = 1 and a programming write has occurred. To increase the

access time of the program margin read the off-page access time is 17

clocks instead of the usual 2-clock off-page read access time. The

program margin read and subsequent on-page program verify reads

Expanded program hardware interlock

operatio n: P rogram margin reads.

Programming writes accepted; all eight

program pages can be programmed. Writes

can be to any array location. Program page

buffers updated using only data, lower

address, and block address. Normal register

accesses. CMFRCTL write can change

EHV. If write is to a register, no data is

stored in program page buffer.

S1 T6 Write SES = 0 or master reset

S4 T4 Write EHV = 1

Program operation: High voltage applied to

array or sh adow informa tion to program

CMFR bitcells. Pulse width timer active if

SCLKR[2:0] ≠ 0; HVS can be polled to time

program pulse. Programming writes not

accepted. During programming, array

cannot be accessed (bus error). Normal

re gister accesses. CMFRCT L write can

change only EHV.

S1 T7 Master reset

S5 T5 EHV = 0 and HV S = 0

Program margin read operation: Reads

determine if bits on selected page need

modification by program operation. Once bit

is fully programmed, data stored in program

page is updated; no further programming

occurs for that bit and va lue read is 0.

While it is not necessary to read all words on a

page to determine if another program pulse

is needed, all pages being programmed

must be read once after each program

pulse.

S4 T8 Write EHV = 1

S1 T9 Write SES = 0 or a master reset

Table 9-7. Program Interlock State Descriptions (Continued)

State Mode Next

State Tr ansition Req uiremen t

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Technical Data MMC2107 –Rev. 2.0

212 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

return a 1 for any bit that has not completely programmed. Bits left in the

non-programmed state after the programming write read as a 0s. Bits

that have completed programming read as 0s and update the data in the

programming page buffer so that no further programming of those bits

occurs.

The program margin read occurs while doing the off-page read. A

program margin read must be done for all pages that are being

programmed after each program pulse.

CAUTION: Failure to read e ach page th at is bein g progra mmed afte r each pr ogram

pulse may result in the loss of informati on in the array. While this does

not physically damage the array a full erase of all blocks being

programmed must be done before the CMFR can be used reliably.

9.8.4.3 Programming Shadow Information

Programming the shadow information uses the same procedure as

programming the array except that only program page 0 is used to

program the shadow information. Before starting the program sequence

SIE must be a 1. BLOCK and PROTECT bits do not affect programming

of the shadow locations.

Table 9-8. Results of Programming Margin Read

Current Data

in Program

Page Buffer

Current

Bit State Read

Output

New Data

for the Prog ram

Page Buffer

0 Programmed — 00 1

0 Erased — 11 0

1 Programmed — 00 1

1 Erased — 10 1

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Non -Vola t ile Memor y FLASH ( C MFR)

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 213

9.8.4.4 Program Pulse-Width and Amplitude Modulation

To prevent bits from possibly becoming depleted (over programmed),

the first programming pulses should be of reduced duration and with

reduced dr ai n voltage . Refer to Tab le 9-9 for t he requ i red programming

steps to insure FLASH reliability.

NOTE: The values of PAWS[2:0] and NVR should be updated on the

appropriate pulse to change the programming voltage and CLKPM

should be updated to adjust the pulse width.

GDB = 1 for all programming operations.

Marg in reads are req u ired after ever y pulse.

9. 8.4.5 Overprogr ammi ng

Programming a bit without a program margin read after each program

pul se or exce eding the specified program tim es or volt ages resul ts in a n

overprogrammed state. Once a bit is overprogrammed, data in the array

blo ck that is locate d i n the sa me colum n is lost as th e overprogramm ed

bit causes the entire column to appear programmed. To restore an array

block with an overprogrammed bit, the block must be erased and

reprogrammed.

Table 9-9. Required Programming Algorithm

Voltage Step PA WS[2:0] N VR Pulse Widt h Nu mber of Pul ses

–2 V 1 0 0 1 250 µs4

–3 V 1 0 1 1 250 µs4

–4 V 1 1 0 1 250 µs4

–5 V 1 1 1 1 250 µs4

–6 V 1 0 0 0 50 µs20

–7 V 1 0 1 0 50 µs20

–8 V 1 1 0 0 50 µs20

–9 V 1 1 1 0 50 µs20

–9 V 1 1 1 0 100 µs Any addition al

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Technical Data MMC2107 –Rev. 2.0

214 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

9.8.5 Erasing

To modify the charge stored in the isolated element of a bit from a logic 0

state to a logic 1 state, an erase operation is required. The erase

operation cannot change the logic 1 state to a logic 0 state; this transition

must be done by the program operation. Erase is a bulk operation that

affects the stored charge of all the isolated elements in an array block.

To make the block erasable, the array is divided into blocks that are

physically isolated from each other. Each of the array blocks may be

erased in isolation or in any combination. The array block size is fixed for

all blocks at 16 Kbytes and the module is com prised of eight blocks.

Array blocks that are protected (PROTECT[M] = 1) are not erased.

The array blocks selected for erase operation are determined by

BLOCK[7:0].

NOTE: Erasing BLOCK 0 also erases the shadow information.

The erase sequence is outlined in 9.8.5.1 Erase Sequence and

depicted in the flowchart form in Figure 9-9.

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Non -Vola t ile Memor y FLASH ( C MFR)

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 215

9. 8.5.1 Erase Sequ ence

Use this sequence to enable the high voltage to the array or shadow

information for erase operation:

1. Make sure that CMFRMTR is in its reset state, and write

PAWS[2:0] = 111 to override firmware amplitude modulation.

2. In CMFRMCR, write PROTECT[7:0] to disable protection of the

blocks to be erased.

3. Use the procedure in Table 9-6 to write the pulse-width timing

control fields for an erase pulse with BLOCK[7:0] selecting the

blocks to be erased and ERASE = SES = 1 in CMFRCT L.

4. Execute an erase interlock write to any array location.

5. In CMFRCTL, write EHV = 1.

6. Read CMFRCTL until HVS = 0.

7. In CMFRCTL, write EHV = 0.

8. Verify the erase by reading all locations that are being erased,

including the shadow information if the bl ock that contains it is

erased. Off-page reads are erase margin reads that update the

read page buffer. If all the locations read as erased, continue to

the next step oth erw ise, up date P AWS and N VR (i f requir ed, see

Table 9-9). Then go back to step 5.

To redu ce the time for veri fication, upon the fir st read of a 0, go to

step 5. After a locatio n has been veri fied ( all bi ts are er ased), it is

not n ecessar y to r ever ify l oca tions after su bsequ ent era se p ulses.

9. In CMFRCTL, write SES = 0.

10. Make sure that CMFRMTR is in its reset state.

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Technical Data MMC2107 –Rev. 2.0

216 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

Figure 9-9. FLASH Erasing Flowchar t

WRIT E THE PU LSE W IDT H TIMING CONT RO L

FIELDS FOR A ERASE PU LSE (SEE TABLE 9-8)

SC L K R[2 :0], CLK P E[1:0 ], CLK P M[6:0] IN C MFR CTL

EXECUTE AN ERASE INTER LOC K W R IT E TO ANY

ARRAY LOCATIO N TO BE ER ASED

DISABLE HIGH-VOLTAGE PULSE

EHV = 0 IN CMFRCTL

VERIFICATION PRO CE SS

END OF THE E RA S ING SE Q UE NCE

SES = 0 IN CMFRCTL

PULS E APPLIED TO THE

CMFR ARR AY BLOC K?

HV S = 0 IN C MFRCTL

YES

FAILED

3.1.

3.2.

OVERRIDE FIRMWARE AMPLITUDE MODULATION

PAWS [2: 0] = 111 IN CMFRM TR

DISABLE PROTECTI ON OF THE BL OCKS TO BE ERAS ED

PROTECT[7:0] IN CMFRMCR

SELECT ERASE OPERATION AND SELECT

THE ARRAY BLOCK TO BE ERASED

ERASE = 1, BLOCK[7:0] IN CMFRCTL

ENABL E HI GH -VOLTAGE PUL SE FO R ERASING

EHV = 1 IN CMFRCTL

CONFIGURE C MFR FOR PR OGR AM OPERAT IO N

SES = 1 IN CMFR CTL

3.3.

Note: Make sure that CMFRMTR is i its reset stat e at the beginning of the erasing

process and aft erwards.

UPDATE PAWS

A ND NVR,

IF REQUIRED

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Non -Vola t ile Memor y FLASH ( C MFR)

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 217

Figure 9-10. Erase State Diagram

S2 S3

S1 S4

T6T1 T2 T4

RESET

Table 9-10 Erase Interlock State Descriptions

State Mode Next

State Tr ansition Req uiremen t

Normal operatio n : Normal array reads and

and pulse-width timing control can be

modified.

S2 T2 Write ERAS E = 1 and SES = 1

Erase hardware interlock write: Normal read

operation. CMFR accepts erase hardware

interlock write to any array location. Normal

r egister access (except CMFRMCR).

CMFRCTL write cannot set EHV. Register

writ e (except CMFRMCR) is not erase

hardware interlock write; CMFR remains in

S2. CMFRMCR write causes transition to

S3.

S1 T1 Write SES = 0 or a master reset

S3 T3

Har dware inte rloc k: Write to any array

location is erase interlock write. Register

write other than CMFRMCR is not erase

hardware interlock write; CM FR rem ains in

S2. CMFRMCR write causes transition to

S3; NVM fuses cleared during high-voltage

pulse

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Technical Data MMC2107 –Rev. 2.0

218 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

9. 8.5.2 Erase Margin R eads

The CMF R provides an e rase m arg in read with el ectr ical mar gin for the

erase state. Erase margin reads provide sufficient margin to assure

specified data retention. The erase margin read is enabled when

SES = 1 and the erase write has occurred. The erase margin read and

subsequent on-page erase verify reads return a 0 for any bit that has not

completely erased. Bits that have completed erasing read as a 1s. To

increase th e access time of t he er ase ma rgin r ead, t he off- page access

time is 17 clocks instead o f the usual 2 -clock off-pa ge read access tim e.

The erase margin read occurs while doing an off-page read. All locations

within the block(s) that are being erased must read as a 1 to determine

that no more erase pulses are required.

High voltage write enable: Eras e margin

reads occur. CMFR accepts erase hardware

inte rl o ck wri te . Normal registe r ac cesse s

(except CMF RM CR). CMFRMCR write

causes NVM fuses to be cleared during the

high-voltage pulse. If CMFRMCR was

writ ten, a CMFRMCR read returns the NVM

fuses value. CMFRCTL write can change

EHV. When HVS goes high, NVR and

PAWS are locked.

S1 T6 Write SES = 0 or a master reset

S4 T4 Write EHV = 1

Erase operation: High voltage appli ed to

array blocks to erase bitcells. Pulse-width

timer active if SCLKR[2: 0] ≠ 0; HVS can be

polled to time the erase pulse. Duri ng erase,

array cannot be accessed (bus error).

Normal reg ister accesse s. CMFRCTL write

can change only EHV.

S1 T7 Maste r reset

S5 T5 EHV = 0 and HV S = 0

Erase margin read operatio n : Reads

determine if bits in selected blocks need

modification by the erase operati on. Erased

bit reads as 1. All words in erased blocks

must be read to determine if erase is

complete.

S4 T8 Write EHV = 1

S1 T9 Write SES = 0 or a master reset

Table 9-10 Erase Interlock State Descr iptions (Continued)

State Mode Next

State Tr ansition Req uiremen t

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Non -Vola t ile Memor y FLASH ( C MFR)

Functional Description

MMC21 07 –Rev. 2.0 Technical Data

MOTOROLA Non-Volatile Memory FLASH (CMF R) 219

9.8.5.3 Erasing Shadow Information Words

The shadow information words are erased with either array block 0

depending upon the array configuration. To verify that the shadow

information words are erased with block 0, erase margin reads should

be performed with the SIE bit set in CMFRMCR while the shadow

information is read. For the erase operation to be completed, block 0

must also be fully verified.

NOTE: Setting SIE = 1 disables normal array access and should be cleared

after verifying the shadow information.

9.8.6 Erase Pulse Amplitude and Width Modulation

Refer to Table 9-11 for the required erase algorithm to insure r eliability

of the FLASH.

NOTE: The values of PAWS[2:0] and NVR should be updated on the

appropriate pulse to change the erase voltage.

GDB = 0 for all erase operations.

Margin reads are required after the first –9-V pulse.

Table 9-11. Required Erase Algorithm

Voltage Step PA WS[2:0] N VR Pulse Widt h Nu mber of Pul ses

–2 V 1 0 0 1 100 ms 1

–3 V 1 0 1 1 100 ms 1

–4 V 1 1 0 1 100 ms 1

–5 V 1 1 1 1 100 ms 1

–6 V 1 0 0 0 100 ms 1

–7 V 1 0 1 0 100 ms 1

–8 V 1 1 0 0 100 ms 1

–9 V 1 1 1 0 100 ms 20

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Technical Data MMC2107 –Rev. 2.0

220 Non-Volatile Memory FLASH (CMF R) MOTOROLA

Non-Volatile Memory FLASH (CMFR)

9.8.7 Emulation Operation

In emul ation mode, to suppo rt emulat ion of the internal FLA SH me mory

with external memory devices, the CMFR responds to an array access

only by terminating the access. During emulation, the CMFR does not

drive any data and the data should be provided by an external device.

This synchronizes the timing of 1-clock on-page accesses and 2-clock

off-page accesses during emulation from external memory.

9.9 Master Reset