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1
FEATURES
DESCRIPTION
APPLICATIONS
10-Bit
Pipelined
ADC
Error
Correction
Logic
Timing/DutyCycleAdjust(PLL)
Internal
Reference
3-State
Output
S/H
D9A
·
·
·
D0A
10-Bit
Pipelined
ADC
Error
Correction
Logic
3-State
Output
S/H
D9B
·
·
·
D0B
INA
AVDD OEA
VDRV
SDATA SEN SCLK SEL
OVRA
OVRB
INA
CM
INT/EXT CLK
DVA
DVB
REFT
REFB
INB
VIN
OEB
STPD
INB
ADS5237
VIN
Serial
Interface
DISABLE_PLL
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
Dual, 10-Bit, 65MSPS, +3.3VAnalog-to-Digital Converter
2
•Single +3.3V Supply•High SNR: 61.7dBFS at f
IN
= 5MHz
The ADS5237 is a dual, high-speed, high dynamicrange, 10-bit, pipelined analog-to-digital converter•Total Power Dissipation:
(ADC). This device includes a high-bandwidthInternal Reference: 366mW
sample-and-hold amplifier that gives excellentExternal Reference: 330mW
spurious performance up to and beyond the Nyquist•Internal or External Reference
rate. The differential nature of the sample-and-holdamplifier and ADC circuitry minimizes even-order•Low DNL: ± 0.1LSB
harmonics and gives excellent common-mode noise•Flexible Input Range: 1.5V
PP
to 2V
PP
immunity.•TQFP-64 Package
The ADS5237 provides for setting the full-scale rangeof the converter without any external referencecircuitry. The internal reference can be disabled,•Communications IF Processing
allowing low-drive, external references to be used for•Communications Base Stations
improved tracking in multichannel systems.•Test Equipment
The ADS5237 provides an over-range indicator flag•Medical Imaging
to indicate an input signal that exceeds the full-scale•Video Digitizing
input range of the converter. This flag can be used toreduce the gain of front-end gain control circuitry.•CCD Digitizing
There is also an output enable pin to allow formultiplexing and testing on a printed circuit board(PCB).
The ADS5237 employs digital error correctiontechniques to provide excellent differential linearity fordemanding imaging applications. The ADS5237 isavailable in a TQFP-64 package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIEDPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORTPRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
ADS5237IPAG Tray, 160ADS5237 TQFP-64 PAG – 40 °C to +85 °C ADS5237IPAG
ADS5237IPAGT Tape and Reel, 250
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
Over operating free-air temperature range, unless otherwise noted.
ADS5237 UNIT
Supply voltage range, AVDD – 0.3 to +3.8 VSupply voltage range, VDRV – 0.3 to +3.8 VVoltage between AVDD and VDRV – 0.3 to +0.3 VVoltage applied to external REF pins – 0.3 to +2.4 VAnalog input pins
(2)
– 0.3 to min [3.3, (AVDD + 0.3)] VCase temperature +100 °COperating free-air temperature range, T
A
– 40 to +85 °CLead temperature +260 °CJunction temperature +105 °CStorage temperature – 65 to +150 °C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may affect device reliability.(2) The dc voltage applied on the input pins should not go below – 0.3V. Also, the dc voltage should be limited to the lower of either 3.3V or(AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25 Ωshould be added in series with eachof the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be defined eitheras a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3V and+3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should not exceed1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V.
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RECOMMENDED OPERATING CONDITIONS
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
ADS5237
PARAMETER MIN TYP MAX UNIT
SUPPLIES AND REFERENCES
Analog supply voltage, AVDD 3.0 3.3 3.6 VOutput driver supply voltage, VDRV 3.0 3.3 3.6 VREF
T
— External reference mode 1.875 2.0 2.05 VREF
B
— External reference mode 0.95 1.0 1.125 VREFCM = (REF
T
+ REF
B
)/2 – External reference mode
(1)
V
CM
± 50mV VReference = (REF
T
– REF
B
) – External reference mode 0.75 1.0 1.1 VAnalog input common-mode range
(1)
V
CM
50mV V
CLOCK INPUT AND OUTPUTS
ADCLK Input sample ratePLL enabled (default) 20 65 MSPSPLL disabled 2 30
(2)
MSPSADCLK duty cyclePLL enabled (default) 45 55 MSPSLow-level voltage clock input 0.6 VHigh-level voltage clock input 2.2 VOperating free-air temperature, T
A
– 40 +85 °CThermal characteristics:
θ
JA
42.8 °C/W
θ
JC
18.7 °C/W
(1) These voltages need to be set to 1.5V ± 50mV if they are derived independent of V
CM
.(2) When the PLL is disabled, the clock duty cycle needs to be controlled well, especially at higher speeds. A 45% – 55% duty cycle variationis acceptable up to a frequency of 30MSPS. If the device needs to be operated in the PLL disabled mode beyond 30MSPS, then theduty cycle needs to be maintained within a 48% – 52% duty cycle.
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ELECTRICAL CHARACTERISTICS
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
T
MIN
= – 40 °C and T
MAX
= +85 °C. Typical values are at T
A
= +25 °C, clock frequency = 65MSPS, 50% clock duty cycle,AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, – 1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unlessotherwise noted.
ADS5237
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
No missing codes TestedDNL Differential nonlinearity f
IN
= 5MHz – 0.5 ± 0.1 +0.5 LSBINL Integral nonlinearity f
IN
= 5MHz – 1 ± 0.1 +1 LSBOffset error
(1)
– 0.75 0.2 +0.75 %FSOffset temperature coefficient
(2)
± 6 ppm/ °CFixed attenuation in channel
(3)
1 %FSFixed attenuation matching across channels 0.01 0.2 dBGain error/reference error
(4)
– 3.5 ± 1.0 +3.5 % FSGain error temperature coefficient ± 40 ppm/ °C
POWER REQUIREMENTS
(5)
Internal Reference
Power dissipation
(5)
Analog only (AVDD) 260 297 mWOutput driver (VDRV) 106 136 mWTotal power dissipation 366 433 mW
External Reference
Power dissipation Analog only (AVDD) 224 mWOutput driver (VDRV) 106 mWTotal power dissipation 330 mWVREF
T
1.875 2 2.05 mWVREF
B
0.95 1 1.125 mW
Total Power-Down 88 mW
REFERENCE VOLTAGES
VREF
T
Reference top (internal) 1.9 2.0 2.1 VVREF
B
Reference bottom (internal) 0.9 1.0 1.1 VV
CM
Common-mode voltage 1.4 1.5 1.6 VV
CM
output current
(6)
± 50mV change in voltage ± 2 mAVREF
T
Reference top (external) 1.875 VVREF
B
Reference bottom (external) 1.125 VExternal reference common-mode V
CM
± 50mV VExternal reference input current
(7)
1.0 mA
(1) Offset error is the deviation of the average code from mid-code with – 1dBFS sinusoid from ideal mid-code (512). Offset error isexpressed in terms of percent of full-scale.(2) If the offset at temperatures T
1
and T
2
is O
1
and O
2
, respectively (where O
1
and O
2
are measured in LSBs), the offset temperaturecoefficient in ppm/ °C is calculated as (O
1
– O
2
)/(T
1
– T
2
)×1
6
/1024.(3) Fixed attenuation in the channel arises because of a fixed attenuation in the sample-and-hold amplifier. When the differential voltage atthe analog input pins is changed from – V
REF
to +V
REF
, the swing of the output code is expected to deviate from the full-scale code(1024LSB) by the extent of this fixed attenuation. NOTE: V
REF
is defined as (REF
T
– REF
B
).(4) The reference voltages are trimmed at production so that (VREF
T
– VREF
B
) is within ± 35mV of the ideal value of 1V. This specificationdoes not include fixed attenuation.(5) Supply current can be calculated from dividing the power dissipation by the supply voltage of 3.3V.(6) The V
CM
output current specified is the drive of the V
CM
buffer if loaded externally.(7) Average current drawn from the reference pins in the external reference mode.
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ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)T
MIN
= – 40 °C and T
MAX
= +85 °C. Typical values are at T
A
= +25 °C, clock frequency = 65MSPS, 50% clock duty cycle,AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, – 1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unlessotherwise noted.
ADS5237
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Differential input capacitance 3 pFAnalog input common-mode range V
CM
± 0.05 VDifferential input voltage range Internal reference 2.02 V
PP
External reference 2.02 ×(VREF
T
– VREF
B
) V
PP
Voltage overload recovery time
(8)
3 CLK
cycles– 3dBFS input, 25 ΩseriesInput bandwidth 300 MHzresistance
DIGITAL DATA INPUTS
Logic family +3V CMOS CompatibleV
IH
High-level input voltage V
IN
= 3.3V 2.2 VV
IL
Low-level input voltage V
IN
= 3.3V 0.6 VC
IN
Input capacitance 3 pF
DIGITAL OUTPUTS
Data format Straight offset binary
(9)
Logic family CMOSLogic coding Straight offset binary or BTCLow output voltage (I
OL
= 50 μA) +0.4 VHigh output voltage (I
OH
= 50 μA) +2.4 V3-state enable time 2 Clocks3-state disable time 2 ClocksOutput capacitance 3 pF
SERIAL INTERFACE
SCLK Serial clock input frequency 20 MHz
CONVERSION CHARACTERISTICS
Sample rate 20 65 MSPSData latency 6 CLK
cycles
(8) A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice thefull-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of theADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code valuewhen the pulse is switched from ON (high) to OFF (low).(9) Option for binary two ’ s complement output.
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AC CHARACTERISTICS
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
T
MIN
= – 40 °C and T
MAX
= +85 °C. Typical values are at T
A
= +25 °C, clock frequency = maximum specified, 50% clock dutycycle, AVDD = 3.3V, VDRV = 3.3V, – 1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unless otherwise noted.
ADS5237
PARAMETER CONDITIONS MIN TYP MAX UNIT
DYNAMIC CHARACTERISTICS
f
IN
= 5MHz 75 86 dBc
SFDR Spurious-free dynamic range f
IN
= 32.5MHz 85 dBc
f
IN
= 70MHz 83 dBc
f
IN
= 5MHz 82 92 dBc
HD
2
2nd-order harmonic distortion f
IN
= 32.5MHz 87 dBc
f
IN
= 70MHz 85 dBc
f
IN
= 5MHz 75 86 dBc
HD
3
3rd-order harmonic distortion f
IN
= 32.5MHz 85 dBc
f
IN
= 70MHz 83 dBc
f
IN
= 5MHz 60.5 61.7 dBFS
SNR Signal-to-noise ratio f
IN
= 32.5MHz 61.0 dBFS
f
IN
= 70MHz 60.7 dBFS
f
IN
= 5MHz 60.4 61.6 dBFS
SINAD Signal-to-noise and distortion f
IN
= 32.5MHz 60.9 dBFS
f
IN
= 70MHz 60.5 dBFS
5MHz full-scale signal applied to one channel;Crosstalk – 85 dBcmeasurement taken on the channel with no input signal
f
1
= 4MHz at – 7dBFSTwo-tone, third-orderIMD3 90.9 dBFSintermodulation distortion
f
2
= 5MHz at – 7dBFS
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TIMING DIAGRAMS
Analog
Input
CLK
DATA[D9:D0]
DV
OE
DATA D9:D0
tOE
tOE
tDV
t1t2
tC
tA
N+1
N+2 N+4
N+3
N
TIMING CHARACTERISTICS
(1)
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
Typical values at T
A
= +25 °C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% dutycycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER MIN TYP MAX UNITS
65MSPS With PLL ON
t
A
Aperture delay 2.1 ns
Aperture jitter 1.0 ps
t
1
Data setup time
(2)
2 3.2 ns
t
2
Data hold time
(3)
6.3 8.5 ns
t
D
Data latency 6 Clocks
t
DR
, t
DF
Data rise/fall time
(4)
0.5 2 3 ns
Data valid (DV) duty cycle 30 40 55 %
t
DV
Input clock rising to DV fall edge 10 11.5 14 ns
(1) Specifications assured by design and characterization; not production tested.(2) Measured from data becoming valid (at a high level = 2.0V and a low level = 0.8V) to the 50% point of the falling edge of DV.(3) Measured from the 50% point of the falling edge of DV to the data becoming invalid.(4) Measured between 20% to 80% of logic levels.
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ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
TIMING CHARACTERISTICS (continued)Typical values at T
A
= +25 °C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% dutycycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER MIN TYP MAX UNITS
50MSPS With PLL ON
t
A
Aperture delay 2.1 ns
Aperture jitter 1.0 ps
t
1
Data setup time 3.2 4.5 ns
t
2
Data hold time 10 11 ns
t
D
Data latency 6 Clocks
t
DR
, t
DF
Data rise/fall time 0.5 2 3 ns
Data valid (DV) duty cycle 30 40 55 %
t
DV
Input clock rising to DV fall edge 11.5 13.5 15.5 ns
40MSPS With PLL ON
t
A
Aperture delay 2.1 ns
Aperture jitter 1.0 ps
t
1
Data setup time 3.7 5.5 ns
t
2
Data hold time 11.5 13.5 ns
t
D
Data latency 6 Clocks
t
DR
, t
DF
Data rise/fall time 0.5 2 3 ns
Data valid (DV) duty cycle 30 40 55 %
t
DV
Input clock rising to DV fall edge 13.5 16 18.5 ns
30MSPS With PLL OFF
t
A
Aperture delay 2.1 ns
Aperture jitter 1.0 ps
t
1
Data setup time 8 10 ns
t
2
Data hold time 14 19 ns
t
D
Data latency 6 Clocks
t
DR
, t
DF
Data rise/fall time 0.5 2 3.5 ns
Data valid (DV) duty cycle 30 45 55 %
t
DV
Input clock rising to DV fall edge 16 19 21 ns
20MSPS With PLL ON
t
A
Aperture delay 2.1 ns
Aperture jitter 1.0 ps
t
1
Data setup time 10 12 ns
t
2
Data hold time 20 25 ns
t
D
Data latency 6 Clocks
t
DR
, t
DF
Data rise/fall time 0.5 2 3.5 ns
Data valid (DV) duty cycle 30 45 55 %
t
DV
Input clock rising to DV fall edge 20 25 30 ns
20MSPS With PLL OFF
t
A
Aperture delay 2.1 ns
Aperture jitter 1.0 ps
t
1
Data setup time 10 12 ns
t
2
Data hold time 20 25 ns
t
D
Data latency 6 Clocks
t
DR
, t
DF
Data rise/fall time 0.5 2 3.5 ns
Data valid (DV) duty cycle 30 45 55 %
t
DV
Input clock rising to DV fall edge 20 25 30 ns
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StartSequence
t1t7
t6
D7
(MSB) D6 D5 D4 D3 D2 D1 D0
t2
t3
t4
t5
CLK
SEN
SCLK
SDATA
Outputschangeon
nextrisingclockedge
afterSENgoeshigh.
Datalatchedon
eachrisingedgeofSCLK.
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
TIMING CHARACTERISTICS (continued)Typical values at T
A
= +25 °C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% dutycycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER MIN TYP MAX UNITS
2MSPS With PLL OFF
t
A
Aperture delay 2.1 ns
Aperture jitter 1.0 ps
t
1
Data setup time 150 200 ns
t
2
Data hold time 200 250 ns
t
D
Data latency 6 Clocks
t
DR
, t
DF
Data rise/fall time 0.5 2 3.5 ns
Data valid (DV) duty cycle 30 45 55 %
t
DV
Input clock rising to DV fall edge 200 225 250 ns
SERIAL INTERFACE TIMING
NOTE: Data are shifted in MSB first.
ADS5237
PARAMETER DESCRIPTION MIN TYP MAX UNIT
t
1
Serial CLK period 50 nst
2
Serial CLK high time 20 nst
3
Serial CLK low time 20 nst
4
Data setup time 5 nst
5
Data hold time 5 nst
6
SEN fall to SCLK rise 8 nst
7
SCLK rise to SEN rise 8 ns
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ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
Table 1. SERIAL REGISTER MAP
(1) (2)
ADDRESS DATA DESCRIPTION
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 X X X 0Normal mode
0 0 0 0 X X X 1Power-down both channels
0 0 0 0 X X 0X Straight offset binary output
0 0 0 0 X X 1X Binary two's complement output
0000X0X X Channel B digital outputs enabled
0000X1X X Channel B digital outputs 3-stated
00000X X X Channel A digital outputs enabled
00001X X X Channel A digital outputs 3-stated
00100 0 0 0 Normal mode
00100 1 0 0 All digital outputs set to '1'
00101 0 0 0 All digital outputs set to '0'
00110 0 X 0 Normal mode
00111 X X 0 Channel A powered down
0011X 1 X 0 Channel B powered down
0 0 1 1 X X 00 PLL enabled (default)
0 0 1 1 X X 10 PLL disabled
(1) X = do not care.(2) Shown for the case where serial interface is used.
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RECOMMENDED POWER-UP SEQUENCING
t1
t3
t5t6
t4t7
t8
t2
AVDD(3Vto3.6V)
VDRV(3Vto3.6V)
DeviceReady
ForADCOperation
DeviceReady
ForADCOperation
DeviceReady
ForSerialRegisterWrite
StartofClock
AVDD
VDRV
SEL
SEN
CLK
STPD
DeviceFully
PowersDown
DeviceFully
PowersUp
500 sm
1 sm
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
Shown for the case where the serial interface is used.
NOTE: 10 μs < t
1
< 50ms; 10 μs < t
2
< 50ms; – 10ms < t
3
< 10ms; t
4
> 10ms; t
5
> 100ns; t
6
> 100ns; t
7
> 10ms; and t
8
> 100 μs.
POWER-DOWN TIMING
NOTE: The shown power-up time is based on 1 μF bypass capacitors on the reference pins. See the Theory of Operation section for details.
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PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AGND
AGND
AVDD
STPD/SDATA
GND
VDRV
OE /SCLK
A
MSBI/SEN
VDRV
OVRA
D9_A(MSB)
D8_A
D7_A
D6_A
D5_A
D4_A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SEL
AGND
AVDD
GND
VDRV
OEB
GND
VDRV
OVRB
NC
NC
D0_B(LSB)
D1_B
D2_B
D3_B
D4_B
AGND
INB+
INB-
AGND
ISET
AGND
AGND
AVDD
INT/EXT
AGND
REFB
REFT
CM
INA-
INA+
AGND
D5_B
D6_B
D7_B
D8_B
D9_B(MSB)
DVB
GND
CLK
GND
DVA
NC
NC
D0_A(LSB)
D1_A
D2_A
D3_A
64 63 62 61 60 59 58 57 56 55 54
17 18 19 20 21 22 23 24 25 26 27
53 52 51 50 49
28 29 30 31 32
ADS5237
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
TQFP-64
(Top View)
Table 2. TERMINAL FUNCTIONSNAME PIN # I/O DESCRIPTION
AGND 2, 47 – 49, 55, 58, 59, 61, 64 Analog ground
AVDD 3, 46, 57 Analog supply
CLK 24 I Clock input
CM 52 O Common-mode voltage output
D0_A (LSB) 29 O Data bit 10 (D0), channel A
D1_A 30 O Data bit 9 (D1), channel A
D2_A 31 O Data bit 8 (D2), channel A
D3_A 32 O Data bit 7 (D3), channel A
D4_A 33 O Data bit 6 (D4), channel A
D5_A 34 O Data bit 5 (D5), channel A
D6_A 35 O Data bit 4 (D6), channel A
D7_A 36 O Data bit 3 (D7), channel A
D8_A 37 O Data bit 2 (D8), channel A
D9_A (MSB) 38 O Data bit 1 (D9), channel A
D0_B (LSB) 12 O Data bit 10 (D0), channel B
D1_B 13 O Data bit 9 (D1), channel B
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ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
Table 2. TERMINAL FUNCTIONS (continued)NAME PIN # I/O DESCRIPTION
D2_B 14 O Data bit 8 (D2), channel B
D3_B 15 O Data bit 7 (D3), channel B
D4_B 16 O Data bit 6 (D4), channel B
D5_B 17 O Data bit 5 (D5), channel B
D6_B 18 O Data bit 4 (D6), channel B
D7_B 19 O Data bit 3 (D7), channel B
D8_B 20 O Data bit 2 (D8), channel B
D9_B (MSB) 21 O Data bit 1 (D9), channel B
DV
A
26 O Data valid, channel A
DV
B
22 O Data valid, channel B
GND 4, 7, 23, 25, 44 Output buffer ground
IN
A
50 I Analog input, channel A
IN
A
51 I Complementary analog input, channel A
IN
B
63 I Analog input, channel B
IN
B
62 I Complementary analog input, channel B
INT/ EXT 56 I Reference select; 0 = External (default), 1 = Internal; force high to set for internal reference operation.
I
SET
60 O Bias current setting resistor of 56.2k Ωto ground
When SEL = 0, MSBI (most significant bit Invert)MSBI/SEN 41 I 1 = Binary two's complement, 0 = Straight offset binary (default)When SEL = 1, SEN (serial write enable)
NC 10, 11, 27, 28
When SEL = 0, OE
A
(output enable channel A)OE
A
/SCLK 42 I 0 = Enabled (default), 1 = 3-stateWhen SEL = 1, SCLK (serial write clock)
OE
B
6 I Output enable, channel B (0 = Enabled [default], 1 = 3-state)
OVR
A
39 O Over-range Indicator, channel A
OVR
B
9 O Over-range Indicator, channel B
REF
B
54 I/O Bottom reference/bypass (2 Ωresistor in series with a 0.1 μF capacitor to ground)
REF
T
53 I/O Top reference/bypass (2 Ωresistor in series with a 0.1 μF capacitor to ground)
Serial interface select signal. Setting SEL = 0 configures pins 41, 42, and 45 as MSBI, OE
A
, andSTPD, respectively. With SEL = 0, the serial interface is disabled. Setting SEL = 1 enables the serialinterface and configures pins 41, 42, and 45 as SEN, SCLK, and SDATA, respectively. SerialSEL 1 I
registers can be programmed using these three signals. When used in this mode of operation, it isessential to provide a low-going pulse on SEL in order to reset the serial interface registers as soonas the device is powered up. SEL therefore also has the functionality of a RESET signal.
When SEL = 0, STPD (power-down)STPD/SDATA 45 I 0 = Normal operation (default), 1 = EnabledWhen SEL = 1, SDATA (serial write data)
VDRV 5, 8, 40, 43 Output buffer supply
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
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DEFINITION OF SPECIFICATIONS
Minimum Conversion RateAnalog Bandwidth
Signal-to-Noise and Distortion (SINAD)
Aperture Delay
Aperture Uncertainty (Jitter)
Clock Duty Cycle
Signal-to-Noise Ratio (SNR)
Differential Nonlinearity (DNL)
SNR=10Log10
PS
PN
Spurious-Free Dynamic RangeEffective Number of Bits (ENOB)
ENOB= SINAD 1.76-
6.02
Two-Tone, Third-Order Intermodulation
Integral Nonlinearity (INL)
Maximum Conversion Rate
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
This is the minimum sampling rate where the ADCstill works.The analog input frequency at which the spectralpower of the fundamental frequency (as determinedby FFT analysis) is reduced by 3dB.
SINAD is the ratio of the power of the fundamental(P
S
) to the power of all the other spectral componentsincluding noise (P
N
) and distortion (P
D
), but notThe delay in time between the rising edge of the input
including dc.sampling clock and the actual time at which thesampling occurs.
SINAD is either given in units of dBc (dB to carrier)The sample-to-sample variation in aperture delay.
when the absolute power of the fundamental is usedas the reference, or dBFS (dB to full-scale) when thepower of the fundamental is extrapolated to thePulse width high is the minimum amount of time that
full-scale range of the converter.the ADCLK pulse should be left in logic ‘ 1 ’ state toachieve rated performance. Pulse width low is theminimum time that the ADCLK pulse should be left in
SNR is the ratio of the power of the fundamental (P
S
)a low state (logic ‘ 0 ’ ). At a given clock rate, these
to the noise floor power (P
N
), excluding the power atspecifications define an acceptable clock duty cycle.
dc and the first eight harmonics.
An ideal ADC exhibits code transitions that areexactly 1 LSB apart. DNL is the deviation of any
SNR is either given in units of dBc (dB to carrier)single LSB transition at the digital output from an
when the absolute power of the fundamental is usedideal 1 LSB step at the analog input. If a device
as the reference, or dBFS (dB to full-scale) when theclaims to have no missing codes, it means that all
power of the fundamental is extrapolated to thepossible codes (for a 10-bit converter, 1024 codes)
full-scale range of the converter.are present over the full operating range.
The ratio of the power of the fundamental to theThe ENOB is a measure of converter performance as
highest other spectral component (either spur orcompared to the theoretical limit based on
harmonic). SFDR is typically given in units of dBc (dBquantization noise.
to carrier).
Distortion
Two-tone IMD3 is the ratio of power of theINL is the deviation of the transfer function from a
fundamental (at frequencies f
1
and f
2
) to the power ofreference line measured in fractions of 1 LSB using a
the worst spectral component of third-orderbest straight line or best fit determined by a least
intermodulation distortion at either frequency 2f
1
– f
2square curve fit. INL is independent from effects of
or 2f
2
– f
1
. IMD3 is either given in units of dBc (dB tooffset, gain or quantization errors.
carrier) when the absolute power of the fundamentalis used as the reference, or dBFS (dB to full-scale)when the power of the fundamental is extrapolated tothe full-scale range of the converter.The encode rate at which parametric testing isperformed. This is the maximum sampling rate wherecertified operation is given.
14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS
Amplitude(dBFS)
InputFrequency(MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
025 305 10 15 20 32.5
SNR=61.8dBFS
fIN =1MHz, -1dBFS
SINAD=61.7dBFS
SFDR=84dBc
16kPointData,16Averages
Amplitude(dBFS)
InputFrequency(MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
025 305 10 15 20 32.5
fIN =5MHz, -1dBFS
SNR=61.7dBFS
SINAD=61.7dBFS
SFDR=85dBc
16kPointData,16Averages
Amplitude(dBFS)
InputFrequency(MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
025 305 10 15 20 32.5
fIN =20MHz, -1dBFS
SNR=61.6dBFS
SINAD=61.6dBFS
SFDR=81dBc
16kPointData,16Averages
Amplitude(dBFS)
InputFrequency(MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
025 305 10 15 20 32.5
f =9.5MHz
1
f =10.2MHz
2
2-ToneIMD=93dBFS
16k-PointData
16Averages
INL(LSB)
Code
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
0384 512 640 768 896128 256 1024
fIN =5MHz
DNL(LSB)
Code
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
0768256 512 1024
f =5MHz
IN
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
T
MIN
= – 40 °C and T
MAX
= +85 °C. Typical values are at T
A
= +25 °C, clock frequency = 65MSPS, 50% clock duty cycle,AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, – 1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unlessotherwise noted.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
Figure 1. Figure 2.
SPECTRAL PERFORMANCE INTERMODULATION DISTORTION
Figure 3. Figure 4.
DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY
Figure 5. Figure 6.
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IAVDD,IDVDD(mA)
SampleRate(MHz)
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
20 25 30 35 40 45 50 55 60 65 70
f =5MHz
IN
IAVDD
IVDRV
Signal-to-NoiseRatio(dBFS)
InputFrequency(MHz)
64
63
62
61
60
59
58
57
56
070
ExternalReference
REF =1.95V
T
REF =0.95V
B
10 20 30 40 50 60
Spurious-FreeDynamicRange(dBc)
InputFrequency(MHz)
95
90
85
80
75
70
65
60
070
ExternalReference
REF =1.95V
T
REF =0.95V
B
10 20 30 40 50 60
Signal-to-NoiseRatio(dBFS)
InputFrequency(MHz)
66
64
62
60
58
56
54
070
10 20 30 40 50 60
InternalReference
Spurious-FreeDynamicRange(dBc)
InputFrequency(MHz)
95
90
85
80
75
70
65
60
070
10 20 30 40 50 60
InternalReference
SNR(dBFS),SFDR(dBc)
DutyCycle(%)
95
90
85
80
75
70
65
60
30 35 50 55 60 6540 45 70
f =5MHz
IN
SNR
SFDR
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)T
MIN
= – 40 °C and T
MAX
= +85 °C. Typical values are at T
A
= +25 °C, clock frequency = 65MSPS, 50% clock duty cycle,AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, – 1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unlessotherwise noted.
IAVDD, IVDRV vs CLOCK FREQUENCY SNR vs INPUT FREQUENCY
Figure 7. Figure 8.
SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY
Figure 9. Figure 10.
DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLESFDR vs INPUT FREQUENCY WITH PLL ENABLED (default)
Figure 11. Figure 12.
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SNR(dBFS),SFDR(dBc)
Temperature( C)°
95
90
85
80
75
70
65
60
55
-40 -15 +60+10 +35 +85
f =5MHz
IN
SNR
SFDR
PowerDissipation(mW)
Temperature( C)°
405
390
375
360
345
330
-40 +10 +35 +60-15 +85
f =5MHz
IN
SNR(dBFS,dBc)
InputAmplitude(dBFS)
70
60
50
40
30
20
10
0
-50 -30 -20 -10-40 0
f =10MHz
IN
dBFS
dBc
SFDR(dBc,dBFS)
InputAmplitude(dBFS)
90
80
70
60
50
40
30
20
10
0
-50 -30 -20 -10-40 0
f =10MHz
IN
dBFS
dBc
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)T
MIN
= – 40 °C and T
MAX
= +85 °C. Typical values are at T
A
= +25 °C, clock frequency = 65MSPS, 50% clock duty cycle,AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, – 1dBFS, I
SET
= 56.2k Ω, and internal voltage reference, unlessotherwise noted.
DYNAMIC PERFORMANCE vs TEMPERATURE POWER DISSIPATION vs TEMPERATURE
Figure 13. Figure 14.
SWEPT POWER — SNR SWEPT POWER — SFDR
Figure 15. Figure 16.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 17
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APPLICATION INFORMATION
THEORY OF OPERATION INPUT CONFIGURATION
INPUT DRIVER CONFIGURATIONS
Transformer-Coupled Interface
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
The ADS5237 is a dual-channel, simultaneous The analog input for the ADS5237 consists of asampling analog-to-digital converter (ADC). Its low differential sample-and-hold architecture implementedpower and high sampling rate of 65MSPS are using a switched capacitor technique; see Figure 17 .achieved using a state-of-the-art switched capacitor The sampling circuit consists of a low-pass RC filterpipeline architecture built on an advanced low-voltage at the input to filter out noise components thatCMOS process. The ADS5237 operates from a +3.3V potentially could be differentially coupled on the inputsupply voltage for both its analog and digital supply pins. The inputs are sampled on two 4pF capacitors.connections. The ADC core of each channel consists The RLC model is illustrated in Figure 17 .of a combination of multi-bit and single-bit internalpipeline stages. Each stage feeds its data into thedigital error correction logic, ensuring excellentdifferential linearity and no missing codes at the10-bit level. The conversion process is initiated by the
If the application requires a signal conversion from arising edge of the external clock. Once the signal is
single-ended source to drive the ADS5237captured by the input sample-and-hold amplifier, the
differentially, an RF transformer could be a goodinput sample is sequentially converted within the
solution. The selected transformer must have apipeline stages. This process results in a data latency
center tap in order to apply the common-mode dcof six clock cycles, after which the output data is
voltage (V
CM
) necessary to bias the converter inputs.available as a 10-bit parallel word, coded in either
AC grounding the center tap generates the differentialstraight offset binary (SOB) or binary two's
signal swing across the secondary winding. Considercomplement (BTC) format. Because a common clock
a step-up transformer to take advantage of signalcontrols the timing of both channels, the analog
amplification without the introduction of another noisesignal is sampled simultaneously. Data on the parallel
source. Furthermore, the reduced signal swing fromports are updated simultaneously as well. Further
the source may lead to improved distortionprocessing can be timed using the individual data
performance. The differential input configuration mayvalid output signal of each channel. The ADS5237
provide a noticeable advantage for achieving goodfeatures internal references that are trimmed to
SFDR performance over a wide range of inputensure a high level of accuracy and matching. The
frequencies. In this mode, both inputs (IN and IN) ofinternal references can be disabled to allow for
the ADS5237 see matched impedances.external reference operation.
Figure 18 illustrates the schematic for the suggestedtransformer-coupled interface circuit. The componentvalues of the RC low-pass filter may be optimized,depending on the desired roll-off frequency.
18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
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5nH
to9nH
3.2pF
to4.8pF
IN OUT
INP
1.5pFto
2.5pF
1W
15W
to25W
5nH
to9nH
INN
1.5pFto
2.5pF
1W
15W
to25W
60W
to120W
1.5pF
to1.9pF
IN OUT
3.2pF
to4.8pF
IN OUT
15W
to25W
15W
to25W
60W
to120W
IN OUT
IN
OUT
15 to35W W
IN OUT
IN OUT
OUTP
OUTN
SwitchesthatareON
inSAMPLEphase.
SwitchesthatareON
inHOLDphase.
VIN
IN
IN CM
+1.5V
24.9W
24.9W
0.1 Fm
22pF
RT
1:n
0.1 Fm
RG
R2
R1
OPA690
49.9W
1/2
ADS5237
OneChannelofTwo
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
Figure 17. Input Circuitry
Figure 18. Converting a Single-Ended Input Signal into a Differential Signal Using an RF-Transformer
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 19
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DC-Coupled Input with Differential Amplifier
REFERENCE CIRCUIT
Internal Reference
1 Fm
CF
CF
1/2
ADS5237
THS4503
RISO
RISO
RS
VS
RG
RT
RF
RF
VOCM
10 Fm0.1 Fm
0.1 Fm
IN
IN
CM
RG
AVDD
+5V
REFTCM REFB
ISET
INT/EXTADS5237
0.1 Fm2.2 Fm
+ +
2W2W
56kW
AVDD
2.2 Fm0.1 Fm
Input Over-Voltage Recovery
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
Applications that have a requirement for DC-couplinga differential amplifier, such as the THS4503 , can beused to drive the ADS5237; this design is shown in
All bias currents required for the proper operation ofFigure 19 . The THS4503 amplifier easily allows a
the ADS5237 are set using an external resistor at I
SETsingle-ended to differential conversion, which reduces
(pin 60), as shown in Figure 20 . Using a 56.2k Ωcomponent cost.
resistor on I
SET
generates an internal referencecurrent of about 20 μA. This current is mirroredinternally to generate the bias current for the internalblocks. While a 5% resistor tolerance is adequate,deviating from this resistor value alters and degradesdevice performance. For example, using a largerexternal resistor at I
SET
reduces the reference biascurrent and thereby scales down the device operatingpower.
Figure 19. Using the THS4503 with the ADS5237
In addition, the V
OCM
pin on the THS4503 can bedirectly tied to the common-mode pin (CM) of theADS5237 to set up the necessary bias voltage for theconverter inputs. In the circuit example shown inFigure 19 , the THS4503 is configured for unity gain. Ifrequired, a higher gain can easily be achieved as wellby adding small capacitors (such as 10pF) in parallel
Figure 20. Internal Reference Circuitwith the feedback resistors to create a low-pass filter.Because the THS4503 is driving a capacitive load,
As part of the internal reference circuit, the ADS5237small series resistors in the output ensure stable
provides a common-mode voltage output at pin 52,operation. Further details of this design and the
CM. This common-mode voltage is typically +1.5V.overall operation of the THS4503 may be found in its
While this voltage is similar to the common-modeproduct data sheet (available for download at
voltage used internally within the ADC pipeline core,www.ti.com ). In general, differential amplifiers provide
the CM pin has an independent buffer amplifier,a high-performance driver solution for baseband
which can deliver up to ± 2mA of current to anapplications, and other differential amplifier models
external circuit for proper input signal level shiftingmay be selected depending on the system
and biasing. In order to obtain optimum dynamicrequirements.
performance, the analog inputs should be biased tothe recommended common-mode voltage (1.5V).While good performance can be maintained over aThe differential full-scale input range supported by the
certain CM-range, larger deviations may compromiseADS5237 is 2V
PP
. For a nominal value of V
CM
device performance and could also negatively affect(+1.5V), IN and IN can swing from 1V to 2V. The
the overload recovery behavior. Using the internalADS5237 is especially designed to handle an
reference mode requires the INT/ EXT pin to beover-voltage differential peak-to-peak voltage of 4V
forced high, as shown in Figure 20 .(2.5V and 0.5V swings on IN and IN). If the input
The ADS5237 requires solid high-frequencycommon-mode voltage is not considerably different
bypassing on both reference pins, REF
T
and REF
B
;from V
CM
during overload (less than 300mV),
see Figure 20 . Use ceramic 0.1 μF capacitors (sizerecovery from an over-voltage input condition is
0603, or smaller), located as close as possible to theexpected to be within three clock cycles. All of the
pins.amplifiers in the sample-and-hold stage and the ADCcore are especially designed for excellent recoveryfrom an overload signal.
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External Reference
SNR=20Log10
1
(2 f t )pIN JA
(1)
PLL CONTROL
OUTPUT INFORMATION
CLOCK INPUT
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
IF-sampling applications; for example, where thesampling frequency is lower than the input frequencyThe ADS5237 also supports the use of external
(under-sampling). The following equation can be usedreference voltages. External reference voltage mode
to calculate the achievable SNR for a given inputinvolves applying an external top reference at REF
T
frequency and clock jitter (t
JA
in ps
RMS
):(pin 53) and a bottom reference at REF
B
(pin 54).Setting the ADS5237 for external reference modealso requires taking the INT/ EXT pin low. In thismode, the internal reference buffer is 3-stated.
The ADS5237 enters into a power-down mode if theBecause the switching current for the two ADC
sampling clock rate drops below a limit ofchannels comes from the externally-forced
approximately 2MSPS. If the sampling rate isreferences, it is possible for the device performance
increased above this threshold, the ADS5237to be slightly lower than when the internal references
automatically resumes normal operation.are used. It should be noted that in external referencemode, V
CM
and I
SET
continue to be generated fromthe internal bandgap voltage, as they are in theinternal reference mode. Therefore, it is important to
The ADS5237 has an internal PLL that is enabled byensure that the common-mode voltage of the
default. The PLL enables a wide range of clock dutyexternally-forced reference voltages matches to
cycles. Good performance is obtained for duty cycleswithin 50mV of V
CM
(+1.5V
DC
).
up to 40% – 60%, though the ensured electricalspecifications presume that the duty cycle is betweenThe external reference circuit must be designed to
45% – 55%. The PLL automatically limits the minimumdrive the internal reference impedance seen between
frequency of operation to 20MSPS. For operationthe REF
T
and REF
B
pins. To establish the drive
below 20MSPS, the PLL can be disabled byrequirements, consider that the external reference
programming the internal registers through the serialcircuit needs to supply an average switching current
interface. With the PLL disabled, the clock speed canof at least 1mA. This dynamic switching current
go down to 2MSPS. With the PLL disabled, the clockdepends on the actual device sampling rate and the
duty cycle needs to be constrained closer to 50%.signal level. The external reference voltages can varyas long as the value of the external top referencestays within the range of +1.875V to +2.0V, and theexternal bottom reference stays within +1.0V to
The ADS5237 provides two channels with 10 data+1.125V. Consequently, the full-scale input range can
outputs (D9 to D0, with D9 being the MSB and D0 thebe set between 1.5V
PP
and 2V
PP
(FSR = 2x [REF
T
–
LSB), data-valid outputs (DV
A
, DV
B
, pin 26 and pinREF
B
] ).
22, respectively), and individual out-of-range indicatoroutput pins (OVR
A
/OVR
B
, pin 39 and pin 9,respectively).The ADS5237 requires a single-ended clock source.
The output circuitry of the ADS5237 has beenThe clock input, CLK, represents a CMOS-compatible
designed to minimize the noise produced bylogic input with an input impedance of about 5pF. For
transients of the data switching, and in particular itshigh input frequency sampling, it is recommended to
coupling to the ADC analog circuitry.use a clock source with very low jitter. A low-jitterclock is essential in order to preserve the excellent acperformance of the ADS5237. The converter itself isspecified for a low 1.0ps (rms) jitter. Generally, as theinput frequency increases, clock jitter becomes moredominant in maintaining a good signal-to-noise ratio(SNR). This condition is particularly critical in
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 21
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DATA OUTPUT FORMAT (MSBI)
OUTPUT LOADING
OUTPUT ENABLE ( OE)
SERIAL INTERFACE
OVER-RANGE INDICATOR (OVR)
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
range. It changes to high if the applied signalexceeds the full-scale range. It should be noted thatThe ADS5237 makes two data output formats
each of the OVR outputs is updated along with theavailable: the Straight Offset Binary code (SOB) or
data output corresponding to the particular sampledthe Binary Two's Complement code (BTC). The
analog input voltage. Therefore, the OVR state isselection of the output coding is controlled by the
subject to the same pipeline delay as the digital dataMSBI (pin 41). Because the MSBI pin has an internal
(six clock cycles).pull-down, the ADS5237 operates with the SOB codeas its default setting. Forcing the MSBI pin highenables BTC coding. The two code structures areidentical, with the exception that the MSB is inverted
It is recommended that the capacitive loading on thefor BTC format, as shown in Table 3 .
data output lines be kept as low as possible,preferably below 15pF. Higher capacitive loadingcauses larger dynamic currents as the digital outputsare changing. Such high current surges can feedDigital outputs of the ADS5237 can be set to
back to the analog portion of the ADS5237 andhigh-impedance (3-state), exercising the output
adversely affect device performance. If necessary,enable pins, OE
A
(pin 42), and OE
B
(pin 6). Internal
external buffers or latches close to the converterpull-downs configure the output in enable mode for
output pins may be used to minimize the capacitivenormal operation. Applying a logic high voltage
loading.disables the outputs. Note that the OE-function is notdesigned to be operated dynamically (that is, as afast multiplexer) because it may lead to corruptconversion results. Refer to the Electrical
The ADS5237 has a serial interface that can be usedCharacteristics table to observe the specified 3-state
to program internal registers. The serial interface isenable and disable times.
disabled if SEL is connected to '0'.
When the serial interface is to be enabled, SELserves the function of a RESET signal. After theIf the analog input voltage exceeds the full-scale supplies have stabilized, it is necessary to give therange set by the reference voltages, an over-range device a low-going pulse on SEL. This pulse resultscondition exists. The ADS5237 incorporates a in all internal registers resetting to the default value offunction that monitors the input voltage and detects '0' (inactive). Without a reset, it is possible thatany such out-of-range condition. This operation registers may be in the non-default state onfunctions for each of the two channels independently. power-up. This condition may cause the device toThe current state can be read at the over-range malfunction.indicator pins (pins 9 and 39). This output is lowwhen the input voltage is within the defined input
Table 3. Coding Table for Differential Input Configuration and 2V
PP
Full-Scale Input Range
STRAIGHT OFFSET BINARY (SOB; MSBI = 0) BINARY TWO'S COMPLEMENT (BTC; MSBI = 1)
DIFFERENTIAL INPUT D9............D0 D9............D0
+FS (IN = +2V, IN = +1V) 1111 1111 11 0111 1111 11+1/2 FS 1100 0000 00 0100 0000 00Bipolar Zero (IN = IN = CMV) 1000 0000 00 0000 0000 00– 1/2 FS 0100 0000 00 1100 0000 00– FS (IN = +1V, IN = +2V) 0000 0000 00 1000 0000 00
22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS5237
www.ti.com
POWER-DOWN MODE
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
capacitances on REF
T
and REF
B
less than 1 μF, thereference voltages settle to within 1% of theirThe ADS5237 has a power-down pin, STPD (pin 45).
steady-state values in less than 500 μs. Either of theThe internal pull-down is in default mode for the
two channels can also be selectively powered-downdevice during normal operation. Forcing the STPD pin
through the serial interface when it is enabled.high causes the device to enter into power-downmode. In power-down mode, the reference and clock The ADS5237 also has an internal circuit thatcircuitry as well as all the channels are powered monitors the state of stopped clocks. If ADCLK isdown. Device power consumption drops to less than stopped for longer than 250ns, or if it runs at a speed90mW. As previously mentioned, the ADS5237 also less than 2MHz, this monitoring circuit generates aenters into a power-down mode if the clock speed logic signal that puts the device in a partialdrops below 2MSPS (see the Clock Input section). power-down state. As a result, the powerconsumption of the device is reduced when CLK isWhen STPD is pulled high, the internal buffers driving
stopped. The recovery from such a partialREF
T
and REF
B
are 3-stated and the outputs are
power-down takes approximately 100 μs. Thisforced to a voltage roughly equal to half of the
constraint is described in Table 4 .voltage on AV
DD
. Speed of recovery from thepower-down mode depends on the value of theexternal capacitance on the REF
T
and REF
B
pins. For
Table 4. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage
DESCRIPTION TYP REMARKS
Recovery from power-down mode (STPD = 1 to STPD = 0). 500 μs Capacitors on REF
T
and REF
B
less than 1 μF.Recovery from momentary clock stoppage ( < 250ns). 10 μsRecovery from extended clock stoppage ( > 250ns). 100 μs
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): ADS5237
www.ti.com
LAYOUT AND DECOUPLING
ADS5237
SBAS420A – AUGUST 2007 – REVISED OCTOBER 2007
the lead and trace inductance, the capacitors shouldCONSIDERATIONS be located as close to the supply pins as possible.Where double-sided component mounting is allowed,Proper grounding and bypassing, short lead length,
they are best placed directly under the package. Inand the use of ground planes are particularly
addition, larger bipolar decoupling capacitors (2.2 μFimportant for high frequency designs. Achieving
to 10 μF), effective at lower frequencies, may also beoptimum performance with a fast sampling converter
used on the main supply pins. They can be placed onsuch as the ADS5237 requires careful attention to the
the PCB in proximity (< 0.5in) to the ADC.PCB layout to minimize the effects of board parasiticsand to optimize component placement. A multilayer If the analog inputs to the ADS5237 are drivenboard usually ensures best results and allows differentially, it is especially important to optimizeconvenient component placement. towards a highly symmetrical layout. Small tracelength differences may create phase shifts,The ADS5237 should be treated as an analog
compromising a good distortion performance. For thiscomponent and the supply pins connected to clean
reason, the use of two single op amps rather thananalog supplies. This layout ensures the most
one dual amplifier enables a more symmetrical layoutconsistent performance results, because digital
and a better match of parasitic capacitances. The pinsupplies often carry a high level of switching noise
orientation of the ADS5237 quad-flat package followsthat could couple into the converter and degrade
aflow-through design, with the analog inputs locateddevice performance. As mentioned previously, the
on one side of the package while the digital outputsoutput buffer supply pins (VDRV) should also be
are located on the opposite side. This designconnected to a low-noise supply. Supplies of adjacent
provides a good physical isolation between thedigital circuits may carry substantial current
analog and digital connections. While designing thetransients. The supply voltage should be filtered
layout, it is important to keep the analog signal tracesbefore connecting to the VDRV pin of the converter.
separated from any digital lines to prevent noiseAll ground pins should directly connect to an analog
coupling onto the analog portion.ground.
Single-ended clock lines must be short and shouldBecause of its high sampling frequency, the
not cross any other signal traces.ADS5237 generates high frequency current transientsand noise (clock feedthrough) that are fed back into Short circuit traces on the digital outputs will minimizethe supply and reference lines. If not sufficiently capacitive loading. Trace length should be kept shortbypassed, this feedthrough adds noise to the to the receiving gate (< 2in) with only one CMOS gateconversion process. All AV
DD
pins may be bypassed connected to one digital output.with 0.1 μF ceramic chip capacitors (size 0603, orsmaller). A similar approach may be used on theoutput buffer supply pins, VDRV. In order to minimize
24 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS5237
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS5237IPAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
ADS5237IPAGG4 ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
ADS5237IPAGT ACTIVE TQFP PAG 64 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
ADS5237IPAGTG4 ACTIVE TQFP PAG 64 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Nov-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS5237IPAGT TQFP PAG 64 250 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS5237IPAGT TQFP PAG 64 250 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
4040282/C 11/96
Gage Plane
33
0,17
0,27
16
48
1
7,50 TYP
49
64
SQ
9,80
1,05
0,95
11,80
12,20
1,20 MAX
10,20 SQ
17
32
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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