LT4351
1
4351fd
TYPICAL APPLICATION
DESCRIPTION
MOSFET Diode-OR
Controller
The LT
®
4351 creates a near ideal diode using external
single or back-to-back N-channel MOSFETs. This ideal
diode function permits low loss ORing of multiple power
sources. Power sources can easily be ORed together to
increase total system power and reliability with minimal
effect on supply voltage or efficiency. Disparate power
supplies can be efficiently ORed together.
The IC monitors the input supply with respect to the load
and turns on the MOSFET(s) when the input supply is
higher. If the MOSFET’s RDS(ON) is sufficiently small, the
LT4351 will regulate the voltage across the MOSFET(s)
to 15mV. A STATUS pin indicates the MOSFET on-state.
An internal boost regulator generates the MOSFET gate
drive voltage. Low operating voltage allows for ORing of
supplies as low as 1.2V.
The LT4351 will disable power passage during undervolt-
age or overvoltage conditions. These voltages are set by
resistive dividers on the UV and OV pins. The undervoltage
threshold has user programmable hysteresis. Overvoltage
detection is filtered to reduce false triggering.
The LT4351 is available in a 10-pin MSOP package.
Dual 5V Redundant Supply
FEATURES
APPLICATIONS
n Low Loss Replacement for ORing Diode in Multiple
Sourced Power Supplies
n External N-Channel MOSFETs for High Current
Capability
n Internal Boost Regulator Supply for MOSFET
Gate Drive
n Wide Input Range: 1.2V to 18V
n Fast Switching MOSFET Gate Control
n Input Under and Overvoltage Detection
n STATUS and FAULT Outputs for Monitoring
n Internal MOSFET Gate Clamp
n Available in a 10-pin MSOP Package
n Paralleled Power Supplies
n Uninterrupted Supplies
n High Availability Systems
n N + 1 Redundant Power Supplies
LOADCLOAD
GATE OUTVIN
VDD
SW
LT4351
UV
OV
STATUS
1µF
24.9k
1%
232Ω
1%
1.47k
1%
10µF
5V
POWER
SUPPLY
1
4.7µH
MBR0530
MBR0530
FAULT
GND
Si4862DYSi4862DY
1×1×
GATEOUT
5V COMMON
VIN
VDD
SW
LT4351
UV
OV
4351 TA01
GND
POWER
SUPPLY
2
1µF
24.9k
1%
232Ω
1%
1.47k
1%
10µF
5V
4.7µH
MBR0530
MBR0530
STATUS
FAULT
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
and PowerPath and ThinSOT are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
LT4351
2
4351fd
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN Voltage ................................................ –0.3V to 19V
OUT Voltage ............................................. –0.3V to 19V
VDD Voltage .............................................. –0.3V to 30V
FAULT, STATUS Voltages .......................... –0.3V to 30V
FAULT, STATUS Current .......................................... 8mA
UV, OV Voltages ......................................... –0.3V to 9V
SW Voltage .............................................. –0.3V to 32V
Operating Temperature Range
LT4351C .................................................. 0°C to 70°C
LT4351I ............................................... –40°C to 85°C
Junction Temperature (Note 2) ............................ 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(Note 1)
1
2
3
4
5
GATE
VDD
VIN
SW
GND
10
9
8
7
6
OUT
STATUS
FAULT
UV
OV
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 120°C/W
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT4351CMS#PBF LT4351CMS#TRPBF LTZZ 10-Lead Plastic MSOP 0°C to 70°C
LT4351IMS#PBF LT4351IMS#TRPBF LTA 1 10-Lead Plastic MSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply and Protection
VIN Operating Range l1.2 18 V
IVIN VIN Supply Current VIN = 1.2V, VOUT = 1.1V, VDD = 12.3V
VIN = 18V, VOUT = 17.9V, VDD = 29.1V
l
l
1.41
1.71
2
2.1
mA
mA
VUV(TH) Undervoltage Turn-Off Voltage
Threshold
UV Falling l290 300 310 mV
IUV(HYST) IUV Hysteresis Difference Between IUV at VUV(TH) + 10mV and
VUV(TH) – 10mV
l7 10 13 µA
IUV UV Input Bias Current VUV = VUV(TH) + 10mV l–100 –400 nA
VOV(TH) Overvoltage Threshold OV Rising l290 300 310 mV
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT = 5V, VDD = 16.1V, VUV = 0.4V, VOV = 0.2V, GATE Open, unless
otherwise specified.
LT4351
3
4351fd
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT = 5V, VDD = 16.1V, VUV = 0.4V, VOV = 0.2V, GATE Open, unless
otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IOV OV Input Bias Current VOV = VOV(TH) – 10mV l–100 –400 V
VF(ON) FAULT Pin On-Voltage IF = 5mA in Fault Condition l0.14 0.25 V
IF(OFF) FAULT Pin Leakage Current VF = 30V, VIN = 4.9V l0.04 1 µA
Boost Supply
VBR Boost Regulation Trip Voltage Measured as VDD to VIN, Rising Edge l10.2 10.7 11.4 V
tOFF Boost Supply Off-Time 600 ns
ISWLIM Boost Supply Switch Current Limit l350 450 650 mA
Gate Drive
VIOR Input-to-Output Regulated Voltage l4 15 25 mV
∆VGL Gate Voltage Limit VIN = 5V, VOUT = 4.9V, VDD = 13V Measured with
Respect to VDD
l–2.3 –3 V
∆VG(MAX) Maximum Gate Voltage VIN = 5V, VOUT = 4.9V, VDD = 16.1V Measured with
Respect to VOUT
l7 7.4 7.8 V
VG(OFF) Gate Off-Voltage VOUT = 5.1V l0.16 0.30 V
IGSO Gate Source Current VOUT = 4.9V, VGATE = 9V 0.670 A
IGSK Gate Sink Current VOUT = 5.1V, VGATE = 9V 0.670 A
VDD Operating Range l30 V
IVDD VDD Supply Current VIN = 1.2V, VOUT = 1.1V, VDD = 12.3V, GATE Open
VIN = 18V, VOUT = 17.9V, VDD = 29.1V, GATE Open
l
l
3
3.6
4
5.6
mA
mA
Status Functions
∆VGIS Minimum Gate Voltage for Turning
On Status
VOUT = 4.9V, ISTATUS = 1mA l0.75 1 V
VIOGF VIN to VOUT Fault Voltage with
Open Gate
VOUT Falling, Measured with Respect to VIN 185 210 230 mV
VST(ON) Status Pin On-Voltage IST = 5mA, VOUT = 4.9V, Status On l0.13 0.25 V
IST(OFF) Status Pin Leakage Current VST = 30V, Status Off, VIN = 4.9V l0.04 1 µA
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • 120°C/W)
LT4351
4
4351fd
TYPICAL PERFORMANCE CHARACTERISTICS
Overvoltage Threshold vs VIN
Overvoltage Hysteresis
vs Temperature
Overvoltage Turn-Off Delay
vs Overvoltage Overdrive
Undervoltage Threshold
vs Temperature
Overvoltage Threshold
vs Temperature Undervoltage Threshold vs VIN
TA = 25°C, unless otherwise noted.
IVIN vs Temperature IVDD vs Temperature Gate Off-Voltage vs Temperature
TEMPERATURE (°C)
–50
290
VUV(TH) (mV)
292
296
298
300
310
304
050 75
4351 G01
294
306
308
302
–25 25 100 125
VIN = 1.2V
VIN = 5V
VIN = 12V
VIN = 20V
TEMPERATURE (°C)
–50
293
VOV(TH) (mV)
297
299
305
050 75
4351 G02
295
301
303
–25 25 100 125
VIN = 1.2V
VIN = 5V
VIN = 12V
VIN = 20V
VIN (V)
0
VUV(TH) (mV)
302
306
310
16
4351 G03
298
294
300
304
308
296
292
290 42 86 12 14 18
10 20
VIN (V)
0
VUV(TH) (mV)
302
306
310
16
4351 G04
298
294
300
304
308
296
292
290 42 86 12 14 18
10 20
TEMPERATURE (°C)
–50 –25
0
OV HYSTERESIS (mV)
10
25
050 75
4351 G05
5
20
15
25 100 125
VIN = 5V
OV VOLTAGE ABOVE THRESHOLD (mV)
0
0
TURN-OFF DELAY (µs)
2
6
8
10
20
14
10 20 25
3451 G06
4
16
18
12
515 30 35
VIN = 5V
TEMPERATURE (°C)
–50
1.0
IVIN (mA)
1.1
1.3
1.4
1.5
2.0
1.7
050 75
4351 G07
1.2
1.8
1.9
1.6
–25 25 100 125
VIN = 1.2V
VIN = 5V
VIN = 12V
VIN = 20V
TEMPERATURE (°C)
–50
2.0
IVDD (mA)
3.0
3.5
4.5
050 75
4351 G08
2.5
4.0
–25 25 100 125
VIN = 1.2V
VIN = 5V
VIN = 12V
VIN = 20V
TEMPERATURE (°C)
–50
0
VGOFF (V)
0.05
0.15
0.20
0.25
0.50
0.35
050 75
4351 G09
0.10
0.40
0.45
0.30
–25 25 100 125
VIN = 5V
VOUT = 5V
VIN = 5V
VOUT = 5.1V
LT4351
5
4351fd
TYPICAL PERFORMANCE CHARACTERISTICS
GATE Pin Turn On and Off Waveform
with 10nF Capacitor Load Typical SW Pin Waveform
Typical SW Pin Waveform
SW Pin Waveform at Maximum
Boost Regulator Output
TA = 25°C, unless otherwise noted.
50ns/DIV
VGATE
2V/DIV
VIN = 5V
VOUT = 4.9V TO 5.1V SQUARE WAVE
4351 G10
TURN ON
TURN OFF
500ns/DIV
VSW
5V/DIV
VIN = 5V
L = 4.7µH
4351 G11
10µs/DIV
VSW
5V/DIV
VIN = 5V
4.7µH INDUCTOR
4351 G12 10µs/DIV
VSW
5V/DIV
VIN = 5V
4.7µH INDUCTOR
4351 G13
LT4351
6
4351fd
PIN FUNCTIONS
GATE (Pin 1): MOSFET Gate Drive Pin. This pin is tied to
the gate(s) of the external N-channel MOSFET(s). The GATE
pin drives high when UV is above the VUV(TH) threshold,
OV is below the VOV(TH) threshold and VIN is greater than
OUT by 15mV. When not driven high, GATE actively pulls
to GND. GATE can sink or source up to 600mA.
VDD (Pin 2): Gate Drive Supply Pin. This is the supply
pin for the gate drive amplifier. It is either generated by
the onboard boost regulator or supplied externally. When
turning on the MOSFET(s), a large high current pulse
flows through this pin. Bypass the pin with a 1µF capaci-
tor placed in close proximity to the part. The voltage on
this pin is also the feedback for the boost regulator. If the
VDD voltage exceeds the VIN voltage by 10.7V, the boost
switch is held off.
VIN (Pin 3): Input Supply Pin. This pin is the supply pin
for the control circuitry and the boost regulator. It is also
one input in conjunction with OUT for controlling the
MOSFET(s). Bypassing should include a low ESR/ESL
capacitor placed in close proximity to the part.
SW (Pin 4): Boost Regulator Switch Pin. This pin is the
boost regulator switch output. It is connected to the boost
inductor and the boost diode. Peak switch current is limited
internally to 450mA. A Schottky diode between GND and
SW is required. If an external VDD supply is used, leave
this pin open.
GND (Pin 5): Device Ground Pin. This pin is ground for the
boost switch, gate driver as well as the control circuitry.
Tie the VIN and VDD bypass capacitors and ground plane
close to this pin to minimize the effects of switching cur-
rents on part performance.
OV (Pin 6): Overvoltage Shutdown Pin. This pin is used
for input overvoltage detection. It is connected to a resis-
tive divider from VIN. When the voltage exceeds the OV
threshold (0.3V), GATE is pulled to GND disabling power
transfer. In addition, the FAULT pin pulls low indicating a
fault. Overvoltage detection has filtering on it to prevent
false triggering. The filtering depends on the level of over-
drive. Filtered tripping will occur when OV exceeds 0.3V.
If OV exceeds 0.33V, the gate immediately turns off (no
filtering). If overvoltage detection is not required, ground
the OV pin. See the Applications Information section for
further information.
UV (Pin 7): Undervoltage Shutdown Pin. This pin is used
for the undervoltage detect function. It is connected to
a resistive divider from VIN. When the voltage is below
the UV threshold, GATE pulls to GND disabling power
transfer. In addition, the FAULT pin pulls low indicating a
fault. When the UV pin voltage drops below the threshold,
a 10µA current is pulled from the divider to provide hys-
teresis. If undervoltage detection is not required, tie the
UV pin to a voltage greater than 320mV and not greater
than VIN. Do not force more than 9V on UV due to an
internal clamp. See the Applications Information section
for further information.
FAULT (Pin 8): Fault Comparator Status Pin. This pin pulls
low when a fault occurs. A fault has occurred if the UV pin
is below threshold or the OV pin is above threshold. The
FAULT pin low indicates that there is a problem with the
VIN (source) supply. GATE is pulled to GND during a fault,
disabling the MOSFET(s) and prohibits common supply
contamination. If the GATE pin goes to compliance (GATE
equals the lesser of VDD – 2.3V or OUT + 7.4V) and VIN is
greater than OUT by more than 0.21V, FAULT turns on as
an indicator that the MOSFETs are probably not function-
ing. Leave this pin open if not used.
STATUS (Pin 9): MOSFET Status Pin. This pin pulls low
when GATE is above VIN by more than 0.7V and VIN is
greater than OUT by 15mV. This indicates the MOSFET is
on. Leave this pin open if not used.
OUT (Pin 10): Common Supply Pin. This pin is connected
to the supply common and is used in conjunction with VIN
as one input controlling the MOSFET(s).
LT4351
7
4351fd
BLOCK DIAGRAM
+
–
15mV
ENABLE
ENABLE
QSW
CUV
COV
0.3V
0.3V
0.33V
COVF
GND
OV
UV
R2
R1
RA
SW VDD VIN GATE
VIN
–
+
–
+
324
6
5
7
OPEN
MOSFET
DETECT
600ns
ONE
SHOT
–
+
1
10
9
8
10.7V
REG
–
+
–
+
RB
–
+
–
+
VIN
FROM INDIVIDUAL SUPPLY
TO COMMON SUPPLY
VOUT
OUT
OUT
ST
STATUS
FAULT
4351 BD
DRIVER
LT4351
8
4351fd
OPERATION
Increasingly, system designers have to deal with multiple
supply sources. The multiplicity may provide parallel,
redundant supplies for increased reliability or provide
a means of connecting disparate supplies. In all cases
the desire is for behavior like a diode but with no loss or
voltage drop.
ORing diodes have been the conventional means of con-
necting these supplies. The disadvantage of this approach
is that diodes introduce efficiency loss because of their
forward voltage drop. This variable voltage drop also de-
generates supply tolerance. Additionally, diodes provide
no information concerning the status of the sourcing
supply. Separate control must also be added to ensure
that a supply that is out of range is not allowed to affect
the common supply.
The LT4351 eliminates these problems by using N-channel
MOSFETs as the pass elements. The MOSFET is turned on
when power is being passed, allowing for a low voltage
drop from the supply to the load. When the input source
voltage drops below the output common supply voltage it
turns off the MOSFET, thereby matching the function and
performance of an ideal diode.
The LT4351 drives either a single MOSFET or dual back-
to-back MOSFETs. Dual MOSFETs are chosen to eliminate
current flow from the input supply to the output supply
when the VIN voltage is greater than OUT.
A driver amplifier monitors the input (VIN) and output
(OUT) and controls the MOSFETs. If VIN exceeds OUT
by 15mV, GATE goes high and turns on the MOSFET(s)
allowing for power passage.
Undervoltage and overvoltage comparators CUV , COV
and COVF also control power passage. A resistive divider
in conjunction with the UV and OV pins sets appropriate
thresholds such that the MOSFET(s) is off when the UV
pin is below 300mV or OV pin is above 300mV.
To help deal with the transients on the supply lines, the UV
input has current hysteresis. When the UV voltage drops
below the 300mV threshold, a 10µA current is pulled from
the pin. Thus the user can set the hysteresis level through
appropriate values in the divider.
Overvoltage shutdown occurs in two stages. The first oc-
curs when the OV pin exceeds the 300mV reference. When
OV just exceeds the reference, an internal capacitor starts
charging, delaying the signal to turn off the MOSFET(s).
The second occurs when the OV pin exceeds 330mV. The
OVF comparator will immediately trip pulling GATE to GND.
This affords a delay inversely proportional to the amount of
overdrive. This also provides for glitch immunity without
compromising response time in the event of a serious
overvoltage condition.
The FAULT output indicates the status of the COV , COVF
and CUV comparators. It pulls low during a fault condi-
tion. It also pulls low when GATE is at compliance and
VIN > OUT by more than 0.21V indicating a probable
nonfunctioning MOSFET. Compliance occurs when GATE
is at the lesser of OUT + 7.4V or VDD – 2.3V. FAULT derives
its drive from the greater of VIN or OUT. It is active if VIN
or OUT is greater than 0.9V. If VIN or OUT is below this
level, the output state is not guaranteed.
The gate drive consists of a high current, wide bandwidth
amplifier (driver). When the amplifier is enabled, it attempts
to regulate the GATE voltage such that the voltage across
the MOSFET(s) is approximately 15mV. If the MOSFET(s)
on resistance is so high as to prevent regulation, then
GATE goes to compliance and the MOSFET(s) fully turns
on. The inputs to the amplifier are VIN and OUT. The GATE
pin sources current from VDD and sinks current to GND.
The maximum GATE to VIN voltage is the lesser of VDD –
2.3V or 7.4V above VOUT or VIN (internal clamp voltage).
The STATUS comparator, ST, pulls low when GATE ex-
ceeds VIN by 0.7V. This occurs when VIN > OUT + 15mV.
The STATUS pin pulls low as an indication that power is
passing through the MOSFET(s).
If VIN is greater than OUT by 0.21V and GATE > VIN + 7.4V
or at compliance (GATE = VDD – 2.3V), STATUS will go
high as an indication of a likely open MOSFET. FAULT will
pull low in this state indicating the probable fault.
The gate drive amplifier and STATUS function derive power
from VDD. The circuit requires VDD > 2.5V. If VDD is present,
the gate drive amplifier and STATUS are active independent
of the state of VIN. If in a fault, GATE pulls actively low. In
the event of VDD collapse there still is an active pull-down
(though of lesser strength) of GATE powered from OUT,
guaranteeing turn off.
LT4351
9
4351fd
Setting Fault Thresholds
The gate drive amplifier implements the ideal diode func-
tion. The fault comparators (UV and OV) prevent out of
range input voltages from affecting the output by disabling
the amplifier during these conditions. Think of the UV and
OV as gating the ideal diode function, something a regular
diode cannot do.
A resistive divider from VIN to UV and one from VIN to OV
are the usual way of setting the FAULT thresholds. For UV
the resistor values are set by:
R2 =UV
HYST
IUVHYST
R1=V
UV
UV
FAULT – V
UV
•R2
where UVHYST is the desired undervoltage hysteresis at
the input. UVFAULT is the desired undervoltage trip volt-
APPLICATIONS INFORMATION
Figure 1
age at the input. VUV is the part undervoltage trip point
(0.3V) and IHYSTUV is the undervoltage hysteresis current
(10µA). See Figure 1.
The divider on the OV pin is a straightforward resistive
divider (Figure 2):
RB=OVFAULT
VOV
– 1
RA
RA=0.3V
RA,RBDivider Current
where OVFAULT is the desired overvoltage trip point at the
input and VOV is the OV pin threshold (0.3V). The OV pin
has 7mV of voltage hysteresis at room.
It is possible to do both dividers together using only three
resistors though with more interdependence in compo-
nents (Figure 3). The input bias current for UV and OV is
less than 200nA, so keep resistor values less than 10k.
The on-chip boost regulator uses a constant off-time
control scheme. When VDD is below the regulation trip
voltage, the switch turns on after a 600ns off-time. When
the switch turns on current ramps up in the inductor until
the current limit is reached (450mA). The switch turns
off and the inductor’s current flows through the external
diode to charge up the VDD capacitor. If VDD is still too low,
the switch turns on again after a fixed off-time of 600ns.
OPERATION
The boost regulator regulates VDD to approximately 10.7V
above VIN When VDD is above this level, the SW transistor
turn-on is disabled. When VDD falls below this level by the
hysteresis level, the SW transistor is allowed to turn on.
There is approximately 0.15V of hysteresis.
Figure 2 Figure 3 Figure 4
R2
R1
UV
IHYS
10µA
VUV
300mV
VIN
UV TURNING ON UV TURNING OFF
R2
R1
UV
IHYS
10µA
VUV
300mV
4351 F01
VIN
RB
RA
OV VOV
300mV
4351 F02
VIN
R2
R3
R1
OV
UV
4351 F03
VIN
C1
R2A
R2B
R1
UV
4351 F04
VIN
LT4351
10
4351fd
In that case, the resistor values are set by:
R3 =UV
HYST
IUVHYST
R2 =
V
UV –UV
FAULT
OV
FAULT
•VOV
UV
FAULT – V
UV
•R3
R1=VOV •UV
FAULT
OV
FAULT
•UV
FAULT
– V
UV
( )
•R3
Hysteresis helps prevent erratic behavior due to the noise
on VIN. Two of the most common noise sources are: VIN
dipping when the MOSFETs first turn on and draw down
the voltage on the VIN capacitors, and the boost regulator
switch turning on and drawing current from the VIN ca-
pacitors. Use low ESR capacitors for VIN and OUT filtering.
Note that because the UV pin uses current hysteresis,
placing a capacitor on UV to ground to filter noise will
reduce the effective hysteresis. Filtering can be achieved
by splitting the R2 resistor, as shown in Figure 4.
To defeat undervoltage fault detection, the UV pin should
be tied higher than 0.33V. UV can be tied to VIN provided
VIN < 9V. Overvoltage fault detection can be defeated by
grounding the OV pin. Do not exceed VIN.
APPLICATIONS INFORMATION
External Shutdown
To externally turn off the MOSFETs, such as to disable the
supply, use an open-collector transistor pulling down on
the UV pin. Note this will not turn off the boost regulator
which will continue to operate.
Boost Regulator
The boost regulator will start working as soon as VIN is
greater than 0.85V. The regulator will supply all the cur-
rent for the gate drive amplifier. While the amplifier itself
requires only about 3mA, larger current pulses are required
when charging the MOSFET gate. The reservoir capacitor
on VDD will provide this current (Figure 6).
The regulator performance is relatively insensitive to the
inductor value. The inductor value does control the fre-
quency of operation. A 4.7µH inductor is recommended
for VIN voltages less than 10V and 10µH for VIN voltages
greater than 10V. Several inductors that work well with
the LT4351 are listed in Table 1. Many different sizes and
shapes are available. Consult each manufacturer for more
detailed information and for their entire selection of related
parts. The switching frequency for the boost regulator is
around 1MHz so ferrite core inductors should be used
to obtain the best efficiency. The inductor must handle a
peak current of 0.7A minimum and have a DC resistance
of 0.5Ω or less. Shielded inductors are recommended to
reduce the noise due to inductive switching.
Table 1. Recommended Inductors
PART NUMBER IND (µH) DCR (mΩ) VENDOR
LPS3314-472ML
LPS4012-103ML
4.7
10
175
350
Coilcraft
847-639-6400
www.coilcraft.com
744029004
744042100
4.7
10
200
150
Würth Elektronik
www.we-online.com
SD3112-4R7-R
SD3118-100-R
4.7
10
246
295
Coiltronics
www.coiltronics.com
L1
D1
D2
QSW
GND
SW VDD
CDD
4351 F06
VIN
LT4351
Figure 5. Graphical Representation of the UV and OV Functions
OVERVOLTAGE FILTERED FAULT
INPUT
REFERRED
OV
REFERRED
UV
REFERRED
VUV = 0.33V
VUV = 0.3V
VUV < 0.3V
VOV > 0.3V
VOV = 0.3V
4351 F05
OVFAULT
UVFAULT + UVHYST
UVFAULT
UNDERVOLTAGE HYSTERESIS
OVERVOLTAGE FAULT:
GATE LOW
UNDERVOLTAGE FAULT:
GATE LOW
GATE CONTROLLED
BY VIN – VOUT
Figure 6
LT4351
11
4351fd
For VIN less than 2V, choose a DC resistance less than 0.2Ω.
Note that VDD current referred to the input supply is higher.
A first order approximation of the input current is:
IVINVDD =1+10.6
VIN
•IVDD
80%
Under normal operation, the VDD current is under 10mA
and the boost regulator operates in Burst Mode
®
operation.
If any additional load is added, ensure that the regulator is
capable of supplying that load. As the load is increased,
the boost regulator will switch into continuous mode op-
eration. Further increases in load will collapse the boost
regulator voltage.
Operating the regulator with increased load will cause
increased IC power dissipation and temperature, which
must be taken into consideration.
A 100ns delay from detecting the switch current limit to
turning off the power switch produces an overshoot of the
inductor current from the 0.45A switch limit. The amount
of overshoot depends on the boost regulator inductance.
Choosing an inductor that can handle 0.75A peak current
will be sufficient for the recommended inductors.
Diode Selection
Schottky diodes, with their low forward voltage drop and
fast switching speed, are the best match for the LT4351
boost regulator. Select a diode that can handle 0.75A peak
current and a reverse breakdown of 15V greater than the
maximum VIN.
APPLICATIONS INFORMATION
VDD Capacitor Selection
Low ESR (Equivalent Series Resistance) capacitors should
be used on VDD to minimize the output ripple voltage.
Multilayer ceramic capacitors are the best choice, as
they have a very low ESR and are available in very small
packages. Always use a capacitor with a voltage rating at
least 12V greater than VIN.
Capacitors
Two types of input capacitors are generally needed for the
LT4351. The first is a large bulk capacitor that takes care
of ringing associated with inductance of the input supply
lines and provides charge for the load when switching the
MOSFET. The input parasitic inductance in conjunction with
CB and its ESR create an LCR network. The input LCR can
be stimulated by the boost regulator switch current or load
current transients when the MOSFETs are on. To reduce
ringing associated with input inductance, CB should be:
CB≥4•LIN
RESR
2
where CB is the capacitor value, RESR is the capacitor’s
ESR and LIN is the inductance of the input lines.
While damped ringing is not necessarily bad, it may pro-
duce unexpected results as the LT4351 ideal diode reacts
to the varying VIN to OUT voltage. Typically an electrolytic
or tantalum low ESR capacitor would be used. Figure 7a
illustrates VIN for a low value of CB and Figure 7b shows
it with a correctly sized value.
Figure 7a. Example of Input Voltage Ringing
with Low CIN Capacitor at MOSFET Turn Off
Figure 7b. Example of Input Voltage with
Sufficient CIN Capacitor at MOSFET Turn Off
10µs/DIV
VIN
200mV
4351 F07a 10µs/DIV
VIN
200mV
4351 F07b
LT4351
12
4351fd
APPLICATIONS INFORMATION
As an example, for 500nH of inductance and RESR of about
100mΩ, then:
C≥4•500nF
0.1
2=200µF
Check vendor data for ESR and iterate to get the best
value. Additional CB capacitance may be required for load
concerns.
If the boost regulator is being used, place a 10µF low ESR
ceramic capacitor from VIN to GND. Place a 10µF and a
0.1µF ceramic capacitor close to VIN and GND. These
capacitors should have low ESR (less than 10mΩ for the
10µF and 40mΩ for the 0.1µF). These capacitors help to
eliminate problems associated with noise produced by the
boost regulator. They are decoupled from the VIN supply
by a small 1Ω resistor, as shown in Figure 8. The LT4351
will perform better with a small ceramic capacitor (10µF)
on OUT to GND.
External Boost Supply
The VDD pin may be powered by an external supply. In
this case, simply omit the boost regulator inductor and
diode and leave the SW pin open. Suitable VDD capacitance
(minimum of a 1µF ceramic) should remain due to the
current pulses required for the gate driver.
The VDD current consists of 3.5mA of DC current with the
current required to charge the MOSFET’s gate which is
dependent on the gate charge required and frequency of
switching. Typically the average current will be under 10mA.
MOSFET Selection
The LT4351 uses either a single N-channel MOSFET or
back-to-back N-channel MOSFETs as the pass element.
Back-to-back MOSFETs prevent the MOSFET body diode
from passing current.
Use a single MOSFET if current flow is allowable from
input to output when the input supply is above the output
(limited overvoltage protection). In this case the MOSFET
should have a source on the input side so the body diode
conducts current to the load. Back-to-back MOSFETs are
normally connected with their sources tied together to
provide added protection against exceeding maximum
gate to source voltage.
Selection of MOSFETs should be based on RDS(ON), BVDSS
and BVGSS. BVDSS should be high enough to prevent
breakdown when VIN or OUT are at their maximum value.
RDS(ON) should be selected to keep within the MOSFET
power rating at the maximum load current (I2 • RDS(ON))
BVGSS should be at least 8V. The LT4351 will clamp the
GATE to 7.5V above the lesser of VIN or OUT. For back-
to-back MOSFETs where sources are tied together, this
allows the use of MOSFETs with a VGS max rating of 8V
or more. If a single MOSFET is used, care must be taken
to ensure the VGS max rating is not exceeded. When the
MOSFET is turned off, the GATE voltage is near ground,
the source at VIN. Thus, MOSFET VGS max must be greater
than VIN(MAX).
If a single MOSFET is used with source to VIN, then BVGSS
should be greater than the maximum VIN since the MOSFET
gate is at 0.2V when off.
Figure 8. VIN Capacitors
VIN
1Ω
CV3
10µF
CV1
10µF
CB
LIN
PARASITIC
CV2
0.1µF
VIN
GATE
LT4351
4351 F08
GND
LT4351
13
4351fd
APPLICATIONS INFORMATION
The gate drive amplifier will attempt to regulate the voltage
across the MOSFETs to 15mV. Regulation will be achieved if:
RDS <15mV
2•ILOAD
for two MOSFETs and
RDS <15mV
ILOAD
for a single MOSFET
This requires very low RDS values. This may be achieved
by paralleling MOSFETs, but be careful to keep intercon-
nection trace resistance low. In the event that regulation
cannot be achieved, the gate drive amplifier will drive GATE
to its clamp and achieve the best RDS possible at that level.
STATUS
The STATUS pin sinks current when the input (VIN) is
above output (OUT) by 15mV and GATE is above VIN by
0.7V. This will normally indicate that power is being passed
though the MOSFETs.
In the event of a nonfunctional MOSFET, the GATE voltage
will be driven high (to the GATE clamp voltage). If VIN is
greater than OUT by more than 0.21V, the FAULT pin will
sink current to signal the potential problem.
There is no direct measurement or confirmation of cur-
rent flowing in the MOSFETs. Current is shared between
sources based on their voltage and series resistance. If
precision load sharing is desired, the LTC4350 may be a
more suitable part.
Redundant Supplies
The LT4351 is an improved solution for ORing redundant
supplies because of its lower forward drop versus con-
ventional diodes. The lower forward drop significantly
improves overall efficiency, improves the voltage tolerance
at the load and provides for a more accurate transition
from supply to supply and more accurate load sharing
between supplies.
ORing can be done either at the load or at the source.
Figure 9 shows some examples. ORing at the load is usu-
ally the safest method since it protects against shorts in
interconnects.
The LT4351 tighter forward-voltage tolerance makes it
easier to balance current between similar supplies using
the droop method. The droop method uses the supply
voltage and series resistance in the power path to provide
load sharing. In this case, size the MOSFET’s RDS(ON) low
to allow for regulation.
LT4351
BOARD
LT4351
LOAD
SOURCE 1
BACKPLANE
SOURCE 2
LT4351 BOARD
LT4351
LOAD
4351 F09
SOURCE 1
BACKPLANE
SOURCE 2
Figure 9. Redundant Backplane Supplies
LT4351
14
4351fd
APPLICATIONS INFORMATION
ORing Disparate Supplies
The LT4351 provides an easy solution for connecting
together different types of power sources. Again, because
of the low forward drop, the efficiency of the system is
improved and the voltage transition between supplies is
more accurate. In addition, the undervoltage and overvolt-
age features of the LT4351 provide options for enabling
and disabling the supplies that are not available from a
common diode. Figure 10 shows some examples of con-
necting disparate supplies.
Once VIN is greater than 1.2V and VDD is up, the part then
operates normally. The UV and OV pins will control the
enabling of the gate driver and once enabled, the VIN to
OUT voltage controls MOSFET turn on.
If VDD is still being charged when the gate driver turns
on the MOSFET, the GATE pin tracks with the VDD in-
crease until it reaches either the gate clamp voltage or
the compliance of the gate driver. If VDD is present with-
out VIN or OUT, the GATE pin actively sinks low.
Power Dissipation
The internal power dissipation of the LT4351 is comprised
of the following four major components: DC power dis-
sipation from VIN, DC power dissipation from VDD, the
dissipation in the boost switch including the base drive, and
dynamic power dissipation due to current used to charge
and discharge the MOSFETs. The DC components are:
PDCVIN = IVIN • VIN
PDCVDD = IVDD • VDD
Figure 11 shows the internal dissipation of the boost
regulator as a function of VIN and inductor value. Figure
11 represents the worst-case condition with the regulator
on all the time, which does not occur in normal practice.
Figure 11. PBOOST(MAX)
LT4351
Isolated System Supply
from Wall Adapter Isolated Battery Backup
Three Source ORing Provides Protection
Against Out of Range Supplies
WALL
ADAPTER
SYSTEM
SUPPLY LOAD
LT4351
BATTERY
WALL
ADAPTER
LOAD
+
LT4351
BATTERY
LT4351
LT4351
WALL
ADAPTER
LOAD
4351 F10
+
SYSTEM
SUPPLY
Figure 10
VIN (V)
0
PBOOST (W)
0.20
0.25
L = 10µH
L = 4.7µH
20
4351 F11
0.15
0.10 510 15
0.30
Start-Up Considerations
There is no inherent shutdown in the part. As VIN ramps
up, the boost regulator starts at about 0.85V and becomes
fully operational by 1.1V. The undervoltage and overvolt-
age comparators become accurate by 1.2V. The gate drive
amplifier keeps GATE low during this period with either
a passive pull-down, a weak active pull-down if OUT is
greater than 0.8V or with the full gate drive sink if VDD is
above 2.2V.
LT4351
15
4351fd
APPLICATIONS INFORMATION
Since the boost regulator supplies current for VDD, the
current is the VDD supply current (3.5mA) plus the aver-
age current to charge the gate. For a gate charge of 50nC
at a 10kHz rate, this adds 0.5mA of current. The power
dissipated by the boost regulator to supply the 4mA is
shown in Figure 12, representing a more typical situation.
Finally, the gate driver dissipates power internally when
charging and discharging the gate of the MOSFETs. This
power depends on the input capacitance of the MOSFETs
and the frequency of charge and discharge. The power
associated with this can be approximated by:
PGATE =fG•VDD •QG•1– VIN
16
where QG is the required gate charge to charge the MOSFET
to the clamp voltage (7.4V) and fG is the frequency at which
the gate is charged and discharged. Normally fG is low and
the resulting power would be very low. Figure 13 shows
PGATE for a 50nC gate charge at a 1kHz rate.
Total power dissipation is the sum of all of PDCVIN, PDCVDD,
PBOOST and PGATE. Figure 14 is representative of the total
power dissipation of a typical application at steady state.
The die junction temperature is then computed as:
TJ = TA + θJA • PTOTAL
where TJ is the die junction temperature, TA is the ambi-
ent temperature, θJA is the thermal resistance of the part
(120°C/W) and PTOTAL is ascertained from the above.
Therefore, a 0.1W power dissipation causes a 12° tem-
perature rise above ambient.
Figure 12. PBOOST(TYP)
VIN (V)
0
PBOOST (W)
0.015
0.020
L = 4.7µH
20
4351 F12
0.010
0.005 510 15
0.025
Figure 13. PGATE vs VIN (VDD = VIN + 10.7)
VIN (V)
0
PGATE (W)
0.002
0.003
20
4351 F13
0.001
0510 15
0.004 fGATE = 1kHz
QG = 50nC
VIN (V)
0
POWER (W)
0.10
0.12
20
4351 F14
0.08
0.06 510 15
0.16
0.14
L = 10µH
L = 4.7µH
VDD = VIN + 10
0.5mA GATE CURRENT
Figure 14. Total Power (Typical)
LT4351
16
4351fd
GATE OUTVIN
UV
OV
1µF
10µF
MBR0530
MBR0530
R1
1.69k
1%
RB
25.5k
1%
VIN
5V
LT4351
SW
VDD
STATUS
5
FAULT
GND
Si4838DY
3
7
6
4
2
1 10
9
8
RA
1.47k
1%
R2
24.9k
1%
1Ω
0.1µF
220µF
10µF
5V
2k
4351 F15
OUT
2k
10µF
4.7µH
Figure 15. 5V/5A Design Example
Design Example
The following demonstrates the calculations involved for
setting design components for a 5V system that requires
5A. Two supplies are used to do this. The VIN supply will
be deemed in spec when it is within ±5% of nominal. Allow
5% of hysteresis for UV.
So,
UVFAULT = 4.75V, UVHYST = 0.25V
OVFAULT = 5.5
Two separate resistive dividers are used.
For the UV divider:
R2 =UVHYST
IUVHYST
=0.25V
10µA=25k Use 24.9k
( )
R1=R2 •VUV
UVFAULT – VUV
=24.9k •0.3V
4.75V – 0.3V
R1 = 1.68k. The closest 1% value is 1.69k
The OV resistors are set as a straight resistive divider.
If the current in the RA, RB divider is 200µA, then:
RA=0.3V
200mA =1.5k use 1.47k (1%)
then
RB=OVFAULT
VOV
– 1
RA=5.5
0.3 – 1
1.47k
RB = 25.48, use 25.5k
For regulation, the MOSFETs must have:
RDS <15mV
2•5A =1.5mΩ
This very low value cannot be accomplished with a single
set of MOSFETs so a decision must be made whether to
use multiple MOSFETs or to live with an unregulated off-
set. Since low mΩ RDS(ON) is available, the IR drop using
a single MOSFET would still be acceptable. For RDS(ON)
= 4mΩ the drop is 2 • 5A • 4mΩ = 40mV. The finished
schematic is shown in Figure 15.
Layout Considerations
There are two considerations for board layout. The first
is that VIN and VDD bypass capacitors should be as close
to the part as possible. The GND pin should represent the
common tie point. The resistive dividers for UV and OV
should tie here as well.
Take care that current flow to the load (both through VIN
and GND), does not inadvertently produce errors due to
IR drops in PCB traces.
Keep the traces to the MOSFETs wide and short and close
to the part. The PCB traces associated with the power path
through the MOSFETs should have low resistance.
APPLICATIONS INFORMATION
LT4351
17
4351fd
TYPICAL APPLICATIONS
Lead Acid Battery Backup
5V Redundant Supply with External VDD
GATE OUTVIN
UV
OV
1µF
R1
1.69k
1%
RB
25.5k
1% LT4351
SW
VDD
STATUS
5
FAULT
GND
1ST SOURCE
Si4838DY
3
1Ω
10µF
7
6
4
2
1 10
9
8
RA
1.47k
1%
R2
24.9k
1% 0.1µF
100µF
10µF
10µF
2k
4351 F15
2k
LOAD
4351 TA03
COMMON
5V
SOURCE
12V
SOURCE
2ND
5V SOURCE
2ND
12V SOURCE
2ND LT4351
CIRCUIT
+
GATE OUTVIN
UV
OV
1µF
10µF
MBR0530
MBR0530
R1
365Ω
1%
RB
73.2k
1%
10µH
12V
LEAD-ACID
BATTERY
CHARGER
LT4351
SW
VDD
STATUS
5
FAULT
GND
Si4408DY
3
7
6
4
2
1 10
9
8
RA
1.5k
1%
R2
12.7k
1%
1Ω
0.1µF
220µF
10µF
10µF
10k
4351TA02
OUT
LOAD
10k
UVFAULT = 10.8V
OVFAULT = 15V
14V
POWER
SUPPLY
+
+
LT4351
18
4351fd
PACKAGE DESCRIPTION
MSOP (MS) 0307 REV E
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
1234 5
4.90 ± 0.152
(.193 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LT4351
19
4351fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
C 12/10 Reversed orientation of N-channel MOSFETs in Typical Application drawing. 1
D 12/11 Revised VBR Maximum value in Electrical Characteristics section 3
(Revision history begins at Rev C)
LT4351
20
4351fd
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
LT 1211 REV D • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC4352 Ideal Diode Controller with Monitor Controls N-Channel MOSFET, 0V to 18V Operation
LTC4354 Negative Voltage Diode-OR Controller and Monitor Controls Two N-Channel MOSFETs, 1µs Turn-Off, 80V Operation
LTC4355 Positive Voltage Diode-OR Controller and Monitor Controls Two N-Channel MOSFETs, 0.5µs Turn-Off, 80V Operation
LTC4357 Positive High Voltage Ideal Diode Controller Controls Single N-Channel MOSFET, 0.5µs Turn-Off, 80V Operation
LTC4358 5A Ideal Diode Integrated N-Channel MOSFET, 0.5µs Turn-Off, 9V to 26.5V
LTC4412 Low Loss PowerPath™ Controller in ThinSOT™ P-Channel MOSFET, 3V to 28V Range
GATE OUTVIN
UV
OV
1µF
MBR0530
MBR0530
R1
1.07k
1%
10µH
12.6V
BATTERY1
CHARGER
LT4351
SW
VDD
STATUS
5
FAULT
GND
Si4408DY
3
1Ω
1Ω
7
6
4
2
1 10
9
8
R2
40.1k
1%
0.1µF
10µF
100µF
UVFAULT = 11.8V
10µF
10k
5%
10k
5%
OUT
100k
5%
10µF
+
GATE OUTVIN
UV
OV
1µF
MBR0530
MBR0530
300k
5%
10µH 1N914
12.6V
BATTERY2
CHARGER
LT4351
SW
VDD
STATUS
5
FAULT
GND
POWER IS SWITCHED TO BATTERY2 WHEN BATTERY1 DROPS TO 11.8V
Si4408DY
3
7
6
4
2
1 10
9
8
120k
5%
10µF
0.1µF
10µF
10µF
10k
4351TA04
OUT
100µF
10k
LOAD
+
+
100µF
+
Primary Battery with Secondary Battery Backup
