AN429 - Motorola / Freescale Semiconductor

Order this

document

as AN429/D

MOTOROLA

—

SEMICONDUCTOR

APPLICATION NOTE

AN429

MC68332

QSPI

interface

for

the

MCM2814

EEPROM

Mark

Malolani

Motorola

Semiconductors

Ltd

East

Kilbride

Glasgow

INTRODUCTION

This application note

describes

the

software

and

hardware

necessary

to use

the

MCM2814

serial

EEPROM

with

the

MC68332

Queued

Serial

Peripheral

Interface,

OSPI.

well

giving

specific

details

accessing

the

MCM281

EEPROM

with

the

OSPI.

this

application note

can

also

used

provide

general

information

configuring

and

using

the

OSPI

with

SPI

compatible

devices.

The

main

areas

covered

are

hardware

configuration,

the

general

operation

the

OSPI

and

description

software

which

allows

programming

and

reading

data

from

the

MGM2814. Information

interfacing

the

software

with

high

level

‘C’

language

programs

also

covered,

with

short

demonstration

program

included.

HARDWARE

CONFIGURATION

Figure

shows

simple

system

with

four

MCM2814

EEPROMs

connected

directly

the

MG68332

OSPI.

The

MCM2814

serially

accessed 256

byte

FEPROM,

which

can

used

either

SPI

protocol

systems.

this

application

SPI

mode

selected

pulling

the

MCM281

MODE

the

..-5V

supply

level,

Vdd.

the

MCM2814

generates

its

programming voltage

(Vpp)

internally,

only

single

supply

necessary.

the

simplest

configuration, selection

the

individual

EEPROMs

accomplished

connecting

the

OSPI slave

select

lines,

PCSO-3,

directly

the

MCM2814

SPI

slave

select

lines,

SPISS.

With

this

configuration

maximum

four

EEPROMs

other

SPI

devices

can

individually

selected.

than

four

devices

are

connected

the

SPI

bus,

decoder

can

added

select

maximum

devices.

P053

P052

PcS1

PcSo

—

MC68332

OSPI

MISO

MOSI

50K

Vdd

SPISS

MODE

SPISO

SPISI

SPICK

MCM281

SPISS

Vdd

MODE

SPISO

SPISI

SPICK

MCM281

SPISS

Vdd

MODE

SPISO

SPISI

SPICK

MCM281

—m

SPISS

Vdd

MODE

SPISO

SPISI

PIG

MCM281

Figure

—

Basic

Hardware

MOTOROLA

AN429/D

MOTOROLA

LTD.

1990

SPI

AND

OSPI

OVERVIEW

The

SPI

bus

consists

oftwo

serial

data

lines,

clock

line

and

one or

slave

select

lines.

The

two

data

lines,

MOSI and

MISO, are

used by

the

master

device

the

bus

transmit

and

receive

data

respectively.

The

clock

and

slave

select

lines,

designated

SCK

and P050-3

the

OSPI.

are

gener-

ated

the

master,

which

this

case

the

OSPI.

When

the

SPI

master

accesses

particular

SPI

device,

the

slave

select

line

for

that

particular

device

driven

low

before

the

required

number

bits

are

transferred

during

SCK

transitions.

The

SPI

protocol defines

that

data

transmission

and

recep

;,on

always

occur

simultaneously,

while

data

transmit-

from

the

master

the

MOSI

line,

data

being

received

~iong

the MISO

line.

the

master

only

has

read

data

from

levice,

may

transmit

uninitialised

‘don’t

care’

values

:i’ng

MOSI,

and

conversely

the

master

only

has

write

~ta

device

may ignore

the

data

received

along

MISO.

enhancements

the

OSPI

over

the

SPI

consist

mainly

the

queued

architecture

the

OSPI.

Rather

than

having

program

each

individual

transfer

before

transmitted,

the

SPI,

the

OSPI

can

be configured

automatically

carry

out

number

transfers

without

intervention

from

the

processor.

Each

transfer

can

individually

configured

access

specific

device

using

the

PCSO-3

lines.

Individual

control

the

number

bits

per

transfer,

bus

timing

delays

and

the

state

the

PCS

lines

between

transfers

also

possible.

The

transfer

data

and

control

information

contained

three

queues:-

the

receive

data

queue

RECRAM,

the

trans

mit

data

queue

TRANRAM

and

the

command

data

queue

COMD.RAM.

The

transmit

and receive

queues

are

bits

wide, although

each

SPI

transfer

can

from

bits

long,

defined

BITS

SPCRO

and

BITSE

the

command entries.

The

command

data

queue

byte

wide,

with

each

byte

configuring

various

aspects

one

transfer,

such

the

number

bits

the

transfer,

bus

delays

and

device

selection.

Figure

shows

the

bit

usage

of the

command

bytes.

All

three queues

are

entries

deep,

resulting

bytes

each

for

the

transmit

and

receive

data

queues

and

bytes

for

the

command

queue

bits.

Command

Queue Entry

7 6 5

432

ICONTIBtTSE

DT OSOKI P0531

P052

P0511

P050

STATE

ACTION

Slave

Select Lines

POS

3-0

return

default

states,

defined

QPDR,

between

transfers

POS

3-0

not

change

between

transfers

Transfer

length defaults

8 bits

Bits

field

SPORO

defines

transfer

length

bits)

Default

delay

clocks

after

each

transter

Delay

specified

DTL

field

SPORi

Default

delay

of 1/2

clock

between

device

selection

and

transfer

Delay

specified by

DSCKL

field

SPORi

Defines

the state

the

slave

select

lines PCS3-0

during

transfer

FIgure

2—

Command

entry

format

BIT

CONT

BITSE

OSCK

P053-0

MOTOROLA

AN429/D

NVMRWC

SOFTWARE

OVERVIEW

The

MC68332

assembly

language

software,

NVMRWC,

contains routines

both

read

and

write

EEPROM data

via

the

OSPI,

and

configured

called

function

from

language

program.

The

read

routine

entered

at <ee_read>,

and

used

read

bytes

data

starting

from

any MCM281

location.

Figures

and

show

the

main

program

flow

for

the

read

action,

and

example

read

operation.

QSTART~ee

read>

)

Store

registers

local

stack

area

Start

transfers by

enabling

OSPI

The

write

routine

starts

<ee_write>,

and

able

write

bytes

data

starting

any

location,

long

all

the

bytes

are

within

a 4

byte boundary. This

limitation

due

the

operation

the MCM2814,

which

detailed

the

data

sheet

for

the

device. Program

flow

for

the

write

action

and

example

transfer

are

shown

figures

and

Transmit Data

Queue

TRAN.RAM

READ

($A7)

Address

($20)

xx xx

Entry

-L

Receive

Data

Queue

REC.RAM

2~X

~I~QA~1a

~xI~$2~dat~ ~a~1a

Entry

,j-

Command Queue CMD.RAM

CONT/BITSE/DT/DSCK

PCS3-0

7 6 5 4 3210

I.-

Example queue set-up

for

read

bytes

data

starting

from

MCM2814 address

$20.

with

the

device

select code,

(PCS3-O), set

0010.

Note

the

use of

bit

transfers

for

each

two

bytes

data.

un-initialised

unused

data,

underlined

data

received

from

MCM2814.

FIgure

—

EEPROM

read

flowchart

FIgure

—

EEPROM

read

example

Wait

until

QSPI

has

finished

any

pending

transfers

before

initializing

Get

passed

parameters

from

‘C’

call

[

I——

Initialize

transmit

data

queue,

command

queue

and

main

QSPI

control

registers

using

parameters from

C’

call

U—”

Has

OSPI

finished

transfers?

1 1

0 0010

1 1

0 0010

1 1

0010

Copy

data from

receive queue

into

‘C’

parameter

area

using

MC68332

loop

mode

~PASSL

00Th

Entry

AN429/D

MOTOROLA 3

START

.~ee

write>

)

Store

registers

local

stack

area

Wait

until

OSPI

has

finished

any

pending transfers before

initializing

Get

passed

parameters from ‘0’

call

:uitialize

transmit data queue,

command

queue

and

main

OSPI

control

registers

using

parameters from

‘C’

call

Transmit Data Queue

TXD.RAM

Vpp

($A6)

WRITE

($A2)

Address

($10)

Data

($AA)

Data

($55)

Vpp

OFF

($A4)

———-I

Receive

Data

Queue

REC.RAM

Start

transfers by

enabling

OSPI

Command Queue CMD.RAM

Has

programming

delay

elapsed?

YES

Initialise

SPCR2

send

Vpp

OFF

command

Figure

5—

EEPROM

wrIte

flowchart

CONT/BITSE/DT/DSCK

PCS3-0

3210

0 0

0 0001

0 0

0 0001

0 0

0 0001

L 4

Example

queue

set-up for

write

bytes

data starting

from

MCM2814 address

$10,

with

the

device

select

code, (PCS3-0),

set

0010.

un-initialised

unused data,

underlined data

received

from

McM2814.

Figure

—

EEPROM

wrIte

example

Entry

AN429/D

WORKSPACE

ALLOCATION

LINK.

UNLK

AND

MOVEM

The

routines

<ee_read>

and

<ee_write>

return

with

all

processor

registers restored

their

origimal

state.

complish

this,

the registers

are

written

the

stack

entry,

and

recovered

before returning.

The

instruction,

LINK

A6,#&-28,

creates

byte

stack

frame

for

this

purpose

moving

the

stack

pointer.

A7,

past

the

reserved

area,

and

act

the frame

pointer.

Storing

the

processor

registers

accomplished

single

instruction

the MOVEM

(move

multiple)

command.

MOVEM.L

DO/D1/D2/D3/AO/A1/A2,(A71

stores

all

the

listed

registers

long

words

starting

the

address

pointed

the

stack

pointer

A7.

the

LINK

instruction

sets

point

the

lowest

address

the

reserved

bytes,

all

the

registers

are

stored

this

area.

Figure

shows

the

stack

organisation

detail.

The

MOVEM

instruction

used

again

the

end

the

program,

with

the

order

the

operands reversed,

to recover

the

values,

and

the reserved

stack

area

deallo

cated

the

UNLK

(unlink)

instruction.

This

recovers

the

original

value

the

specified

local

stack

pointer,

A6,

and

resets

the

main

stack

pointer,

A7,

its

value.

(Stack

pointer

—b

after

LINK)

(AG

after

LINK)

(Stack

pointer

before

LINK)

Temporary store

‘C’

return address

Parameter

‘DEV’

Parameter

‘ADDR’

Parameter

‘BYTE

COUNT’

Address

array

‘BYTE

BUFFER

’

Un-used stack

bytes

reserved by

LINK

(contents

after

MOVEM)

Stack

condition

entry

Long

word

byte)

width

FIgure

—

Stack

allocatIon

AN429/D

Decreasing

address

MOTOROLA

INITIALISING

THE

OSPI

Before

the

OSPI

is used

for

EEPROM

read

write,

initialised

the

desired

startup

state.

The

subroutine

allows

the

OSPI

complete

any

pending

trans-

fers

before

stopped

and

initialised.

this

stage

initiali

sation

consists

mainly

configuring the

OSPI

hardware

assigning

the

lines

MISO,MOSI,SCK and

PCSO-3

the

OSPI.

with

MOSI

and

PCSO-3

set

outputs

which

default

high.

The

OSPI

also

set

to non

wired-or

outputs

and

SPI

master

with

clock

rate of

100KHz

this

point.

Note

that

known

the

OSPI

will

idle

and

suitable

state

when

EEPROM

read

orwrite

requested,

if it

acceptable to halt

the

OSPI

with

transfers

pending,

the

initialisation

subroutine could

simplified,

FUNCTION

PARAMETER

PASSING

MC68332

LOOP

MODE

.A.’hen

either reading or

writing

EEPROM

data,

the

software

to retrieve

the

parameters

that

the

program

has

placed

the

stack.

NVMRWC

configured

work

with

2ompiler

that

passes

the

variables

the

stack

locations

‘wn

figure

the

compiler

passes

the

variables

fferent

manner, the

program

must

altered

accord

The

parameters

are

initially

stored

the

MC68332

mal

registers

follows:-

—

Address

MC68332

memory

the

data

array,

<BYTE_BUFFER>

—

Number

bytes

transfer,

<BYTE_COUNT>

—

MCM2814 starting

byte

address,

<ADDR>

Note

that

the memory

address

the

main

array,

rather

than

the

actual

data.

This

allows

NVMRWC

read

modify

the

data

the

array

when

necessary

using

pointer.

example

this

when

the

EEPROM

data

passed

back

the

array

after

read

the

routine

<PAS

SLOOP>.

This

program

section

uses

MOVE

instruction

copy

byte

data

from

the

OSPI

receive

data

queue

the

array,

and

decrement

false,

DBF

instruction

to cause

the

program

loop

around

until

count

reaches

the

MOVE

instruction

occupies

one

word, the

MC68332

automatically

enters

‘Loop

Mode’

when

this

program

sec-

tion

encountered.

When

this

mode,

instruction

fetches

are

made to

memory,

thus

greatly speeding

execu-

tion.

—

Device selection

code

for

PCSO-3

pins,

<DEV>

TRANSMIT

DATA

QUEUE

INITIALISATION

The

transmit

data queue

has

initialised

with

the

correct

sequence

MCM2814

commands

and

data

before

E E

PROM

read

write

can

carried

out.

Reading data

from

the

E E

PROM

uses

the simplest

sequence, consisting

the

following>

MCM2814

READ

command

1SA7)

Starting

byte

address

read

The

remainder

the

transmit

queue

does

not

need

initialised,

after

this

sequence

has

been

sent

the

MCM28l

transmits

data,

and

longer monitors

incoming

data.

Because

the

MCM281

remains selected

between

all

the

individual

byte

transfers,

the

full

bit

width

the

data

queues

can

used

increase

the

maximum

possible

transfer

size.

The

example

figure

shows

that

the

read

code

and

the

byte

address are

sent

one

bit

transfer,

with

the

receive

queue

holding

bytes

received

EEPROM data.

When

writing

data

the

EEPROM,

the

following

sequence

transmitted:

Vpp

command

($A6)

WRITE

DATA

command

(SA2)

Starting

byte

address

programmed

bytes

data

Vpp

OFF

command

CSA4)

Because

the

EEPROM

has

deselected

at various

points

during

the

sequence,

all

transfers

are

bit

only.

example

transfer

shown

figure

<“OROLA

AN429/D

COMMAND

QUEUE

INITIALISATION

The

command

queue

configured

with

the

device

selection

state

during

and

between

transfers,

timing

information

and

bit

size information.

For

EEPROM

read

write

sequence

the

device

select

code

remains

constant throughout,

all

the transfers

are

intended

for

single

device.

This

device

select code,

which

determined from

the

parameter

<DEV>,

written

into

the

PCSO-3

field

all

the

COMD entries

used.

MCM2814

read

sequence

treated

one

command,

and

the

device

must

remain

selected

for

its

full

duration,

even

between

the

individual

transfers.

accomplish

this

the

CONT

bits

are

set

for

all

the

COMD

entries

except

the

one

which

controls

the

last

transfer.

Because

MCM2814

write

sequence

consists

three

command

blocks

lVpp

ON, WRITE and Vpp

OFF)

and

the

device

has

deselected

between

the

blocks,

the

CONT

bits

have

cleared

for

the

last

transfer

each

block.

This

can

seen in

the

example,

figure

where

the

CONT

bits

are

clear in

the

COMD

entries

corresponding

the

Vpp

command,

the

last

data

byte

and

the

Vpp

OFF

command.

all

EEPROM

writes

are

byte

size,

BITSE

clear

for

all

the

command

queue

entries.

This forces

the

OSPI

use

the

default

transfer

size,

which

bits.

For

the

EEPROM

read

operation

all

transfers

are

bit,

BITSE

set

for

all

the

COMD

entries.

This

causes

the

OSPI

use

the

transfer

size

programmed

into

the

BITS

field

SPCRO,

which

has

previously

been

set

16.

necessary,

the

BITS

field

can

used

select

alternative

transfer

sizes

from

bits.

conform

with

the

MCM2814

timing

spec.

delay

generated

after

each

transfer

setting bit

the

com

mand

queue

entries,

causing

the

OSPI

use

the

5p~S

delay

specified

control

SPCR1.

extra delay

needed

between

selection

the

MCM2814

and

data

transfer,

the

DSCK

bits,

which

control

this

delay,

are

cleared

the

command

queue

tries.

MAIN

QSPI

CONTROL

REGISTERS

Before

the

OSPI

transfers

can

started,

the

main

configu

ration

SPCR2

configured.

This

the

first

and

last

OSPI

entry

numbers

that

are

sent

which

are

dependent

the

type

transfer

and

parameters,

eg.

the

number

bytes

read/write.

The

WRAP control

bits,

which

control

the

OSPI

wrapping

operation

which the

OSPI

constantly loops

around

group

queue

entries,

are

set

disable

this

function.

OSPI

transfers

are

started

setting

the

OSPI

enable

bit,

SPE,

SPCR1.

The

program

then

loops,

testing

for

comple

tion of

transfers

polling

the

SPI

finished

flag,

SPIF.

the

status

SPSR.

DEMONSTRATION

PROGRAM

EECALL

small

demonstration

program,

EECALL,

shows

the

way

that

program

can

utilise the

assembly

language

program

NVMRWC

well

demonstrating

its functions.

Several

functions

can

invoked

single keypress.

These

func

tions

are:

—

(Set

Parameters)

—

This

option allows

the

user

define

the

parameters

Start

Address,

No.

of Bytes and

Device

Code.

W—

(Write

Data)

—

This option

makes

one

call

the

assem

bly

language

routine

<EE_WRITE>

using

the

parameters

which

have

been

set

previously.

The

user

prompted

enter

the

data

programmed,

byte

byte.

This

data

entered

single

ASCII

characters,

with

carriage

return

necessary.

—

(Read

Data)

—

One

call

made

the

assembly

language

routine

<EE_READ>

using

the

previously

set

parameters.

The

returned

data

printed

ASCII

format,

with

each

byte

separated

slash

(.1)

character.

—

(EE

PROM

Dump)

—

The

entire

contents

one

E E

PROM

(as

selected

the

previously

set

device

code)

are

printed

screen

ASCII

table

format.

This

option

calls

<EE_READ>

times,

with

each

call

reading

bytes

EEPROM.

—

(Text

Entry)

—When

this

option

selected,

the

user

can

enter

text

message

undefined

length

programmed

into

EEPROM.

terminate

the

message

hash

l#)

must

entered.

Programming

carried

out

character

character,

using

call

<EE_WRITE>

program each

byte

—

(Exit)

—

Exits

the

program

EECALL

executing

an RTS.

AN429~O

MOTOROLA .7

EECALL.C

Basic front—end

program

to test

and

show use of

assember

calls

EE_READ

and

EE_WRITE

to read

and

write

data

MQ42814

LEPROM

connected

to OSPI.

*include

<terminal.

typedef

unsigned

char

byte;

byte

i,tbc,dev,addr,tadd,byte

count,byte_buffer(29];

iovar;

char

extern

byteee_write

(byte

d,byte

a,bytebcount,byte

*b_buffer);

extern

byte

ee_read

(byte

d,byte

a,byte

b_count,byte

buffer);

void

pstring

(s)

char

*5;

while

(*s)

putchar(*s++);

main()

byte

error;

dev—14;

addrOxl

byte_count’-4;

for

(i—0;i<4;i++)

byte_buffer~i]=i+40;

Initialise

pass

parameters

initialize

I/O

device

pstring(”Enter

pstringQ’

pstring(”

\“X\”

terminate

the

program\n\r”);

\“WV’

Write

EEPROM

\n\r”);

\“RV’

Read

the

EEPROM\n\r”);

\“P\”

set

Parameters\n\r”);

\“D\”

Dump

entire

EEPROM\n\r”);

\“T\”

enter

Text

message\n\r”);

while

((c

—

toupper(getcharo))

—

‘X’)

—

‘W’)

pstring

(“Write

Data\n\r”);

for (i—O;i<byte_count;

i++)

pstring

(“\n\rEnter

char

c—getchar0;

Jutchar

(c);

byte

buffer

[il—c;

—

“I;

pstring(”\n\rWriting

Data

E.EPR~.

error

—

ee_write(dev,addr,byte_count,byte

buffer);

error

—

error+l;

AN429/D

open

MOTOROLA

—

‘T’)

printf

(“Program

text

from

address

%d.\n\r”,addr);

pstring

(“Enter

Text

•

terxuinate\n\r”);

tadd

—

addr;

tbc

while

(Cc

getcharO)

!—

‘I’)

yutchar

(c);

byte_buffer[0]—c;

error

—

write

(dev,tadd,tbc,byte_buffer);

++tadd;

—

R’)

patring

(“Read

Data\n\r”);

read(dev,addr,byte_count,byte

buffer);

for

(i—O;i<byte_count;i++)

putchar

(byte_buffer[i]);

putchar(

‘I’);

pstring

(“\n\r”);

—

‘0’)

patring

(“Block

EEPROM

durnp\n\r”);

tbc

—

16;

tadd

printf(”\n

%4d —“,tadd);

ee_read(dev,tadd,tbc,byte_buffer);

for

(i—0;i<16;

i++)

(byte

buffer)>]

byte_buffer[i]

—

putchar

(byte_bufferfi]);

tadd

—

tadd+

16;

putchar(’

‘I;

Iwhile

(tadd>0);

pstring(”\n\r”);

— ‘P’)

pstring

(“Parameters”);

pstring(”\n\rEnter

no.

of bytes

0—29

:“);

scanf

(“%d”,

&iovar);

while

(

iovar

byte_count

—

(byte)iovar;

pstring(”Enter

start

address

0—255

:“);

do scanf

(“%d”,

Liovar);

while

Ciovar

255);

addr

(byte)iovar;

printf

(“Bytes

—

Address

—

%d.\n”,bytecount,addr);

pstring

(“\n\r”);

pstrinq(”\n\rX:eXit

W:Write

R:Read

P:Paranieters

D:Dump

T:Text\n\r”);

pstring

(“7”);

pstring(”EXIT

PROGRAl’1\n\r”);

AN429/D

MOTOROLA

(This

page

intentionally

left

blank)

AN4

29/I

MOTOROLA

MCM2814

EEPROM

Readand

Write

Subroutinesfor

the

MC68332

OSPI

Configured

‘C’

languageextermal

call

Motorola

1990

Call

format:

F.E_READ

(0EV,

ADDR,

BYTE_COUNT,

*BYTE_BUFFER)

LIB

68332.REG

Include

MC68332

equates

section

.data

***********

****************************************

EEPROM

read

******

*********************************************

* ***

CREATE

LOCAL STACK

FRAME

AND

STORE

REGI STERS

ee read

LINK

A6,#&—28

Allocate

local

stack

area

bytes

and

use

local

stack

pointer

MOVEM.L

DO/D1/D2/D3/AO/A1/A2,

(A7)

Store

registers

local

stack

frame

***

INITIALISEQSPI

BSR

OSPINIT

* ***

FETCH

PARAMETERS

FROM

LEA

(&52,A7),AO

MOVE.L

-(AO),Al

MOVE.L

-(AO),DO

MOVE.L

-(AOLDl

MOVE.L

-(AO),D2

Disable

QSPI and

initialise

I/O

STACK USING

POINTER

Point

element

above first

parameter

Put

BYTE_BUFFER

address

Put

BYTE

COUNT

in DO

Put

ADOR

Put

DEV

***

LOAD TXD

QUEUE

WITH

~Z2

184

COt’24ANDS

Read byte

con~nand

MC~428l4

byte

address

MOVE.B

•$A7,TXD

MOVE.B

Dl,’IXD+l

***

ENSURE

BYTE_COUNT

ANDI.W

•$OOFF,DO

CMP.B

•$1E,DO

BCS

B_COKi

MOVE.B

•$1D,DO

B_COKi

TST

BNE

B_COK2

MOVE.B

•S0l,DO

BYTE_COUNT

should

B_COK2

MOVE.W

00,01

store

READ

coriwnand

store

byteaddress

into

TXD

queue

(Dl

can

used

now)

RANGE

Clear

MSB

(word

will

used

DBcc)

Should

BYTE_COUNT

&30

BYTE_COUNT

~3O?

No.

force

&29

BYTE_COUNT

No,

force

O.K.

now

Working

copy

BYTE_COUNT

***

SET

CCJMD

QUEUE

Use

0EV

code

calculate

ORI.B

#$EO,D2

MOVEA.

•COMD,

CCMD

queue

entries

Calculate

entry

with

CONT bit set

bit

transfer

Use

COMO

queue

pointer

No.

bit

transfers

—

Calculate value

in D2

for

ADD.B

ASR.B

SUB.B

Setup

COMDLOOP

~VE .B

DBF

Setup

ANDI

MOVE.

((BYTE_COUNT+2)/2)

DBcc loop

set

COMO

queue

BYTE_COUNT

(BYTE_COUNT+2)/2

(BYTE_~OUNT+2)/2—1

all

C~4D

entries

except

last

with

CONT

bitset

02,

(AO)+

Dl,

COMOLOOP

last

COMO

entry

with

CONT

clear

(deselect

EEPROM

end)

•S6F,D2

Calculate

entry

with

CONT

bit

clear

02,

(AD)

Install

COMO

queue

\N429/D

#$02,

#1,Dl

#$01,Dl

MOTOROLA

* ***

CALCULATE

LAST

QSPI

MOVE.B

DO,Dl

ADD.B

•$02,D1

ASR.B

~1,D1

MOVE.B D1,SPCR2

MOVE.B

#S0O,

SPCR2+1

~READ

DATA FROM

MC~42814

MOVE.W

•S8003,

SPCRl

~ WAIT FOR

END

TRANSMISSION

WTLOOP

TST.B

SPSR

BPL

WTLOOP

ENTRY

NO.

AND

INCORPORATE

SPCR2

Make

working

copy

BYTE_COUNT

(BYTE_COUNT+2)

Put

into

SPCR2

MSB

and

start

entry

LSB

Enable

0521,

DTL

delay

approx

5u5

Test

SPIF

bit

and

wait

till

set

* ***

PASS

DATA

BACK

TO C

PRCX3RAM

ARRAY

SUB.B

#SO1,DO

Use

BYTE_COUNT-i

loop

counter

MOVEA.L

#REC+3,AO

Use

REC

queue

pointer

Use

MC68332

LOOP

MODE

PASSLOOP MOVE.B

(AO)+,(Al)+

DBF

DO,PASSLOOP

fill

array

Copy

one

data

entry

from

REC

queue

(loop

until

00<0

* ***

RESTORE

REGISTERS

AND

DE-ALLOCATE

STACK

MOVEM.L

(A7)

,DO/Dl/02/D3/AO/Al/A2

UNIX

RTS

write

Retrieve

registers

from

local

stack

frame

And

de—allocate

local

stack

********************************

******************

EEPROM

write

******

****

***************

************

**************

CREATE

LOCAL STACK FRAME

AND

STORE

REGISTERS

LINK

A6,~&-28

Allocate

local

stack

area

bytes

for

reg.

store,

using

as stack

pointer

MOVEM.L

DO/D1/D2/D3/AO/Al/A2,

(A7)

Store

registers

in local

stack

frame

‘~‘~‘

INITIALISE QSPI

BSR

QSPINIT

***

FETCH PARAMETERS

FROM

LEA (52,A7),AO

MOVE.L

-(AO),Al

MOVE.L

-(AO),DO

MOVE.L

-(AO),Dl

MOVE.L

-(AO),D2

Stack

pointer

unchanged

Disable

and

initialise

OSPI

STACK USING

POINTER

Pointto

element

above

first

parameter

Put

BYTE_BUFFER

address

Put

BYTE_COUNT

Put

ADDR

Put

0EV

LOAD

QUEUE

WITH

14ZM2814

CO~t1ANDS

Vpp

coiwnand

Write

data

corrtnand

reserved

for

byte

address

data

off

conunand

•$A6,

TXD+l

•$A2,

TXD+3

Dl,

TXD+5

Vpp

MOVE.

MOVE

MOVE.

Vpp

conunand

WRITE

coirvriand

Use

ADDR

byte

address

(Dl

can

used

now)

Adjust

SUB.B

ANDI.W

MOVE

Byte_Count

•soi,oo

•S03,DO

00,01

for

use

DBcc

loop

Need

BYTE_COUNT

loop

counter

range

0-3

for

use

DBcc

loop,

not

1-4

Working

copy

AN429/IJ

MOTOROLA

PROGRAM

COW)

AND TXD

Program

start

TXD

MOVEA.L

•COW),AO

MOVEA.L

#TXD+7,A2

ORI.B

•S20,02

MOVE.B

D2,

(AO)+

ORI.B •$AO,D2

MOVE.B

02,

(AO)+

MOVE.B

D2,(AO)+

QUEUES

and

COW)

queues

Use

CCt’!D

queue

pointer

Use

TXD

queue

pointer

Calculate

COW)

entrywith

CONT

bit

clear

Use

entry

for

Vpp

(CONT

clear)

Calculate

COW)

entrywith

CONT

set

Use

entry

for

WRITE

DATA

and

ADDR,

(CONT

set)

PROGRAM

DATALOOP

MOVE.

ADDA.L

MOVE.

DBF

TXD

AND

CMD

QUEUES

(Al)+,

(A2)+

•

$01,

02,

(AO)+

Dl,

DATALOOP

Put

byte

of write

data

TXD

queue

TXD

buffer

i’K)RD

wide,

increment

Put

entry

into

COW)

queue

(CONT

set)

Loop

until

finished

Finish

MOVE.

ANDI.B

MOVE.

MOVE

off

COW)

and

•$A4,

(A2)

#$2F,D2

02,

(—l,AO)

D2,

(AO)

* ***

CALCULATE

WHAT

QUEUE

ADD.B

•$03,DO

MOVE.B

DO,

SPCR2

MOVE.B

•SOO,SPCR2+1

***

START

TRANSMISSION

AND

MOVE.W

•$8003,SPCR1

MOVE.L

#$00008000,Dl

LOOP DBF

Dl,

LOOP

TXD

queue

setup

Vpp

OFF

conunand

TXD

queue

Calculate

COW)

entry

with

CONT

clear

Change

last

data

COW)

entry

CONT

clear

Last

COW)

entry

(Vpp

OFF),

CONT

clear

ENTRIES

SEND

FOR

PROGRAMMING

Last

data

entry

no.

2+BYTE_BUFFER

Put

into

SPCR2

MSB

and

start

entry

LSB

PROGRAMMING

DELAY

Start

progranuning

Progranuning

delay

(approx

2Oms)

* ***

CALCULATE

WHAT

QUEUE

ENTRIES

SEND

FOR

Vpp OFF

ADD.B

•$0l,DO

Vpp

OFF

conunand

inunediately

after

MOVE.B

DO,SPCR2

MOVE.B

DO,SPCR2+l

progranuning

sequence

Put

into

SPI~R2

MSB

and

LSB

that

only

this

cormnand

sent

RESTORE

REGISTERS

AND

DE-ALLOCATE

STACK

MOVEM.L

(A7)

,DO/D1/D2/D3/AO/Al/A2

UNIX

RTS

Retrieve

registers

from

local

stack

frame

And

de—allocate

local

stack

MOTOROLA

AN429/D

****

******

******************************

QSPINIT

Orderly

stop

and

initialise

QSPI

hardware

*****

************************************

QSPINIT

ORI.B

•$80,SPCRO

ANDI.B

•$BF,SPCR2

ANDI.B

#$7F,SPSR

active

SPCRl

MISS

Ensure

QSPI

mester

Clear

WREN

(stop

wrapping)

Clear SPIF to

enable sensing

when

transmission

has

finished

Test SPE bit to see if

QSPI

enabled

Goto

MISS

disabled

Wait

till

QSPI

reached

ANDI.B

*$06,SPCR3

NOSPIF

TST.B

SPSR

BPL NOSPIF

Disable

QSPI

ANDI.B

•S7F,SPCR1

end

current

queue

Ensuresystem

not

HALTed

Wait

until

SPlFinished

Clear

SPE

bit

Initialise

QSPI for

accessing

M~42814

MOVE.W

•S8054,SPCRO

Set

MASTER,

WIRED

OR,

bits,

100KHZ

MOVE.W

•$7B7E,QPAR

Configure

MOSI,MISO+PCSO-3

QSPI

lines

MOVE.W

•$OOFA,QPDR

MOSI+PCSO

default

high

ANDI.B

•S7F,SPSR

Clear

SPIF

enable

sensing

when

transmission

has

finished

RTS

Allow

other

programs

(eg

program)

access

routine

labels

ee_write

and

ee_read

export

ee_write

export

read

AN429/l

QSPI

TST.B

BPL

MISS

MOTOROLA

(This

page

IntentIonally

left

blank)

AN429/D

MOTOROLA

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Conditions

Supply.

ordering

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the

Customer

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Terms

Conditions

and nothing

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in this

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farms

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Iwith

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exception

the

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this

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copy

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Conditions

Supply

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request.

Motorola

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make

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any

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the

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its

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use

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“Uyplcal”

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