ICL7660, ICL7660A S E M I C O N D U C T O R CMOS Voltage Converters November 1995 Features Description Simple Conversion of +5V Logic Supply to 5V Supplies Simple Voltage Multiplication (VOUT = (-) nVIN) Typical Open Circuit Voltage Conversion Efficiency 99.9% Typical Power Efficiency 98% Wide Operating Voltage Range - ICL7660 . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 10.0V - ICL7660A . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 12.0V * ICL7660A 100% Tested at 3V * Easy to Use - Requires Only 2 External Non-Critical Passive Components * No External Diode Over Full Temp. and Voltage Range * * * * * The Harris ICL7660 and ICL7660A are monolithic CMOS power supply circuits which offer unique performance advantages over previously available devices. The ICL7660 performs supply voltage conversions from positive to negative for an input range of +1.5V to +10.0V resulting in complementary output voltages of -1.5V to -10.0V and the ICL7660A does the same conversions with an input range of +1.5V to +12.0V resulting in complementary output voltages of -1.5V to -12.0V. Only 2 non-critical external capacitors are needed for the charge pump and charge reservoir functions. The ICL7660 and ICL7660A can also be connected to function as voltage doublers and will generate output voltages up to +18.6V with a +10V input. Applications * * * * Contained on the chip are a series DC supply regulator, RC oscillator, voltage level translator, and four output power MOS switches. A unique logic element senses the most negative voltage in the device and ensures that the output N-Channel switch source-substrate junctions are not forward biased. This assures latchup free operation. On Board Negative Supply for Dynamic RAMs Localized Processor (8080 Type) Negative Supplies Inexpensive Negative Supplies Data Acquisition Systems Ordering Information PART NUMBER TEMP RANGE o o 0 C to +70 C ICL7660CTV oC to +70oC ICL7660CBA 0 ICL7660CPA 0oC to +70oC ICL7660MTV (Note) oC 0 o to +70oC o The oscillator, when unloaded, oscillates at a nominal frequency of 10kHz for an input supply voltage of 5.0V. This frequency can be lowered by the addition of an external capacitor to the "OSC" terminal, or the oscillator may be overdriven by an external clock. PACKAGE 8 Pin Metal Can 8 Lead Plastic SOIC (N) The "LV" terminal may be tied to GROUND to bypass the internal series regulator and improve low voltage (LV) operation. At medium to high voltages (+3.5V to +10.0V for the ICL7660 and +3.5V to +12.0V for the ICL7660A), the LV pin is left floating to prevent device latchup. 8 Lead Plastic DIP 8 Pin Metal Can ICL7660ACBA 0 C to +70 C 8 Lead Plastic SOIC (N) ICL7660ACBAT 0oC to +70oC 8 Lead Plastic SOIC (N) Tape and Reel ICL7660ACPA 0oC to +70oC 8 Lead Plastic DIP -40oC to +85oC 8 Lead Plastic SOIC (N) ICL7660AIBA 0oC to +85oC ICL7660AIBAT 8 Lead Plastic SOIC (N) Tape and Reel -40oC to +85oC 8 Lead Plastic DIP ICL7660AIPA NOTE: Add /883B to part number if 883B processing is required. Pinouts ICL7660, ICL7660A (PDIP, SOIC) TOP VIEW ICL7660 (CAN) TOP VIEW V+ (AND CASE) NC 1 8 V+ CAP+ 2 7 OSC GND 3 6 LV CAP- 4 5 VOUT 8 NC CAP+ 1 7 2 GND OSC 6 5 3 LV VOUT 4 CAPCAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1995 1 File Number 3072.2 Specifications ICL7660, ICL7660A Absolute Maximum Ratings Thermal Information Supply Voltage ICL7660 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10.5V ICL7660A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V LV and OSC Input Voltage . . . . . . -0.3V to (V+ +0.3V) for V+ < 5.5V (Note 1) (V+ -5.5V) to (V+ +0.3V) for V+ > 5.5V Current into LV (Note 1) . . . . . . . . . . . . . . . . . . . 20A for V+ > 3.5V Output Short Duration (VSUPPLY 5.5V) . . . . . . . . . . . . Continuous Thermal Resistance JA JC Plastic DIP Package . . . . . . . . . . . . . . . . 150oC/W Plastic SOIC Package . . . . . . . . . . . . . . . 170oC/W Metal Can Package (ICL7660 Only) . . . . 156oC/W 68oC/W Storage Temperature Range. . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Temperature Range ICL7660M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC ICL7660C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC Electrical Specifications ICL7660AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC ICL7660AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC ICL7660 and ICL7660A, V+ = 5V, TA = +25oC, COSC = 0, Test Circuit Figure 11 Unless Otherwise Specified ICL7660 PARAMETER Supply Current SYMBOL I+ TEST CONDITIONS RL = MIN ICL7660A TYP MAX MIN TYP MAX UNITS - 170 500 - 80 165 A Supply Voltage Range - Lo VL+ MIN TA MAX, RL = 10k, LV to GND 1.5 - 3.5 1.5 - 3.5 V Supply Voltage Range - Hi VH+ MIN TA MAX, RL = 10k, LV to Open 3.0 - 10.0 3 - 12 V Output Source Resistance ROUT IOUT = 20mA, TA = +25oC - 55 100 - 60 100 IOUT = 20mA, 0oC TA +70oC - - 120 - - 120 IOUT = 20mA, -55oC TA +125oC - - 150 - - - IOUT = 20mA, -40oC TA +85oC - - - - - 120 V+ = 2V, IOUT = 3mA, LV to GND 0oC TA +70oC - - 300 - - 300 V+ = 2V, IOUT = 3mA, LV to GND, -55oC TA +125oC - - 400 - - - - 10 - - 10 - kHz RL = 5k 95 98 - 96 98 - % VOUT EF RL = 97 99.9 - 99 99.9 - % ZOSC V+ = 2V - 1.0 - - 1 - M V = 5V - 100 - - - - k Oscillator Frequency fOSC Power Efficiency PEF Voltage Conversion Efficiency Oscillator Impedance ICL7660A, V+ = 3V, TA = +25oC, OSC = Free running, Test Circuit Figure 11, Unless Otherwise Specified Supply Current (Note 3) Output Source Resistance I+ ROUT V+ = 3V, RL = , +25oC - - - - 26 100 A 0oC < TA < +70oC - - - - - 125 A -40oC < TA < +85oC - - - - - 125 A V+ = 3V, IOUT = 10mA - - - - 97 150 0oC < TA < +70oC - - - - - 200 -40oC < TA < +85oC - - - - - 200 2 Specifications ICL7660, ICL7660A Electrical Specifications ICL7660 and ICL7660A, V+ = 5V, TA = +25oC, COSC = 0, Test Circuit Figure 11 Unless Otherwise Specified (Continued) ICL7660 PARAMETER SYMBOL Oscillator Frequency (Note 3) Voltage Conversion Efficiency Power Efficiency fOSC TEST CONDITIONS TYP MAX MIN TYP MAX UNITS V+ = 3V (same as 5V conditions) - - - 5.0 8 - kHz 0oC < TA < +70oC - - - 3.0 - - kHz -40oC < TA < +85oC - - - 3.0 - - kHz - - - 99 - - % TMIN < TA < TMAX - - - 99 - - % V+ = 3V, RL = 5k - - - 96 - - % TMIN < TA < TMAX - - - 95 - - % VOUTEFF V+ = 3V, RL = PEFF MIN ICL7660A NOTE: 1. Connecting any input terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from sources operating from external supplies be applied prior to "power up" of the ICL7660, ICL7660A. 2. Derate linearly above +50oC by 5.5mW/oC 3. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very small but finite stray capacitance present, of the order of 5pF. 4. The Harris ICL7660A can operate without an external diode over the full temperature and voltage range. This device will function in existing designs which incorporate an external diode with no degradation in overall circuit performance. Functional Block Diagram V+ CAP+ RC OSCILLATOR /2 VOLTAGE LEVEL TRANSLATOR CAP- VOUT OSC LV VOLTAGE REGULATOR LOGIC NETWORK 3 ICL7660, ICL7660A Typical Performance Curves (Test Circuit of Figure 11) 10K SUPPLY VOLTAGE (V) 8 OUTPUT SOURCE RESISTANCE () 10 SUPPLY VOLTAGE RANGE (NO DIODE REQUIRED) 6 4 2 TA = +25oC 1000 100 10 0 -55 -25 0 25 50 100 0 125 1 2 o TEMPERATURE ( C) FIGURE 1. OPERATING VOLTAGE AS A FUNCTION OF TEMPERATURE POWER CONVERSION EFFICIENCY (%) OUTPUT SOURCE RESISTANCE () IOUT = 1mA 300 250 200 V+ = +2V 100 50 V+ = 5V 0 -55 -25 0 25 50 75 100 125 100 98 5 6 7 8 TA = +25oC 96 IOUT = 1mA 94 92 IOUT = 15mA 90 88 86 84 82 V+ = +5V 80 100 TEMPERATURE (oC) 1K 10K OSC. FREQUENCY fOSC (Hz) FIGURE 3. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF TEMPERATURE FIGURE 4. POWER CONVERSION EFFICIENCY AS A FUNCTION OF OSC. FREQUENCY 10K 20 OSCILLATOR FREQUENCY fOSC (kHz) OSCILLATOR FREQUENCY fOSC (Hz) 4 FIGURE 2. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF SUPPLY VOLTAGE 350 150 3 SUPPLY VOLTAGE (V+) 1K 100 V+ = 5V TA = +25oC 10 1.0 10 100 COSC (pF) 1000 10K 18 16 14 12 10 8 V+ = +5V 6 -50 -25 0 25 50 75 100 TEMPERATURE (oC) FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION OF EXTERNAL OSC. CAPACITANCE FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A FUNCTION OF TEMPERATURE 4 125 ICL7660, ICL7660A POWER CONVERSION EFFICIENCY (%) V+ = +5V 3 OUTPUT VOLTAGE 100 100 TA = +25oC 4 2 1 0 -1 -2 -3 -4 SLOPE 55 -5 90 PEFF 80 80 70 70 60 60 50 50 40 40 30 30 20 10 0 10 20 30 40 LOAD CURRENT IL (mA) POWER CONVERSION EFFICIENCY (%) OUTPUT VOLTAGE V = 2V +1 0 -1 SLOPE 150 1 60 100 TA = +25oC 0 50 FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS AFUNCTION OF LOAD CURRENT + -2 10 V+ = +5V 0 LOAD CURRENT IL (mA) +2 20 TA = +25oC 0 FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT 90 I+ 2 3 4 5 LOAD CURRENT IL (mA) 6 7 SUPPLY CURRENT I+ (mA) 5 (Test Circuit of Figure 11) (Continued) 20.0 90 16.0 PEFF 70 14.0 60 12.0 50 10.0 40 8.0 30 6.0 20 4.0 TA = +25oC 10 2.0 V + = 2V 0 0 0 8 18.0 I+ 80 SUPPLY CURRENT (mA) (NOTE 1) Typical Performance Curves 1.5 3.0 4.5 6.0 7.5 9.0 LOAD CURRENT IL (mA) FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT NOTE 1. These curves include in the supply current that current fed directly into the load RL from the V+ (See Figure 11). Thus, approximately half the supply current goes directly to the positive side of the load, and the other half, through the ICL7660/ICL7660A, to the negative side of the load. Ideally, VOUT 2VIN, IS 2IL, so VIN x IS VOUT x IL. IS V+ 1 2 C1 + 10F - 3 4 (+5V) 8 ICL7660 ICL7660A 7 IL 6 5 RL COSC (NOTE) -VOUT C2 10F + NOTE: For large values of COSC (>1000pF) the values of C1 and C2 should be increased to 100F. FIGURE 11. ICL7660, ICL7660A TEST CIRCUIT 5 ICL7660, ICL7660A Detailed Description Theoretical Power Efficiency Considerations The ICL7660 and ICL7660A contain all the necessary circuitry to complete a negative voltage converter, with the exception of 2 external capacitors which may be inexpensive 10F polarized electrolytic types. The mode of operation of the device may be best understood by considering Figure 12, which shows an idealized negative voltage converter. Capacitor C1 is charged to a voltage, V+, for the half cycle when switches S1 and S3 are closed. (Note: Switches S2 and S4 are open during this half cycle.) During the second half cycle of operation, switches S2 and S4 are closed, with S1 and S3 open, thereby shifting capacitor C1 negatively by V+ volts. Charge is then transferred from C1 to C2 such that the voltage on C2 is exactly V+, assuming ideal switches and no load on C2. The ICL7660 approaches this ideal situation more closely than existing non-mechanical circuits. In theory a voltage converter can approach 100% efficiency if certain conditions are met. where V1 and V2 are the voltages on C1 during the pump and transfer cycles. If the impedances of C1 and C2 are relatively high at the pump frequency (refer to Figure 12) compared to the value of RL, there will be a substantial difference in the voltages V1 and V2. Therefore it is not only desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C1 in order to achieve maximum efficiency of operation. Do's And Don'ts 1. Do not exceed maximum supply voltages. 2. Do not connect LV terminal to GROUND for supply voltages greater than 3.5V. 3. Do not short circuit the output to V+ supply for supply voltages above 5.5V for extended periods, however, transient conditions including start-up are okay. 4. When using polarized capacitors, the + terminal of C1 must be connected to pin 2 of the ICL7660 and ICL7660A and the + terminal of C2 must be connected to GROUND. S2 5. If the voltage supply driving the ICL7660 and ICL7660A has a large source impedance (25 - 30), then a 2.2F capacitor from pin 8 to ground may be required to limit rate of rise of input voltage to less than 2V/s. VIN C1 3 3 6. User should insure that the output (pin 5) does not go more positive than GND (pin 3). Device latch up will occur under these conditions. A 1N914 or similar diode placed in parallel with C2 will prevent the device from latching up under these conditions. (Anode pin 5, Cathode pin 3). C2 S4 S3 The output switches have extremely low ON resistance and virtually no offset. E = 1/2 C1 (V12 - V22) The voltage regulator portion of the ICL7660 and ICL7660A is an integral part of the anti-latchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation the "LV" pin should be connected to GROUND, disabling the regulator. For supply voltages greater than 3.5V the LV terminal must be left open to insure latchup proof operation, and prevent device damage. 2 B The ICL7660 and ICL7660A approach these conditions for negative voltage conversion if large values of C1 and C2 are used. ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE OCCURS. The energy lost is defined by: This problem is eliminated in the ICL7660 and ICL7660A by a logic network which senses the output voltage (VOUT) together with the level translators, and switches the substrates of S3 and S4 to the correct level to maintain necessary reverse bias. S1 The driver circuitry consumes minimal power. C The impedances of the pump and reservoir capacitors are negligible at the pump frequency. In the ICL7660 and ICL7660A, the 4 switches of Figure 12 are MOS power switches; S1 is a P-channel device and S2, S3 and S4 are N-channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S3 and S4 must always remain reverse biased with respect to their sources, but not so much as to degrade their "ON" resistances. In addition, at circuit start-up, and under output short circuit conditions (VOUT = V+), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power losses and probable device latchup. 8 A 5 VOUT = -VIN 7 FIGURE 12. IDEALIZED NEGATIVE VOLTAGE CONVERTER 6 ICL7660, ICL7660A V+ 1 8 2 10F + ICL7660 ICL7660A 3 - 4 RO 7 6 - 5 V+ + 10F VOUT VOUT = - V+ + FIGURE 13A. CONFIGURATION FIGURE 13B. THEVENIN EQUIVALENT FIGURE 13. SIMPLE NEGATIVE CONVERTER t1 t2 B 0 V A -(V+) FIGURE 14. OUTPUT RIPPLE V+ 1 2 3 C1 8 7 ICL7660 ICL7660A "1" 1 6 4 2 5 3 C1 8 RL 7 ICL7660 ICL7660A "n" 6 4 5 C2 + FIGURE 15. PARALLELING DEVICES V+ 1 2 10F + - 3 4 8 ICL7660 ICL7660A "1" 7 1 6 5 2 10F + - 3 4 10F 8 ICL7660 ICL7660A "n" 7 6 10F - VOUT = - nV+ 5 + + FIGURE 16. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE 7 ICL7660, ICL7660A potentially swamp out a low 1/(fPUMP * C1) term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as 10. Typical Applications Simple Negative Voltage Converter The majority of applications will undoubtedly utilize the ICL7660 and ICL7660A for generation of negative supply voltages. Figure 13 shows typical connections to provide a negative supply negative (GND) for supply voltages below 3.5V. Output Ripple ESR also affects the ripple voltage seen at the output. The total ripple is determined by 2 voltages, A and B, as shown in Figure 14. Segment A is the voltage drop across the ESR of C2 at the instant it goes from being charged by C1 (current flow into C2) to being discharged through the load (current flowing out of C2). The magnitude of this current change is 2* IOUT, hence the total drop is 2* IOUT * eSRC2V. Segment B is the voltage change across C2 during time t2, the half of the cycle when C2 supplies current to the load. The drop at B is lOUT * t2/C2V. The peak-to-peak ripple voltage is the sum of these voltage drops: The output characteristics of the circuit in Figure 13A can be approximated by an ideal voltage source in series with a resistance as shown in Figure 13B. The voltage source has a value of -V+. The output impedance (RO) is a function of the ON resistance of the internal MOS switches (shown in Figure 12), the switching frequency, the value of C1 and C2, and the ESR (equivalent series resistance) of C1 and C2. A good first order approximation for RO is: RO 2(RSW1 + RSW3 + ESRC1) + 2(RSW2 + RSW4 + ESRC1) + VRIPPLE 1 fOSC + 2 (ESRC2) ] IOUT Again, a low ESR capacitor will reset in a higher performance output. , RSWX = MOSFET switch resistance) 2 Paralleling Devices Combining the four RSWX terms as RSW, we see that: RO 2 (fPUMP) (C2) + ESRC2 (fPUMP) (C1) (fPUMP = [ 1 Any number of ICL7660 and ICL7660A voltage converters may be paralleled to reduce output resistance. The reservoir capacitor, C2, serves all devices while each device requires its own pump capacitor, C1. The resultant output resistance would be approximately: 1 2 (RSW) + (fPUMP) (C1) + 4 (ESRC1) + ESRC2 RSW, the total switch resistance, is a function of supply voltage and temperature (See the Output Source Resistance graphs), typically 23 at +25oC and 5V. Careful selection of C1 and C2 will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce the 1/(fPUMP * C1) component, and low ESR capacitors will lower the ESR term. Increasing the oscillator frequency will reduce the 1/(fPUMP * C1) term, but may have the side effect of a net increase in output impedance when C1 > 10F and there is no longer enough time to fully charge the capacitors every cycle. In a typical application where fOSC = 10kHz and C = C1 = C2 = 10F: ROUT = ROUT (of ICL7660/ICL7660A) n (number of devices) Cascading Devices The ICL7660 and ICL7660A may be cascaded as shown to produced larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is 10 devices for light loads. The output voltage is defined by: VOUT = -n (VIN), RO 2 (23) + 1 (5 * 103) (10-5) where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7660 and ICL7660A ROUT values. + 4 (ESRC1) + ESRC2 RO 46 + 20 + 5 (ESRC) Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could potentially swamp out a low 1/(fPUMP * C1) term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as 10. RO 2 (23) + Changing the ICL7660/ICL7660A Oscillator Frequency It may be desirable in some applications, due to noise or other considerations, to increase the oscillator frequency. This is achieved by overdriving the oscillator from an external clock, as shown in Figure 17. In order to prevent possible device latchup, a 1k resistor must be used in series with the clock output. In a situation where the designer has generated the external clock frequency using TTL logic, the addition of a 10k pullup resistor to V+ supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be 1/2 of the clock frequency. Output transitions occur on the positive-going edge of the clock. 1 (5 * 103) (10-5) + 4 (ESRC1) + ESRC2 RO/ 46 + 20 + 5 (ESRC) Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could 8 ICL7660, ICL7660A V+ 1 V+ 1k 2 10F + ICL7660 ICL7660A 3 - Combined Negative Voltage Conversion and Positive Supply Doubling 8 4 CMOS GATE 7 Figure 20 combines the functions shown in Figures 13 and Figure 19 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for example, suitable for generating +9V and -5V from an existing +5V supply. In this instance capacitors C1 and C3 perform the pump and reservoir functions respectively for the generation of the negative voltage, while capacitors C2 and C4 are pump and reservoir respectively for the doubled positive voltage. There is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the finite impedance of the common charge pump driver at pin 2 of the device. 6 5 VOUT - 10F + FIGURE 17. EXTERNAL CLOCKING It is also possible to increase the conversion efficiency of the ICL7660 and ICL7660A at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is shown in Figure 18. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C1) and reservoir (C2) capacitors; this is overcome by increasing the values of C1 and C2 by the same factor that the frequency has been reduced. For example, the addition of a 100pF capacitor between pin 7 (OSC) and V+ will lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C1 and C2 (from 10F to 100F). V+ 1 2 + C1 - 3 8 ICL7660 ICL7660A 4 + C1 - 8 2 7 3 ICL7660 ICL7660A 4 7 - + 5 + C2 Voltage Splitting The bidirectional characteristics can also be used to split a higher supply in half, as shown in Figure 21. The combined load will be evenly shared between the two sides. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit, and then the circuit of Figure 16, +15V can be converted (via +7.5, and -7.5) to a nominal -15V, although with rather high series output resistance (~250). V+ + RL1 50F 1 The source impedance of the output (VOUT) will depend on the output current, but for V+ = 5V and an output current of 10mA it will be approximately 60. VOUT = V+ - V2 RL2 50F 2 + 3 - 4 4 50F 8 6 8 ICL7660 ICL7660A 7 6 5 + V+ 3 C4 FIGURE 20. COMBINED NEGATIVE VOLTAGE CONVERTER AND POSITIVE DOUBLER VOUT - The ICL7660 and ICL7660A may be employed to achieve positive voltage doubling using the circuit shown in Figure 19. In this application, the pump inverter switches of the ICL7660 and ICL7660A are used to charge C1 to a voltage level of V+ -VF (where V+ is the supply voltage and VF is the forward voltage drop of diode D1). On the transfer cycle, the voltage on C1 plus the supply voltage (V+) is applied through diode D2 to capacitor C2. The voltage thus created on C2 becomes (2V+) - (2VF) or twice the supply voltage minus the combined forward voltage drops of diodes D1 and D2. 7 VOUT = (2V+) (VFD1) - (VFD2) 6 Positive Voltage Doubling ICL7660 ICL7660A D2 6 - FIGURE 18. LOWERING OSCILLATOR FREQUENCY 2 C3 + C2 COSC + 1 D1 5 V+ 1 VOUT = - (nVIN - VFDX) V- D1 FIGURE 21. SPLITTING A SUPPLY IN HALF VOUT = (2V+) - (2VF) D2 5 + - + C1 - C2 FIGURE 19. POSITIVE VOLTAGE DOUBLER 9 ICL7660, ICL7660A Regulated Negative Voltage Supply 50k +8V In some cases, the output impedance of the ICL7660 and ICL7660A can be a problem, particularly if the load current varies substantially. The circuit of Figure 22 can be used to overcome this by controlling the input voltage, via an ICL7611 low-power CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since the ICL7660s and ICL7660As output does not respond instantaneously to change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the ICL7660 and ICL7660A, while maintaining adequate feedback. An increase in pump and storage capacitors is desirable, and the values shown provides an output impedance of less than 5 to a load of 10mA. 56k +8V ICL7611 100k + 1 8 2 ICL8069 100F + - ICL7660 ICL7660A 3 4 250k VOLTAGE ADJUST 12 11 16 1 4 3 15 2 10F - 3 4 RS232 DATA OUTPUT 8 ICL7660 ICL7660A 7 IH5142 6 13 14 5 10F 6 VOUT 100F + FIGURE 22. REGULATING THE OUTPUT VOLTAGE +5V LOGIC SUPPLY + 7 5 800k Further information on the operation and use of the ICL7660 and ICL7660A may be found in A051 "Principals and Applications of the ICL7660 and ICL7660A CMOS Voltage Converter". 1 10F + - Other Applications TTL DATA INPUT - 100 50k + FIGURE 23. RS232 LEVELS FROM A SINGLE 5V SUPPLY 10 +5V -5V ICL7660, ICL7660A Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE N INCHES E1 INDEX AREA 1 2 3 N/2 SYMBOL -B- -AE D BASE PLANE A2 -C- SEATING PLANE A L D1 e B1 D1 B 0.010 (0.25) M C L eA A1 eC C A B S C eB NOTES: MILLIMETERS MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 D1 0.005 - 0.13 10.16 - 5 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eB - 0.430 - 10.92 7 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4 N 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 8 8 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 11 ICL7660, ICL7660A Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N NOTES: MILLIMETERS MAX A1 e MIN 8 0o 8 7 8o Rev. 0 12/93 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 12 ICL7660, ICL7660A Metal Can Packages (Can) T8.C MIL-STD-1835 MACY1-X8 (A1) REFERENCE PLANE A 8 LEAD METAL CAN PACKAGE e1 L L2 L1 INCHES OD2 A A k1 Oe OD OD1 2 N 1 F Ob1 Ob k C L BASE AND SEATING PLANE Q BASE METAL Ob1 SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.185 4.19 4.70 - Ob 0.016 0.019 0.41 0.48 1 Ob1 0.016 0.021 0.41 0.53 1 Ob2 0.016 0.024 0.41 0.61 - OD 0.335 0.375 8.51 9.40 - OD1 0.305 0.335 7.75 8.51 - OD2 0.110 0.160 2.79 4.06 - e 0.200 BSC 5.08 BSC - e1 0.100 BSC 2.54 BSC - F - 0.040 - 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 L 0.500 0.750 12.70 19.05 1 L1 - 0.050 - 1.27 1 L2 0.250 - 6.35 - 1 Q 0.010 0.045 0.25 1.14 LEAD FINISH Ob2 SECTION A-A NOTES: 1. (All leads) Ob applies between L1 and L2. Ob1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. MILLIMETERS - 45o BSC 45o BSC 3 45o BSC 45o BSC 3 N 8 8 4 2. Measured from maximum diameter of the product. Rev. 0 5/18/94 3. is the basic spacing from the centerline of the tab to terminal 1 and is the basic spacing of each lead or lead position (N -1 places) from , looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries. Sales Office Headquarters For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS NORTH AMERICA Harris Semiconductor P. O. Box 883, Mail Stop 53-210 Melbourne, FL 32902 TEL: 1-800-442-7747 (407) 729-4984 FAX: (407) 729-5321 EUROPE Harris Semiconductor Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 S E M I C O N D U C T O R 13 ASIA Harris Semiconductor PTE Ltd. No. 1 Tannery Road Cencon 1, #09-01 Singapore 1334 TEL: (65) 748-4200 FAX: (65) 748-0400