CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1995 1
SEMICONDUCTOR
ICL7660, ICL7660A
CMOS Voltage Converters
Description
The Harris ICL7660 and ICL7660A are monolithic CMOS
power supply circuits which offer unique performance
advantages over previously available devices. The ICL7660
performs supply voltage conversions from positive to
negative for an input range of +1.5V to +10.0V resulting in
complementary output voltages of -1.5V to -10.0V and the
ICL7660A does the same conversions with an input range of
+1.5V to +12.0V resulting in complementary output voltages
of -1.5V to -12.0V. Only 2 non-critical external capacitors are
needed for the charge pump and charge reservoir functions.
The ICL7660 and ICL7660A can also be connected to
function as voltage doublers and will generate output
voltages up to +18.6V with a +10V input.
Contained on the chip are a series DC supply regulator, RC
oscillator, voltage level translator, and four output power
MOS switches. A unique logic element senses the most
negative voltage in the device and ensures that the output
N-Channel switch source-substrate junctions are not forward
biased. This assures latchup free operation.
The oscillator, when unloaded, oscillates at a nominal
frequency of 10kHz for an input supply voltage of 5.0V. This
frequency can be lowered by the addition of an external
capacitor to the “OSC” terminal, or the oscillator may be
overdriven by an external clock.
The “LV” terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV)
operation. At medium to high voltages (+3.5V to +10.0V for
the ICL7660 and +3.5V to +12.0V for the ICL7660A), the LV
pin is left floating to prevent device latchup.
November 1995
Pinouts
ICL7660, ICL7660A (PDIP, SOIC)
TOP VIEW ICL7660 (CAN)
TOP VIEW
NC
CAP+
GND
CAP-
1
2
3
4
8
7
6
5
V+
OSC
LV
VOUT
V+ (AND CASE)
LV
CAP+
NC
GND
OSC
VOUT
2
4
6
1
3
7
5
8
CAP-
File Number 3072.2
Features
• Simple Conversion of +5V Logic Supply to ± 5V Supplies
• Simple Voltage Multiplication (VOUT = (-) nVIN)
• Typical Open Circuit Voltage Conversion Efficiency 99.9%
• Typical Power Efficiency 98%
• Wide Operating Voltage Range
- ICL7660 . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 10.0V
- ICL7660A. . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 12.0V
• ICL7660A 100% Tested at 3V
• Easy to Use - Requires Only 2 External Non-Critical
Passive Components
• No External Diode Over Full Temp. and Voltage Range
Applications
• On Board Negative Supply for Dynamic RAMs
• Localized µProcessor (8080 Type) Negative Supplies
• Inexpensive Negative Supplies
• Data Acquisition Systems
Ordering Information
PART NUMBER TEMP RANGE PACKAGE
ICL7660CTV 0oC to +70oC 8 Pin Metal Can
ICL7660CBA 0oC to +70oC 8 Lead Plastic SOIC (N)
ICL7660CPA 0oC to +70oC 8 Lead Plastic DIP
ICL7660MTV (Note) 0oC to +70oC 8 Pin Metal Can
ICL7660ACBA 0oC to +70oC 8 Lead Plastic SOIC (N)
ICL7660ACBAT 0oC to +70oC 8 Lead Plastic SOIC (N)
Tape and Reel
ICL7660ACPA 0oC to +70oC 8 Lead Plastic DIP
ICL7660AIBA -40oC to +85oC 8 Lead Plastic SOIC (N)
ICL7660AIBAT 0oC to +85oC 8 Lead Plastic SOIC (N)
Tape and Reel
ICL7660AIPA -40oC to +85oC 8 Lead Plastic DIP
NOTE: Add /883B to part number if 883B processing is required.
2
Specifications ICL7660, ICL7660A
Absolute Maximum Ratings Thermal Information
Supply Voltage
ICL7660 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+10.5V
ICL7660A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+13.0V
LV and OSC Input Voltage . . . . . . -0.3V to (V+ +0.3V) for V+ < 5.5V
(Note 1) (V+ -5.5V) to (V+ +0.3V) for V+ > 5.5V
Current into LV (Note 1) . . . . . . . . . . . . . . . . . . . 20µA for V+ > 3.5V
Output Short Duration (VSUPPLY ≤5.5V) . . . . . . . . . . . . Continuous
Thermal Resistance θJA θJC
Plastic DIP Package . . . . . . . . . . . . . . . . 150oC/W -
Plastic SOIC Package. . . . . . . . . . . . . . . 170oC/W -
Metal Can Package (ICL7660 Only) . . . . 156oC/W 68oC/W
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65oC to +150oC
Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Temperature Range
ICL7660M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
ICL7660C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oCICL7660AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC
ICL7660AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
Electrical Specifications ICL7660 and ICL7660A, V+ = 5V, TA = +25oC, COSC = 0, Test Circuit Figure 11
Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
ICL7660 ICL7660A
UNITSMIN TYP MAX MIN TYP MAX
Supply Current I+ RL = ∞- 170 500 - 80 165 µA
Supply Voltage Range - Lo VL+ MIN ≤ TA≤ MAX, RL = 10kΩ, LV to GND 1.5 - 3.5 1.5 - 3.5 V
Supply Voltage Range - Hi VH+ MIN ≤ TA≤ MAX, RL = 10kΩ, LV to Open 3.0 - 10.0 3 - 12 V
Output Source Resistance ROUT IOUT = 20mA, TA = +25oC - 55 100 - 60 100 Ω
IOUT = 20mA, 0oC≤ TA≤ +70oC - - 120 - - 120 Ω
IOUT = 20mA, -55oC≤ TA≤ +125oC - - 150 - - - Ω
IOUT = 20mA, -40oC≤ TA≤ +85oC -----120Ω
V
+
= 2V, IOUT = 3mA, LV to GND
0oC≤ TA≤ +70oC- - 300 - - 300 Ω
V+ = 2V, IOUT = 3mA, LV to GND,
-55oC≤ TA≤ +125oC--400---Ω
Oscillator Frequency fOSC -10- -10-kHz
Power Efficiency PEF RL = 5kΩ95 98 - 96 98 - %
Voltage Conversion Efficiency VOUT EF RL = ∞97 99.9 - 99 99.9 - %
Oscillator Impedance ZOSC V+ = 2V - 1.0 - - 1 - MΩ
V = 5V -100----kΩ
ICL7660A, V+ = 3V, TA = +25oC, OSC = Free running, Test Circuit Figure 11, Unless Otherwise Specified
Supply Current (Note 3) I+ V+ = 3V, RL = ∞, +25oC ----26100µA
0
o
C < TA< +70oC -----125µA
-40oC < TA < +85oC -----125µA
Output Source Resistance ROUT V+ = 3V, IOUT = 10mA ----97150Ω
0
o
C < TA< +70oC -----200Ω
-40oC < TA < +85oC -----200Ω
3
Specifications ICL7660, ICL7660A
Functional Block Diagram
Oscillator Frequency (Note 3) fOSC V+ = 3V (same as 5V conditions) - - - 5.0 8 - kHz
0oC < TA< +70oC - - - 3.0 - - kHz
-40oC < TA < +85oC - - - 3.0 - - kHz
Voltage Conversion Efficiency VOUTEFF V+ = 3V, RL = ∞---99--%
T
MIN < TA < TMAX ---99--%
Power Efficiency PEFF V+ = 3V, RL = 5kΩ---96--%
T
MIN < TA < TMAX ---95--%
NOTE:
1. Connecting any input terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no
inputs from sources operating from external supplies be applied prior to “power up” of the ICL7660, ICL7660A.
2. Derate linearly above +50oC by 5.5mW/oC
3. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually
a very small but finite stray capacitance present, of the order of 5pF.
4. The Harris ICL7660A can operate without an external diode over the full temperature and voltage range. This device will function in
existing designs which incorporate an external diode with no degradation in overall circuit performance.
Electrical Specifications ICL7660 and ICL7660A, V+ = 5V, TA = +25oC, COSC = 0, Test Circuit Figure 11
Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS
ICL7660 ICL7660A
UNITSMIN TYP MAX MIN TYP MAX
RC
OSCILLATOR ÷2VOLTAGE
LEVEL
TRANSLATOR
VOLTAGE
REGULATOR LOGIC
NETWORK
OSC LV
V+
CAP+
CAP-
VOUT
4
ICL7660, ICL7660A
Typical Performance Curves
(Test Circuit of Figure 11)
FIGURE 1. OPERATING VOLTAGE AS A FUNCTION OF
TEMPERATURE FIGURE 2. OUTPUT SOURCE RESISTANCE AS A FUNCTION
OF SUPPLY VOLTAGE
FIGURE 3. OUTPUT SOURCE RESISTANCE AS A FUNCTION
OF TEMPERATURE FIGURE 4. POWER CONVERSION EFFICIENCY AS A
FUNCTION OF OSC. FREQUENCY
FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION
OF EXTERNAL OSC. CAPACITANCE FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A
FUNCTION OF TEMPERATURE
10
SUPPLY VOLTAGE RANGE
(NO DIODE REQUIRED)
8
6
4
2
0-55 -25 0 25 50 100 125
TEMPERATURE (oC)
SUPPLY VOLTAGE (V)
10K
TA = +25oC
1000
100
1001 2345678
SUPPLY VOLTAGE (V+)
OUTPUT SOURCE RESISTANCE (Ω)
350
300
250
200
150
100
50
0
-55 -25 0 25 50 75 100 125
TEMPERATURE (oC)
OUTPUT SOURCE RESISTANCE (Ω)
IOUT = 1mA
V+ = +2V
V+ = 5V
POWER CONVERSION EFFICIENCY (%)
TA = +25oC
IOUT = 1mA
IOUT = 15mA
100
98
96
94
92
90
88
86
84
82
80100 1K 10K
OSC. FREQUENCY fOSC (Hz)
V+ = +5V
OSCILLATOR FREQUENCY fOSC (Hz)
10K
1K
100
10
V+ = 5V
TA = +25oC
1.0 10 100 1000 10K
COSC (pF)
20
18
16
14
12
10
8
6-50 -25 0 25 50 75 100 125
OSCILLATOR FREQUENCY fOSC (kHz)
TEMPERATURE (oC)
V+ = +5V
5
ICL7660, ICL7660A
FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT
CURRENT FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS AFUNCTION OF LOAD CURRENT
FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT
CURRENT FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD CURRENT
NOTE 1. These curves include in the supply current that current fed directly into the load RL from the V+ (See Figure 11). Thus, approxi-
mately half the supply current goes directly to the positive side of the load, and the other half, through the ICL7660/ICL7660A, to the nega-
tive side of the load. Ideally, VOUT ∼2VIN, IS∼ 2IL, so VIN x IS∼ VOUT x IL.
NOTE: For large values of COSC (>1000pF) the values of C1 and C2 should be increased to 100µF.
FIGURE 11. ICL7660, ICL7660A TEST CIRCUIT
Typical Performance Curves
(Test Circuit of Figure 11) (Continued)
TA = +25oC
V+ = +5V
5
4
3
2
1
0
-1
-2
-3
-4
-5
OUTPUT VOLTAGE
LOAD CURRENT IL (mA)
SLOPE 55Ω
PEFF I+
TA = +25oC
V+ = +5V
SUPPLY CURRENT I+ (mA)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
00102030405060
POWER CONVERSION EFFICIENCY (%)
LOAD CURRENT IL (mA)
TA = +25oC
V+ = 2V
+2
+1
0
-1
-2
SLOPE 150Ω
012345678
LOAD CURRENT IL (mA)
OUTPUT VOLTAGE
100
90
80
70
60
50
40
30
20
10
0
POWER CONVERSION EFFICIENCY (%)
PEFF
I+
LOAD CURRENT IL (mA)
0 1.5 3.0 4.5 6.0 7.5 9.0
20.0
18.0
16.0
14.0
12.0
10.0
8.0
6.0
4.0
2.0
0
SUPPLY CURRENT (mA) (NOTE 1)
TA = +25oC
V+ = 2V
1
2
3
4
8
7
6
5
+
-
C1
10µF
ISV+(+5V)
IL
RL
-VOUT
C2
10µF
ICL7660
COSC
+
-
(NOTE)
ICL7660A
6
ICL7660, ICL7660A
Detailed Description
The ICL7660 and ICL7660A contain all the necessary cir-
cuitry to complete a negative voltage converter, with the
exception of 2 external capacitors which may be inexpensive
10µF polarized electrolytic types. The mode of operation of
the device may be best understood by considering Figure
12, which shows an idealized negative voltage converter.
Capacitor C1 is charged to a voltage, V+, for the half cycle
when switches S1 and S3 are closed. (Note: Switches S2
and S4 are open during this half cycle.) During the second
half cycle of operation, switches S2 and S4 are closed, with
S1 and S3 open, thereby shifting capacitor C1 negatively by
V+ volts. Charge is then transferred from C1 to C2 such that
the voltage on C2 is exactly V+, assuming ideal switches and
no load on C2. The ICL7660 approaches this ideal situation
more closely than existing non-mechanical circuits.
In the ICL7660 and ICL7660A, the 4 switches of Figure 12
are MOS power switches; S1 is a P-channel device and S2,
S3 and S4 are N-channel devices. The main difficulty with
this approach is that in integrating the switches, the sub-
strates of S3 and S4 must always remain reverse biased with
respect to their sources, but not so much as to degrade their
“ON” resistances. In addition, at circuit start-up, and under
output short circuit conditions (VOUT = V+), the output volt-
age must be sensed and the substrate bias adjusted accord-
ingly. Failure to accomplish this would result in high power
losses and probable device latchup.
This problem is eliminated in the ICL7660 and ICL7660A by
a logic network which senses the output voltage (VOUT)
together with the level translators, and switches the sub-
strates of S3 and S4 to the correct level to maintain neces-
sary reverse bias.
The voltage regulator portion of the ICL7660 and ICL7660A
is an integral part of the anti-latchup circuitry, however its
inherent voltage drop can degrade operation at low voltages.
Therefore, to improve low voltage operation the “LV” pin
should be connected to GROUND, disabling the regulator.
For supply voltages greater than 3.5V the LV terminal must
be left open to insure latchup proof operation, and prevent
device damage.
FIGURE 12. IDEALIZED NEGATIVE VOLTAGE CONVERTER
VOUT = -VIN
C2
VIN
C1
S3S4
S1S2
8
3
2
5
3
7
Theoretical Power Efficiency
Considerations
In theory a voltage converter can approach 100% efficiency
if certain conditions are met.
A The driver circuitry consumes minimal power.
B The output switches have extremely low ON resis-
tance and virtually no offset.
C The impedances of the pump and reservoir capaci-
tors are negligible at the pump frequency.
The ICL7660 and ICL7660A approach these conditions for
negative voltage conversion if large values of C1 and C2 are
used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E = 1/2 C1 (V12 - V22)
where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C1 and C2 are rela-
tively high at the pump frequency (refer to Figure 12) com-
pared to the value of RL, there will be a substantial
difference in the voltages V1 and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate output
voltage ripple, but also to employ a correspondingly large
value for C1 in order to achieve maximum efficiency of oper-
ation.
Do’s And Don’ts
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GROUND for supply volt-
ages greater than 3.5V.
3. Do not short circuit the output to V+ supply for supply
voltages above 5.5V for extended periods, however,
transient conditions including start-up are okay.
4. When using polarized capacitors, the + terminal of C1
must be connected to pin 2 of the ICL7660 and
ICL7660A and the + terminal of C2 must be connected
to GROUND.
5. If the voltage supply driving the ICL7660 and ICL7660A
has a large source impedance (25Ω - 30Ω), then a
2.2µF capacitor from pin 8 to ground may be required to
limit rate of rise of input voltage to less than 2V/µs.
6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will
occur under these conditions. A 1N914 or similar diode
placed in parallel with C2 will prevent the device from
latching up under these conditions. (Anode pin 5, Cath-
ode pin 3).
7
ICL7660, ICL7660A
FIGURE 13A. CONFIGURATION FIGURE 13B. THEVENIN EQUIVALENT
FIGURE 13. SIMPLE NEGATIVE CONVERTER
FIGURE 14. OUTPUT RIPPLE
FIGURE 15. PARALLELING DEVICES
FIGURE 16. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE
1
2
3
4
8
7
6
5
+
-
10µF
ICL7660
VOUT = -V+
V+
+
-
10µF
ICL7660A
V++
-
ROVOUT
A
t2t1
B
0
-(V+)
V
1
2
3
4
8
7
6
5
ICL7660
V+
C1ICL7660A 1
2
3
4
8
7
6
5
ICL7660
C1ICL7660A
RL
+
-
C2
“n”
“1”
1
2
3
4
8
7
6
5
V+
1
2
3
4
8
7
6
5
+
-
10µF
+
-
10µF
+
-
10µF+
-
10µF
VOUT = -nV+
ICL7660
ICL7660A
“n”
ICL7660
ICL7660A
“1”
8
ICL7660, ICL7660A
Typical Applications
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660 and ICL7660A for generation of negative supply volt-
ages. Figure 13 shows typical connections to provide a nega-
tive supply negative (GND) for supply voltages below 3.5V.
The output characteristics of the circuit in Figure 13A can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 13B. The voltage source has
a value of -V+. The output impedance (RO) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 12), the switching frequency, the value of C1 and C2,
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for RO is:
RSW, the total switch resistance, is a function of supply volt-
age and temperature (See the Output Source Resistance
graphs), typically 23Ω at +25oC and 5V. Careful selection of
C1 and C2 will reduce the remaining terms, minimizing the
output impedance. High value capacitors will reduce the
1/(fPUMP • C
1
) component, and low ESR capacitors will
lower the ESR term. Increasing the oscillator frequency will
reduce the 1/(fPUMP •C1) term, but may have the side effect
of a net increase in output impedance when C1 > 10µF and
there is no longer enough time to fully charge the capacitors
every cycle. In a typical application where fOSC = 10kHz and
C = C1 = C2 = 10µF:
RO≅ 46 + 20 + 5 (ESRC)
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(fPUMP • C1) term, rendering
an increase in switching frequency or filter capacitance inef-
fective. Typical electrolytic capacitors may have ESRs as
high as 10Ω.
RO/ ≅ 46 + 20 + 5 (ESRC)
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
RO≅2(RSW1 + RSW3 + ESRC1) +
2(RSW2 + RSW4 + ESRC1) +
1+ ESRC2
(fPUMP) (C1)
(fPUMP = fOSC , RSWX = MOSFET switch resistance)
2
Combining the four RSWX terms as RSW, we see that:
RO≅2 (RSW) + 1+ 4 (ESRC1) + ESRC2
(fPUMP) (C1)
RO≅2 (23) + 1+ 4 (ESRC1) + ESRC2
(5 • 103) (10-5)
RO≅2 (23) + 1+ 4 (ESRC1) + ESRC2
(5 • 103) (10-5)
potentially swamp out a low 1/(fPUMP • C1) term, rendering
an increase in switching frequency or filter capacitance inef-
fective. Typical electrolytic capacitors may have ESRs as
high as 10Ω.
Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown in
Figure 14. Segment A is the voltage drop across the ESR of
C2 at the instant it goes from being charged by C1 (current
flow into C2) to being discharged through the load (current
flowing out of C2). The magnitude of this current change is
2• IOUT, hence the total drop is 2• IOUT • eSRC2V. Segment B
is the voltage change across C2 during time t2, the half of the
cycle when C2 supplies current to the load. The drop at B is
lOUT • t2/C2V. The peak-to-peak ripple voltage is the sum of
these voltage drops:
Again, a low ESR capacitor will reset in a higher perfor-
mance output.
Paralleling Devices
Any number of ICL7660 and ICL7660A voltage converters
may be paralleled to reduce output resistance. The reservoir
capacitor, C2, serves all devices while each device requires
its own pump capacitor, C1. The resultant output resistance
would be approximately:
Cascading Devices
The ICL7660 and ICL7660A may be cascaded as shown to
produced larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
VOUT = -n (VIN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approxi-
mately the weighted sum of the individual ICL7660 and
ICL7660A ROUT values.
Changing the ICL7660/ICL7660A Oscillator Frequency
It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an exter-
nal clock, as shown in Figure 17. In order to prevent possible
device latchup, a 1kΩ resistor must be used in series with
the clock output. In a situation where the designer has gen-
erated the external clock frequency using TTL logic, the
addition of a 10kΩ pullup resistor to V+ supply is required.
Note that the pump frequency with external clocking, as with
internal clocking, will be 1/2 of the clock frequency. Output
transitions occur on the positive-going edge of the clock.
VRIPPLE ≅[1+ 2 (ESRC2)]IOUT
2 (fPUMP) (C2)
ROUT = ROUT (of ICL7660/ICL7660A)
n (number of devices)
9
ICL7660, ICL7660A
FIGURE 17. EXTERNAL CLOCKING
It is also possible to increase the conversion efficiency of the
ICL7660 and ICL7660A at low load levels by lowering the
oscillator frequency. This reduces the switching losses, and
is shown in Figure 18. However, lowering the oscillator fre-
quency will cause an undesirable increase in the impedance
of the pump (C1) and reservoir (C2) capacitors; this is over-
come by increasing the values of C1 and C2 by the same
factor that the frequency has been reduced. For example,
the addition of a 100pF capacitor between pin 7 (OSC) and
V+ will lower the oscillator frequency to 1kHz from its nomi-
nal frequency of 10kHz (a multiple of 10), and thereby
necessitate a corresponding increase in the value of C1 and
C2 (from 10µF to 100µF).
FIGURE 18. LOWERING OSCILLATOR FREQUENCY
Positive Voltage Doubling
The ICL7660 and ICL7660A may be employed to achieve
positive voltage doubling using the circuit shown in Figure
19. In this application, the pump inverter switches of the
ICL7660 and ICL7660A are used to charge C1 to a voltage
level of V+ -VF (where V+ is the supply voltage and VFis the
forward voltage drop of diode D1). On the transfer cycle, the
voltage on C1 plus the supply voltage (V+) is applied through
diode D2 to capacitor C2. The voltage thus created on C2
becomes (2V+) - (2VF) or twice the supply voltage minus the
combined forward voltage drops of diodes D1 and D2.
The source impedance of the output (VOUT) will depend on
the output current, but for V+ = 5V and an output current of
10mA it will be approximately 60Ω.
FIGURE 19. POSITIVE VOLTAGE DOUBLER
1
2
3
4
8
7
6
5
+
-
10µFICL7660
VOUT
V+
+
-10µF
V+
CMOS
GATE
1kΩ
ICL7660A
1
2
3
4
8
7
6
5
+
-VOUT
V+
+
-C2
C1
COSC
ICL7660
ICL7660A
1
2
3
4
8
7
6
5
V+
D2
C1C2
VOUT =
(2V+) - (2VF)
+
-
+
-
D1
ICL7660
ICL7660A
Combined Negative Voltage Conversion
and Positive Supply Doubling
Figure 20 combines the functions shown in Figures 13 and
Figure 19 to provide negative voltage conversion and posi-
tive voltage doubling simultaneously. This approach would
be, for example, suitable for generating +9V and -5V from an
existing +5V supply. In this instance capacitors C1 and C3
perform the pump and reservoir functions respectively for
the generation of the negative voltage, while capacitors C2
and C4 are pump and reservoir respectively for the doubled
positive voltage. There is a penalty in this configuration
which combines both functions, however, in that the source
impedances of the generated supplies will be somewhat
higher due to the finite impedance of the common charge
pump driver at pin 2 of the device.
FIGURE 20. COMBINED NEGATIVE VOLTAGE CONVERTER
AND POSITIVE DOUBLER
Voltage Splitting
The bidirectional characteristics can also be used to split a
higher supply in half, as shown in Figure 21. The combined
load will be evenly shared between the two sides. Because
the switches share the load in parallel, the output impedance
is much lower than in the standard circuits, and higher cur-
rents can be drawn from the device. By using this circuit, and
then the circuit of Figure 16, +15V can be converted (via
+7.5, and -7.5) to a nominal -15V, although with rather high
series output resistance (~250Ω).
FIGURE 21. SPLITTING A SUPPLY IN HALF
1
2
3
4
8
7
6
5
V+
D1
D2
C4
VOUT = (2V+) -
(VFD1)- (VFD2)
+
-
C2
+
-
C3
+
-
VOUT =
- (nVIN - VFDX)
C1
+
-
ICL7660
ICL7660A
1
2
3
4
8
7
6
5
+
-
+
-
50µF
50µF
+
-
50µF
RL1
VOUT = V+ - V-
2
V+
V-
RL2
ICL7660
ICL7660A
10
ICL7660, ICL7660A
Regulated Negative Voltage Supply
In some cases, the output impedance of the ICL7660 and
ICL7660A can be a problem, particularly if the load current
varies substantially. The circuit of Figure 22 can be used to
overcome this by controlling the input voltage, via an
ICL7611 low-power CMOS op amp, in such a way as to
maintain a nearly constant output voltage. Direct feedback is
inadvisable, since the ICL7660s and ICL7660As output does
not respond instantaneously to change in input, but only
after the switching delay. The circuit shown supplies enough
delay to accommodate the ICL7660 and ICL7660A, while
maintaining adequate feedback. An increase in pump and
storage capacitors is desirable, and the values shown
provides an output impedance of less than 5Ω to a load
of 10mA.
Other Applications
Further information on the operation and use of the ICL7660
and ICL7660A may be found in A051 “Principals and
Applications of the ICL7660 and ICL7660A CMOS Voltage
Converter”.
FIGURE 22. REGULATING THE OUTPUT VOLTAGE
1
2
3
4
8
7
6
5
+
-
100µF
100µF
VOUT
+
-10µF
ICL7611
+
-100Ω
50k
+8V
100k
50k
ICL8069
56k
+8V
800k 250k
VOLTAGE
ADJUST
-
+
ICL7660
ICL7660A
FIGURE 23. RS232 LEVELS FROM A SINGLE 5V SUPPLY
1
2
3
4
8
7
6
5
+
-
+
-
10µF
16
TTL DATA
INPUT
15
4
10µF
13 14
12 11
+5V LOGIC SUPPLY
RS232
DATA
OUTPUT
IH5142
1
3+5V
-5V
ICL7660
ICL7660A
11
ICL7660, ICL7660A
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C A
MBS
eA-C-
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.355 0.400 9.01 10.16 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93
12
ICL7660, ICL7660A
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
0.25(0.010) B
MM
α
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
α
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
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Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
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FAX: (65) 748-0400
SEMICONDUCTOR
13
ICL7660, ICL7660A
Metal Can Packages (Can)
NOTES:
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
2. Measured from maximum diameter of the product.
3. α is the basic spacing from the centerline of the tab to terminal 1
and βis the basic spacing of each lead or lead position (N -1
places) from α,looking at the bottom of the package.
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
Øb
ØD2
Øek1
k
β
Øb1
BASE AND
SEATING PLANE
F
Q
ØD ØD1
L1
L2
REFERENCE PLANE
L
A
α
Øb2
Øb1
BASE METAL LEAD FINISH
SECTION A-A
A
A
N
e1
C
L
2
1
T8.C MIL-STD-1835 MACY1-X8 (A1)
8 LEAD METAL CAN PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.165 0.185 4.19 4.70 -
Øb 0.016 0.019 0.41 0.48 1
Øb1 0.016 0.021 0.41 0.53 1
Øb2 0.016 0.024 0.41 0.61 -
ØD 0.335 0.375 8.51 9.40 -
ØD1 0.305 0.335 7.75 8.51 -
ØD2 0.110 0.160 2.79 4.06 -
e 0.200 BSC 5.08 BSC -
e1 0.100 BSC 2.54 BSC -
F - 0.040 - 1.02 -
k 0.027 0.034 0.69 0.86 -
k1 0.027 0.045 0.69 1.14 2
L 0.500 0.750 12.70 19.05 1
L1 - 0.050 - 1.27 1
L2 0.250 - 6.35 - 1
Q 0.010 0.045 0.25 1.14 -
α45o BSC 45o BSC 3
β45o BSC 45o BSC 3
N8 84
Rev. 0 5/18/94
