0 Virtex-5 Data Sheet: DC and Switching Characteristics R DS202 (v3.6) November 5, 2007 0 0 Advance Product Specification Virtex-5 Electrical Characteristics VirtexTM-5 FPGAs are available in -3, -2, -1 speed grades, with -3 having the highest performance. Virtex-5 DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Virtex-5 data sheet, part of an overall set of documentation on the Virtex-5 family of FPGAs, is available on the Xilinx website: * * * * * * * * * * Virtex-5 Family Overview Virtex-5 User Guide Virtex-5 Configuration Guide Virtex-5 XtremeDSPTM Design Considerations Virtex-5 Packaging and Pinout Specification Virtex-5 RocketIOTM GTP Transceiver User Guide Virtex-5 Tri-mode Ethernet MAC User Guide Virtex-5 Integrated Endpoint Block User Guide for PCI Express(R) Designs Virtex-5 System Monitor User Guide Virtex-5 PCB Designer's Guide All specifications are subject to change without notice. Virtex-5 DC Characteristics Table 1: Absolute Maximum Ratings Symbol Description Units VCCINT Internal supply voltage relative to GND -0.5 to 1.1 V VCCAUX Auxiliary supply voltage relative to GND -0.5 to 3.0 V VCCO Output drivers supply voltage relative to GND -0.5 to 3.75 V VBATT Key memory battery backup supply -0.5 to 4.05 V VREF Input reference voltage -0.5 to 3.75 V VIN(3) 3.3V I/O input voltage relative to GND(4) (user and dedicated I/Os) -0.75 to 4.05 V -0.75 to VCCO + 0.5 V -0.75 to 4.05 V -0.75 to VCCO + 0.5 V -65 to 150 C +220 C +125 C 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os) VTS Voltage applied to 3-state 3.3V output(4) (user and dedicated I/Os) Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os) TSTG TSOL TJ Storage temperature (ambient) Maximum soldering temperature(2) Maximum junction temperature(2) Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. For soldering guidelines and thermal considerations, see UG195: Virtex-5 Packaging and Pinout Specification on the Xilinx website. 3. 3.3V I/O absolute maximum limit applied to DC and AC signals. 4. For 3.3V I/O operation, refer to UG190: Virtex-5 User Guide, Chapter 6, 3.3V I/O Design Guidelines. (c) 2006-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. PowerPC is a trademark of IBM, Inc. All specifications are subject to change without notice. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 1 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 2: Recommended Operating Conditions Symbol VCCINT VCCAUX(1) VCCO(2,4,5) Description Temperature Range Min Max Units Commercial 0.95 1.05 V Industrial 0.95 1.05 V Commercial 2.375 2.625 V Industrial 2.375 2.625 V Commercial 1.14 3.45 V Supply voltage relative to GND, TJ = -40C to +100C Industrial 1.14 3.45 V 3.3V supply voltage relative to GND, TJ = 0C to +85C Commercial GND - 0.20 3.45 V Industrial GND - 0.20 3.45 V 2.5V and below supply voltage relative to GND, TJ = 0C to +85C Commercial GND - 0.20 VCCO + 0.2 V 2.5V and below supply voltage relative to GND, TJ = -40C to +100C Industrial GND - 0.20 VCCO + 0.2 V Internal supply voltage relative to GND, TJ = 0C to +85C Internal supply voltage relative to GND, TJ = -40C to +100C Auxiliary supply voltage relative to GND, TJ = 0C to +85C Auxiliary supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TJ = 0C to +85C 3.3V supply voltage relative to GND, TJ = -40C to +100C VIN IIN VBATT(3) Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. Commercial 10 mA Industrial 10 mA Battery voltage relative to GND, TJ = 0C to +85C Commercial 1.0 3.6 V Industrial 1.0 3.6 V Battery voltage relative to GND, TJ = -40C to +100C Notes: 1. Recommended maximum voltage drop for VCCAUX is 10 mV/ms. 2. Configuration data is retained even if VCCO drops to 0V. 3. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX. 4. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. 5. The configuration supply voltage VCC_CONFIG is also known as VCCO_0 Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 V VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 2.0 V IREF VREF leakage current per pin 10 A Input or output leakage current per pin (sample-tested) 10 A Input capacitance (sample-tested) 8 pF IL CIN IRPU(1) Data Rate Min Typ Max Units Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V 20 150 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V 10 90 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V 5 45 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V 3 30 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V 2 15 A IRPD(1) Pad pull-down (when selected) @ VIN = 2.5V 5 110 A IBATT(2) Battery supply current 150 nA n Temperature diode ideality factor r Series resistance 1.0002 n 5.0 Notes: 1. Typical values are specified at nominal voltage, 25C. 2. Maximum value specified for worst case process at 25C. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 2 R Virtex-5 Data Sheet: DC and Switching Characteristics Important Note Typical values for queiscent supply current are now specified at nominal voltage, 85C junction temperatures (Tj). Xilinx recommends analyzing static power consumption at Tj = 85C because the majority of designs operate near the high end of the commercial temperature range. Data sheets for older products (e.g., Virtex-4 devices) still specify typical quiescent supply current at Tj = 25C. Queiscent supply current is specified by speed grade for Virtex-5 devices. Use the XPOWERTM Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for conditions other than those specified in Table 4. Table 4: Typical Quiescent Supply Current Speed and Temperature Grade Symbol Description ICCINTQ Quiescent VCCINT supply current ICCOQ Quiescent VCCO supply current DS202 (v3.6) November 5, 2007 Advance Product Specification Device Units -3 (C) -2 (C & I) -1 (C & I) XC5VLX30 480 480 300 mA XC5VLX30T 507 507 317 mA XC5VLX50 651 651 449 mA XC5VLX50T 689 689 475 mA XC5VLX85 1072 1072 883 mA XC5VLX85T 1115 1115 866 mA XC5VLX110 1391 1391 1109 mA XC5VLX110T 1448 1448 1154 mA XC5VLX220 N/A 2783 2278 mA XC5VLX220T N/A 2844 2328 mA XC5VLX330 N/A 4193 3432 mA XC5VLX330T N/A 4267 3492 mA XC5VSX35T 720 720 554 mA XC5VSX50T 1092 1092 840 mA XC5VSX95T N/A 1924 1475 mA XC5VLX30 1.5 1.5 1.5 mA XC5VLX30T 1.5 1.5 1.5 mA XC5VLX50 2 2 2 mA XC5VLX50T 2 2 2 mA XC5VLX85 3 3 3 mA XC5VLX85T 3 3 3 mA XC5VLX110 4 4 4 mA XC5VLX110T 4 4 4 mA XC5VLX220 N/A 8 8 mA XC5VLX220T N/A 8 8 mA XC5VLX330 N/A 12 12 mA XC5VLX330T N/A 12 12 mA XC5VSX35T 1.5 1.5 1.5 mA XC5VSX50T 2 2 2 mA XC5VSX95T N/A 4 4 mA www.xilinx.com 3 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 4: Typical Quiescent Supply Current (Continued) Speed and Temperature Grade Symbol Description Device ICCAUXQ Quiescent VCCAUX supply current Units -3 (C) -2 (C & I) -1 (C & I) XC5VLX30 38 38 38 mA XC5VLX30T 43 43 43 mA XC5VLX50 57 57 57 mA XC5VLX50T 62 62 62 mA XC5VLX85 93 93 93 mA XC5VLX85T 98 98 98 mA XC5VLX110 125 125 125 mA XC5VLX110T 130 130 130 mA XC5VLX220 N/A 229 229 mA XC5VLX220T N/A 236 236 mA XC5VLX330 N/A 345 345 mA XC5VLX330T N/A 353 353 mA XC5VSX35T 49 49 49 mA XC5VSX50T 74 74 74 mA XC5VSX95T N/A 131 131 mA Notes: 1. Typical values are specified at nominal voltage, 85C junction temperatures (Tj). Industrial(I) grade devices have the same typical values as commercial (C) grade devices at 85C, but higher values at 100C. Use the XPE tool to calculate 100C values. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. Power-On Power Supply Requirements Table 5 shows the minimum current required by Virtex-5 devices for proper power-on and configuration. Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply. If the current minimums shown in Table 5 are met, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages. The power supplies can be can be turned on in any sequence, though the specifications shown in Table 5 are for the recommended power-on sequence of VCCINT, VCCAUX, and VCCO. Xilinx does not specify the current for other power-on sequences. The FPGA must be configured after VCCINT is applied. Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies. Table 5: Power-On Current for Virtex-5 Devices ICCAUXMIN ICCINTMIN Device Typ(1) Max Typ(1) ICCOMIN Max Typ(1) Max Units XC5VLX30 235 76 50 mA XC5VLX30T 246 86 50 mA XC5VLX50 320 114 50 mA XC5VLX50T 336 124 50 mA XC5VLX85 492 186 100 mA XC5VLX85T 515 196 100 mA DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 4 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 5: Power-On Current for Virtex-5 Devices (Continued) ICCAUXMIN ICCINTMIN Typ(1) Device Typ(1) Max ICCOMIN Typ(1) Max Max Units XC5VLX110 623 250 100 mA XC5VLX110T 651 260 100 mA XC5VLX220 1023 458 150 mA XC5VLX220T 1056 472 150 mA XC5VLX330 1470 690 150 mA XC5VLX330T 1509 706 150 mA XC5VSX35T 307 98 50 mA XC5VSX50T 472 148 50 mA XC5VSX95T 804 262 100 mA Notes: 1. Typical values are specified at nominal voltage, 25C. Table 6: Power Supply Ramp Time Symbol Description Ramp Time Units VCCINT Internal supply voltage relative to GND 0.20 to 50.0 ms VCCO Output drivers supply voltage relative to GND 0.20 to 50.0 ms VCCAUX Auxiliary supply voltage relative to GND 0.20 to 50.0 ms SelectIOTM DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are cho- sen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 7: SelectIO DC Input and Output Levels I/O Standard VIH VIL VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA LVTTL -0.3 0.8 2.0 3.45 0.4 2.4 Note(3) Note(3) LVCMOS33, LVDCI33 -0.3 0.8 2.0 3.45 0.4 VCCO - 0.4 Note(3) Note(3) LVCMOS25, LVDCI25 -0.3 0.7 1.7 VCCO + 0.3 0.4 VCCO - 0.4 Note(3) Note(3) LVCMOS18, LVDCI18 -0.3 35% VCCO 65% VCCO VCCO + 0.3 0.45 VCCO - 0.45 Note(4) Note(4) LVCMOS15, LVDCI15 -0.3 35% VCCO 65% VCCO VCCO + 0.3 25% VCCO 75% VCCO Note(4) Note(4) LVCMOS12 -0.3 35% VCCO 65% VCCO VCCO + 0.3 25% VCCO 75% VCCO Note(6) Note(6) PCI33_3(5) -0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO Note(5) Note(5) PCI66_3(5) -0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO Note(5) Note(5) PCI-X(5) -0.2 35% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO Note(5) Note(5) DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 5 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 7: SelectIO DC Input and Output Levels (Continued) I/O Standard VIH VIL VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA GTLP -0.3 VREF - 0.1 VREF + 0.1 - 0.6 N/A 36 N/A GTL -0.3 VREF - 0.05 VREF + 0.05 - 0.4 N/A 32 N/A -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 25% VCCO 75% VCCO 6.3 6.3 I(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 8 -8 HSTL II(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 16 -16 HSTL III(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 24 -8 HSTL I_12 HSTL HSTL IV(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 48 -8 I(2) -0.3 50% VCCO - 0.1 50% VCCO + 0.1 VCCO + 0.3 - - - - DIFF HSTL II(2) -0.3 50% VCCO - 0.1 50% VCCO + 0.1 VCCO + 0.3 - - - - SSTL2 I -0.3 VREF - 0.15 VREF + 0.15 VCCO + 0.3 VTT - 0.61 VTT + 0.61 8.1 -8.1 SSTL2 II -0.3 VREF - 0.15 VREF + 0.15 VCCO + 0.3 VTT - 0.81 VTT + 0.81 16.2 -16.2 DIFF SSTL2 I -0.3 50% VCCO - 0.15 50% VCCO + 0.15 VCCO + 0.3 - - - - DIFF SSTL2 II -0.3 50% VCCO - 0.15 50% VCCO + 0.15 VCCO + 0.3 - - - - SSTL18 I -0.3 VREF - 0.125 VREF + 0.125 VCCO + 0.3 VTT - 0.47 VTT + 0.47 6.7 -6.7 SSTL18 II -0.3 VREF - 0.125 VREF + 0.125 VCCO + 0.3 VTT - 0.60 VTT + 0.60 13.4 -13.4 DIFF SSTL18 I -0.3 50% VCCO - 0.125 50% VCCO + 0.125 VCCO + 0.3 - - - - DIFF SSTL18 II -0.3 50% VCCO - 0.125 50% VCCO + 0.125 VCCO + 0.3 - - - - DIFF HSTL Notes: 1. Tested according to relevant specifications. 2. Applies to both 1.5V and 1.8V HSTL. 3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA. 4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA. 5. For more information on PCI33_3, PCI66_3, and PCI-X, refer to refer to UG190: Virtex-5 User Guide, Chapter 6, 3.3V I/O Design Guidelines. 6. Supported drive strengths of 2, 4, 6, or 8 mA. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 6 R Virtex-5 Data Sheet: DC and Switching Characteristics HT DC Specifications (HT_25) Table 8: HT DC Specifications Symbol VCCO DC Parameter Supply Voltage VOD Differential Output Voltage VOD Change in VOD Magnitude VOCM Output Common Mode Voltage VOCM Conditions RT = 100 across Q and Q signals Min Typ Max Units 2.38 2.5 2.63 V 495 600 715 mV 15 mV 715 mV 15 mV 1000 mV 15 mV 780 mV 15 mV -15 RT = 100 across Q and Q signals 495 Change in VOCM Magnitude -15 VID Input Differential Voltage 200 VID Change in VID Magnitude -15 VICM Input Common Mode Voltage 440 Change in VICM Magnitude -15 VICM 600 600 600 LVDS DC Specifications (LVDS_25) Table 9: LVDS DC Specifications Symbol VCCO DC Parameter Conditions Supply Voltage Min Typ Max Units 2.38 2.5 2.63 V 1.675 V VOH Output High Voltage for Q and Q RT = 100 across Q and Q signals VOL Output Low Voltage for Q and Q RT = 100 across Q and Q signals 0.825 VODIFF Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High RT = 100 across Q and Q signals 247 350 600 mV VOCM Output Common-Mode Voltage RT = 100 across Q and Q signals 1.125 1.250 1.375 V VIDIFF Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High 100 350 600 mV VICM Input Common-Mode Voltage 0.3 1.2 2.2 V Min Typ Max Units 2.38 2.5 2.63 V - 1.785 V V Extended LVDS DC Specifications (LVDSEXT_25) Table 10: Extended LVDS DC Specifications Symbol VCCO DC Parameter Conditions Supply Voltage VOH Output High Voltage for Q and Q RT = 100 across Q and Q signals VOL Output Low Voltage for Q and Q RT = 100 across Q and Q signals 0.715 - - V VODIFF Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High RT = 100 across Q and Q signals 350 - 820 mV VOCM Output Common-Mode Voltage RT = 100 across Q and Q signals 1.125 1.250 1.375 V VIDIFF Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Common-mode input voltage = 1.25V 100 - 1000 mV VICM Input Common-Mode Voltage Differential input voltage = 350 mV 0.3 1.2 2.2 V DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 7 R Virtex-5 Data Sheet: DC and Switching Characteristics LVPECL DC Specifications (LVPECL_25) These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower com- mon-mode ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see UG190: Virtex-5 User Guide, Chapter 6, SelectIO Resources. Table 11: LVPECL DC Specifications Symbol DC Parameter Min Typ Max Units VOH Output High Voltage VCC - 1.025 1.545 VCC - 0.88 V VOL Output Low Voltage VCC - 1.81 0.795 VCC - 1.62 V VICM Input Common-Mode Voltage 0.6 2.2 V 0.100 1.5 V VIDIFF Differential Input Voltage(1,2) Notes: 1. Recommended input maximum voltage not to exceed VCCAUX + 0.2V. 2. Recommended input minimum voltage not to go below -0.5V. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 8 R Virtex-5 Data Sheet: DC and Switching Characteristics RocketIO GTP Transceiver Specifications RocketIO GTP Transceiver DC Characteristics Table 12: Absolute Maximum Ratings Symbol Description Units MGTAVCCPLL Analog supply voltage for the GTP_DUAL shared PLL relative to GND -0.5 to 1.32 V MGTAVTTTX Analog supply voltage for the GTP_DUAL transmitters relative to GND -0.5 to 1.32 V MGTAVTTRX Analog supply voltage for the GTP_DUAL receivers relative to GND -0.5 to 1.32 V MGTAVCC Analog supply voltage for the GTP_DUAL common circuits relative to GND -0.5 to 1.32 V MGTAVTTRXC Analog supply voltage for the resistor calibration circuit of the GTP_DUAL column -0.5 to 1.32 V Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. Table 13: Recommended Operating Conditions(1)(2) Symbol Description MGTAVCCPLL(1) Analog supply voltage for the GTP_DUAL shared PLL relative to GND Min Max Units 1.14 1.26 V MGTAVTTTX(1) Analog supply voltage for the GTP_DUAL transmitters relative to GND 1.14 1.26 V MGTAVTTRX(1) Analog supply voltage for the GTP_DUAL receivers relative to GND 1.14 1.26 V Analog supply voltage for the GTP_DUAL common circuits relative to GND 0.95 1.05 V 1.14 1.26 V MGTAVCC(1) MGTAVTTRXC(1) Analog supply voltage for the resistor calibration circuit of the GTP_DUAL column Notes: 1. Each voltage listed requires the filter circuit described in UG196: Virtex-5 RocketIO GTP Transceiver User Guide. 2. Voltages are specified for the temperature range of TJ = -40C to +100C. Table 14: DC Characteristics Over Recommended Operating Conditions(2) Symbol Description Min Typ Max Units IMGTAVTTTX GTP_DUAL tile transmitter termination supply current(3) 71 90 mA IMGTAVCCPLL GTP_DUAL tile shared PLL supply current 36 60 mA IMGTAVTTRXC GTP_DUAL tile resistor termination calibration supply current 0.1 0.5 mA IMGTAVTTRX GTP_DUAL tile receiver termination supply current(3) 0.1 0.5 mA GTP_DUAL tile internal analog supply current 56 110 mA 50 50.5 IMGTAVCC RREF Precision reference resistor for internal calibration termination 49.5 Notes: 1. Typical values are specified at nominal voltage, 25C, with a 3.2 Gb/s line rate. 2. ICC numbers are given per GTP_DUAL tile with both GTP devices operating with default settings. 3. AC coupled TX/RX link. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 9 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 15: Quiescent Supply Current Symbol ICCINTQ IVTTTXQ IAVCCPLLQ IVTTRXCQ Description Device Quiescent internal supply current Quiescent transmitter supply current Quiescent GTP_DUAL PLL supply current Quiescent receiver termination switching supply current DS202 (v3.6) November 5, 2007 Advance Product Specification Typ(1) Max Units XC5VLX30T mA XC5VLX50T mA XC5VLX85T mA XC5VLX110T mA XC5VLX220T mA XC5VLX330T mA XC5VSX35T mA XC5VSX50T mA XC5VSX95T mA XC5VLX30T mA XC5VLX50T mA XC5VLX85T mA XC5VLX110T mA XC5VLX220T mA XC5VLX330T mA XC5VSX35T mA XC5VSX50T mA XC5VSX95T mA XC5VLX30T mA XC5VLX50T mA XC5VLX85T mA XC5VLX110T mA XC5VLX220T mA XC5VLX330T mA XC5VSX35T mA XC5VSX50T mA XC5VSX95T mA XC5VLX30T mA XC5VLX50T mA XC5VLX85T mA XC5VLX110T mA XC5VLX220T mA XC5VLX330T mA XC5VSX35T mA XC5VSX50T mA XC5VSX95T mA www.xilinx.com 10 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 15: Quiescent Supply Current (Continued) Symbol ITTRXQ IVCCQ Description Device Quiescent receiver termination supply current Quiescent internal analog supply current Typ(1) Max Units XC5VLX30T mA XC5VLX50T mA XC5VLX85T mA XC5VLX110T mA XC5VLX220T mA XC5VLX330T mA XC5VSX35T mA XC5VSX50T mA XC5VSX95T mA XC5VLX30T mA XC5VLX50T mA XC5VLX85T mA XC5VLX110T mA XC5VLX220T mA XC5VLX330T mA XC5VSX35T mA XC5VSX50T mA XC5VSX95T mA Notes: 1. Typical values are specified at nominal voltage, 25C. 2. Given for entire die. Powered and unconfigured. 3. Unconnected (if channel is driven to voltage). 4. More accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 11 R Virtex-5 Data Sheet: DC and Switching Characteristics RocketIO GTP Transceiver DC Input and Output Levels Table 16 summarizes the DC output specifications of the Virtex-5 RocketIO GTP Transceivers. Figure 1 shows the single-ended output voltage swing. Figure 2 shows the peak-to-peak differential output voltage. Consult UG196: Virtex-5 RocketIO GTP Transceiver User Guide for further details. Table 16: GTP Transceiver DC Specifications Symbol DC Parameter DVPPIN Differential peak-to-peak input voltage VIN VCMIN DVPPOUT VSEOUT VCMOUT RIN ROUT TOSKEW Conditions Min Typ Units External AC coupled 3.2 Gb/s 150 2000 mV External AC coupled > 3.2 Gb/s 180 2000 mV Absolute input voltage DC coupled MGTAVTTRX = 1.2V -400 1200 mV Common mode input voltage DC coupled MGTAVTTRX = 1.2V Differential peak-to-peak output voltage (1) TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON 1400 mV Single-ended output voltage swing (1) TXBUFDIFFCTRL = 000, TX_DIFF_BOOST = ON 700 mV Common mode output voltage Equation based MGTAVTTTX = 1.2V 800 mV 1200 - Amplitude/2 mV Differential input resistance 90 100 120 Differential output resistance 90 100 120 15 ps 200 nF Transmitter output skew CEXT Max Recommended external AC coupling capacitor(2) 75 100 Notes: 1. The output swing and preemphasis levels are programmable using the attributes discussed in UG196:Virtex-5 RocketIO GTP Transceiver User Guide and can result in values lower than reported in this table. 2. Values outside of this range can be used as appropriate to conform to specific protocols and standards. +V P VSEOUT N 0 ds202_01_051607 Figure 1: Single-Ended Output Voltage Swing +V DVPPOUT DVPPIN 0 -V P-N ds202_02_051607 Figure 2: Peak-to-Peak Differential Output Voltage DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 12 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 17 summarizes the DC input specifications of the Virtex-5 RocketIO GTP Transceivers. Figure 3 shows the single-ended input voltage swing. Figure 4 shows the peak-to-peak differential clock input voltage swing. Consult UG196: Virtex-5 RocketIO GTP Transceiver User Guide for further details. Table 17: RocketIO GTP Clock DC Input Level Specification(1) Symbol DC Parameter Min Typ Max Units Differential peak-to-peak input voltage 200 800 2000 mV VSEIN Single-ended input voltage 100 400 1000 mV RIN Differential input resistance 80 105 130 Required external AC coupling capacitor 75 100 200 nF DVPPIN CEXT Conditions Notes: 1. VMIN = 0V and VMAX = 1200mV +V P VSEIN N 0 ds202_03_051607 Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak +V P-N DVPPIN 0 -V ds202_04_051607 Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 13 R Virtex-5 Data Sheet: DC and Switching Characteristics RocketIO GTP Switching Characteristics Consult UG196:Virtex-5 RocketIO GTP Transceiver User Guide for further information. Table 18: GTP Transceiver Performance Speed Grade Symbol Description -3 -2 -1 Units FGTPMAX Maximum GTP transceiver data rate 3.75 3.75 3.2 Gb/s FGPLLMAX Maximum PLL frequency 2.0 2.0 2.0 GHz FGPLLMIN Minimum PLL frequency 1.0 1.0 1.0 GHz Table 19: CRC Block Switching Characteristics Speed Grade Symbol FCRC -3 -2 -1 Units 320 320 250 MHz Description CRCCLK maximum frequency Table 20: GTP Transceiver Reference Clock Switching Characteristics All Speed Grades Symbol Description Conditions range(1) Typ Units 350 MHz Reference clock frequency TRCLK Reference clock rise time 20% - 80% 200 400 ps TFCLK Reference clock fall time 80% - 20% 200 400 ps 50 55 % CLK 40 ps 1 ms 200 s Reference clock duty cycle CLK peak-peak (2) TGJTT Reference clock total jitter, TLOCK Clock recovery frequency acquisition time Initial PLL lock TPHASE Clock recovery phase acquisition time Lock to data after PLL has relocked to the reference clock. Includes lock to reference time. 60 Max FGCLK TDCREF CLK Min 45 Notes: 1. The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s. 2. Measured at the package pin. TRCLK 80% 20% TFCLK ds202_05_100506 Figure 5: Reference Clock Timing Parameters DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 14 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 21: GTP User Clock Switching Characteristics(1) Speed Grade Symbol Description Conditions -3 -2 -1 Units FTXOUT TXOUTCLK maximum frequency 375 375 320 MHz FRXREC RXRECCLK maximum frequency 375 375 320 MHz TRX RXUSRCLK maximum frequency 375 375 320 MHz TRX2 RXUSRCLK2 maximum frequency TTX TXUSRCLK maximum frequency TTX2 TXUSRCLK2 maximum frequency RXDATAWIDTH = 0 350 350 320 MHz RXDATAWIDTH = 1 187.5 187.5 160 MHz 375 375 320 MHz TXDATAWIDTH = 0 350 350 320 MHz TXDATAWIDTH = 1 187.5 187.5 160 MHz Notes: 1. Clocking must be implemented as described in UG196: Virtex-5 RocketIO GTP Transceiver User Guide Table 22: GTP Transmitter Switching Characteristics Symbol Description Min Typ FGTX Serial data rate range 0.1 TRTX TX Rise time 140 TFTX TX Fall time 120 Max Units FGTPMAX Gb/s ps ps TLLSKEW TX lane-to-lane skew(1) 2 + 500 ps UI VTXOOBVDPP Electrical idle amplitude 20 mV TTXOOBTRANS Electrical idle transition time 40 ns 0.35 UI 0.19 UI 0.35 UI 0.19 UI 0.30 UI 0.14 UI 0.30 UI 0.14 UI 0.20 UI 0.10 UI 0.20 UI 0.10 UI Jitter(2) TJ3.75 Total DJ3.75 Deterministic Jitter(2) TJ3.2 Total Jitter(2) DJ3.2 Deterministic Jitter(2) 3.75 Gb/s 3.20 Gb/s Jitter(2) TJ2.5 Total DJ2.5 Deterministic Jitter(2) TJ2.0 Total Jitter(2) DJ2.0 Deterministic Jitter(2) 2.50 Gb/s 2.00 Gb/s Jitter(2) TJ1.25 Total DJ1.25 Deterministic Jitter(2) TJ1.00 Total Jitter(2) DJ1.00 Deterministic Jitter(2) 1.25 Gb/s 1.00 Gb/s Jitter(2) TJ500 Total DJ500 Deterministic Jitter(2) TJ100 Total Jitter(2) DJ100 Deterministic 500 Mb/s 100 Mb/s Jitter(2) 0.10 UI 0.04 UI 0.02 UI 0.01 UI Notes: 1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites. 2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. 3. All jitter values are based on a Bit-Error Ratio of 1e-12. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 15 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 23: GTP Receiver Switching Characteristics Symbol Description Min Typ Max Units RX oversampler not enabled 0.5 FGTPMAX Gb/s RX oversampler enabled 0.1 0.5 Gb/s OOB detect threshold peak-to-peak OOBDETECT_THRESHOLD = 100 60 165 mV RXSST Receiver spread-spectrum tracking(1) Modulated @ 33 KHz 0 ppm RXRL Run length (CID) Internal AC capacitor bypassed 150 UI 1000 ppm FGRX RXOOBVDPP Serial data rate 2nd-order 105 -5000 Data/REFCLK PPM offset tolerance ACDR JT_SJ3.75 Sinusoidal Jitter(2) 3.75 Gb/s 0.30 UI JT_SJ3.2 Sinusoidal Jitter(2) 3.20 Gb/s 0.40 UI JT_SJ2.50 Sinusoidal Jitter(2) 2.50 Gb/s 0.40 UI JT_SJ2.00 Sinusoidal Jitter(2) 2.00 Gb/s 0.40 UI JT_SJ1.00 Sinusoidal Jitter(2) 1.00 Gb/s 0.30 UI JT_SJ500 Sinusoidal Jitter(2) 500 Mb/s 0.30 UI JT_SJ500 Sinusoidal Jitter(2) 500 Mb/s OS 0.30 UI Sinusoidal Jitter(2) 100 Mb/s OS 0.30 UI 0.87 UI 0.30 UI RXPPMTOL loop enabled -1000 SJ Jitter Tolerance JT_SJ100 SJ Jitter Tolerance with Stressed Eye JT_TJSE3.2 Total Jitter with Stressed Eye(3) 3.20 Gb/s JT_SJSE3.2 Sinusoidal Jitter with Stressed Eye(3) 3.20 Gb/s Notes: 1. 2. 3. 4. Using PLL_RX_DIVSEL_OUT = 1. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter. Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled. All jitter values are based on a Bit Error Ratio of 1e-12. Ethernet MAC Switching Characteristics Consult UG194:Virtex-5 Tri-mode Ethernet Media Access Controller User Guide for further information. Table 24: Maximum Ethernet MAC Performance Speed Grade Description -3 Ethernet MAC Maximum Performance DS202 (v3.6) November 5, 2007 Advance Product Specification -2 10/100/1000 -1 Units Mb/s www.xilinx.com 16 R Virtex-5 Data Sheet: DC and Switching Characteristics System Monitor Analog-to-Digital Converter Specification Table 25: Analog-to-Digital Specifications Parameter Symbol Comments/Conditions Min Typ Max Units AVDD = 2.5V 2%, VREFP = 2.5V, VREFN = 0V, ADCCLK = 5.2 MHz, TA = TMIN to TMAX, Typical values at TA=+25C DC Accuracy: All external input channels such as VP/VN and VAUXP[15:0]/VAUXN[15:0], Unipolar Mode, and Common Mode = 0V Resolution 10 Integral Nonlinearity INL Differential Nonlinearity DNL Bits No missing codes (TMIN to TMAX) 2 LSBs 0.9 LSBs Guaranteed Monotonic Unipolar Offset Error(1) Bipolar Offset Error(1) Uncalibrated 2 30 LSBs Uncalibrated measured in bipolar mode 2 30 LSBs Gain Error(1) Uncalibrated 0.2 2 % Bipolar Gain Error(1) Uncalibrated measured in bipolar mode 0.2 2 % Total Unadjusted Error (Uncalibrated) TUE Deviation from ideal transfer function. VREFP - VREFN = 2.5V 10 Total Unadjusted Error (Calibrated) TUE Deviation from ideal transfer function. VREFP - VREFN = 2.5V 1 Variation of FS code with temperature 0.01 LSB/C 70 dB Calibrated Gain Temperature Coefficient LSBs 2 LSBs CMRRDC VN = VCM = 0.5V 0.5V, VP - VN = 100mV Conversion Time - Continuous tCONV Number of CLK cycles Conversion Time - Event tCONV Number of CLK cycles T/H Acquisition Time tACQ Number of CLK cycles 4 DRP Clock Frequency DCLK DRP clock frequency 8 250 MHz ADC Clock Frequency ADCCLK Derived from DCLK 1 5.2 MHz 40 60 % 0 1 Volts -0.25 +0.25 0 +0.5 +0.3 +0.7 DC Common-Mode Reject Conversion Rate(2) CLK Duty cycle 26 32 21 Analog Inputs(3) Dedicated Analog Inputs Input Voltage Range VP - VN Unipolar Operation Differential Inputs Unipolar Common Mode Range (FS input) Differential Common Mode Range (FS input) Bandwidth Auxiliary Analog Inputs Input Voltage Range VAUXP[0] /VAUXN[0] to VAUXP[15] /VAUXN[15] 20 Unipolar Operation Differential Operation Unipolar Common Mode Range (FS input) Differential Common Mode Range (FS input) Bandwidth Input Leakage Current DS202 (v3.6) November 5, 2007 Advance Product Specification A/D not converting, ADCCLK stopped MHz 0 1 -0.25 +0.25 0 +0.5 +0.3 +0.7 Volts 10 kHz 1.0 A www.xilinx.com 17 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 25: Analog-to-Digital Specifications (Continued) Parameter Symbol Comments/Conditions Min Input Capacitance Typ Max 10 On-chip Supply Monitor Error VCCINT and VCCAUX with calibration enabled On-chip Temperature Monitor Error -40C to +125C with calibration enabled Units pF 1.0 % Reading 4 C External Reference Inputs(4) Positive Reference Input Voltage Range VREFP Measured Relative to VREFN 2.45 2.5 2.55 Volts Negative Reference Input Voltage Range VREFN Measured Relative to AGND -50 0 100 mV Input current IREF ADCCLK = 5.2 MHz 100 A Analog Power Supply AVDD Measured Relative to AVSS 2.55 Volts Analog Supply Current AIDD ADCCLK = 5.2 MHz 8 mA Power Requirements 2.45 5 2.5 Notes: 1. Offset and gain errors are removed by enabling the System Monitor automatic gain calibration feature. See UG192: Virtex-5 System Monitor User Guide. 2. See "System Monitor Timing" in UG192: Virtex-5 System Monitor User Guide. 3. See "Analog Inputs" in UG192: Virtex-5 System Monitor User Guide for a detailed description. 4. Any variation in the reference voltage from the nominal VREFP = 2.5V and VREFN = 0V will result is a deviation from the ideal transfer function.This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing the supply voltage and reference to vary by 2% is permitted. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 18 R Virtex-5 Data Sheet: DC and Switching Characteristics Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Virtex-5 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the Switching Characteristics, page 21. Table 26 shows internal (register-to-register) performance. Table 26: Register-to-Register Performance Register-to-Register (with I/O Delays) Speed Grade Description -3 -2 -1 Units 16:1 Multiplexer 550 500 450 MHz 32:1 Multiplexer 550 500 450 MHz 64:1 Multiplexer 511 467 407 MHz 9 x 9 Logic Multiplier with 4 pipe stages 468 438 428 MHz 9 x 9 Logic Multiplier with 5 pipe stages 550 500 428 MHz 16-bit Adder 550 500 450 MHz 32-bit Adder 550 500 447 MHz 64-bit Adder 423 377 323 MHz Register to LUT to Register 550 500 450 MHz 16-bit Counter 550 500 450 MHz 32-bit Counter 550 500 450 MHz 64-bit Counter 428 381 333 MHz 500 450 400 MHz Single-Port 512 x 36 bits 550 500 450 MHz Single-Port 4096 x 4 bits 550 500 450 MHz Dual-Port A: 4096 x 4 bits and B: 1024 x 18 bits 550 500 450 MHz Single-Port 16 x 8 550 500 450 MHz Single-Port 32 x 8 550 500 450 MHz Single-Port 64 x 8 550 500 450 MHz Basic Functions Memory Cascaded block RAM (64K) Block RAM Pipelined Distributed RAM Dual-Port 16 x 8 MHz Shift Register Chain 16-bit 550 500 450 MHz 32-bit 550 500 450 MHz 64-bit 550 500 438 MHz DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 19 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 26: Register-to-Register Performance (Continued) Register-to-Register (with I/O Delays) Speed Grade Description -3 -2 -1 Units DSP48E Quad 12-bit Adder/Subtracter 550 500 450 MHz DSP48E Dual 24-bit Adder/Subtracter 550 500 450 MHz DSP48E 48-bit Adder/Subtracter 550 500 450 MHz DSP48E 48-bit Counter 550 500 450 MHz DSP48E 48-bit Comparator 550 500 450 MHz DSP48E 25 x 18 bit Pipelined Multiplier 550 500 450 MHz DSP48E Direct 4-tap FIR Filter Pipelined 510 458 397 MHz DSP48E Systolic n-tap FIR Filter Pipelined 550 500 450 MHz Dedicated Arithmetic Logic Notes: 1. Deviced used is the XC5VLX50T- FF1136 Table 27: Interface Performances Speed Grade Description -3 -2 -1 SFI-4.1 (SDR LVDS Interface) 710 MHz 710 MHz 645 MHz SPI-4.2 (DDR LVDS Interface) 1.25 Gb/s 1.0 Gb/s 1.0 Gb/s DDR 200 MHz 200 MHz 200 MHz DDR2 333 MHz 300 MHz 267 MHz QDR II SRAM 300 MHz 300 MHz 250 MHz RLDRAM II 333 MHz 300 MHz 250 MHz Networking Applications Memory Interfaces DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 20 R Virtex-5 Data Sheet: DC and Switching Characteristics Switching Characteristics All values represented in this data sheet are based on speed specification version 1.57. Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. All specifications are always representative of worst-case supply voltage and junction temperature conditions. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 28 correlates the current status of each Virtex-5 device on a per speed grade basis. Table 28: Virtex-5 Device Speed Grade Designations Speed Grade Designations Device XC5VLX30 Advance Preliminary Production -3, -2, -1 XC5VLX30T -3, -2, -1 XC5VLX50 -3, -2, -1 XC5VLX50T -3, -2, -1 XC5VLX85 -3, -2, -1 XC5VLX85T -3, -2, -1 XC5VLX110 -3, -2, -1 XC5VLX110T -3, -2, -1 XC5VLX220 -2, -1 XC5VLX220T -2, -1 XC5VLX330 -2, -1 XC5VLX330T -2, -1 XC5VSX35T -3, -2, -1 XC5VSX50T -3, -2, -1 XC5VSX95T -2, -1 Testing of Switching Characteristics All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. DS202 (v3.6) November 5, 2007 Advance Product Specification For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-5 devices. www.xilinx.com 21 R Virtex-5 Data Sheet: DC and Switching Characteristics Production Silicon and ISE Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 29 lists the production released Virtex-5 family member, speed grade, and the corresponding supported speed specification version and ISE software revisions. Table 29: Virtex-5 Production Software and Speed Specification Release Speed Grade Designations Device -3 -2 XC5VLX30 ISE 9.2i SP2 v1.56 XC5VLX30T ISE 9.2i SP2 v1.56 XC5VLX50 -1 ISE 9.2i SP2 v1.56 ISE 9.2i SP1 v1.55 XC5VLX50T ISE 9.2i SP2 v1.56 ISE 9.2i SP1 v1.55 XC5VLX85 ISE 9.2i SP2 v1.56 ISE 9.2i SP1 v1.55 XC5VLX85T ISE 9.2i SP2 v1.56 ISE 9.2i SP1 v1.55 XC5VLX110 XC5VLX110T ISE 9.2i SP2 v1.56 ISE 9.2i SP2 v1.56 XC5VLX220 N/A ISE 9.2i SP3 v1.57 XC5VLX220T N/A ISE 9.2i SP3 v1.57 XC5VLX330 N/A ISE 9.2i SP3 v1.57 XC5VLX330T N/A ISE 9.2i SP3 v1.57 XC5VSX35T ISE 9.2i SP3 v1.57 XC5VSX50T ISE 9.2i SP3 v1.57 ISE 9.2i SP2 v1.56 XC5VSX95T N/A ISE 9.2i SP3 v1.57 Notes: 1. Blank entries indicate a device and/or speed grade in advance or preliminary status. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 22 R Virtex-5 Data Sheet: DC and Switching Characteristics IOB Pad Input/Output/3-State Switching Characteristics Table 30 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. Table 31 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). Table 30: IOB Switching Characteristics I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -3 -2 -1 -3 -2 -1 -3 -2 -1 LVDS_25 0.80 0.90 1.06 1.13 1.29 1.44 1.13 1.29 1.44 ns LVDSEXT_25 1.01 1.16 1.30 1.17 1.34 1.49 1.17 1.34 1.49 ns HT_25 0.80 0.90 1.06 1.10 1.26 1.40 1.10 1.26 1.40 ns BLVDS_25 0.80 0.90 1.06 1.24 1.38 1.58 1.24 1.38 1.58 ns RSDS_25 (point to point) 0.80 0.90 1.06 1.13 1.29 1.44 1.13 1.29 1.44 ns ULVDS_25 0.80 0.90 1.06 1.10 1.27 1.41 1.10 1.27 1.41 ns PCI33_3 0.62 0.70 0.82 1.85 2.06 2.38 1.85 2.06 2.38 ns PCI66_3 0.62 0.70 0.82 1.85 2.06 2.38 1.85 2.06 2.38 ns PCI-X 0.62 0.70 0.82 1.40 1.56 1.80 1.40 1.56 1.80 ns GTL 0.76 0.85 1.00 1.47 1.63 1.86 1.47 1.63 1.86 ns GTLP 0.76 0.85 1.00 1.51 1.68 1.93 1.51 1.68 1.93 ns HSTL_I 0.76 0.85 1.00 1.42 1.57 1.79 1.42 1.57 1.79 ns HSTL_II 0.76 0.85 1.00 1.39 1.53 1.74 1.39 1.53 1.74 ns HSTL_III 0.76 0.85 1.00 1.44 1.60 1.85 1.44 1.60 1.85 ns HSTL_IV 0.76 0.85 1.00 1.44 1.60 1.83 1.44 1.60 1.83 ns HSTL_I _18 0.76 0.85 1.00 1.40 1.55 1.77 1.40 1.55 1.77 ns HSTL_II _18 0.76 0.85 1.00 1.36 1.51 1.72 1.36 1.51 1.72 ns HSTL_III _18 0.76 0.85 1.00 1.45 1.61 1.85 1.45 1.61 1.85 ns HSTL_IV_18 0.76 0.85 1.00 1.41 1.57 1.81 1.41 1.57 1.81 ns SSTL2_I 0.76 0.85 1.00 1.48 1.64 1.87 1.48 1.64 1.87 ns SSTL2_II 0.76 0.85 1.00 1.40 1.55 1.76 1.40 1.55 1.76 ns LVTTL, Slow, 2 mA 0.62 0.70 0.82 4.10 4.47 5.01 4.10 4.47 5.01 ns LVTTL, Slow, 4 mA 0.62 0.70 0.82 2.87 3.09 3.41 2.87 3.09 3.41 ns LVTTL, Slow, 6 mA 0.62 0.70 0.82 2.66 2.91 3.29 2.66 2.91 3.29 ns LVTTL, Slow, 8 mA 0.62 0.70 0.82 2.09 2.30 2.61 2.09 2.30 2.61 ns LVTTL, Slow, 12 mA 0.62 0.70 0.82 1.94 2.15 2.46 1.94 2.15 2.46 ns LVTTL, Slow, 16 mA 0.62 0.70 0.82 1.84 2.04 2.34 1.84 2.04 2.34 ns DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 23 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 30: IOB Switching Characteristics (Continued) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -3 -2 -1 -3 -2 -1 -3 -2 -1 LVTTL, Slow, 24 mA 0.62 0.70 0.82 1.87 2.07 2.38 1.87 2.07 2.38 ns LVTTL, Fast, 2 mA 0.62 0.70 0.82 3.32 3.61 4.05 3.32 3.61 4.05 ns LVTTL, Fast, 4 mA 0.62 0.70 0.82 2.32 2.55 2.90 2.32 2.55 2.90 ns LVTTL, Fast, 6 mA 0.62 0.70 0.82 2.10 2.31 2.63 2.10 2.31 2.63 ns LVTTL, Fast, 8 mA 0.62 0.70 0.82 1.65 1.82 2.09 1.65 1.82 2.09 ns LVTTL, Fast, 12 mA 0.62 0.70 0.82 1.47 1.63 1.89 1.47 1.63 1.89 ns LVTTL, Fast, 16 mA 0.62 0.70 0.82 1.41 1.57 1.81 1.41 1.57 1.81 ns LVTTL, Fast, 24 mA 0.62 0.70 0.82 1.36 1.52 1.74 1.36 1.52 1.74 ns LVCMOS33, Slow, 2 mA 0.62 0.70 0.82 3.63 3.96 4.44 3.63 3.96 4.44 ns LVCMOS33, Slow, 4 mA 0.62 0.70 0.82 2.82 3.09 3.49 2.82 3.09 3.49 ns LVCMOS33, Slow, 6 mA 0.62 0.70 0.82 2.61 2.86 3.24 2.61 2.86 3.24 ns LVCMOS33, Slow, 8 mA 0.62 0.70 0.82 2.06 2.26 2.57 2.06 2.26 2.57 ns LVCMOS33, Slow, 12 mA 0.62 0.70 0.82 1.95 2.14 2.42 1.95 2.14 2.42 ns LVCMOS33, Slow, 16 mA 0.62 0.70 0.82 1.86 2.04 2.31 1.86 2.04 2.31 ns LVCMOS33, Slow, 24 mA 0.62 0.70 0.82 1.87 2.07 2.35 1.87 2.07 2.35 ns LVCMOS33, Fast, 2 mA 0.62 0.70 0.82 2.94 3.20 3.59 2.94 3.20 3.59 ns LVCMOS33, Fast, 4 mA 0.62 0.70 0.82 2.27 2.50 2.84 2.27 2.50 2.84 ns LVCMOS33, Fast, 6 mA 0.62 0.70 0.82 2.06 2.27 2.59 2.06 2.27 2.59 ns LVCMOS33, Fast, 8 mA 0.62 0.70 0.82 1.61 1.79 2.05 1.61 1.79 2.05 ns LVCMOS33, Fast, 12 mA 0.62 0.70 0.82 1.45 1.61 1.86 1.45 1.61 1.86 ns LVCMOS33, Fast, 16 mA 0.62 0.70 0.82 1.40 1.56 1.80 1.40 1.56 1.80 ns LVCMOS33, Fast, 24 mA 0.62 0.70 0.82 1.35 1.51 1.74 1.35 1.51 1.74 ns LVCMOS25, Slow, 2 mA 0.61 0.70 0.82 3.67 3.97 4.42 3.67 3.97 4.42 ns LVCMOS25, Slow, 4 mA 0.61 0.70 0.82 2.37 2.60 2.94 2.37 2.60 2.94 ns LVCMOS25, Slow, 6 mA 0.61 0.70 0.82 2.19 2.41 2.74 2.19 2.41 2.74 ns LVCMOS25, Slow, 8 mA 0.61 0.70 0.82 2.05 2.26 2.56 2.05 2.26 2.56 ns LVCMOS25, Slow, 12 mA 0.61 0.70 0.82 2.10 2.31 2.63 2.10 2.31 2.63 ns LVCMOS25, Slow, 16 mA 0.61 0.70 0.82 1.84 2.02 2.30 1.84 2.02 2.30 ns LVCMOS25, Slow, 24 mA 0.61 0.70 0.82 1.83 2.04 2.34 1.83 2.04 2.34 ns LVCMOS25, Fast, 2 mA 0.61 0.70 0.82 3.14 3.41 3.82 3.14 3.41 3.82 ns LVCMOS25, Fast, 4 mA 0.61 0.70 0.82 1.89 2.08 2.37 1.89 2.08 2.37 ns LVCMOS25, Fast, 6 mA 0.61 0.70 0.82 1.74 1.92 2.20 1.74 1.92 2.20 ns LVCMOS25, Fast, 8 mA 0.61 0.70 0.82 1.66 1.83 2.09 1.66 1.83 2.09 ns LVCMOS25, Fast, 12 mA 0.61 0.70 0.82 1.52 1.69 1.94 1.52 1.69 1.94 ns LVCMOS25, Fast, 16 mA 0.61 0.70 0.82 1.43 1.60 1.85 1.43 1.60 1.85 ns LVCMOS25, Fast, 24 mA 0.61 0.70 0.82 1.40 1.54 1.76 1.40 1.54 1.76 ns DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 24 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 30: IOB Switching Characteristics (Continued) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -3 -2 -1 -3 -2 -1 -3 -2 -1 LVCMOS18, Slow, 2 mA 0.67 0.76 0.89 4.20 4.56 5.09 4.20 4.56 5.09 ns LVCMOS18, Slow, 4 mA 0.67 0.76 0.89 3.03 3.32 3.75 3.03 3.32 3.75 ns LVCMOS18, Slow, 6 mA 0.67 0.76 0.89 2.37 2.61 2.97 2.37 2.61 2.97 ns LVCMOS18, Slow, 8 mA 0.67 0.76 0.89 2.15 2.37 2.69 2.15 2.37 2.69 ns LVCMOS18, Slow, 12 mA 0.67 0.76 0.89 1.95 2.16 2.47 1.95 2.16 2.47 ns LVCMOS18, Slow, 16 mA 0.67 0.76 0.89 1.93 2.14 2.45 1.93 2.14 2.45 ns LVCMOS18, Fast, 2 mA 0.67 0.76 0.89 3.41 3.71 4.16 3.41 3.71 4.16 ns LVCMOS18, Fast, 4 mA 0.67 0.76 0.89 2.36 2.61 2.98 2.36 2.61 2.98 ns LVCMOS18, Fast, 6 mA 0.67 0.76 0.89 1.87 2.06 2.35 1.87 2.06 2.35 ns LVCMOS18, Fast, 8 mA 0.67 0.76 0.89 1.69 1.87 2.13 1.69 1.87 2.13 ns LVCMOS18, Fast, 12 mA 0.67 0.76 0.89 1.51 1.68 1.93 1.51 1.68 1.93 ns LVCMOS18, Fast, 16 mA 0.67 0.76 0.89 1.44 1.61 1.86 1.44 1.61 1.86 ns LVCMOS15, Slow, 2 mA 0.73 0.83 0.98 3.50 3.84 4.34 3.50 3.84 4.34 ns LVCMOS15, Slow, 4 mA 0.73 0.83 0.98 2.17 2.40 2.74 2.17 2.40 2.74 ns LVCMOS15, Slow, 6 mA 0.73 0.83 0.98 1.99 2.20 2.52 1.99 2.20 2.52 ns LVCMOS15, Slow, 8 mA 0.73 0.83 0.98 1.91 2.12 2.43 1.91 2.12 2.43 ns LVCMOS15, Slow, 12 mA 0.73 0.83 0.98 1.74 1.95 2.25 1.74 1.95 2.25 ns LVCMOS15, Slow, 16 mA 0.73 0.83 0.98 1.71 1.91 2.20 1.71 1.91 2.20 ns LVCMOS15, Fast, 2 mA 0.73 0.83 0.98 2.80 3.07 3.48 2.80 3.07 3.48 ns LVCMOS15, Fast, 4 mA 0.73 0.83 0.98 1.76 1.95 2.23 1.76 1.95 2.23 ns LVCMOS15, Fast, 6 mA 0.73 0.83 0.98 1.62 1.80 2.06 1.62 1.80 2.06 ns LVCMOS15, Fast, 8 mA 0.73 0.83 0.98 1.57 1.74 2.00 1.57 1.74 2.00 ns LVCMOS15, Fast, 12 mA 0.73 0.83 0.98 1.43 1.60 1.86 1.43 1.60 1.86 ns LVCMOS15, Fast, 16 mA 0.73 0.83 0.98 1.37 1.53 1.77 1.37 1.53 1.77 ns LVCMOS12, Slow, 2 mA 0.84 0.96 1.14 3.58 3.98 4.58 3.58 3.98 4.58 ns LVCMOS12, Slow, 4 mA 0.84 0.96 1.14 2.10 2.33 2.66 2.10 2.33 2.66 ns LVCMOS12, Slow, 6 mA 0.84 0.96 1.14 2.00 2.18 2.45 2.00 2.18 2.45 ns LVCMOS12, Slow, 8 mA 0.84 0.96 1.14 1.91 2.14 2.48 1.91 2.14 2.48 ns LVCMOS12, Fast, 2 mA 0.84 0.96 1.14 3.05 3.38 3.87 3.05 3.38 3.87 ns LVCMOS12, Fast, 4 mA 0.84 0.96 1.14 1.71 1.91 2.20 1.71 1.91 2.20 ns LVCMOS12, Fast, 6 mA 0.84 0.96 1.14 1.58 1.78 2.08 1.58 1.78 2.08 ns LVCMOS12, Fast, 8 mA 0.84 0.96 1.14 1.52 1.70 1.97 1.52 1.70 1.97 ns DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 25 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 30: IOB Switching Characteristics (Continued) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -3 -2 -1 -3 -2 -1 -3 -2 -1 LVDCI_33 0.62 0.70 0.82 1.50 1.66 1.90 1.50 1.66 1.90 ns LVDCI_25 0.61 0.70 0.82 1.55 1.71 1.93 1.55 1.71 1.93 ns LVDCI_18 0.67 0.76 0.89 1.65 1.78 1.99 1.65 1.78 1.99 ns LVDCI_15 0.73 0.83 0.98 1.58 1.75 2.02 1.58 1.75 2.02 ns LVDCI_DV2_25 0.61 0.70 0.82 1.36 1.51 1.74 1.36 1.51 1.74 ns LVDCI_DV2_18 0.67 0.76 0.89 1.43 1.60 1.85 1.43 1.60 1.85 ns LVDCI_DV2_15 0.73 0.83 0.98 1.48 1.65 1.91 1.48 1.65 1.91 ns GTL_DCI 0.76 0.85 1.00 1.36 1.47 1.65 1.36 1.47 1.65 ns GTLP_DCI 0.76 0.85 1.00 1.37 1.52 1.76 1.37 1.52 1.76 ns LVPECL_25 0.80 0.90 1.06 1.28 1.42 1.62 1.28 1.42 1.62 ns HSTL_I_12 0.76 0.85 1.00 1.45 1.61 1.85 1.45 1.61 1.85 ns HSTL_I_DCI 0.76 0.85 1.00 1.41 1.56 1.77 1.41 1.56 1.77 ns HSTL_II_DCI 0.76 0.85 1.00 1.34 1.48 1.69 1.34 1.48 1.69 ns HSTL_II_T_DCI 0.76 0.85 1.00 1.41 1.56 1.77 1.41 1.56 1.77 ns HSTL_III_DCI 0.76 0.85 1.00 1.57 1.72 1.95 1.57 1.72 1.95 ns HSTL_IV_DCI 0.76 0.85 1.00 1.34 1.46 1.64 1.34 1.46 1.64 ns HSTL_I_DCI_18 0.76 0.85 1.00 1.36 1.50 1.70 1.36 1.50 1.70 ns HSTL_II_DCI_18 0.76 0.85 1.00 1.30 1.43 1.64 1.30 1.43 1.64 ns HSTL_II _T_DCI_18 0.76 0.85 1.00 1.36 1.50 1.70 1.36 1.50 1.70 ns HSTL_III_DCI_18 0.76 0.85 1.00 1.55 1.69 1.91 1.55 1.69 1.91 ns HSTL_IV_DCI_18 0.76 0.85 1.00 1.31 1.44 1.62 1.31 1.44 1.62 ns DIFF_HSTL_I_18 0.80 0.90 1.06 1.40 1.55 1.77 1.40 1.55 1.77 ns DIFF_HSTL_I_DCI_18 0.80 0.90 1.06 1.36 1.50 1.70 1.36 1.50 1.70 ns DIFF_HSTL_I 0.80 0.90 1.06 1.42 1.57 1.79 1.42 1.57 1.79 ns DIFF_HSTL_I_DCI 0.80 0.90 1.06 1.41 1.56 1.77 1.41 1.56 1.77 ns DIFF_HSTL_II_18 0.80 0.90 1.06 1.36 1.51 1.72 1.36 1.51 1.72 ns DIFF_HSTL_II_DCI_18 0.80 0.90 1.06 1.30 1.43 1.64 1.30 1.43 1.64 ns DIFF_HSTL_II 0.80 0.90 1.06 1.39 1.53 1.74 1.39 1.53 1.74 ns DIFF_HSTL_II_DCI 0.80 0.90 1.06 1.34 1.48 1.69 1.34 1.48 1.69 ns DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 26 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 30: IOB Switching Characteristics (Continued) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade Units -3 -2 -1 -3 -2 -1 -3 -2 -1 SSTL2_I_DCI 0.76 0.85 1.00 1.42 1.56 1.78 1.42 1.56 1.78 ns SSTL2_II_DCI 0.76 0.85 1.00 1.34 1.48 1.70 1.34 1.48 1.70 ns SSTL2_II_T_DCI 0.76 0.85 1.00 1.42 1.56 1.78 1.42 1.56 1.78 ns SSTL18_I 0.76 0.85 1.00 1.46 1.61 1.84 1.46 1.61 1.84 ns SSTL18_II 0.76 0.85 1.00 1.39 1.53 1.75 1.39 1.53 1.75 ns SSTL18_I_DCI 0.76 0.85 1.00 1.39 1.53 1.74 1.39 1.53 1.74 ns SSTL18_II_DCI 0.76 0.85 1.00 1.30 1.44 1.64 1.30 1.44 1.64 ns SSTL18_II_T_DCI 0.76 0.85 1.00 1.39 1.53 1.74 1.39 1.53 1.74 ns DIFF_SSTL2_I 0.80 0.90 1.06 1.48 1.64 1.87 1.48 1.64 1.87 ns DIFF_SSTL2_I_DCI 0.80 0.90 1.06 1.42 1.56 1.78 1.42 1.56 1.78 ns DIFF_SSTL18_I 0.80 0.90 1.06 1.46 1.61 1.84 1.46 1.61 1.84 ns DIFF_SSTL18_I_DCI 0.80 0.90 1.06 1.39 1.53 1.74 1.39 1.53 1.74 ns DIFF_SSTL2_II 0.80 0.90 1.06 1.40 1.55 1.76 1.40 1.55 1.76 ns DIFF_SSTL2_II_DCI 0.80 0.90 1.06 1.34 1.48 1.70 1.34 1.48 1.70 ns DIFF_SSTL18_II 0.80 0.90 1.06 1.39 1.53 1.75 1.39 1.53 1.75 ns DIFF_SSTL18_II_DCI 0.80 0.90 1.06 1.30 1.44 1.64 1.30 1.44 1.64 ns Table 31: IOB 3-state ON Output Switching Characteristics (TIOTPHZ) Speed Grade Symbol TIOTPHZ DS202 (v3.6) November 5, 2007 Advance Product Specification Description T input to Pad high-impedance -3 -2 -1 Units 0.88 1.01 1.12 ns www.xilinx.com 27 R Virtex-5 Data Sheet: DC and Switching Characteristics I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 32 shows the test setup parameters used for measuring input delay. Table 32: Input Delay Measurement Methodology I/O Standard Attribute Description VL (1,2) VH (1,2) VMEAS (1,4,5) VREF (1,3,5) LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL 0 3.0 1.4 - LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS33 0 3.3 1.65 - LVCMOS, 2.5V LVCMOS25 0 2.5 1.25 - LVCMOS, 1.8V LVCMOS18 0 1.8 0.9 - LVCMOS, 1.5V LVCMOS15 0 1.5 0.75 - PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI33_3 Per PCI Specification - PCI, 66 MHz, 3.3V PCI66_3 Per PCI Specification - PCI-X, 133 MHz, 3.3V PCIX Per PCI-X Specification - GTL (Gunning Transceiver Logic) GTL VREF - 0.2 VREF + 0.2 VREF 0.80 GTL Plus GTLP VREF - 0.2 VREF + 0.2 VREF 1.0 HSTL (High-Speed Transceiver Logic), Class I & II HSTL_I, HSTL_II VREF - 0.5 VREF + 0.5 VREF 0.75 HSTL, Class III & IV HSTL_III, HSTL_IV VREF - 0.5 VREF + 0.5 VREF 0.90 HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 VREF - 0.5 VREF + 0.5 VREF 0.90 HSTL, Class III & IV, 1.8V HSTL_III_18, HSTL_IV_18 VREF - 0.5 VREF + 0.5 VREF 1.08 SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V SSTL3_I, SSTL3_II VREF - 1.00 VREF + 1.00 VREF 1.5 SSTL, Class I & II, 2.5V SSTL2_I, SSTL2_II VREF - 0.75 VREF + 0.75 VREF 1.25 SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II VREF - 0.5 VREF + 0.5 VREF 0.90 AGP-2X/AGP (Accelerated Graphics Port) AGP VREF - (0.2 x VCCO) VREF + (0.2 x VCCO) VREF AGP Spec LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 1.2 - 0.125 1.2 + 0.125 1.2 LVDSEXT (LVDS Extended Mode), 2.5V LVDSEXT_25 1.2 - 0.125 1.2 + 0.125 1.2 LDT (HyperTransport), 2.5V LDT_25 0.6 - 0.125 0.6 + 0.125 0.6 LVPECL (Low-Voltage Positive Electron-Coupled Logic), 2.5V LVPECL_25 1.15 - 0.3 1.15 - 0.3 1.15 Notes: 1. Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage. Parameters for all other DCI standards are the same as for the corresponding non-DCI standards. 2. Input waveform switches between VLand VH. 3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. 4. Input voltage level from which measurement starts. 5. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 6. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 28 R Virtex-5 Data Sheet: DC and Switching Characteristics Output Delay Measurements Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setup shown in Figure 6. Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it. Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method: 1. Simulate the output driver of choice into the generalized test setup, using values from Table 33. VREF 2. Record the time to VMEAS . FPGA Output 3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. RREF 4. Record the time to VMEAS . VMEAS 5. Compare the results of steps 2 and 4. The increase or decrease in delay yields the actual worst-case propagation delay (clock-to-input) of the PCB trace. (voltage level when taking delay measurement) CREF (probe capacitance) ds202_06_041107 Figure 6: Generalized Test Setup Table 33: Output Delay Measurement Methodology I/O Standard Attribute Description RREF ( ) CREF(1) ( pF ) VMEAS (V) VREF (V) LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL (all) 1M 0 1.4 0 LVCMOS (Low-Voltage CMOS ), 3.3V LVCMOS33 1M 0 1.65 0 LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0 LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0 LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0 LVCMOS, 1.2V LVCMOS12 1M 0 0.75 0 PCI (Peripheral Component Interface), 33 MHz, 3.3V PCI33_3 (rising edge) 25 10 (2) 0.94 0 25 10 (2) 2.03 3.3 PCI66_3 (rising edge) 25 10 (2) 0.94 0 PCI66_3 (falling edge) 25 10 (2) 2.03 3.3 PCIX (rising edge) 25 10 (3) 0.94 PCIX (falling edge 25 10 (3) 2.03 3.3 GTL (Gunning Transceiver Logic) GTL 25 0 0.8 1.2 GTL Plus GTLP 25 0 1.0 1.5 HSTL (High-Speed Transceiver Logic), Class I HSTL_I 50 0 VREF 0.75 HSTL, Class II HSTL_II 25 0 VREF 0.75 HSTL, Class III HSTL_III 50 0 0.9 1.5 HSTL, Class IV HSTL_IV 25 0 0.9 1.5 HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9 HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.9 PCI33_3 (falling edge) PCI, 66 MHz, 3.3V PCI-X, 133 MHz, 3.3V DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 29 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 33: Output Delay Measurement Methodology (Continued) I/O Standard Attribute Description RREF ( ) CREF(1) ( pF ) VMEAS (V) VREF (V) HSTL, Class III, 1.8V HSTL_III_18 50 0 1.1 1.8 HSTL, Class IV, 1.8V HSTL_IV_18 25 0 1.1 1.8 SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL18_I 50 0 VREF 0.9 SSTL, Class II, 1.8V SSTL18_II 25 0 VREF 0.9 SSTL, Class I, 2.5V SSTL2_I 50 0 VREF 1.25 SSTL, Class II, 2.5V SSTL2_II 25 0 VREF 1.25 LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 50 0 VREF 1.2 LVDSEXT (LVDS Extended Mode), 2.5V LVDS_25 50 0 VREF 1.2 BLVDS (Bus LVDS), 2.5V BLVDS_25 1M 0 1.2 0 LDT (HyperTransport), 2.5V LDT_25 50 0 VREF 0.6 LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V LVPECL_25 1M 0 0.90 0 LVDCI/HSLVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V LVDCI_33, HSLVDCI_33 1M 0 1.65 0 LVDCI/HSLVDCI, 2.5V LVDCI_25, HSLVDCI_25 1M 0 1.25 0 LVDCI/HSLVDCI, 1.8V LVDCI_18, HSLVDCI_18 1M 0 0.9 0 LVDCI/HSLVDCI, 1.5V LVDCI_15, HSLVDCI_15 1M 0 0.75 0 HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI 50 0 VREF 0.75 HSTL, Class III & IV, with DCI HSTL_III_DCI, HSTL_IV_DCI 50 0 0.9 1.5 HSTL, Class I & II, 1.8V, with DCI HSTL_I_DCI_18, HSTL_II_DCI_18 50 0 VREF 0.9 HSTL, Class III & IV, 1.8V, with DCI HSTL_III_DCI_18, HSTL_IV_DCI_18 50 0 1.1 1.8 SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI 50 0 VREF 0.9 SSTL, Class I & II, 2.5V, with DCI SSTL2_I_DCI, SSTL2_II_DCI 50 0 VREF 1.25 GTL (Gunning Transceiver Logic) with DCI GTL_DCI 50 0 0.8 1.2 GTL Plus with DCI GTLP_DCI 50 0 1.0 1.5 Notes: 1. CREF is the capacitance of the probe, nominally 0 pF. 2. Per PCI specifications. 3. Per PCI-X specifications. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 30 R Virtex-5 Data Sheet: DC and Switching Characteristics Input/Output Logic Switching Characteristics Table 34: ILOGIC Switching Characteristics Speed Grade Symbol Description -3 -2 -1 Units Setup/Hold TICE1CK/TICKCE1 CE1 pin Setup/Hold with respect to CLK 0.43 -0.24 0.49 -0.24 0.59 -0.24 ns TISRCK/TICKSR SR/REV pin Setup/Hold with respect to CLK 0.85 -0.20 1.00 -0.20 1.22 -0.20 ns TIDOCK/TIOCKD D pin Setup/Hold with respect to CLK without Delay 0.34 -0.12 0.37 -0.12 0.39 -0.12 ns TIDOCKD/TIOCKDD DDLY pin Setup/Hold with respect to CLK (using IODELAY) 0.31 -0.09 0.33 -0.09 0.36 -0.08 ns Combinatorial TIDI D pin to O pin propagation delay, no Delay 0.24 0.26 0.30 ns TIDID DDLY pin to O pin propagation delay (using IODELAY) 0.20 0.22 0.26 ns TIDLO D pin to Q1 pin using flip-flop as a latch without Delay 0.44 0.50 0.58 ns TIDLOD DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY) 0.41 0.46 0.55 ns TICKQ CLK to Q outputs 0.47 0.52 0.60 ns TRQ SR/REV pin to OQ/TQ out 1.12 1.28 1.53 ns TGSRQ Global Set/Reset to Q outputs 7.30 7.30 10.10 ns Minimum Pulse Width, SR/REV inputs 0.78 0.95 1.20 ns, Min Sequential Delays Set/Reset TRPW DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 31 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 35: OLOGIC Switching Characteristics Speed Grade Symbol Description -3 -2 -1 Units Setup/Hold TODCK/TOCKD D1/D2 pins Setup/Hold with respect to CLK 0.30 -0.21 0.36 -0.21 0.44 -0.21 ns TOOCECK/TOCKOCE OCE pin Setup/Hold with respect to CLK 0.16 -0.07 0.19 -0.07 0.23 -0.07 ns TOSRCK/TOCKSR SR/REV pin Setup/Hold with respect to CLK 0.93 -0.20 1.02 -0.20 1.16 -0.20 ns TOTCK/TOCKT T1/T2 pins Setup/Hold with respect to CLK 0.28 -0.18 0.34 -0.18 0.41 -0.18 ns TOTCECK/TOCKTCE TCE pin Setup/Hold with respect to CLK 0.20 -0.06 0.23 -0.06 0.29 -0.06 ns D1 to OQ out or T1 to TQ out 0.62 0.70 0.83 ns TOCKQ CLK to OQ/TQ out 0.61 0.62 0.62 ns TRQ SR/REV pin to OQ/TQ out 1.63 1.89 2.27 ns TGSRQ Global Set/Reset to Q outputs 7.30 7.30 10.10 ns Minimum Pulse Width, SR/REV inputs 0.80 0.98 1.25 ns, Min Combinatorial TDOQ Sequential Delays Set/Reset TRPW DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 32 R Virtex-5 Data Sheet: DC and Switching Characteristics Input Serializer/Deserializer Switching Characteristics Table 36: ISERDES Switching Characteristics Speed Grade Symbol Description -3 -2 -1 Units Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin Setup/Hold with respect to CLKDIV 0.10 0.00 0.11 0.00 0.12 0.00 ns TISCCK_CE / TISCKC_CE(2) CE pin Setup/Hold with respect to CLK (for CE1) 0.43 -0.24 0.49 -0.24 0.59 -0.24 ns TISCCK_CE2 / TISCKC_CE2(2) CE pin Setup/Hold with respect to CLKDIV (for CE2) 0.03 0.11 0.04 0.13 0.06 0.15 ns Setup/Hold for Data Lines TISDCK_D /TISCKD_D D pin Setup/Hold with respect to CLK 0.34 -0.12 0.37 -0.12 0.39 -0.12 ns TISDCK_DDLY /TISCKD_DDLY DDLY pin Setup/Hold with respect to CLK (using IODELAY) 0.31 -0.09 0.33 -0.09 0.36 -0.08 ns TISDCK_DDR /TISCKD_DDR D pin Setup/Hold with respect to CLK at DDR mode 0.34 -0.12 0.37 -0.12 0.39 -0.12 ns TISDCK_DDLY_DDR TISCKD_DDLY_DDR D pin Setup/Hold with respect to CLK at DDR mode (using IODELAY) 0.31 -0.09 0.33 -0.09 0.36 -0.08 ns CLKDIV to out at Q pin 0.46 0.51 0.60 ns D input to DO output pin 0.20 0.22 0.26 ns Sequential Delays TISCKO_Q Propagation Delays TISDO_DO Notes: 1. Recorded at 0 tap value. 2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in TRACE report. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 33 R Virtex-5 Data Sheet: DC and Switching Characteristics Output Serializer/Deserializer Switching Characteristics Input Delay Switching Characteristics Table 37: OSERDES Switching Characteristics Speed Grade Symbol Description -3 -2 -1 Units Setup/Hold TOSDCK_D/TOSCKD_D D input Setup/Hold with respect to CLKDIV 0.21 -0.02 0.24 -0.02 0.30 -0.02 ns TOSDCK_T/TOSCKD_T(1) T input Setup/Hold with respect to CLK 0.28 -0.18 0.34 -0.18 0.41 -0.18 ns TOSDCK_T2/TOSCKD_T2(1) T input Setup/Hold with respect to CLKDIV 0.21 -0.03 0.24 -0.03 0.28 -0.03 ns TOSCCK_OCE/TOSCKC_OCE OCE input Setup/Hold with respect to CLK 0.16 -0.07 0.19 -0.07 0.23 -0.07 ns TOSCCK_S SR (Reset) input Setup with respect to CLKDIV 0.52 0.58 0.70 ns TOSCCK_TCE/TOSCKC_TCE TCE input Setup/Hold with respect to CLK 0.20 -0.06 0.23 -0.06 0.29 -0.06 ns Sequential Delays TOSCKO_OQ Clock to out from CLK to OQ 0.59 0.60 0.61 ns TOSCKO_TQ Clock to out from CLK to TQ 0.61 0.62 0.62 ns TOSDO_TTQ T input to TQ Out 0.62 0.70 0.83 ns TOSCO_OQ Asynchronous Reset to OQ 1.57 1.82 2.19 ns TOSCO_TQ Asynchronous Reset to TQ 1.63 1.89 2.27 ns Combinatorial Notes: 1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in TRACE report. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 34 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 38: Input/Output Delay Switching Characteristics Speed Grade Symbol Description TIDELAYRESOLUTION IODELAY Chain Delay Resolution TIDELAYCTRLCO_RDY Reset to Ready for IDELAYCTRL FIDELAYCTRL_REF REFCLK frequency IDELAYCTRL_REF_PRECISION REFCLK precision -3 -2 -1 1/(64 x FREF x 1e6)(1) Units ps 3.00 3.00 3.00 s 200.00 200.00 200.00 MHz 10 10 10 MHz 50.00 50.00 50.00 ns TIDELAYCTRL_RPW Minimum Reset pulse width TIDELAYPAT_JIT Pattern dependent period jitter in delay chain for clock pattern 0 0 0 Note 2 Pattern dependent period jitter in delay chain for randon data pattern (PRBS 23) 5 5 5 Note 2 TIODELAY_CLK_MAX Maximum frequency of CLK input to IODELAY 300 250 250 MHz TIODCCK_CE / TIODCKC_CE CE pin Setup/Hold with respect to CK 0.29 -0.06 0.34 -0.06 0.42 -0.06 ns TIODCK_INC/ TIODCKC_INC INC pin Setup/Hold with respect to CK 0.18 0.02 0.20 0.04 0.24 0.06 ns TIODCK_RST/ TIODCKC_RST RST pin Setup/Hold with respect to CK 0.25 -0.12 0.28 -0.12 0.33 -0.12 ns Notes: 1. Average Tap Delay at 200 MHz = 78 ps. 2. Units in ps, peak-to-peak per tap, in High Performance mode. CLB Switching Characteristics Table 39: CLB Switching Characteristics Speed Grade Symbol Description -3 -2 -1 Units An - Dn LUT address to A 0.08 0.09 0.10 ns, Max An - Dn LUT address to AMUX/CMUX 0.20 0.22 0.25 ns, Max An - Dn LUT address to BMUX_A 0.31 0.35 0.40 ns, Max TITO An - Dn inputs to A - D Q outputs 0.67 0.77 0.90 ns, Max TAXA AX inputs to AMUX output 0.39 0.44 0.53 ns, Max TAXB AX inputs to BMUX output 0.46 0.52 0.61 ns, Max TAXC AX inputs to CMUX output 0.31 0.36 0.42 ns, Max TAXD AX inputs to DMUX output 0.55 0.62 0.73 ns, Max TBXB BX inputs to BMUX output 0.36 0.41 0.48 ns, Max TBXD BX inputs to DMUX output 0.45 0.51 0.59 ns, Max TCXB CX inputs to CMUX output 0.33 0.36 0.42 ns, Max TCXD CX inputs to DMUX output 0.37 0.42 0.49 ns, Max TDXD DX inputs to DMUX output 0.38 0.42 0.49 ns, Max Combinatorial Delays TILO DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 35 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 39: CLB Switching Characteristics (Continued) Speed Grade Symbol Description -3 -2 -1 Units TOPCYA An input to COUT output 0.43 0.50 0.59 ns, Max TOPCYB Bn input to COUT output 0.39 0.44 0.51 ns, Max TOPCYC Cn input to COUT output 0.33 0.37 0.43 ns, Max TOPCYD Dn input to COUT output 0.30 0.34 0.40 ns, Max TAXCY AX input to COUT output 0.36 0.42 0.50 ns, Max TBXCY BX input to COUT output 0.26 0.30 0.37 ns, Max TCXCY CX input to COUT output 0.20 0.22 0.26 ns, Max TDXCY DX input to COUT output 0.20 0.22 0.26 ns, Max TBYP CIN input to COUT output 0.09 0.10 0.11 ns, Max TCINA CIN input to AMUX output 0.24 0.27 0.31 ns, Max TCINB CIN input to BMUX output 0.27 0.30 0.35 ns, Max TCINC CIN input to CMUX output 0.29 0.32 0.36 ns, Max TCIND CIN input to DMUX output 0.31 0.35 0.41 ns, Max Clock to AQ - DQ outputs 0.35 0.40 0.47 ns, Max Sequential Delays TCKO Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK TDICK/TCKDI A - D input to CLK on A - D Flip Flops 0.36 0.19 0.41 0.21 0.49 0.24 ns, Min TRCK DX input to CLK when used as REV 0.37 0.42 0.51 ns, Min TCECK/TCKCE CE input to CLK on A - D Flip Flops 0.18 -0.04 0.20 -0.04 0.23 -0.04 ns, Min TSRCK/TCKSR SR input to CLK on A - D Flip Flops 0.41 -0.19 0.49 -0.19 0.59 -0.19 ns, Min TCINCK/TCKCIN CIN input to CLK on A - D Flip Flops 0.14 0.14 0.16 0.16 0.18 0.19 ns, Min TSRMIN SR input minimum pulse width 0.90 0.90 0.90 ns, Min TRQ Delay from SR or REV input to AQ - DQ flip-flops 0.74 0.86 1.03 ns, Max TCEO Delay from CE input to AQ - DQ flip-flops 0.46 0.52 0.63 ns, Max FTOG Toggle frequency (for export control) 1412 1265 1098 MHz Set/Reset Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. These items are of interest for Carry Chain applications. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 36 R Virtex-5 Data Sheet: DC and Switching Characteristics CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 40: CLB Distributed RAM Switching Characteristics Speed Grade Symbol Description -3 -2 -1 Units Sequential Delays TSHCKO Clock to A - B outputs 1.08 1.26 1.54 ns, Max TSHCKO_1 Clock to AMUX - BMUX outputs 1.19 1.38 1.68 ns, Max Setup and Hold Times Before/After Clock CLK TDS/TDH A - D inputs to CLK 0.72 0.20 0.84 0.22 1.03 0.26 ns, Min TAS/TAH Address An inputs to clock 0.41 0.20 0.46 0.22 0.54 0.27 ns, Min TWS/TWH WE input to clock 0.34 -0.06 0.39 -0.04 0.46 -0.02 ns, Min TCECK/TCKCE CE input to CLK 0.36 -0.08 0.42 -0.07 0.51 -0.06 ns, Min Clock CLK TMPW Minimum pulse width 0.70 0.82 1.00 ns, Min TMCP Minimum clock period 1.40 1.64 2.00 ns, Min Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. 2. TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path. CLB Shift Register Switching Characteristics (SLICEM Only) Table 41: CLB Shift Register Switching Characteristics Speed Grade Symbol Description -3 -2 -1 Units Sequential Delays TREG Clock to A - D outputs 1.23 1.43 1.73 ns, Max TREG_MUX Clock to AMUX - DMUX output 1.33 1.55 1.87 ns, Max TREG_M31 Clock to DMUX output via M31 output 0.99 1.15 1.38 ns, Max Setup and Hold Times Before/After Clock CLK TWS/TWH WE input 0.21 -0.06 0.24 -0.04 0.29 -0.02 ns, Min TCECK/TCKCE CE input to CLK 0.23 -0.08 0.27 -0.07 0.33 -0.06 ns, Min TDS/TDH A - D inputs to CLK 0.57 0.07 0.66 0.09 0.78 0.11 ns, Min DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 37 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 41: CLB Shift Register Switching Characteristics (Continued) Speed Grade Symbol Description -3 -2 -1 Units 0.60 0.70 0.85 ns, Min Clock CLK TMPW Minimum pulse width Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. Block RAM and FIFO Switching Characteristics Table 42: Block RAM and FIFO Switching Characteristics Speed Grade Symbol Description -3 -2 -1 Units Clock CLK to DOUT output (without output register)(2)(3) 1.79 1.92 2.19 ns, Max Clock CLK to DOUT output (with output register)(4)(5) 0.61 0.69 0.82 ns, Max Clock CLK to DOUT output with ECC (without output register)(2)(3) 2.64 3.03 3.61 ns, Max Clock CLK to DOUT output with ECC (with output register)(4)(5) 0.66 0.77 0.93 ns, Max Clock CLK to DOUT output with Cascade (without output register)(2) 2.10 2.44 2.94 ns, Max Clock CLK to DOUT output with Cascade (with output register)(4) 0.91 1.07 1.30 ns, Max TRCKO_FLAGS Clock CLK to FIFO flags outputs(6) 0.76 0.87 1.02 ns, Max TRCKO_POINTERS Clock CLK to FIFO pointer outputs(7) 1.10 1.26 1.48 ns, Max TRCKO_ECCR Clock CLK to BITERR (with output register) 0.66 0.77 0.93 ns, Max Clock CLK to BITERR (without output register) 2.48 2.85 3.41 ns, Max Clock CLK to ECCPARITY in standard ECC mode 1.29 1.47 1.74 ns, Max Clock CLK to ECCPARITY in ECC encode only mode 0.77 0.89 1.05 ns, Max Block RAM and FIFO Clock to Out Delays TRCKO_DO and TRCKO_DOR(1) TRCKO_ECC DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 38 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 42: Block RAM and FIFO Switching Characteristics (Continued) Speed Grade Symbol Description -3 -2 -1 Units Setup and Hold Times Before/After Clock CLK TRCCK_ADDR/TRCKC_ADDR ADDR inputs 0.34 0.30 0.40 0.32 0.48 0.36 ns, Min TRDCK_DI/TRCKD_DI DIN inputs(8) 0.27 0.28 0.30 0.28 0.35 0.29 ns, Min DIN inputs with ECC in standard mode(8) 0.33 0.32 0.37 0.33 0.42 0.36 ns, Min DIN inputs with ECC encode only(8) 0.68 0.32 0.72 0.33 0.77 0.36 ns, Min TRCCK_EN/TRCKC_EN Block RAM Enable (EN) input 0.32 0.15 0.36 0.15 0.42 0.15 ns, Min TRCCK_REGCE/TRCKC_REGCE CE input of output register 0.15 0.22 0.16 0.24 0.18 0.27 ns, Min TRCCK_SSR/TRCKC_SSR Synchronous Set/ Reset (SSR) input 0.17 0.23 0.21 0.25 0.26 0.28 ns, Min TRCCK_WE/TRCKC_WE Write Enable (WE) input 0.44 0.16 0.51 0.17 0.63 0.18 ns, Min TRCCK_WREN/TRCKC_WREN WREN/RDEN FIFO inputs(9) 0.36 0.30 0.41 0.34 0.48 0.40 ns, Min Reset RST to FIFO Flags/Pointers(10) 1.10 1.26 1.48 ns, Max FMAX Block RAM in all modes 550 500 450 MHz FMAX_CASCADE Block RAM in Cascade mode 500 450 400 MHz FMAX_FIFO FIFO in all modes 550 500 450 MHz FMAX_ECC Block RAM in ECC mode 415 375 325 MHz TRDCK_DI_ECC/TRCKD_DI_ECC Reset Delays TRCO_FLAGS Maximum Frequency Notes: 1. Trace will report all of these parameters as TRCKO_DO. 2. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. 3. These parameters also apply to synchronous FIFO with DO_REG = 0. 4. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. 5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1. 6. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. 7. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. 8. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B. 9. These parameters also apply to RDEN. 10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 39 R Virtex-5 Data Sheet: DC and Switching Characteristics DSP48E Switching Characteristics Table 43: DSP48E Switching Characteristics Symbol Description Speed -3 -2 -1 Units Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_{AA, BB, ACINA, BCINB}/ TDSPCKD_{AA, BB, ACINA, BCINB} {A, B, ACIN, BCIN} input to {A, B} register CLK 0.17 0.17 0.21 0.23 0.26 0.30 ns TDSPDCK_CC/TDSPCKD_CC C input to C register CLK 0.14 0.26 0.16 0.31 0.20 0.37 ns 1.30 0.19 1.44 0.19 1.71 0.19 ns Setup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_{AM, BM, ACINM, BCINM}/ TDSPCKD_{AM, BM, ACINM, BCINM} {A, B, ACIN, BCIN} input to M register CLK Setup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_{AP, BP, ACINP, BCINP}_M/ TDSPCKD_{AP, BP, ACINP, BCINP}_M {A, B, ACIN, BCIN} input to P register CLK using multiplier 2.39 -0.30 2.74 -0.30 3.25 -0.30 ns TDSPDCK_{AP, BP, ACINP, BCINP}_NM/ TDSPCKD_{AP, BP, ACINP, BCINP}_NM {A, B, ACIN, BCIN} input to P register CLK not using multiplier 1.35 -0.10 1.54 -0.10 1.83 -0.10 ns TDSPDCK_CP/TDSPCKD_CP C input to P register CLK 1.30 -0.13 1.42 -0.13 1.70 -0.13 ns TDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/ TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP} {PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK 1.06 0.11 1.17 0.11 1.31 0.11 ns TDSPCCK_{CEA1A, CEA2A, CEB1B, CEB2B}/ TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B} {CEA1, CEA2A, CEB1B, CEB2B} input to {A, B} register CLK 0.24 0.21 0.28 0.25 0.33 0.31 ns TDSPCCK_CECC/TDSPCKC_CECC CEC input to C register CLK 0.19 0.17 0.21 0.21 0.26 0.28 ns TDSPCCK_CEMM/TDSPCKC_CEMM CEM input to M register CLK 0.25 0.18 0.29 0.21 0.36 0.26 ns TDSPCCK_CEPP/TDSPCKC_CEPP CEP input to P register CLK 0.56 0.01 0.63 0.01 0.73 0.01 ns TDSPCCK_{RSTAA, RSTBB}/ TDSPCKC_{RSTAA, RSTBB} {RSTA, RSTB} input to {A, B} register CLK 0.24 0.23 0.28 0.26 0.33 0.31 ns TDSPCCK_RSTCC/ TDSPCKC_RSTCC RSTC input to C register CLK 0.19 0.17 0.21 0.21 0.26 0.28 ns TDSPCCK_RSTMM/ TDSPCKC_RSTMM RSTM input to M register CLK 0.25 0.18 0.29 0.21 0.36 0.26 ns TDSPCCK_RSTPP/TDSPCKC_RSTPP RSTP input to P register CLK 0.56 0.01 0.63 0.01 0.73 0.01 ns Setup and Hold Times of the CE Pins Setup and Hold Times of the RST Pins DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 40 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 43: DSP48E Switching Characteristics (Continued) Symbol Description Speed -3 -2 -1 Units Combinatorial Delays from Input Pins to Output Pins TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M {A, B} input to {P, CARRYOUT} output using multiplier 2.78 3.22 3.84 ns TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM {A, B} input to {P, CARRYOUT} output not using multiplier 1.59 1.77 2.22 ns TDSPDO_{CP, CCRYOUT, CRYINP, CRYINCRYOUT} {C, CARRYIN} input to {P, CARRYOUT} output 1.50 1.67 2.08 ns Combinatorial Delays from Input Pins to Cascading Output Pins TDSPDO_{AACOUT, BBCOUT} {A, B} input to {ACOUT, BCOUT} output 1.00 1.12 1.31 ns TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_M {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier 2.78 3.22 3.84 ns TDSPDO_{APCOUT, ACRYCOUT, AMULTSIGNOUT, BPCOUT, BCRYCOUT, BMULTSIGNOUT}_NM {A, B} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier 1.72 1.92 2.42 ns TDSPDO_{CPCOUT, CCRYCOUT, CMULTSIGNOUT, CRYINPCOUT, CRYINCRYCOUT, CRYINMULTSIGNOUT} {C, CARRYIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 1.63 1.82 2.28 ns Combinatorial Delays from Cascading Input Pins to All Output Pins TDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_M {ACIN, BCIN} input to {P, CARRYOUT} output using multiplier 2.78 3.22 3.84 ns TDSPDO_{ACINP, ACINCRYOUT, BCINP, BCINCRYOUT}_NM {ACIN, BCIN} input to {P, CARRYOUT} output not using multiplier 1.59 1.77 2.22 ns TDSPDO_{ACINACOUT, BCINBCOUT} {ACIN, BCIN} input to {ACOUT, BCOUT} output 1.00 1.12 1.31 ns TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT, BCINMULTSIGNOUT}_M {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier 2.78 3.22 3.84 ns TDSPDO_{ACINPCOUT, ACINCRYCOUT, ACINMULTSIGNOUT, BCINPCOUT, BCINCRYCOUT, BCINMULTSIGNOUT}_NM {ACIN, BCIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier 1.72 1.92 2.42 ns TDSPDO_{PCINP, CRYCINP, MULTSIGNINP, PCINCRYOUT, CRYCINCRYOUT, MULTSIGNINCRYOUT} {PCIN, CARRYCASCIN, MULTSIGNIN} input to {P, CARRYOUT} output 1.30 1.45 1.82 ns TDSPDO_{PCINPCOUT, CRYCINPCOUT, MULTSIGNINPCOUT, PCINCRYCOUT, CRYCINCRYCOUT, MULTSIGNINCRYCOUT, PCINMULTSIGNOUT, CRYCINMULTSIGNOUT, MULTSIGNINMULTSIGNOUT} {PCIN, CARRYCASCIN, MULTSIGNIN} input to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 1.43 1.60 2.02 ns Clock to Outs from Output Register Clock to Output Pins TDSPCKO_{PP, CRYOUTP} CLK (PREG) to {P, CARRYOUT} output 0.45 0.48 0.56 ns TDSPCKO_{CRYCOUTP, PCOUTP, MULTSIGNOUTP} CLK (PREG) to {CARRYCASCOUT, PCOUT, MULTSIGNOUT} output 0.48 0.53 0.62 ns DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 41 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 43: DSP48E Switching Characteristics (Continued) Symbol Description Speed -3 -2 -1 Units Clock to Outs from Pipeline Register Clock to Output Pins TDSPCKO_{PM, CRYOUTM} CLK (MREG) to {P, CARRYOUT} output 1.81 2.10 2.47 ns TDSPCKO_{PCOUTM, CRYCOUTM, MULTSIGNOUTM} CLK (MREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 1.91 2.13 2.66 ns Clock to Outs from Input Register Clock to Output Pins TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_M CLK (AREG, BREG) to {P, CARRYOUT} output using multiplier 3.09 3.57 4.23 ns TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_NM CLK (AREG, BREG) to {P, CARRYOUT} output not using multiplier 1.90 2.11 2.63 ns TDSPCKO_{PC, CRYOUTC} CLK (CREG) to {P, CARRYOUT} output 1.89 2.11 2.62 ns Clock to Outs from Input Register Clock to Cascading Output Pins TDSPCKO_{ACOUTA, BCOUTB} CLK (AREG, BREG) to {ACOUT, BCOUT} 0.61 0.68 0.79 ns TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA, PCOUTB, CRYCOUTB, MULTSIGNOUTB}_M CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output using multiplier 3.09 3.57 4.23 ns TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA, PCOUTB, CRYCOUTB, MULTSIGNOUTB}_NM CLK (AREG, BREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output not using multiplier 2.03 2.27 2.82 ns TDSPCKO_{PCOUTC, CRYCOUTC, MULTSIGNOUTC} CLK (CREG) to {PCOUT, CARRYCASCOUT, MULTSIGNOUT} output 2.03 2.26 2.82 ns FMAX With all registers used 550 500 450 MHz FMAX_PATDET With pattern detector 515 465 410 MHz FMAX_MULT_NOMREG Two register multiply without MREG 374 324 275 MHz FMAX_MULT_NOMREG_PATDET Two register multiply without MREG with pattern detect 345 300 254 MHz Maximum Frequency DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 42 R Virtex-5 Data Sheet: DC and Switching Characteristics Configuration Switching Characteristics Table 44: Configuration Switching Characteristics Speed Grade Symbol Description -3 -2 -1 Units Power-up Timing Characteristics TPL Program Latency 3 3 3 ms, Max TPOR Power-on-Reset 10 50 10 50 10 50 ms, Min/Max TICCK CCLK (output) delay 400 400 400 ns, Min TPROGRAM Program Pulse Width 250 250 250 ns, Min Master/Slave Serial Mode Programming Switching(1) TDCCK/TCCKD DIN Setup/Hold, slave mode 4.0 0.0 4.0 0.0 4.0 0.0 ns, Min TDSCCK/TSCCKD DIN Setup/Hold, master mode 4.0 0.0 4.0 0.0 4.0 0.0 ns, Min TCCO DOUT 7.5 7.5 7.5 ns, Max FMCCK Maximum Frequency, master mode with respect to nominal CCLK. 100 100 100 MHz, Max FMCCKTOL Frequency Tolerance, master mode with respect to nominal CCLK. 50 50 50 % FMSCCK Slave mode external CCLK 100 100 100 MHz SelectMAP Mode Programming Switching(1) TSMDCCK/TSMCCKD SelectMAP Data Setup/Hold 3.0 0.5 3.0 0.5 3.0 0.5 ns, Min TSMCSCCK/TSMCCKCS CS_B Setup/Hold 3.0 0.5 3.0 0.5 3.0 0.5 ns, Min TSMCCKW/TSMWCCK RDWR_B Setup/Hold 8.0 0.5 8.0 0.5 8.0 0.5 ns, Min TSMCKBY BUSY Propagation Delay 7.5 7.5 7.5 ns, Max TSMCKCSO CSO_B clock to out (330 pull-up resistor required) 10 10 10 ns, Min TSMCO CCLK to DATA out in readback 9.0 9.0 9.0 ns, Max TSMCKBY CCLK to BUSY out in readback 7.5 7.5 7.5 ns, Max FSMCCK Maximum Frequency, master mode with respect to nominal CCLK. 100 100 100 MHz, Max FMCCKTOL Frequency Tolerance, master mode with respect to nominal CCLK. 50 50 50 % Boundary-Scan Port Timing Specifications TTAPTCK TMS and TDI Setup time before TCK 1.0 1.0 1.0 ns, Min TTCKTAP TMS and TDI Hold time after TCK 2.0 2.0 2.0 ns, Min TTCKTDO TCK falling edge to TDO output valid 6 6 6 ns, Max DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 43 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 44: Configuration Switching Characteristics (Continued) Speed Grade Symbol Description -3 -2 -1 Units FTCK Maximum configuration TCK clock frequency 66 66 66 MHz, Max FTCKB Maximum boundary-scan TCK clock frequency 66 66 66 MHz, Max BPI Master Flash Mode Programming Switching TBPICCO(4) ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs valid after CCLK rising edge 10 10 10 ns TBPIDCC/TBPICCD Setup/Hold on D[15:0] data input pins 3.0 0.5 3.0 0.5 3.0 0.5 ns TINITADDR Minimum period of initial ADDR[25:0] address cycles 3.0 3.0 3.0 CCLK cycles SPI Master Flash Mode Programming Switching TSPIDCC/TSPIDCCD DIN Setup/Hold before/after the rising CCLK edge 4.0 0.0 4.0 0.0 4.0 0.0 ns TSPICCM MOSI clock to out 10 10 10 ns TSPICCFC FCS_B clock to out 10 10 10 ns TFSINIT/TFSINITH FS[2:0] to INIT_B rising edge Setup and Hold 2 2 2 s CCLK Output (Master Modes) TMCCKL Master CCLK clock minimum Low time 3.0 3.0 3.0 ns, Min TMCCKH Master CCLK clock minimum High time 3.0 3.0 3.0 ns, Min TSCCKL Slave CCLK clock minimum Low time 2.0 2.0 2.0 ns, Min TSCCKH Slave CCLK clock minimum High time 2.0 2.0 2.0 ns, Min CCLK Input (Slave Modes) Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK FDCK Maximum frequency for DCLK 500 450 400 MHz TDMCCK_DADDR/TDMCKC_DADDR DADDR Setup/Hold 1.2 0.0 1.35 0.0 1.56 0.0 ns TDMCCK_DI/TDMCKC_DI DI Setup/Hold 1.2 0.0 1.35 0.0 1.56 0.0 ns TDMCCK_DEN/TDMCKC_DEN DEN Setup/Hold time 1.2 0.0 1.35 0.0 1.56 0.0 ns TDMCCK_DWE/TDMCKC_DWE DWE Setup/Hold time 1.2 0.0 1.35 0.0 1.56 0.0 ns TDMCKO_DO CLK to out of DO(3) 1.0 1.12 1.3 ns TDMCKO_DRDY/TDMCKCO_DRDY CLK to out of DRDY 1.0 1.12 1.3 ns Notes: 1. Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages. 2. To support longer delays in configuration, use the design solutions described in UG190: Virtex-5 User Guide. 3. DO will hold until next DRP operation. 4. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 44 R Virtex-5 Data Sheet: DC and Switching Characteristics Clock Buffers and Networks Table 45: Global Clock Switching Characteristics (Including BUFGCTRL) Speed Grade Symbol Description -3 -2 -1 Units TBCCCK_CE/TBCCKC_CE(1) CE pins Setup/Hold 0.27 0.00 0.27 0.00 0.31 0.00 ns TBCCCK_S/TBCCKC_S(1) S pins Setup/Hold 0.27 0.00 0.27 0.00 0.31 0.00 ns TBCCKO_O BUFGCTRL delay from I0/I1 to O 0.19 0.22 0.25 ns TBGCKO_O BUFG delay from I0 to O 0.19 0.22 0.25 ns FMAX Global clock tree (BUFG) for LX30, LX30T, LX50, LX50T, LX85, LX85T, LX110, LX110T, SX35T, and SX50T devices 710 650 600 MHz FMAX Global clock tree (BUFG) for LX220, LX220T, LX330, LX330T, and SX95T devices N/A 500 450 MHz Maximum Frequency Notes: 1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. Table 46: Input/Output Clock Switching Characteristics (BUFIO) Speed Grade Symbol TBUFIOCKO_O Description -3 -2 -1 Units Clock to out delay from I to O 1.08 1.16 1.29 ns I/O clock tree (BUFIO) 710 710 644 MHz Maximum Frequency FMAX Table 47: Regional Clock Switching Characteristics (BUFR) Speed Grade Symbol Description -3 -2 -1 Units TBRCKO_O Clock to out delay from I to O 0.56 0.59 0.67 ns TBRCKO_O_BYP Clock to out delay from I to O with Divide Bypass attribute set 0.23 0.24 0.26 ns TBRDO_CLRO Propagation delay from CLR to O 0.61 0.70 0.82 ns Regional clock tree (BUFR) 300 250 250 MHz Maximum Frequency FMAX DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 45 R Virtex-5 Data Sheet: DC and Switching Characteristics PLL Specification Table 48: PLL Specification Speed Grade Symbol Description -3 -2 -1 Units FINMAX Maximum Input Clock Frequency 710 710 645 MHz FINMIN Minimum Input Clock Frequency 19 19 19 MHz FINJITTER Maximum Input Clock Period Jitter FINDUTY Allowable Input Duty Cycle: 19--49 MHz 25/75 % Allowable Input Duty Cycle: 50--199 MHz 30/70 % Allowable Input Duty Cycle: 200--399 MHz 35/65 % Allowable Input Duty Cycle: 400--499 MHz 40/60 % Allowable Input Duty Cycle: >500 MHz 45/55 % <20% of clock input period or 1 ns Max FVCOMIN Minimum PLL VCO Frequency 400 400 400 MHz FVCOMAX Maximum PLL VCO Frequency 1440 1200 1000 MHz FBANDWIDTH Low PLL Bandwidth at Typical 1 1 1 MHz High PLL Bandwidth at Typical 4 4 4 MHz 120 120 120 ps TSTAPHAOFFSET Static Phase Offset of the PLL Outputs TOUTJITTER PLL Output Jitter(1) TOUTDUTY PLL Output Clock Duty Cycle Precision(2) Note 1 Time(4) 150 200 200 ps 100 100 100 s TLOCKMAX PLL Maximum Lock FOUTMAX PLL Maximum Output Frequency for LX30, LX30T, LX50, LX50T, LX85, LX85T, LX110, LX110T, SX35T, and SX50T devices 710 650 600 MHz PLL Maximum Output Frequency for LX220, LX220T, LX330, LX330T, and SX95T devices N/A 500 450 MHz 3.125 3.125 3.125 MHz FOUTMIN PLL Minimum Output Frequency(3) TEXTFDVAR External Clock Feedback Variation RSTMINPULSE Minimum Reset Pulse Width FPFDMAX <20% of clock input period or 1 ns Max 5 5 5 ns Maximum Frequency at the Phase Frequency Detector 550 500 450 MHz FPFDMIN Minimum Frequency at the Phase Frequency Detector 19 19 19 MHz TFBDELAY Maximum Delay in the Feedback Path 3 ns Max or one CLKIN cycle Notes: 1. Values for this parameter are available in the Architecture Wizard. 2. Includes global clock buffer. 3. Calculated as FVCO/128 assuming output duty cycle is 50%. 4. The LOCK signal must be sampled after TLOCKMAX. The LOCK signal is invalid after configuration or reset until the TLOCKMAX time has expired. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 46 R Virtex-5 Data Sheet: DC and Switching Characteristics DCM Switching Characteristics Table 49: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode Speed Grade Symbol Description -3 -2 -1 Units 32.00 32.00 32.00 MHz 150.00 135.00 120.00 MHz 64.00 64.00 64.00 MHz 300.00 270.00 240.00 MHz 2.0 2.0 2.0 MHz 100.00 90.00 80.00 MHz 32.00 32.00 32.00 MHz 180.00 160.00 140.00 MHz 32.00 32.00 32.00 MHz 150.00 135.00 120.00 MHz 1.00 1.00 1.00 MHz 180.00 160.00 140.00 MHz 1.00 1.00 1.00 KHz 550.00 500.00 450.00 MHz 120.00 120.00 120.00 MHz 550.00 500.00 450.00 MHz 240.00 240.00 240.00 MHz 550.00 500.00 450.00 MHz 7.5 7.5 7.5 MHz 366.67 333.34 300.00 MHz 140.00 140.00 140.00 MHz 400.00 375.00 350.00 MHz 120.00 120.00 120.00 MHz 550.00 500.00 450.00 MHz 25.00 25.00 25.00 MHz 400.00 375.00 350.00 MHz 1.00 1.00 1.00 KHz 550.00 500.00 450.00 MHz Outputs Clocks (Low Frequency Mode) F1XLFMSMIN CLK0, CLK90, CLK180, CLK270 F1XLFMSMAX F2XLFMSMIN CLK2X, CLK2X180 F2XLFMSMAX FDVLFMSMIN CLKDV FDVLFMSMAX FFXLFMSMIN CLKFX, CLKFX180 FFXLFMSMAX Input Clocks (Low Frequency Mode) FDLLLFMSMIN CLKIN (using DLL outputs)(1, 3, 4) FDLLLFMSMAX FCLKINLFFXMSMIN CLKIN (using DFS outputs only)(2, 3, 4) FCLKINLFFXMSMAX FPSCLKLFMSMIN PSCLK FPSCLKLFMSMAX Outputs Clocks (High Frequency Mode) F1XHFMSMIN CLK0, CLK90, CLK180, CLK270 F1XHFMSMAX F2XHFMSMIN CLK2X, CLK2X180 F2XHFMSMAX FDVHFMSMIN CLKDV FDVHFMSMAX FFXHFMSMIN CLKFX, CLKFX180 FFXHFMSMAX Input Clocks (High Frequency Mode) FDLLHFMSMIN CLKIN (using DLL outputs)(1, 3, 4) FDLLHFMSMAX FCLKINHFFXMSMIN CLKIN (using DFS outputs only)(2, 3, 4) FCLKINHFFXMSMAX FPSCLKHFMSMIN PSCLK FPSCLKHFMSMAX Notes: 1. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input frequency. 4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55 to 55/45). DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 47 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 50: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode Speed Grade Symbol Description -3 -2 -1 Units 19.00 19.00 19.00 MHz 32.00 32.00 32.00 MHz 38.00 38.00 38.00 MHz 64.00 64.00 64.00 MHz 1.19 1.19 1.19 MHz 21.34 21.34 21.34 MHz 19.00 19.00 19.00 MHz 40.00 40.00 40.00 MHz 19.00 19.00 19.00 MHz 32.00 32.00 32.00 MHz 1.00 1.00 1.00 MHz 40.00 40.00 40.00 MHz 1.00 1.00 1.00 KHz 300.00 270.00 240.00 MHz Outputs Clocks (Low Frequency Mode) F1XMRMIN CLK0, CLK90, CLK180, CLK270 F1XMRMAX F2XMRMIN CLK2X, CLK2X180 F2XMRMAX FDLLMRMIN CLKDV FDLLMRMAX FFXMRMIN CLKFX, CLKFX180 FFXMRMAX Input Clocks (Low Frequency Mode) FCLKINDLLMRMIN CLKIN (using DLL outputs)(1, 3, 4) FCLKINDLLMRMAX FCLKINFXMRMIN CLKIN (using DFS outputs only)(2, 3, 4) FCLKINFXMRMAX FPSCLKMRMIN PSCLK FPSCLKMRMAX Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input frequency. 4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55 to 55/45). DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 48 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 51: Input Clock Tolerances Symbol Description Frequency Range Value Units < 1 MHz 25 - 75 % 1 - 50 MHz 25 - 75 % 50 - 100 MHz 30 - 70 % 100 - 200 MHz 40 - 60 % 200 - 400 MHz(4) 45 - 55 % > 400 MHz 45 - 55 % Duty Cycle Input Tolerance (in %) TDUTYCYCRANGE_1 PSCLK only TDUTYCYCRANGE_1_50 TDUTYCYCRANGE_50_100 TDUTYCYCRANGE_100_200 PSCLK and CLKIN TDUTYCYCRANGE_200_400 TDUTYCYCRANGE_400 Speed Grade Input Clock Cycle-Cycle Jitter (Low Frequency Mode) -3 -2 -1 Units CLKIN (using DLL outputs)(1) 300.00 300.00 345.00 ps outputs)(2) 300.00 300.00 345.00 ps TCYCHFDLL CLKIN (using DLL outputs)(1) 150.00 150.00 173.00 ps TCYCHFFX CLKIN (using DFS outputs)(2) 150.00 150.00 173.00 ps TPERLFDLL CLKIN (using DLL outputs)(1) 1.00 1.00 1.15 ns TPERLFFX CLKIN (using DFS outputs)(2) 1.00 1.00 1.15 ns CLKIN (using DLL outputs)(1) 1.00 1.00 1.15 ns outputs)(2) 1.00 1.00 1.15 ns 1.00 1.00 1.15 ns TCYCLFDLL TCYCLFFX CLKIN (using DFS Input Clock Cycle-Cycle Jitter (High Frequency Mode) Input Clock Period Jitter (Low Frequency Mode) Input Clock Period Jitter (High Frequency Mode) TPERHFDLL TPERHFFX CLKIN (using DFS Feedback Clock Path Delay Variation TCLKFB_DELAY_VAR CLKFB off-chip feedback Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. If both DLL and DFS outputs are used, follow the more restrictive specifications. 4. This duty cycle specification does not apply to the GTP_DUAL to DCM connection. The GTP transceivers drive the DCMs at the following frequencies: 320 MHz for -1 speed grade devices, 375 MHz for -2 speed grade devices, or 375 MHz for -3 speed grade devices. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 49 R Virtex-5 Data Sheet: DC and Switching Characteristics Output Clock Jitter Table 52: Output Clock Jitter Speed Grade Symbol Description Constraints -3 -2 -1 Units Clock Synthesis Period Jitter TPERJITT_0 CLK0 120 120 120 ps TPERJITT_90 CLK90 120 120 120 ps TPERJITT_180 CLK180 120 120 120 ps TPERJITT_270 CLK270 120 120 120 ps TPERJITT_2X CLK2X, CLK2X180 200 200 230 ps TPERJITT_DV1 CLKDV (integer division) 150 150 180 ps TPERJITT_DV2 CLKDV (non-integer division) 300 300 345 ps TPERJITT_FX CLKFX, CLKFX180 Note 1 Note 1 Note 1 ps Notes: 1. Values for this parameter are available in the Architecture Wizard. Output Clock Phase Alignment Table 53: Output Clock Phase Alignment Speed Grade Symbol Description Constraints Units -3 -2 -1 50 50 60 ps Phase Offset Between CLKIN and CLKFB TIN_FB_OFFSET CLKIN/CLKFB Phase Offset Between Any DCM Outputs(4) TOUT_OFFSET_1X CLK0, CLK90, CLK180, CLK270 140 140 160 ps TOUT_OFFSET_2X CLK2X, CLK2X180, CLKDV 150 150 200 ps TOUT_OFFSET_FX CLKFX, CLKFX180 160 160 220 ps TDUTY_CYC_DLL(3) DLL outputs(1) 150 150 180 ps TDUTY_CYC_FX DFS outputs(2) 150 150 180 ps Duty Cycle Precision Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. 3. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION = TRUE. 4. All phase offsets are in respect to group CLK1X. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 50 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 54: Miscellaneous Timing Parameters Speed Grade Symbol Description -3 -2 -1 Units Time Required to Achieve LOCK TDLL_240 DLL output - Frequency range > 240 MHz (1) 80.00 80.00 80.00 s TDLL_120_240 DLL output - Frequency range 120 - 240 MHz (1) 250.00 250.00 250.00 s TDLL_60_120 DLL output - Frequency range 60 - 120 MHz (1) 900.00 900.00 900.00 s DLL output - Frequency range 50 - 60 MHz(1) 1300.00 1300.00 1300.00 s TDLL_40_50 DLL output - Frequency range 40 - 50 MHz (1) 2000.00 2000.00 2000.00 s TDLL_30_40 DLL output - Frequency range 30 - 40 MHz (1) 3600.00 3600.00 3600.00 s TDLL_24_30 DLL output - Frequency range 24 - 30 MHz(1) 5000.00 5000.00 5000.00 s TDLL_30 DLL output - Frequency range < 30 MHz (1) 5000.00 5000.00 5000.00 s 10.00 10.00 10.00 ms 10.00 10.00 10.00 ms Multiplication factor for DLL lock time with Fine Shift 2.00 2.00 2.00 TRANGE_MS Absolute shifting range in maximum speed mode 7.00 7.00 7.00 ns TRANGE_MR Absolute shifting range in maximum range mode 10.00 10.00 10.00 ns TTAP_MS_MIN Tap delay resolution (Min) in maximum speed mode 7.00 7.00 7.00 ps TTAP_MS_MAX Tap delay resolution (Max) in maximum speed mode 30.00 30.00 30.00 ps TTAP_MR_MIN Tap delay resolution (Min) in maximum range mode 10.00 10.00 10.00 ps TTAP_MR_MAX Tap delay resolution (Max) in maximum range mode 40.00 40.00 40.00 ps TDLL_50_60 TFX_MIN DFS outputs(2) TFX_MAX TDLL_FINE_SHIFT Fine Phase Shifting Delay Lines Notes: 1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. 2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. Table 55: Frequency Synthesis Attribute Min Max CLKFX_MULTIPLY 2 33 CLKFX_DIVIDE 1 32 Table 56: DCM Switching Characteristics Symbol Description Speed Grade -3 -2 -1 Units TDMCCK_PSEN/ TDMCKC_PSEN PSEN Setup/Hold 1.20 0.00 1.35 0.00 1.56 0.00 ns TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC PSINCDEC Setup/Hold 1.20 0.00 1.35 0.00 1.56 0.00 ns TDMCKO_PSDONE Clock to out of PSDONE 1.00 1.12 1.30 ns DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 51 R Virtex-5 Data Sheet: DC and Switching Characteristics Virtex-5 Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 57. Values are expressed in nanoseconds unless otherwise noted. Table 57: Global Clock Input to Output Delay Without DCM or PLL Symbol Description Device Speed Grade -3 -2 -1 Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL TICKOF Global Clock and OUTFF without DCM or PLL XC5VLX30 5.54 6.04 6.73 ns XC5VLX30T 5.54 6.04 6.73 ns XC5VLX50 5.59 6.09 6.79 ns XC5VLX50T 5.59 6.09 6.79 ns XC5VLX85 5.78 6.28 6.99 ns XC5VLX85T 5.78 6.28 6.99 ns XC5VLX110 5.84 6.35 7.06 ns XC5VLX110T 5.84 6.35 7.06 ns XC5VLX220 N/A 6.99 7.71 ns XC5VLX220T N/A 6.99 7.71 ns XC5VLX330 N/A 7.17 7.91 ns XC5VLX330T N/A 7.17 7.91 ns XC5VSX35T 5.72 6.22 6.92 ns XC5VSX50T 5.77 6.27 6.97 ns XC5VSX95T N/A 6.59 7.30 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 52 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 58: Global Clock Input to Output Delay With DCM in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode. TICKOFDCM Global Clock and OUTFF with DCM XC5VLX30 2.33 2.56 2.93 ns XC5VLX30T 2.33 2.56 2.93 ns XC5VLX50 2.35 2.58 2.95 ns XC5VLX50T 2.35 2.58 2.95 ns XC5VLX85 2.41 2.63 3.00 ns XC5VLX85T 2.41 2.63 3.00 ns XC5VLX110 2.46 2.69 3.06 ns XC5VLX110T 2.46 2.69 3.06 ns XC5VLX220 N/A 2.83 3.18 ns XC5VLX220T N/A 2.83 3.18 ns XC5VLX330 N/A 3.00 3.37 ns XC5VLX330T N/A 3.00 3.37 ns XC5VSX35T 2.44 2.67 3.03 ns XC5VSX50T 2.46 2.69 3.05 ns XC5VSX95T N/A 2.64 3.00 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 53 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 59: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode. TICKOFDCM_0 Global Clock and OUTFF with DCM XC5VLX30 3.45 3.71 4.15 ns XC5VLX30T 3.45 3.71 4.15 ns XC5VLX50 3.47 3.73 4.17 ns XC5VLX50T 3.47 3.73 4.17 ns XC5VLX85 3.60 3.86 4.29 ns XC5VLX85T 3.60 3.86 4.29 ns XC5VLX110 3.65 3.92 4.36 ns XC5VLX110T 3.65 3.92 4.36 ns XC5VLX220 N/A 4.41 4.85 ns XC5VLX220T N/A 4.41 4.85 ns XC5VLX330 N/A 4.58 5.04 ns XC5VLX330T N/A 4.58 5.04 ns XC5VSX35T 3.63 3.89 4.33 ns XC5VSX50T 3.65 3.91 4.35 ns XC5VSX95T N/A 4.16 4.59 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 54 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 60: Global Clock Input to Output Delay With PLL in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in System-Synchronous Mode. TICKOFPLL Global Clock and OUTFF with PLL XC5VLX30 2.03 2.12 2.41 ns XC5VLX30T 2.03 2.12 2.41 ns XC5VLX50 2.05 2.14 2.43 ns XC5VLX50T 2.05 2.14 2.43 ns XC5VLX85 2.10 2.18 2.47 ns XC5VLX85T 2.10 2.18 2.47 ns XC5VLX110 2.16 2.24 2.54 ns XC5VLX110T 2.16 2.24 2.54 ns XC5VLX220 N/A 2.58 2.86 ns XC5VLX220T N/A 2.58 2.86 ns XC5VLX330 N/A 2.75 3.05 ns XC5VLX330T N/A 2.75 3.05 ns XC5VSX35T 2.14 2.22 2.51 ns XC5VSX50T 2.16 2.24 2.53 ns XC5VSX95T N/A 2.32 2.60 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is included in the timing calculation. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 55 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 61: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode. TICKOFPLL_0 Global Clock and OUTFF with PLL XC5VLX30 3.98 4.33 4.82 ns XC5VLX30T 3.98 4.33 4.82 ns XC5VLX50 4.01 4.35 4.84 ns XC5VLX50T 4.01 4.35 4.84 ns XC5VLX85 4.13 4.47 4.96 ns XC5VLX85T 4.13 4.47 4.96 ns XC5VLX110 4.19 4.53 5.03 ns XC5VLX110T 4.19 4.53 5.03 ns XC5VLX220 N/A 5.03 5.53 ns XC5VLX220T N/A 5.03 5.53 ns XC5VLX330 N/A 5.20 5.71 ns XC5VLX330T N/A 5.20 5.71 ns XC5VSX35T 4.16 4.51 5.00 ns XC5VSX50T 4.19 4.53 5.02 ns XC5VSX95T N/A 4.77 5.27 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is included in the timing calculation. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 56 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 62: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL in System-Synchronous Mode. TICKOFDCM_PLL Global Clock and OUTFF with DCM and PLL XC5VLX30 2.47 2.70 3.06 ns XC5VLX30T 2.47 2.70 3.06 ns XC5VLX50 2.49 2.72 3.08 ns XC5VLX50T 2.49 2.72 3.08 ns XC5VLX85 2.55 2.77 3.13 ns XC5VLX85T 2.55 2.77 3.13 ns XC5VLX110 2.60 2.83 3.19 ns XC5VLX110T 2.60 2.83 3.19 ns XC5VLX220 N/A 2.97 3.31 ns XC5VLX220T N/A 2.97 3.31 ns XC5VLX330 N/A 3.14 3.49 ns XC5VLX330T N/A 3.14 3.49 ns XC5VSX35T 2.58 2.81 3.16 ns XC5VSX50T 2.60 2.83 3.18 ns XC5VSX95T N/A 2.78 3.13 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM and PLL output jitter are already included in the timing calculation. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 57 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 63: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL in Source-Synchronous Mode. TICKOFDCM0_PLL Global Clock and OUTFF with DCM and PLL XC5VLX30 3.59 3.85 4.27 ns XC5VLX30T 3.59 3.85 4.27 ns XC5VLX50 3.61 3.87 4.29 ns XC5VLX50T 3.61 3.87 4.29 ns XC5VLX85 3.74 4.00 4.42 ns XC5VLX85T 3.74 4.00 4.42 ns XC5VLX110 3.79 4.06 4.48 ns XC5VLX110T 3.79 4.06 4.48 ns XC5VLX220 N/A 4.55 4.98 ns XC5VLX220T N/A 4.55 4.98 ns XC5VLX330 N/A 4.72 5.17 ns XC5VLX330T N/A 4.72 5.17 ns XC5VSX35T 3.77 4.03 4.45 ns XC5VSX50T 3.79 4.05 4.48 ns XC5VSX95T N/A 4.30 4.72 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM and PLL output jitter are already included in the timing calculation. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 58 R Virtex-5 Data Sheet: DC and Switching Characteristics Virtex-5 Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 65. Values are expressed in nanoseconds unless otherwise noted. Table 64: Global Clock Setup and Hold Without DCM or PLL Symbol Description Device Speed Grade -3 -2 -1 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay) Global Clock and IFF(2) without DCM or PLL XC5VLX30 1.49 -0.35 1.60 -0.35 1.77 -0.35 ns XC5VLX30T 1.49 -0.35 1.60 -0.35 1.76 -0.35 ns XC5VLX50 1.48 -0.30 1.59 -0.30 1.76 -0.30 ns XC5VLX50T 1.48 -0.30 1.59 -0.30 1.76 -0.30 ns XC5VLX85 1.75 -0.49 1.89 -0.49 2.09 -0.49 ns XC5VLX85T 1.75 -0.49 1.89 -0.49 2.09 -0.49 ns XC5VLX110 1.74 -0.43 1.88 -0.43 2.09 -0.43 ns XC5VLX110T 1.73 -0.43 1.88 -0.43 2.09 -0.43 ns XC5VLX220 N/A 2.57 -0.74 2.86 -0.74 ns XC5VLX220T N/A 2.57 -0.74 2.86 -0.74 ns XC5VLX330 N/A 2.55 -0.56 2.85 -0.56 ns XC5VLX330T N/A 2.57 -0.56 2.86 -0.56 ns XC5VSX35T 1.47 -0.16 1.59 -0.16 1.76 -0.16 ns XC5VSX50T 1.62 -0.31 1.74 -0.31 1.93 -0.31 ns XC5VSX95T N/A 2.10 -0.44 2.32 -0.44 ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input Flip-Flop or Latch 3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0" is listed, there is no positive hold time. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 59 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 65: Global Clock Setup and Hold With DCM in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCM/ TPHDCM No Delay Global Clock and IFF(2) with DCM in System-Synchronous Mode XC5VLX30 1.53 -0.50 1.70 -0.50 1.88 -0.50 ns XC5VLX30T 1.53 -0.50 1.70 -0.50 1.88 -0.50 ns XC5VLX50 1.52 -0.48 1.68 -0.48 1.86 -0.48 ns XC5VLX50T 1.52 -0.48 1.68 -0.48 1.86 -0.48 ns XC5VLX85 1.58 -0.43 1.76 -0.43 1.95 -0.43 ns XC5VLX85T 1.57 -0.43 1.76 -0.43 1.95 -0.43 ns XC5VLX110 1.58 -0.37 1.76 -0.37 1.95 -0.37 ns XC5VLX110T 1.58 -0.37 1.76 -0.37 1.95 -0.37 ns XC5VLX220 N/A 2.17 -0.27 2.44 -0.27 ns XC5VLX220T N/A 2.17 -0.27 2.44 -0.27 ns XC5VLX330 N/A 2.17 -0.10 2.44 -0.10 ns XC5VLX330T N/A 2.17 -0.10 2.44 -0.10 ns XC5VSX35T 1.60 -0.39 1.78 -0.39 1.98 -0.39 ns XC5VSX50T 1.58 -0.37 1.76 -0.37 1.95 -0.37 ns XC5VSX95T N/A 2.10 -0.41 2.35 -0.41 ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CLK0, DCM, and jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 60 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 66: Global Clock Setup and Hold With DCM in Source-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCM0/ TPHDCM0 No Delay Global Clock and IFF(2) with DCM in Source-Synchronous Mode XC5VLX30 0.27 0.62 0.27 0.62 0.27 0.66 ns XC5VLX30T 0.27 0.62 0.27 0.62 0.27 0.66 ns XC5VLX50 0.26 0.64 0.26 0.64 0.26 0.68 ns XC5VLX50T 0.25 0.64 0.26 0.64 0.26 0.68 ns XC5VLX85 0.23 0.76 0.24 0.76 0.24 0.80 ns XC5VLX85T 0.23 0.76 0.24 0.76 0.24 0.80 ns XC5VLX110 0.23 0.82 0.24 0.82 0.24 0.87 ns XC5VLX110T 0.23 0.82 0.24 0.82 0.24 0.87 ns XC5VLX220 N/A 0.21 1.31 0.22 1.36 ns XC5VLX220T N/A 0.21 1.31 0.22 1.36 ns XC5VLX330 N/A 0.21 1.48 0.22 1.55 ns XC5VLX330T N/A 0.21 1.48 0.22 1.55 ns XC5VSX35T 0.25 0.80 0.27 0.80 0.27 0.84 ns XC5VSX50T 0.24 0.82 0.25 0.82 0.25 0.86 ns XC5VSX95T N/A 0.24 1.06 0.24 1.11 ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CLK0, DCM, and jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 61 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 67: Global Clock Setup and Hold With PLL in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSPLL/ TPHPLL No Delay Global Clock and IFF(2) with PLL in System-Synchronous Mode XC5VLX30 1.51 -0.81 1.67 -0.81 1.91 -0.81 ns XC5VLX30T 1.51 -0.81 1.67 -0.81 1.91 -0.81 ns XC5VLX50 1.49 -0.79 1.65 -0.79 1.88 -0.79 ns XC5VLX50T 1.49 -0.79 1.65 -0.79 1.88 -0.79 ns XC5VLX85 1.52 -0.74 1.70 -0.74 1.95 -0.74 ns XC5VLX85T 1.52 -0.74 1.70 -0.74 1.95 -0.74 ns XC5VLX110 1.51 -0.68 1.69 -0.68 1.95 -0.68 ns XC5VLX110T 1.51 -0.68 1.69 -0.68 1.95 -0.68 ns XC5VLX220 N/A 1.77 -0.52 2.08 -0.52 ns XC5VLX220T N/A 1.77 -0.52 2.08 -0.52 ns XC5VLX330 N/A 1.75 -0.35 2.07 -0.35 ns XC5VLX330T N/A 1.77 -0.35 2.08 -0.35 ns XC5VSX35T 1.56 -0.70 1.73 -0.70 1.98 -0.70 ns XC5VSX50T 1.54 -0.68 1.71 -0.68 1.96 -0.68 ns XC5VSX95T N/A 1.83 -0.58 2.11 -0.58 ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CLKOUT0, PLL, and jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 62 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 68: Global Clock Setup and Hold With PLL in Source-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSPLL0/ TPHPLL0 No Delay Global Clock and IFF(2) with PLL in Source-Synchronous Mode XC5VLX30 -0.21 1.15 -0.21 1.23 -0.21 1.33 ns XC5VLX30T -0.21 1.15 -0.21 1.23 -0.21 1.33 ns XC5VLX50 -0.22 1.17 -0.22 1.25 -0.22 1.35 ns XC5VLX50T -0.22 1.17 -0.22 1.25 -0.22 1.35 ns XC5VLX85 -0.24 1.29 -0.24 1.37 -0.24 1.48 ns XC5VLX85T -0.24 1.29 -0.24 1.37 -0.24 1.48 ns XC5VLX110 -0.24 1.35 -0.24 1.43 -0.24 1.54 ns XC5VLX110T -0.24 1.35 -0.24 1.43 -0.24 1.54 ns XC5VLX220 N/A -0.31 1.93 -0.31 2.04 ns XC5VLX220T N/A -0.32 1.93 -0.32 2.04 ns XC5VLX330 N/A -0.31 2.10 -0.31 2.22 ns XC5VLX330T N/A -0.32 2.10 -0.32 2.22 ns XC5VSX35T -0.22 1.33 -0.22 1.41 -0.22 1.51 ns XC5VSX50T -0.24 1.35 -0.24 1.43 -0.24 1.53 ns XC5VSX95T N/A -0.26 1.67 -0.26 1.78 ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CLKOUT0, PLL, and jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 63 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 69: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode Symbol Description Device Speed Grade -3 -2 -1 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCMPLL/ TPHDCMPLL No Delay Global Clock and IFF(2) with DCM and PLL in System-Synchronous Mode XC5VLX30 1.66 -0.37 1.83 -0.37 2.00 -0.37 ns XC5VLX30T 1.65 -0.37 1.83 -0.37 2.00 -0.37 ns XC5VLX50 1.63 -0.34 1.80 -0.34 1.98 -0.34 ns XC5VLX50T 1.63 -0.34 1.80 -0.34 1.98 -0.34 ns XC5VLX85 1.68 -0.29 1.87 -0.29 2.07 -0.29 ns XC5VLX85T 1.68 -0.29 1.87 -0.29 2.07 -0.29 ns XC5VLX110 1.67 -0.23 1.87 -0.23 2.07 -0.23 ns XC5VLX110T 1.66 -0.23 1.86 -0.23 2.06 -0.23 ns XC5VLX220 N/A 2.26 -0.13 2.55 -0.13 ns XC5VLX220T N/A 2.25 -0.13 2.55 -0.13 ns XC5VLX330 N/A 2.23 0.04 2.53 0.04 ns XC5VLX330T N/A 2.25 0.04 2.54 0.04 ns XC5VSX35T 1.72 -0.26 1.91 -0.26 2.10 -0.26 ns XC5VSX50T 1.70 -0.23 1.88 -0.23 2.07 -0.23 ns XC5VSX95T N/A 2.22 -0.27 2.47 -0.27 ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CLK0, DCM, CLKOUT0, PLL, and jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 64 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 70: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode Speed Grade Symbol Description Device -3 -2 -1 Units Example Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin,(1) Using DCM, PLL, and Global Clock Buffer. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in IOB Switching Characteristics, page 23. TPSDCMPLL_0/ TPHDCMPLL_0 No Delay Global Clock and IFF (2) with DCM and PLL in Source-Synchronous Mode XC5VLX30 0.39 0.75 0.40 0.75 0.40 0.79 ns XC5VLX30T 0.39 0.75 0.40 0.75 0.40 0.79 ns XC5VLX50 0.37 0.78 0.38 0.78 0.38 0.81 ns XC5VLX50T 0.37 0.78 0.38 0.78 0.38 0.81 ns XC5VLX85 0.34 0.90 0.36 0.90 0.36 0.93 ns XC5VLX85T 0.33 0.90 0.36 0.90 0.36 0.93 ns XC5VLX110 0.32 0.96 0.35 0.96 0.35 1.00 ns XC5VLX110T 0.32 0.96 0.35 0.96 0.35 1.00 ns XC5VLX220 N/A 0.30 1.45 0.32 1.49 ns XC5VLX220T N/A 0.30 1.45 0.32 1.49 ns XC5VLX330 N/A 0.28 1.62 0.31 1.68 ns XC5VLX330T N/A 0.30 1.62 0.32 1.68 ns XC5VSX35T 0.38 0.93 0.39 0.93 0.39 0.97 ns XC5VSX50T 0.35 0.96 0.37 0.96 0.37 0.99 ns XC5VSX95T N/A 0.35 1.20 0.35 1.24 ns Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CLK0, DCM, CLKOUT0, PLL, and jitter. Package skew is not included in these measurements. 2. IFF = Input Flip-Flop DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 65 R Virtex-5 Data Sheet: DC and Switching Characteristics ChipSyncTM Source-Synchronous Switching Characteristics The parameters in this section provide the necessary values for calculating timing budgets for Virtex-5 source-synchronous transmitter and receiver data-valid windows. Table 71: Duty Cycle Distortion and Clock-Tree Skew Symbol Description Device TDCD_CLK Global Clock Tree Duty Cycle Distortion (1) TCKSKEW Global Clock Tree Skew (2) Speed Grade Units -3 -2 -1 0.12 0.12 0.12 ns XC5VLX30 0.21 0.22 0.22 ns XC5VLX30T 0.21 0.22 0.22 ns XC5VLX50 0.26 0.27 0.28 ns XC5VLX50T 0.26 0.27 0.28 ns XC5VLX85 0.42 0.43 0.45 ns XC5VLX85T 0.42 0.43 0.45 ns XC5VLX110 0.48 0.50 0.51 ns XC5VLX110T 0.48 0.50 0.51 ns XC5VLX220 N/A 1.07 1.10 ns XC5VLX220T N/A 1.07 1.10 ns XC5VLX330 N/A 1.25 1.29 ns XC5VLX330T N/A 1.25 1.29 ns XC5VSX35T 0.38 0.39 0.39 ns XC5VSX50T 0.43 0.44 0.45 ns XC5VSX95T N/A 0.72 0.74 ns All TDCD_BUFIO I/O clock tree duty cycle distortion All 0.10 0.10 0.10 ns TBUFIOSKEW I/O clock tree skew across one clock region All 0.07 0.07 0.08 ns TDCD_BUFR Regional clock tree duty cycle distortion All 0.25 0.25 0.25 ns Notes: 1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 66 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 72: Package Skew Symbol Description Device Package Value Units FF324 80 ps FF676 142 ps FF665 93 ps FF324 80 ps FF676 142 ps FF1153 175 ps FF665 93 ps FF1136 162 ps FF676 142 ps FF1153 174 ps FF1136 164 ps FF676 142 ps FF1153 173 ps FF1760 190 ps FF1136 163 ps FF1738 171 ps XC5VLX220 FF1760 178 ps XC5VLX220T FF1738 156 ps XC5VLX330 FF1760 177 ps XC5VLX330T FF1738 155 ps XC5VSX35T FF665 103 ps FF665 103 ps FF1136 157 ps FF1136 176 ps XC5VLX30 XC5VLX30T XC5VLX50 XC5VLX50T XC5VLX85 XC5VLX85T TPKGSKEW Package Skew(1) XC5VLX110 XC5VLX110T XC5VSX50T XC5VSX95T Notes: 1. These values represent the worst-case skew between any two SelectMap I/Os in the package: shortest flight time to longest flight time from Pad to Ball (7.0 ps per mm). 2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package. Table 73: Sample Window Symbol Description Device Speed Grade -3 -2 -1 Units TSAMP Sampling Error at Receiver Pins(1) All 450 500 550 ps TSAMP_BUFIO Sampling Error at Receiver Pins using BUFIO(2) All 350 400 450 ps Notes: 1. This parameter indicates the total sampling error of Virtex-5 DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 DCM jitter - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew. 2. This parameter indicates the total sampling error of Virtex-5 DDR input registers across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers' edges of operation. These measurements do not include package or clock tree skew. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 67 R Virtex-5 Data Sheet: DC and Switching Characteristics Table 74: ChipSync Pin-to-Pin Setup/Hold and Clock-to-Out Symbol Description Speed Grade Units -3 -2 -1 -0.56 1.59 -0.54 1.72 -0.54 1.91 ns 4.42 4.82 5.40 ns Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO TPSCS/TPHCS Setup/Hold of I/O clock Pin-to-Pin Clock-to-Out Using BUFIO TICKOFCS Clock-to-Out of I/O clock Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 68 R Virtex-5 Data Sheet: DC and Switching Characteristics Revision History The following table shows the revision history for this document. Date Version Revision 04/14/06 1.0 Initial Xilinx release. 05/12/06 1.1 * * First version posted to the Xilinx website. Minor typograpical edits. Revised design software version on page 21. Revised TIDELAYRESOLUTION in Table 38, page 35. Revised TDSPCKO in Table 43, page 40. Added register-to-register parameters to Table 26. 05/24/06 1.2 * * 08/04/06 1.3 * Added VDRINT, VDRI, and CIN values to Table 3. * * Added HSTL_I_12 and LVCMOS12 to Table 7 and renumbered the notes. Removed pin-to-pin performance (Table 12). Updated and added values to register-register performance Table 26 (was Table 13). Added values to Table 27. Updated the speed specification version above Table 28. Added to Table 30 the I/O standards: HSTL_II_T_DCI, HSTL_II_T_DCI_18, SSTL2_II_T_DCI, and SSTL18_II_T_DCI. Revised FMAX values in Table 42, and RDWR_B Setup/Hold values in Table 44. * * * * * 09/06/06 10/13/06 2.0 2.1 * In Table 48, changed FVCOMAX, removed TLOCKMIN, and revised TLOCKMAX values, also removed note pointing to Architecture Wizard. Removed Note 2 on Table 61. Added new sections for LXT devices and added LXT devices to the appropriate tables. The addition of the RocketIO GTP Transceiver Specifications required the tables to be renumbered. Changed maximum VIN values in Table 1 and Table 2. * Updated values and added Tj = 85C to Table 4, page 3. * * * Revised the cascade block RAM Memory, page 19 section in Table 26 to 64K with new I/O delays. Revised the setup and hold times in Table 34, page 31. Added FMAX_CASCADE to Table 42, page 38. * Revised FFXLFMSMAX and FCLKINLFFXMSMAX in Table 49, page 47. * * * * * * Added System Monitor parameters. Added XC5VLX85T to appropriate tables. Revised Table 16 including notes. Added Table 17, and Figure 3 and Figure 4. Added Table 19, page 14: RocketIO CRC block. Revised design software version and Table 28 on page 21. Updated ILOGIC Switching Characteristics, page 31 Updated FMAX_ECC in Table 42, page 38. * Changed hold times for TSMDCCK/ TSMCCKD and TBPIDCC/TBPICCD in Table 44, page 43. * Revised TFBDELAY, FOUTMIN, FOUTMAX, and FINJITTER Table 48, page 46. * Revised Table 49, page 47. * * DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 69 R Virtex-5 Data Sheet: DC and Switching Characteristics Date Version 01/05/07 2.2 02/02/07 3.0 Revision * Added IIN to Table 2. Added XC5VLX220T to appropriate tables. * * * * * * * Added LVDCI33, LVDCI25, LVDCI18, LVDCI15 to Table 7. Update the symbols in the GTP Transceiver Table 12, Table 13, and Table 14. Add values for -1 speed grade in Table 18, page 14. Added SFI-4.1 values to Table 27, page 20. Removed -3 speed grade from available LX220 device list in Table 28, page 21. Added maximum frequency to Table 46 and Table 47, page 45. In Table 49, page 47 changed the all the CLKDV, CLKFX, and CLKFX180 Min values and the CLKIN Min values in the Input Clocks (High Frequency Mode) section. Added values to Table 52 and Table 53, page 50. Added XC5VSX35T, XC5VSX50T, and SX5VSX95T devices to appropriate tables. Revised the IRPU values in Table 3, page 2. Revised the ICCAUXQ values in Table 4, page 3. Added values to Table 5, page 4. Minor added notes and changed descriptions in Table 13, page 9 and Table 14, page 9. Revised the SFI-4.1 (SDR LVDS Interface) -1 values in Table 27, page 20. Revised gain error, bipolar gain error, and event conversion time in Table 25, page 17 Changed the design software version that matches this datasheet above Table 28 on page 21. In Switching Characteristics, the following values are revised: - LVCMOS25, Fast, 12 mA in Table 30, page 23. - Setup and Hold and TICKQ in Table 34, page 31. - TOCKQ in Table 35, page 32. - Sequential delay values in Table 37, page 34. - TCXB, TCEO, and TDICK in Table 39, page 35. - TRCKO_DO, TRCKO_POINTERS, TRCKO_ECCR, TRCKO_ECC, TRCCK_ADDR, TRDCK_DI, TRDCK_DI_ECC, TRCCK_WREN, and TRCO_FLAGS in Table 42, page 38. - TDSPDCK_CC, TDSPCCK_{RSTAA, RSTBB}, TDSPCKO_{PP, CRYOUTP}, FMAX_MULT_NOMREG and FMAX_MULT_NOMREG_PATDET in Table 43, page 40. - TBCCKO_O, and TBGCKO_O in Table 45, page 45. - TBUFIOCKO_O and FMAX in Table 46, page 45. - TBRCKO_O and TBRCKO_O_BYP in Table 47, page 45. - Parameters in Table 48, page 46 including notes. In Virtex-5 Pin-to-Pin Output Parameter Guidelines: - Revised values in Table 57, Table 58, and Table 59. In Virtex-5 Pin-to-Pin Input Parameter Guidelines: - Clarified description in Table 64, page 59. - Revised values in Table 64, Table 65, and Table 66. - Removed duplicate TBUFR_MAX_FREQ and TBUFIO_MAX_FREQ from Table 71. Revised values in Table 74, page 68. * * * * * * * * * * * * * DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 70 R Virtex-5 Data Sheet: DC and Switching Characteristics Date Version 05/18/07 3.1 Revision * * * * * Added typical values for n and r in Table 3. Revised and added values to Table 4. Revised standard I/O levels in Table 7. Additions and updates to Table 14, Table 16, Table 17, Table 18, Table 19, Table 20, Table 21, Table 22, and Table 23. Added Ethernet MAC Switching Characteristics, page 16. Changed the design software version that matches this datasheet above Table 28 on page 21. Added new section: I/O Standard Adjustment Measurement Methodology, page 28. In Switching Characteristics, the following values are revised: - LVTTL, Slow and Fast, 2 mA, 4 mA, and 6 mA (Table 30). - LVCMOS33, Slow and Fast, 2 mA, 4 mA, and 6 mA (Table 30). - LVCMOS25, Slow and Fast, 2 mA and 4 mA, and Fast 12 mA (Table 30). - LVCMOS18, Slow and Fast, 2 mA, 4 mA, and 6 mA (Table 30). - LVCMOS15 and LVCMOS12, Slow and Fast, 2 mA (Table 30). - TIDOCK and TIDOCKD in Table 34. - Setup/Hold for Control Lines and Data Lines in Table 36. - Add TIDELAYPAT_JIT and revised TIDELAYRESOLUTION in Table 38, page 35 and added Notes 1 and 2. - Revised TRCK page 36 and removed TCKSR Table 39, page 35. - Replaced TTWC with TMCP symbol in Table 40, page 37. - Revised TCECK in Table 41. - Revised TRCKO_FLAGS and TRDCK_DI_ECC encode only in Table 42. - Revised Hold Times of Data/Control Pins to the Input Register Clock. Setup/Hold times of {PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK. Hold times of some of the CE pins. Hold times of some of the RST pins. Hold times of {A, B} input to {P, CARRYOUT} output using multiplier and {ACIN, BCIN} input to {P, CARRYOUT} output using multiplier, CLK (AREG, BREG) to {P, CARRYOUT} output using multiplier, in Table 43. - Updated and added values to Table 44, page 43. Revised -1 speed FMAX value in Table 46, page 45. * Added Note 4 to TLOCKMAX and revised FINDUTY, FINMAX,and FVCOMAX in Table 48, page 46. * Added values to Table 52 and Table 53. Changed TOUT_OFFSET in Table 53. * In Virtex-5 Pin-to-Pin Output Parameter Guidelines: - Revised values in Table 57 through Table 63. In Virtex-5 Pin-to-Pin Input Parameter Guidelines: - Revised values in Table 64 through Table 70. In ChipSyncTM Source-Synchronous Switching Characteristics: - Revised values in Table 71, page 66. - Added package skew values to Table 72, page 67. - Revised values in Table 74, page 68. * * * * * * DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 71 R Virtex-5 Data Sheet: DC and Switching Characteristics Date Version 06/15/07 3.2 Revision * Updated TSTG in Table 1. * Corrected VOH/VOL in Table 9 and Table 10, page 7. * Changed the design software version that matches this data sheet above Table 28 on page 21. Added "Production Silicon and ISE Software Status," page 22. Added TIODELAY_CLK_MAX and revised TCKSR in Table 38, page 35. * * * * * In Virtex-5 Pin-to-Pin Output Parameter Guidelines: Revised values in Table 58 through Table 63. In Virtex-5 Pin-to-Pin Input Parameter Guidelines: Revised values in Table 65 through Table 70. Corrected units to ns in Table 71, page 66. Added conditions to DVPPIN in Table 16, page 12. * Changed the FGTXMAX symbol name to FGTPMAX. * * * Updated GTP maximum line rates to 3.75 Gb/s in Table 18, page 14. Updated maximum frequencies in Table 21, page 15. Added 3.75 Gb/s condition and changed maximum value of FGTX in Table 22, page 15. * * * Added 3.75 Gb/s sinusoidal jitter specification and changed maximum value of FGRX in Table 23, page 16. Changed analog input common mode ranges in Table 25, page 17. Changed TPKGSKEW values in Table 72, page 67. * Added maximum value of IREF to Table 3, page 2. * * * Revised Table 28 and changed the design software version in Table 29 for production devices. In Table 38, page 35, added High Performance Mode to Note 2. In Table 44, page 43, revised description of TSMDCCK/TSMCCKD. * Added Note 4 to TDUTYCYCRANGE_200_400 frequency range in Table 51, page 49. * In Virtex-5 Pin-to-Pin Input Parameter Guidelines: Revised note 1 in Table 64 through Table 69. Added IBATT value and Note 2 to Table 3. * 06/26/07 07/26/07 09/27/07 3.3 3.4 3.5 * * * Added DRP Clock Frequency and Note 4 to Table 25. Revised the typical and maximum values and units for gain error and bipolar gain error. Removed unsupported XC5VSX95T -3 speed grade from Table 28 and Table 29. Removed unsupported I/O standards (LVDS_33, LVDSEXT_33, and ULVDS_25) from Table 25. Also updated LVDSEXT, 2.5V in Table 33. Added values to Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK in Table 44. In Virtex-5 Pin-to-Pin Input Parameter Guidelines: Revised note 1 in Table 64 through Table 70. Removed note 1 from Table 26, page 19. FMAX of clock is not an applicable limitation. * * * * * Revised DDR2 memory interface performance in Table 27, page 20. Revised Table 29 to add ISE 9.2i SP3 where applicable. Removed XC5VSX95T -3 speed grade support from applicable tables. Removed unsupported I/O standard (LVPECL_33) from Table 32 and added LVPECL_25. Added TSMCO and TSMCKBY to Table 44, page 43. * * * Revised note 3 in Table 49, page 47 and Table 50, page 48. Clarified notes in Table 60 to Table 63, and Table 67 to Table 70. Revised note 1 in Table 72. * * * * 11/05/07 3.6 DS202 (v3.6) November 5, 2007 Advance Product Specification www.xilinx.com 72