NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Feature CAS Latency Frequency -3C/3CI* -AC/ACI* -BE* -BD* (DDR2-667-CL5) (DDR2-800-CL5) (DDR2-1066-CL7) (DDR2-1066-CL6) Speed Bins Units Parameter Min. Max. Min. Max. Min. Max. Min. Max. tCK(Avg.) Clock Frequency 125 333 125 400 125 533 125 533 MHz tRCD 15 - 12.5 - 12.5 - 11.25 - ns tRP 15 - 12.5 - 12.5 - 11.25 - ns tRC 60 - 57.5 - 57.5 - 56.25 - ns tRAS 40 70K 40 70K 40 70K 40 70K ns tCK(Avg.)@CL3 5 8 5 8 5 8 5 8 ns tCK(Avg.)@CL4 3.75 8 3.75 8 3.75 8 3.75 8 ns tCK(Avg.)@CL5 3 8 2.5 8 2.5 8 2.5 8 ns tCK(Avg.)@CL6 - - 2.5 8 2.5 8 1.875 8 ns tCK(Avg.)@CL7 - - - - 1.875 8 1.875 8 ns *The timing specification of high speed bin is backward compatible with low speed bin 1.8V 0.1V Power Supply Voltage 4 internal memory banks Programmable CAS Latency: Data-Strobes: Bidirectional, Differential Support Industrial grade temperature -40~95 Operating Temperature (-3CI/-ACI) 3, 4, 5 (-3C/-3CI/-AC/-ACI/-BD/-BE) 6 (-AC/-ACI/-BD/-BE) 1KB page size for x8 2KB page size for x16 7 (-BD/-BE) Strong and Weak Strength Data-Output Driver Programmable Additive Latency: 0, 1, 2, 3, 4 5 Auto-Refresh and Self-Refresh Write Latency = Read Latency -1 Power Saving Power-Down modes Programmable Burst Length: 7.8 s max. Average Periodic Refresh Interval 4 and 8 Programmable Sequential / Interleave Burst RoHS Compliance and Halogen Free OCD (Off-Chip Driver Impedance Adjustment) Packages: ODT (On-Die Termination) 4 bit prefetch architecture 60-Ball BGA for x8 components 84-Ball BGA for x16 components 1 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Description The 512Mbit Double-Data-Rate-2 (DDR2) DRAMs is a high-speed CMOS Double Data Rate 2 SDRAM containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The 512Mb chip is organized as 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1066 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance adjustment and (5) an ODT (On-Die Termination) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. A 14 bit address bus for x8 organized components and A 13 bit address bus for x16 component is used to convey row, column, and bank address devices. These devices operate with a single 1.8V 0.1V power supply and are available in BGA packages. 2 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Pin Configuration - 60 balls BGA Package (x8) < TOP View> See the balls through the package X8 1 2 3 7 8 9 VDD NU,/RDQS VSS A VSSQ DQS VDDQ DQ6 VSSQ DM/RDQS B DQS VSSQ DQ7 VDDQ DQ1 VDDQ C VDDQ DQ0 VDDQ DQ4 VSSQ DQ3 D DQ2 VSSQ DQ5 VDDL VREF VSS E VSSDL CK VDD CKE WE F RAS CK ODT BA0 BA 1 G CAS CS A10/ AP A1 H A2 A0 A3 A5 J A6 A4 A7 A9 K A11 A8 A12 NC L NC A13 NC VSS VDD VDD VSS 3 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Pin Configuration - 84 balls BGA Package (x16) < TOP View> See the balls through the package x 16 1 2 3 7 8 9 VDD NC VSS A VSSQ UDQS VDDQ DQ14 VSSQ UDM B UDQS VSSQ DQ15 VDDQ DQ9 VDDQ C VDDQ DQ8 VDDQ DQ12 VSSQ DQ11 D DQ10 VSSQ DQ13 VDD NC VSS E VSSQ LDQS VDDQ DQ6 VSSQ LDM F LDQS VSSQ DQ7 VDDQ DQ1 VDDQ G VDDQ DQ0 VDDQ DQ4 VSSQ DQ3 H DQ2 VSSQ DQ5 VDDL VREF VSS J VSSDL C K VDD CKE WE K RAS CK ODT BA0 BA 1 L CAS CS A10/ AP A1 M A2 A0 A3 A5 N A6 A4 A7 A9 P A11 A8 A12 NC R NC NC NC VSS VDD VDD VSS 4 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Input / Output Functional Description Symbol Type Function Clock: CK and are differential clock inputs. All address and control input signals are sampled CK, Input on the crossing of the positive edge of CK and negative edge of . Output (read) data is referenced to the crossings of CK and (both directions of crossing). Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for CKE Input Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must maintain to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during Self-Refresh. Chip Select: All commands are masked when is registered high. provides for external rank Input selection on systems with multiple memory ranks. , , Input is considered part of the command code. Command Inputs: , and (along with ) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges DM, LDM, UDM Input of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS / is enabled by EMRS command. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge BA0 - BA1 Input command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provides the row address for Activate commands and the column address and Auto Precharge or Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the A0 - A13 Input precharge applies to one bank (A10=low) or all banks (A10=high). If only one bank is to be precharged, the bank is selected by BA0-BA1. The address inputs also provide the op-code during Mode Register Set commands.A13 Row address use on x8 components only. DQ Input/output Data Inputs/Output: Bi-directional data bus. Data Strobe: output with read data, input with write data. Edge aligned with read data, centered with write data. For the x16, LDQS corresponds to the data on DQ0 - DQ7; UDQS corresponds to DQS, () the data on DQ8-DQ15. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single LDQS, (), Input/output ended mode or paired with the optional complementary signals , , to provide UDQS,() differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables the complementary data strobe signals. 5 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Symbol Type Function Read Data Strobe: For x8 components a RDQS and pair can be enabled via EMRS(1) for RDQS, () Input/output real timing. RDQS and is not support x16 components. RDQS and are edge-aligned with real data. If enable RDQS and then DM function will be disabled. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, , RDQS, , and DM signal for ODT Input x8 configuration. For x16 configuration ODT is applied to each DQ, UDQS, , LDQS, , UDM and LDM signal. The ODT pin will be ignored if the EMRS (1) is programmed to disable ODT. NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.8V 0.1V VSSQ Supply DQ Ground VDDL Supply DLL Power Supply: VSSDL Supply DLL Ground VDD Supply Power Supply: VSS Supply Ground VREF Supply SSTL_1.8 reference voltage 1.8V 0.1V 1.8V 0.1V 6 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Ordering Information Green Standard Grade Speed Part Number Package Clock (MHz) CL-T RCD-TRP 333 5-5-5 400 5-5-5 333 5-5-5 400 5-5-5 NT5TU32M16DG-BD 533 6-6-6 NT5TU32M16DG-BE 533 7-7-7 NT5TU64M8DE-3C NT5TU64M8DE-AC Organization 60-Ball BGA NT5TU32M16DG-3C NT5TU32M16DG-AC 84-Ball BGA Industrial Grade Speed Part Number Package NT5TU64M8DE-3CI Organization NT5TU64M8DE-ACI NT5TU32M16DG-3CI NT5TU32M16DG-ACI 60-Ball BGA 84-Ball BGA Clock (MHz) CL-T RCD-TRP 333 5-5-5 400 5-5-5 333 5-5-5 400 5-5-5 7 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Block Diagram (64Mb x 8) Control Logic CKE CK CK CS Command Decode WE CAS RAS Row-Address MUX Mode Registers 17 14 14 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Memory Array Bank 1 Memory Arrayx16) (16384 Bank 0 x512 Memory Arrayx16) (16384 Sensex512 Amplifier Memory Array (16384 x16) Sensex512 Amplifier Memory Array (16384 x16) Sensex512 Amplifier Memory Array (16384 x16) Sensex512 Amplifier Memory Array (16384 x512 x16) Sense Array Amplifier Memory (16384 x16) Sensex512 Amplifier (16384 x32) Sensex256 Amplifier Sense Amplifier CK, CK DLL 8 8 8192 8 8 MUX 8 2 DQS Generator DQ0 - DQ7 32 DQS, DQS 2 I/O Gating DM Mask Logic Bank Control Logic Input Register 256 (x32) 3 10 32 Mask 4 Write FIFO & Drivers Data 8 2 32 COL0,1 Notes: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the bidirectional DQ and DQS signals. CK, CK 2 2 2 2 2 2 2 2 8 8 8 8 2 8 8 8 8 COL0,1 DQS, DQS RDQS , Receivers Column Column Decoder Column Decoder Column Decoder Column Decoder Column Decoder Column Decoder Column Decoder Decoder 8 Column-Address Counter/Latch COL0,1 ODT Control Refresh Counter A0 - A13, BA0 - BA2 Address Register 17 ODT Data 8 Drivers 32 Read Latch 14 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Row-Address Bank 1 Row-Address Bank 0 Latch & Row-Address Latch & Decoder Row-Address Latch & Decoder Row-Address Latch & Decoder Row-Address Latch & Decoder Row-Address Latch & Decoder Row-Address 16384 Latch & Decoder Latch & Decoder Decoder DM 8 2 8 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Block Diagram (32Mb x 16) Control Logic CKE CK CK CS Command Decode WE CAS RAS Row-Address MUX Mode Registers 16 13 13 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Memory Array Bank 1 Memory Arrayx16) (16384 Bank 0 x512 Memory Arrayx16) (16384 Sensex512 Amplifier Memory Array (16384 x16) Sensex512 Amplifier Memory Array (16384 x16) Sensex512 Amplifier Memory Array (16384 x16) Sensex512 Amplifier Memory Array (16384 x512 x16) Sense Amplifier Memory Array (16384 x16) Sensex512 Amplifier (8192 x 256 x 64) Sense Amplifier Sense Amplifier CK, CK DLL 16 8 16384 16 16 MUX 16 4 DQS Generator DQ0 - DQ15 64 UDQS, LDQS, 3 I/O Gating DM Mask Logic Bank Control Logic Input Register 256 (x64) 10 64 Mask 8 Write FIFO & Drivers Data 8 2 64 COL0,1 Notes: 1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. 2. DM is an unidirectional signal (input only), but it is internally loaded to match the load of the bidirectional DQ and DQS signals. CK, CK 2 2 2 2 2 2 2 2 16 16 16 16 16 16 16 16 COL0,1 UDQS, UDQS LDQS, LDQS 2 Receivers Column Column Decoder Column Decoder Column Decoder Column Decoder Column Decoder Column Decoder Column Decoder Decoder 8 3 Column-Address Counter/Latch COL0,1 ODT Control Refresh Counter A0 - A12, BA0 - BA2 Address Register 16 ODT Data 16 Drivers 64 Read Latch 13 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Row-Address Bank 1 Row-Address Bank 0 Latch & Row-Address Latch & Decoder Row-Address Latch & Decoder Row-Address Latch & Decoder Row-Address Latch & Decoder Row-Address Latch & Decoder Row-Address 8192 Latch & Decoder Latch & Decoder Decoder UDM, LDM 16 4 9 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Functional Description The 512Mb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The 512Mb DDR2 SDRAM is internally configured as a quad-bank DRAM. Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command, which is followed by a Read or Write command. The address bits registered coincident with the activate command are used to select the bank and row to be accesses (BA0 and BA1 select the banks, A0-A13 select the row for x8 components, A0-A12 select the row for x16 components). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the Auto-Precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation. Power-up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for POWER UP and Initialization. 1. Either one of the following sequence is required for Power-up. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state (all other inputs may be undefined) The VDD voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min; and during the VDD voltage ramp up, IVDD-VDDQI0.3 volts. Once the ramping of the supply voltages is complete (when VDDQ crosses VDDQ min), the supply voltage specifications in Re-commanded DC operating conditions table. - VDD, VDDL, and VDDQ are driven from a signal power converter output, AND - VTT is limited to 0.95V max, AND - Vref tracks VDDQ/2; Vref must be within 300mV with respect to VDDQ/2 during supply ramp time. - VDDQ>=VREF must be met at all times. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT at a Low state, all other inputs may be undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch-up. During the ramping of the supply voltages, VDDVDDLVDDQ must be maintained and is applicable to both AC and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the ramping of the supply voltages is complete, the supply voltage specifications provided in Re-commanded DC operating conditions table. - Apply VDD/VDDL before or at the same time as VDDQ. - VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDDmin. - Apply VDDQ before or at the same time as VTT. 10 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM - The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be no greater than 500ms. (Note: While VDD is ramping, current may be supplied from VDD through the DRAM to VDDQ.) - Vref must track VDDQ/2; Vref must be within 300mV with respect to VDDQ/2 during supply ramp time. - VDDQ VREF must be met at all time. - Apply VTT. 2. Start clock (CK, ) and maintain stable condition. 3. For the minimum of 200us after stable power (VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and maximum values as stated in Re-commanded DC operating conditions table, and stable clock, then apply NOP or Deselect & take CKE HIGH. 4. Waiting minimum of 400ns then issue pre-charge all command. NOP or Deselect applied during 400ns period. 5. Issue an EMRS command to EMR (2). (Provide LOW to BA0, and HIGH to BA1). 6. Issue an EMRS command to EMR (3). (HIGH to BA0 and BA1). 7. Issue EMRS to enable DLL. (Provide Low to A0, HIGH to BA0 and LOW to BA1 and A13. And A9=A8=A7=LOW must be used when issuing this command.) 8. Issue a Mode Register Set command for DLL reset. (Provide HIGH to A8 and LOW to BA0 and A13) 9. Issue a precharge all command. 10. Issue 2 more auto-refresh commands. 11. Issue a MRS command with LOW to A8 to initialize device operation (i.e. to program operating parameters without resetting the DLL.) 12. At least 200 clocks after step 7, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRs to EMR (1) to set OCD Calibration Default (A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit OCD Calibration Mode (A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1). 13. The DDR2 DRAM is now ready for normal operation. * To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. Example: CK, CK CKE ODT "low" NOP Command tMRD tRP 400 ns PRE ALL CMD EMRS Extended Mode Register Set with DLL enable tMRD MRS Mode Register Set with DLL reset tRP PRE ALL 1st Auto refresh min. 200 cycles to lock the DLL tMRD tRFC tRFC 2nd Auto refresh MRS Follow OCD flowchart EMRS EMRS Follow OCD flowchart 11 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Register Definition Programming the Mode Registration and Extended Mode Registers For application flexibility, burst length, burst type, latency, DLL reset function, write recovery time (tWR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive latency, driver impedance, ODT (On Die Termination), single-ended strobe and OCD (off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MR) and Extended Mode Registers (EMR (#)) can be altered by re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and DLL Reset do not affect array contents, which mean re-initialization including those can be executed any time after power-up without affecting array contents. Mode Registration Set (MRS) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on , , , , BA0 and BA1, while controlling the state of address pins A0 ~ A13. The DDR2 SDRAM should be in all banks precharged (idle) mode with CKE already high prior to writing into the mode register. The mode register set command cycle time (t MRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharged state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8 bit burst length. Burst address sequence type is defined by A3 and latency is defined by A4 ~ A6. A7 is used for test mode and must be set to low for normal MRS operation. A8 is used for DLL reset. A9 ~ A11 are used for write recovery time (WR) definition for Auto-Precharge mode. 12 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM MRS Mode Register Operation Table (Address Input for Mode Set) Address Field BA2* BA1 BA0 A13* A 12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Burst Length MRS mode A2 A1 A0 BL 0 1 0 4 0 1 1 8 BA 1 BA0 MRS mode 0 0 MR 0 1 EMR(1) 1 0 EMR (2) A3 Burst Type 1 1 EMR(3) 0 Sequential 1 Interleave Burst Type Active power down exit time Active power down exit time A12 0 Fast exit (use tXARD) 1 / CAS Latency A6 A5 A4 CAS Latency Slow exit (use tXARDS) 0 0 0 Reserved Write recovery for autoprecharge 0 0 1 Reserved WR (cycles) 0 1 0 Reserved A11 A10 A9 0 Reserved 0 1 1 3 0 0 1 2 1 0 0 4 0 1 0 3 1 0 1 5 0 1 1 4 1 1 0 6 1 0 0 5 1 1 1 7 1 0 1 6 1 1 0 7 1 1 1 8 DDR2-1066 DDR2-800 0 DDR2-667 0 Mode A7 Mode 0 Normal 1 TEST DLL Reset A8 DLL Reset 0 NO 1 YES * BA2 and A13 are reserved for future use and must be set to "0" when programming MR. 13 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Extended Mode Register Set -EMRS (1) Programming Address Field BA2* BA1 BA0 A13 * A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DLL MRS mode BA1 BA0 MRS mode A0 DLL Enable 0 Enable 1 Disable 0 0 MR 0 1 EMR(1) 1 0 EMR(2) 1 1 EMR(3) 0 Full strength Qoff 1 Reduced strength D.I.C Output Driver A1 Impedance Control A12 Qoff *5 0 Output buffer enabled A6 A2 Rtt (Nominal) 1 Output buffer disabled 0 0 ODT Disabled RDQS 0 1 75 ohm 1 0 150 ohm 1 1 50 ohm *2 Rtt A11 RDQS Enable*6 DQS 0 Disable A10 DQS 1 Enable 0 Enable 1 Disable A5 Additive Latency Additive A4 A3 Latency 0 0 0 0 OCD Program 0 0 1 1 A7 OCD Calibration Program 0 1 0 2 0 1 1 3 A9 A8 0 0 0 0 0 1 Drive(1) 1 0 0 4 0 1 0 Drive(0) 1 0 1 5 1 0 0 1 1 0 6 1 1 1 1 1 1 Reserved OCD Calibration mode exit; maintain setting Adjust mode *3 OCD Calibration default*4 * BA2 and A13 are reserved for future use and must be set to 0 when programming the EMR(1). *2 Mandatory for DDR2-1066 *3 When Adjust mode is issued, AL from previously set value must be applied. *4 After setting to default, OCD calibration mode needs to be exited by settin gA9-A7 to 000. *5 Output disabled - DQs, DQSs, DQSs, RDQS, RDQS. This feature is used in conjunction with DIMM IDD measurements when IDDQ is not desired to be included. *6 If RDQS is enabled, the DM function is disabled. RDQS is active for reads and do not care for writes. 14 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Extended Mode Register Set -EMRS (1) The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, disable, OCD program, RQDS enable. The default value of the extended mode register EMRS(1) is not defined, therefore the extended mode register must be written after power-up for proper operation. The extended mode register is written by asserting low on , , , , BA1 and high on BA0, while controlling the state of the address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the EMRS (1). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength output driver. A3-A5 determines the additive latency, A7-A9 are used for OCD control, A10 is used for disable and A11 is used for RDQS enable. A2 and A6 are used for ODT setting. Single-ended and Differential Data Strobe Signals The following table lists all possible combinations for DQS, , RDQS, which can be programmed by A10 & A11 address bits in EMRS(1). RDQS and are available in x8 components only. If RDQS is enabled in x8 components, the DM function is disabled. RDQS is active for reads and don't care for writes. EMRS (1) Strobe Function Matrix A11 A10 (RDQS Enable) ( Enable) 0 (Disable) RDQS/DM DQS Signaling 0 (Enable) DM Hi-Z DQS differential DQS signals 0 (Disable) 1 (Disable) DM Hi-Z DQS Hi-Z single-ended DQS signals 1 (Enable) 0 (Enable) RDQS DQS differential DQS signals 1 (Enable) 1 (Disable) RDQS Hi-Z DQS Hi-Z single-ended DQS signals DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh operation and is automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the DLL is reset, 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Less clock cycles may result in a violation of the t AC or tDQSCK parameters. Output Disable (Qoff) Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the EMRS (1) is set to 0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM outputs allows users to measure IDD currents during Read operations, without including the output buffer current and external load currents. 15 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM EMRS (2) Extended Mode Register Set Programming BA 2 B A1 B A0 A12 A11 A10 0* 0* 0 1 B A1 B A 0 A9 MRS mode 0 0 0 1 MR S EMRS (1) 1 0 EMRS (2) 1 1 EMRS (3): Reserved A8 A7 A6 SRF A7 0 1 A5 A4 A3 A2 0* A1 A0 PASR*** Address Field Extended Mode Register High Temperature Self-Refresh Rate Enable Disable Enabl e** Partial Array Self Refresh (Reserved) A2 A1 A0 0 0 0 0 0 1 Half Array ( B A [2:0 ] = 00 0 , 001, 01 0 , & 011 ) 0 1 0 0 1 1 Quarter Array ( BA [2:0 ] = 00 0 & 001 ) 1/8th array ( BA [2 : 0] = 000 ) 1 0 0 3 / 4 arra y ( BA[2:0]=010 , 011,100 ,101 ,110 , &111 ) 1 0 1 1 1 0 1 1 1 Half array ( B A[ 2 : 0 ] = 100 , 101 , 110 , & 111) Quarter array ( B A [ 2 : 0 ] = 110 & 1 11 ) 1/8 th array ( BA [ 2 : 0 ] =111) Full array *The rest bits in EMRS (2) is reserved for future use and all bits in EMRS (2) expect A0-A2, A7, BA0, and BA1 must be programmed to 0 when setting EMRS(2) during initialization. **DDR2 SDRAM Module user can look at module SPD field Byte 49 bit [0]. ***Optional, if PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the spec. location will be lost if self refresh is entered. Extended Mode Register Set EMRS (2) The Extended Mode Registers (2) controls refresh related features. The default value of the extended mode register(2) is not defined, therefore the extended mode register(2) is written by asserting low on CS, RAS, CAS, WE, BA0, high on BA1, while controlling the states of address pin A0-A13. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register (2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. EMRS(3) Extended Mode Register Set Programming All bits in EMRS(3) expect BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode register during initialization. 16 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment. MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS: OCD calibration mode exit EMRS: Drive (1) EMRS: Drive(0) DQ & DQS High; DQSLow DQ & DQS Low; DQS High ALL OK ALL OK Test Test Need Calibration Need Calibration EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS : EMRS : Enter Adjus t Mode Enter Adjust Mode BL=4 cod e inpu t to all DQs BL =4 code input to all DQs Inc, Dec, or NOP Inc, Dec, or NOP EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End 17 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS (1) mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMRS (1) bit enabling RDQS operation. In Drive (1) mode, all DQ, DQS (and RDQS) signals are driven high and all (and ) signals are driven low. In Drive (0) mode, all DQ, DQS (and RDQS) signals are driven low and all (and ) signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 Ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are specified in the following table. OCD applies only to normal full strength output drive setting defined by EMRS (1) and if half strength is set, OCD default driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS(1) commands not intended to adjust OCD characteristics must specify A7~A9 as '000' in order to maintain the default or calibrated value. Off- Chip-Driver program A9 A8 A7 Operation 0 0 0 OCD calibration mode exit 0 0 1 Drive(1) DQ, DQS, (RDQS) high and low 0 1 0 Drive(0) DQ, DQS, (RDQS) low and high 1 0 0 Adjust mode 1 1 1 OCD calibration default 18 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM OCD impedance adjust To adjust output driver impedance, controllers must issue the ADJUST EMRS (1) command along with a 4 bit burst code to DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 is the table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment can be up to 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the maximum step count range. When Adjust mode command is issued, AL from previously set value must be applied. 4 bit burst code inputs to all DQs DT0 DT1 DT2 DT3 0 0 0 0 0 0 Operation Pull-up driver strength Pull-down driver strength 0 NOP (no operation) NOP (no operation) 0 1 Increase by 1 step NOP 0 1 0 Decrease by 1 step NOP 0 1 0 0 NOP Increase by 1 step 1 0 0 0 NOP Decrease by 1 step 0 1 0 1 Increase by 1 step Increase by 1 step 0 1 1 0 Decrease by 1 step Increase by 1 step 1 0 0 1 Increase by 1 step Decrease by 1 step 1 0 1 0 Decrease by 1 step Decrease by 1 step Other Combinations Reserved For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS / tDH should be met as the following timing diagram. Input data pattern for adjustment, DT0 ~ DT3 is fixed and not affected by MRS addressing mode (i.e. sequential or interleave). 19 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM OCD Adjust Mode OCD calibration mode exit OCD adjust mode CK CK CMD EMRS NOP NOP NOP NOP DQS WL NOP EMRS NOP WR DQS tDS DQ tDH DT0 DT1 DT2 DT3 DM 20 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Drive Mode Drive mode, both Drive (1) and Drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment. In this mode, all outputs are driven out t OIT after "enter drive mode" command and all output drivers are turned-off tOIT after "OCD calibration mode exit" command as the following timing diagram. CK, CK CMD EMRS(1) NOP NOP NOP NOP NOP NOP NOP tOIT tOIT DQS_in EMRS(1) DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0 DQS high for Drive(1) DQS high for Drive(0) DQ_in OCD calibration mode exit Enter Drive Mode On-Die Termination (ODT) ODT (On-Die Termination) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQ, DQS, , RDQS, , and DM signal for x8 configurations via the ODT control pin. For x16 configuration ODT is applied to each DQ, UDQS, , LDQS, , UDM and LDM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-Refresh mode. Functional Representation of ODT VDDQ VDDQ VDDQ sw1 sw2 sw3 Rval1 Rval2 Rval3 DRAM Input Buffer Input Pin Rval1 Rval2 Rval3 sw1 sw2 sw3 VSSQ VSSQ VSSQ Switch sw1, sw2, or sw3 is enabled by the ODT pin. Selection between sw1, sw2, or sw3 is determined by "Rtt (nominal)" in EMRS. Termination included on all DQs, DM, DQS, , RDQS, and pins. 21 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM ODT related timings MRS command to ODT update delay During normal operation the value of the effective termination resistance can be changed with an EMRS command. The update of the Rtt setting is done between tMOD, min and tMOD, max, and CKE must remain HIGH for the entire duration of tMOD window for proper operation. The timings are shown in the following timing diagram. EMRS CMD NOP NOP NOP NOP NOP CK, CK tIS CKE tMOD, max tAOFD Rtt tMOD, min Old setting Updating New setting EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal) Setting in this diagram is the Register and I/O setting, not what is measured from outside. However, to prevent any impedance glitch on the channel, the following conditions must be met. - tAOFD must be met before issuing the EMRS command. - ODT must remain LOW for the entire duration of tMOD window, until tMOD, max is met. Now the ODT is ready for normal operation with the new setting, and the ODT may be raised again to turn on the ODT. Following timing diagram shows the proper Rtt update procedure. EMRS CMD NOP NOP NOP NOP NOP CK, CK tIS CKE tAOND tMOD, max tAOFD Rtt Old setting New setting EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal) Setting in this diagram is the Register and I/O setting, not what is measured from outside. 22 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM ODT On/Off timings ODT timing for active/standby mode T-1 T-0 T-2 T-3 T-4 T-6 T-5 CK, CK tIS CKE tIS tIS ODT tAOND tAOFD(2. 5 tck) Internal Term Res. Rtt tAON, min tAOF, min tAON, max tAOF, max ODT Timing for Power-down mode T0 T1 T2 T3 T4 T5 T6 CK, CK CKE tIS ODT tIS tAOFPD,max tAOFPD,min DQ Rtt tAONPD,min tAONPD,max 23 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Bank Activate Command The Bank Activate command is issued by holding and high plus and low at the rising edge of the clock. The bank addresses BA0 ~ BA1 are used to select the desired bank. The row addresses A0 through A13 are used to determine which row to activate in the selected bank for and x8 organized components. For x16 components row addresses A0 through A12 have to be applied. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle. If an R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay the R/W command which is internally issued to the device. The additive latency value must be chosen to assure t RCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5, and 6 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as t RAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum time interval between Bank Active commands, to other bank, is the Bank A to Bank B delay time (tRRD). In order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices, certain restrictions on operation of the 8 bank devices must be observed. There are two rules. One for restricting the number of sequential ACTcommands that can be issued and another for allowing more time for RAS precharge for a Precharge All command. The rules are list as follow: * 8 bank device sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling tFAW window. Conveting to clocks is done by dividing tFAW by tCK and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clock N+1 through N+9. *8 bank device Precharge All Allowance: tRP for a Precharge All command for an 8 Bank device will equal to tRP+tCK, where tRP is the value for a single bank pre-charge. Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2 T0 T1 T2 T3 T4 Tn Tn+1 Tn+2 Tn+3 CK, CK Internal RAS-CAS delay tRCDmin. Address Bank A Row Addr. Bank A Col. Addr. Bank B Row Addr. Bank B Col. Addr. Bank A Addr. NOP Bank B Addr. Bank A Row Addr. Bank A to Bank B delay tRRD. additive latency AL=2 RAS-RAS delay tRRD. Command Bank A Activate Posted CAS Read A Bank B Activate Read A Begins Posted CAS Read B tRAS Row Active Time (Bank A) Bank A Precharge NOP Bank B Precharge Bank A Activate tRP Row Precharge Time (Bank A) tRC Row Cycle Time (Bank A) ACT 24 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Read and Write Commands and Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting high, and low at the clock's rising edge. must also be defined at this time to determine whether the access cycle is a read operation ( high) or a write operation ( low). The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is restricted to specific segments of the page length. A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL=8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundary respectively, and the minimum to delay (tCCD) is minimum 2 clocks for read or write cycles. Posted Posted operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the bank activate command (or any time during the to delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and the latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL greater than 0 must be written into the EMRS (1). The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus latency (RL=AL+CL). If a user chooses to issue a Read command after the tRCDmin period, the Read Latency is also defined as RL = AL + CL. Example of posted operation: Read followed by a write to the same bank: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4 -1 2 0 1 Activate Bank A Read Bank A 3 4 5 6 7 8 9 10 11 12 CK, CK CMD DQS, DQS DQ AL = 2 Write Bank A WL = RL -1 = 4 CL = 3 >=tRCD RL = AL + CL = 5 Dout0 Dout1 Dout2Dout3 Din0 Din1 Din2 Din3 PostCAS1 25 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Read followed by a write to the same bank: AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 CK, CK AL=0 CMD Read Bank A Activate Bank A >=tRCD Write Bank A CL=3 WL = RL - 1 = 2 DQS, DQS DQ RL = AL + CL = 3 Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 PostCAS5 26 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write burst when burst length = 8 is used, see the "Burst Interruption "section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices. Bust Length and Sequence Starting Address Sequential Addressing Interleave Addressing (A2 A1 A0) (decimal) (decimal) Burst Length x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 4 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 8 Note: 1) Page length is a function of I/O organization 64Mb X 16 organization (CA0-CA9); Page Size = 2K Byte; Page Length = 1024 128Mb X 8 organization (CA0-CA9 ); Page Size = 1K Byte; Page Length = 1024 256Mb x 4 organization (CA0-CA9, CA11); Page Size = 1K Byte; Page Length = 2048 2) Order of burst access for sequential addressing is "nibble-based" and therefore different from SDR or DDR components 27 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Burst Read Command The Burst Read command is initiated by having and low while holding and high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMRS (1)) Basic Burst Read Timing t CH t CL t CK CLK CLK, CLK CLK t DQSCK t AC DQS DQS, DQS DQS t RPRE DQ t RPST t LZ Dout Dout t DQSQmax Dout Dout t DQSQmax t QH t HZ t QH DO-Read Examples: Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP NOP NOP NOP NOP <= tDQSCK DQS, DQS AL = 2 DQ CL = 3 RL = 5 Dout A0 Dout A1 Dout A2 Dout A3 BRead523 28 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Burst Read Operation: RL = 3 (AL = 0, CL = 3, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD READ A NOP NOP NOP NOP NOP NOP NOP NOP <= tDQSCK DQS, DQS CL = 3 RL = 3 DQ's Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 BRead303 Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4 The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around time(tRTW), which is 4 clocks in case of BL=4 operation, 6 clocks in case of BL=8 operation. T0 T1 Tn-1 Tn+1 Tn Tn+2 Tn+3 Tn+4 Tn+5 CK, CK CMD Posted CAS READ A NOP NOP Posted CAS WRITE A NOP NOP NOP NOP NOP tRTW(Read to Write turn around time) DQS, DQS WL = RL - 1 = 4 RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 Din A0 Din A1 Din A2 Din A3 BRBW514 29 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Seamless Burst Read Operation: RL = 5, AL = 2, CL = 3, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK Post CAS READ A CMD NOP Post CAS READ B NOP NOP NOP NOP NOP NOP DQS, DQS AL = 2 CL = 3 RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 SBR523 The seamless burst read operation's supported by enabling a read command at every clock for BL=4 operation, and every 4 clock for BL=8 operation. This operation allows regardless of same or different banks as long as the banks activated. Burst Write Command The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) has to be driven low (preamble) a time tWPRE prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is named "write recovery time" (WR) . DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing measured is mode dependent. Basic Burst Write Timing t DQSH t DQSL DQS DQS, DQS DQS t WPST t WPRE Din t DS Din Din Din t DH 30 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Example: Burst Write Operation: RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP <= tDQSS DQS, DQS NOP Precharge Completion of the Burst Write tWR WL = RL-1 = 4 DQ NOP DIN A0 DIN A1 DIN A2 DIN A3 BW543 31 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4 The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around time(tRTW), which is 4 clocks in case of BL=4 operation, 6 clocks in case of BL=8 operation. Burst Write followed by Burst Read: RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 T8 CK, CK Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6 CMD NOP NOP NOP NOP Post CAS READ A NOP NOP NOP NOP DQS, DQS DQ CL=3 AL=2 tWTR WL = RL - 1 = 4 DIN A0 DIN A1 DIN A2 DIN A3 RL=5 BWBR The minimum number of clocks from the burst write command to the burst read command is (CL - 1) +BL/2 + tWTR where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array. Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS WRITE A NOP Post CAS WRITE B NOP NOP NOP NOP NOP NOP DQS, DQS WL = RL - 1 = 4 DQ DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 SBR The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. 32 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Write Data Mask One write data mask input (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, consistent with the implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM of x4 and x16 bit organization is not used during read cycles. However, DM of x8 bit organization can be used as RDQS during read cycles by EMRS (1) setting. Write Data Mask Timing t DQSH t DQSL DQS DQS, DQS DQS t WPST t WPRE DQ Din Din t DS Din Din t DH DM don't care Burst Write Operation with Data Mask: RL = 3 (AL = 0, CL = 3), WL = 2, t WR = 3, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD WRITE A NOP NOP NOP NOP NOP NOP Precharge Bank A Activate <= tDQSS DQS, DQS WL = RL-1 = 2 DQ tWR tRP DIN A0 DIN A1 DIN A2 DIN A3 DM DM 33 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Burst Interruption Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or Precharge Command is prohibited. 2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or Precharge Command is prohibited. 3. Read burst interrupt occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings are prohibited. 4. Write burst interrupt occur exactly two clocks after the previous Write command. Any other Read burst interrupt timings are prohibited. 5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM. 6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted. 7. Read burst interruption is allowed by a Read with Auto-Precharge command. 8. Write burst interruption is allowed by a Write with Auto-Precharge command. 9. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end. 34 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Examples: Read Burst Interrupt Timing Example: (CL = 3, AL = 0, RL = 3, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD NOP READ A NOP READ B NOP NOP NOP NOP NOP NOP DQS, DQS DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6 Dout B7 RBI Write Burst Interrupt Timing Example: (CL = 3, AL = 0, WL = 2, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD NOP WRITE A NOP WRITE B NOP NOP NOP NOP NOP NOP DQS, DQS DQ Din A0 Din A1 Din A2 Din A3 Din B0 Din B1 Din B2 Din B3 Dout B4 Din B5 Din B6 Din B7 WBI 35 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-charge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0, and BA1 are used to define which bank to precharge when the command is issued. Bank Selection for Precharge by Address Bit Precharge A10 BA1 BA0 LOW LOW LOW Bank 0 only LOW LOW HIGH Bank 1 only LOW HIGH LOW Bank 2 only LOW HIGH HIGH Bank 3 only HIGH Don't Care Don't Care all banks Bank(s) Burst Read Operation Followed by a Precharge Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max (RTP, 2) - 2 clocks. For the earliest possible precharge, the Precharge command may be issued on the rising edge which is "Additive Latency (AL) + BL/2 clocks" after a Read Command, as long as the minimum t RAS timing is satisfied. The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a Read to Precharge command. This time is call tRTP (Read to Precharge). For BL=4 this is the time from the actual read (AL after the Read command) to Precharge command. For BL=8 this is the time from AL + 2 clocks after the Read to the Precharge command. 36 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Examples: Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP 2 clocks T0 T1 T2 T3 NOP NOP Precharge T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP AL + BL/2 clks Bank A Activate NOP >=tRP DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 CL = 3 >=tRC >=tRTP BR-P413 Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP 2 clocks T0 T1 T2 T3 T4 T5 T6 Precharge NOP T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP NOP NOP AL + BL/2 clks DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 CL = 3 >=tRC >=tRTP first 4-bit prefetch second 4-bit prefetch BR-P413(8) 37 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Burst Read Operation Followed by Precharge: RL = 5 (AL = 2, CL = 3), BL = 4, tRTP 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP Precharge AL + BL/2 clks Bank A Activate NOP NOP >=tRP DQS, DQS CL = 3 AL = 2 RL = 5 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 CL = 3 >=tRC >=tRTP BR-P523 Burst Read Operation Followed by Precharge: RL = 6, (AL = 2, CL = 4), BL = 4, tRTP 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP AL + BL/2 clocks Precharge A NOP NOP Bank A Activate NOP >=tRP DQS, DQS AL = 2 CL = 4 DQ RL = 6 Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 CL = 4 >=tRC >=tRTP BR-P624 38 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Burst Read Operation Followed by Precharge: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks T0 T1 T2 T3 T4 T5 T6 NOP NOP Precharge T7 T8 CK, CK CMD READ A NOP NOP AL + BL/2 clks + 1 Bank A Activate NOP NOP >=tRP DQS, DQS CL = 4 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 >=tRAS >=tRTP first 4-bit prefetch BR-P404(8) second 4-bit prefetch Burst Write followed by Precharge Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does not support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see the AC table in this datasheet) and is not the programmed value for tWR in the MRS. Examples: Burst Write followed by Precharge : WL = (RL - 1) = 3, BL = 4, tWR = 3 T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP NOP Precharge A Completion of the Burst Write DQS, DQS >=tWR WL = 3 DQ NOP DIN A0 DIN A1 DIN A2 DIN A3 BW-P3 39 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Burst Write followed by Precharge : WL = (RL - 1) = 4, BL = 4, tWR = 3 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP NOP Precharge A Completion of the Burst Write DQS, DQS tWR WL = 4 DQ NOP DIN A0 DIN A1 DIN A2 DIN A3 BW-P4 40 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-charge Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the Auto-Precharge function is enabled. During Auto-Precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is Latency (CL) clock cycles before the end of the read burst. Auto-Precharge is also implemented for Write Commands. The precharge operation engaged by the Auto-Precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon Latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the precharge operation until the array restore operation has been completed so that the Auto-Precharge command may be issued with any read or write command. Burst Read with Auto-Precharge If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRTP(min) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the next Activate command becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-Precharge to the next Activate command is AL + 2 + tRTP + tRP. Note that both parameters tRTP and tRP have to be rounded up to the next integer value. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) The precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins. (2) The cycle time (tRC) from the previous bank activation has been satisfied. 41 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Examples: Burst Read with Auto-Precharge followed by an activation to the Same Bank (tRC Limit) RL = 5 (AL = 2, CL = 3), BL = 4, tRTP 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP NOP NOP NOP NOP NOP NOP Bank Activate NOP A10 ="high" AL + BL/2 Auto-Precharge Begins DQS, DQS AL = 2 CL = 3 tRP RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 tRAS tRCmin. BR-AP5231 Burst Read with Auto-Precharge followed by an Activation to the Same Bank (tRAS Limit): RL = 5 (AL = 2, CL = 3), BL = 4, tRTP 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP NOP NOP NOP NOP NOP Bank Activate NOP NOP A10 ="high" tRAS(min) Auto-Precharge Begins DQS, DQS AL = 2 CL = 3 tRP RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 tRC BR-AP5232 42 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Burst Read with Auto-Precharge followed by an Activation to the Same Bank: RL = 4 ( AL = 1, CL = 3), BL = 8, tRTP 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP NOP NOP NOP A10 ="high" NOP NOP NOP AL + BL/2 NOP Bank Activate tRP Auto-Precharge Begins DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 >= tRTP BR-AP413(8)2 second 4-bit prefetch first 4-bit prefetch Burst Read with Auto-Precharge followed by an Activation to the Same Bank: RL = 4 ( AL = 1, CL = 3), BL = 4, tRTP > 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP A10 ="high" NOP NOP NOP NOP NOP NOP Bank Activate NOP AL + tRTP + tRP Auto-Precharge Begins DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 tRTP Dout A1 Dout A2 Dout A3 tRP BR-AP4133 first 4-bit prefetch 43 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Burst Write with Auto-Precharge If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (WR), programmed in the MRS register, as long as t RAS is satisfied. The bank undergoing Auto-Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. Examples: Burst Write with Auto-Precharge (tRC Limit): WL = 2, tDAL = 6 (WR = 3, tRP = 3), BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 CK, CK WRITE w/AP CMD NOP NOP NOP A10 ="high" NOP NOP NOP Completion of the Burst Write Bank A Activate NOP Auto-Precharge Begins DQS, DQS WR WL = RL-1 = 2 tRP tDAL DQ DIN A0 DIN A1 DIN A2 DIN A3 tRCmin. >=tRASmin. BW-AP223 Burst Write with Auto-Precharge (tWR + tRP Limit) : WL = 4, tDAL = 6 (tWR = 3, tRP = 3), BL = 4 T 0 T 3 T 4 T 5 T 6 NOP NOP NOP T 7 T 8 T 9 T12 CK, CK CMD Posted CAS WRITE w/AP A10 ="high" NOP NOP NOP NOP Bank A Activate Completion of the Burst Write Auto-Precharge Begins DQS, DQS tWR WL = RL-1 = 4 DQ DIN A0 DIN A1 DIN A2 tRP tDAL DIN A3 >=tRC >=tRAS BW-AP423 44 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Precharge & auto precharge clarification From Command Read Minimum Delay between "From To Command command" to "to command" Units Note Precharge (to same Bank as Read) AL + BL/2 + max(RTP,2) - 2 tCK 1,2 Precharge All AL + BL/2 + max(RTP,2) - 2 tCK 1,2 Precharge ( to same Bank as Read wAP) AL + BL/2 + max(RTP,2) - 2 tCK 1,2 Precharge Al AL + BL/2 + max(RTP,2) - 2 tCK 1,2 Precharge (to same Bank as Write) WL + BL/2 + tWR tCK 2 Precharge Al WL + BL/2 + tWR tCK 2 Precharge (to same bank as Write w/AP) WL + BL/2 + WR tCK 2 Precharge Al tCK 2 Read w/AP Write Write w/AP Precharge Precharge All WL + BL/2 + WR Precharge (to same bank as Precharge) 1 tCK 2 Precharge Al 1 tCK 2 Precharge 1 tCK 2 Precharge Al 1 tCK 2 Note: 1) RTP [cycles] = RU {tRTP(ns)/tCK(ns)}, where RI stands for round up. 2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP or tRPa depending on the latest precharge command issued to that bank. 45 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Refresh SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways: by an explicit Auto-Refresh command, or by an internally timed event in Self-Refresh mode. Dividing the number of device rows into the rolling 64 ms interval defined the average refresh interval t REFI, which is a guideline to controlles for distributed refresh timing. For example, a 1Gbit DDR2 SDRAM has 8392 rows resulting in a tREFI of 7.8 s. Auto-Refresh Command Auto-Refresh is used during normal operation of the DDR2 SDRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an Auto-Refresh command. The DDR2 SDRAM requires Auto-Refresh cycles at an average periodic interval of tREFI (maximum). When , and are held low and high at the rising edge of the clock, the chip enters the Auto-Refresh mode. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time (t RP) before the Auto-Refresh Command can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto-Refresh Command and the next Activate Command or subsequent Auto-Refresh Command must be greater than or equal to the Auto-Refresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 * tREFI. T0 T1 T2 T3 CK, CK "high" CKE CMD Precharge NOP > = t RFC > = t RFC > = t RP NOP AUTO REFRESH NOP AUTO REFRESH NOP NOP ANY AR 46 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Self-Refresh Command The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the Self-Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Command is defined by having , , and held low with high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS (1) command. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode. When the DDR2 SDRAM has entered Self-Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self-Refresh Operation to save power. The user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self-Refresh operation. Once Self-Refresh Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must remain high for the entire Self-Refresh exit period (tXSNR or tXSRD) for proper operation. NOP or DESELECT commands must be registered on each positive clock edge during the Self-Refresh exit interval. Since the ODT function is not supported during Self-Refresh operation, ODT has to be turned off tAOFD before entering Self-Refresh Mode and can be turned on again when the t XSRD timing is satisfied. T0 T1 T2 T3 T4 T5 Tm Tn Tr CK/CK tRP* tis tis CKE tis tAOFD >=tXSRD >= tXSNR ODT CMD Self Refresh Entry NOP CK/CK may be halted Non-Read Command Read Command CK/CK must be stable * Device must be in theing "All banks idle" state to enter Self Refresh mode. * ODT must be turned off prior to entering Self Refresh mode. * tXSRD (>=200 tCK) has to be satisfied for a Read or as Read with Auto-Precharge commend. * tXSNR has to be satisfied for any command execept Read or a Read with Auto-Precharge command, where tXSNR is defined as tRFC + 10ns. * The minium CKE low time is defined by the tCKEmin. timming paramester. * Since CKE is an SSTL input, VREF must maintained during Self-Refresh. 47 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Power-Down Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge or Auto-Refresh is in progress, but power-down IDD specification will not be applied until finishing those operations. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two different power saving modes can be selected within the MRS register, address bit A12. When A12 is set to "low" this mode is referred as "standard active power-down mode" and a fast power-down exit timing defined by the tXARD timing parameter can be used. When A12 is set to "high" this mode is referred as a power saving "low power active power-down mode". This mode takes longer to exit from the power-down mode and the tXARDS timing parameter has to be satisfied. Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other input signals are "Don't Care". Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after CKE goes high. Power-down exit latencies are defined in the AC spec table of this data sheet. Power-Down Entry Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be entered after a precharge, Precharge-All or internal precharge command. It is also allowed to enter power-mode after an Auto-Refresh command or MRS / EMRS(1) command when tMRD is satisfied. Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-Precharge command is allowed after RL + BL/2 is satisfied. Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case of a write command, active power-down mode entry is allowed then WL + BL/2 + tWTR is satisfied. In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge command has been executed, which WL + BL/2 + WR is starting from the write with Auto-Precharge command. In case the DDR2 SDRAM enters the Precharge Power-down mode. 48 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Examples: Active Power-Down Mode Entry and Exit after an Activate Command T0 T1 T2 Tn Tn+1 Tn+2 CK, CK CMD NOP Activate NOP Valid Command NOP NOP NOP tIS CKE tIS tXARD or tXARDS *) Act.PD 0 Active Power-Down Exit Active Power-Down Entry Active Power-Down Mode Entry and Exit after a Read Burst: RL = 4 (AL = 1, CL =3), BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 Tn T8 Tn+1 Tn+2 CK, CK CMD READ READ w/AP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Valid Command tIS CKE RL + BL/2 tIS DQS, DQS AL = 1 DQ tXARD or tXARDS *) CL = 3 RL = 4 Dout A0 Dout A1 Dout A2 Dout A3 Active Power-Down Entry Active Power-Down Exit Act.PD 1 49 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Active Power-Down Mode Entry and Exit after a Write Burst: WL = 2, tWTR = 2, BL = 4 T0 T1 T2 T3 T4 T5 T6 Tn T7 Tn+1 Tn+2 CK, CK CMD WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP Valid Command NOP tIS CKE WL + BL/2 + tWTR tIS DQS, DQS WL = RL - 1 = 2 tWTR DIN A0 DQ DIN A1 DIN A2 tXARD or tXARDS *) DIN A3 Active Power-Down Exit Active Power-Down Entry Act.PD 2 Precharge Power Down Mode Entry and Exit T0 T1 T2 T3 Tn Tn+1 Tn+2 CK, CK CMD Precharge *) NOP NOP NOP NOP NOP NOP Valid Command NOP tIS CKE tIS tXP tRP Precharge Power-Down Entry Precharge Power-Down Exit *) "Precharge" may be an external command or an internal precharge following Write with AP. PrePD 50 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when is low with , , and held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when is brought high, the , , and signals become don't care. Input Clock Frequency Change During operation the DRAM input clock frequency can be changed under the following conditions: a) During Self-Refresh operation b) DRAM is in Precharge Power-down mode and ODT is completely turned off. The DDR2-SDRAM has to be in Precharged Power-down mode and idle. ODT must be allready turned off and CKE must be at a logic "low" state. After a minimum of two clock cycles after tRP and tAOFD have been satisfied the input clock frequency can be changed. A stable new clock frequency has to be provided, before CKE can be changed to a "high" logic level again. After tXP has been satisfied a DLL RESET command via EMRS(1) has to be issued. During the following DLL re-lock period of 200 clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the new clock frequency. Example: Input frequency change during Precharge Power-Down mode T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1 Ty+2 Tz Ty+3 CK, CK CMD NOP NOP NOP NOP NOP NOP NOP NOP NOP DLL RESET NOP Valid Command CKE tRP tAOFD tXP Minimum 2 clocks required before changing the frequency Frequency Change occurs here Stable new clock before power-down exit 200 clocks ODT is off during DLL RESET Frequ.Ch. 51 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Asynchronous CKE Low Event DRAM requires CKE to be maintained "high" for all valid operations as defined in this data sheet. If CKE asynchronously drops "low" during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If this event occurs, the memory controller must satisfy a time delay ( t delay ) before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised "high" again. The DRAM must be fully re-initialized as described the the initialization sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the initialization sequence. See AC timing parametric table for tdelay specification. Asynchronous CKE Low Event stable clocks CK, CK tdelay CKE CKE drops low due to an asynchronous reset event Clocks can be turned off after this point 52 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Truth Table Command Truth Table CKE Function Previous Current Cycle (Extended) Mode Register CS RAS CAS WE BA0-BA2 A13-A11 A10 A9 - A0 Notes Cycle H H L L L L BA Auto-Refresh H H L L L H X X X X 1 Self-Refresh Entry H L L L L H X X X X 1,8 H X X X Self-Refresh Exit L H L H H H X X X X 1,7,8 Single Bank Precharge H H L L H L BA X L X 1,2 Precharge all Banks H H L L H L X X H X 1 Bank Activate H H L L H H BA Write H H L H L L BA Column L Column 1,2,3 Write with Auto-Precharge H H L H L L BA Column H Column 1,2,3 Read H H L H L H BA Column L Column 1,2,3 Read with Auto-Precharge H H L H L H BA Column H Column 1,2,3 No Operation H X L H H H X X X X 1 Device Deselect H X H X X X X X X X 1 H X X X Power Down Entry H L L H H H X X X X 1,4 H X X X Power Down Exit L H L H H H X X X X 1,4 Set OP Code 1, 2 Row Address 1,2 1. All DDR2 SDRAM commands are defined by states of , , , , and CKE at the rising edge of the clock. 2. Bank addresses (BAx) determine which bank is to be operated upon. For (E) MRS BAx selects an (Extended) Mode Register. 3. Burst reads or writes at BL = 4 cannot be terminated. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" inspection for details. 4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refres h requirements outlined. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 6. X means "H or L (but a defined logic level)". 7. Self refresh exit is asynchronous. 8. Vref must be maintained during Self Refresh operation. 53 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Clock Enable (CKE) Truth Table for Synchronous Transitions CKE Current State 2 Previous Current Power-Down Self Refresh Bank(s) Active Command (N) 3 Action (N) , , , Cycle 1 Cycle 1 (N-1) (N) L L X Maintain Power-Down 11, 13, 15 L H DESELECT or NOP Power-Down Exit 4, 8, 11, 13 L L X Maintain Self Refresh 11, 15, 16 L H DESELECT or NOP Self Refresh Exit 4, 5, 9, 16 H L DESELECT or NOP Active Power-Down Entry H L DESELECT or NOP H L AUTOREFRESH H H Precharge Power-Down Entry All Banks Idle Any State other than listed above Notes 3 Self Refresh Entry Refer to the Command Truth Table 4,8,10,11,13 4,8,10,11,13 6, 9, 11,13 7 1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. 3. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N). 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 6. Self Refresh mode can only be entered from the All Banks Idle state. 7. Must be a legal command as defined in the Command Truth Table. 8. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. 9. Valid commands for Self Refresh Exit are NOP and DESELCT only. 10. Power-Down and Self Refresh cannot be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. See section 2.8 "Power Down" and section 2.7.2 "Self Refresh Command" for a detailed list of restrictions. 11. Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks. 12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 13. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefore limited by the refresh requirements. 14. CKE must be maintained high while the device is in OCD calibration mode. 15. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However DT must be driven high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in MRS(1)). 16. Vref must be maintained during Self Refresh operation 54 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Operating Conditions Absolute Maximum DC Ratings Symbol VDD Parameter Voltage on VDD pin relative to VSS Rating Units Notes -1.0 to + 2.3 V 1,3 VDDQ Voltage on VDDQ pin relative to VSS -0.5 to + 2.3 V 1,3 VDDL Voltage on VDDL pin relative to VSS -0.5 to + 2.3 V 1,3 -0.5 to + 2.3 V 1 -55 to + 100 1, 2 VIN, VOUT Voltage on any pin relative to VSS TSTG Storage Temperature 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. 3. When VDD, VDDQ, and VDDL are less than 500mV, Vref may be equal to or less than 300mV. DRAM Component Operating Temperature Range Symbol Parameter Rating Units 0 to 95 (Standard Grade) TOPER Notes 1,2 Operating Temperature - 40 to 95 (Industrial Grade) 1 Note: 1. Operating temperature is the case surface temperature (TCASE) on the center/top side of the DRAM. 2. At 85~ 95 TOPER, it is required to set tRFI=3.9s in auto refresh mode or to set `1' for EMRS (2) bit A7 in self refresh mode. 55 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM AC & DC Operating Conditions DC Operating Conditions Recommended DC Operating Conditions (SSTL_18) Rating Symbol Parameter Units Notes 1.9 V 1 1.8 1.9 V 5 1.7 1.8 1.9 V 1,5 Input Reference Voltage 0.49 * VDDQ 0.5 * VDDQ 0.51 * VDDQ V 2, 3 Termination Voltage VREF - 0.04 VREF VREF + 0.04 V 4 Min. Typ. Max. Supply Voltage 1.7 1.8 VDDDL Supply Voltage for DLL 1.7 VDDQ Supply Voltage for Output VREF VTT VDD 1. VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. 2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of V REF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in V DDQ. 3. Peak to peak ac noise on VREF may not exceed +/- 2% VREF (dc). 4. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors is expected to be set equal to V REF and must track variations in die dc level of VREF. 5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with V DD, VDDQ, and V DDL tied together. ODT DC Electrical Characteristic Parameter / Condition Symbol min. nom. max. Units Notes Rtt eff. impedance value for EMRS(1)(A6,A2)=0,1; 75 ohm Rtt1(eff) 60 75 90 ohms 1 Rtt eff. impedance value for EMRS(1)(A6,A2)=0,1; 150 ohm Rtt2(eff) 120 150 180 ohms 1 Rtt eff. impedance value for EMRS(1)(A6,A2)=1,1; 50 ohm Rtt3(eff) 40 50 60 ohms 1 Deviation of VM with respect to VDDQ / 2 delta VM -6 6 % 2 1) Measurement Definition for Rtt(eff): Apply VIHac and VILac to test pin separately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIHac - VILac) /( I(VIHac) - I(VILac)) 2) Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load: delta VM =(( 2* VM / VDDQ) - 1 ) x 100% 56 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM DC & AC Logic Input Levels DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the cross point of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. In single ended mode, the DQS (and RDQS) signals are internally disabled and don't care. Single-ended DC & AC Logic Input Levels Symbol Parameter DDR2-667/800/1066 Units Min. Max. VREF + 0.125 VDDQ + 0.3 V -0.3 VREF - 0.125 V VIH (dc) DC input logic high VIL (dc) DC input low VIH (ac) AC input logic high VREF + 0.200 VDDQ+Vpeak V VIL (ac) AC input low VSSQ-Vpeak VREF - 0.200 V Single-ended AC Input Test Conditions Symbol Condition Value Units Notes 0.5 * VDDQ V 1, 2 VREF Input reference voltage VSWING(max) Input signal maximum peak to peak swing 1 V 1, 2 SLEW Input signal minimum slew rate 1 V / ns 3, 4 1. This timing and slew rate definition is valid for all single-ended signals except tis, tih, tds, tdh. 2. Input waveform timing is referenced to the input signal crossing through the V REF level applied to the device under test. 3. The input signal minimum slew rate is to be maintained over the range from V IL(dc)max to V IH(ac)min for rising edges and the range from V IH(dc)min to VIL(ac)max for falling edges as shown in the below figure. 4. AC timings are referenced with input waveforms switching from V IL(ac) to V IH(ac) on the positive transitions and V IH(ac) to VIL(ac) on the negative transitions. 57 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Differential DC and AC Input and Output Logic Levels Symbol Parameter min. max. Units Notes 0.5 VDDQ V 1 VID(ac) AC differential input voltage VIX(ac) AC differential cross point input voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2 VOX(ac) AC differential cross point output voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 3 Notes: 1) V ID(ac) specifices the allowable DC execution of each input of differential pair such as CK, , DQS, , LDQS, , UDQS, and . 2) V IX(ac) specifices the input differential voltage lVTR-VCPl required for switching, where VTR is the true input (such as CK, DQS, LDQS, or UDQS) level and VCP is the complementary input (such , , , or ) level. The minimum value is equal to VIH(DC) - VIL(DC). 3) The typical value of VOX(AC) is expected to be about 0.5VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential signals must cross. 58 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Output Buffer Levels Output AC Test Conditions Symbol VOTR Parameter SSTL-18 Class II Units Notes 0.5 * VDDQ V 1 Output Timing Measurement Reference Level 1. The VDDQ of the device under test is referenced. Output DC Current Drive Symbol Parameter SSTL-18 Units Notes IOH(dc) Output Minimum Source DC Current, nominal -13.4 mA 1, 3, 4 IOL(dc) Output Minimum Sink DC Current, nominal 13.4 mA 2, 3, 4 1. VDDQ = 1.7 V; VOUT = 1.42 V. (V OUT-VDDQ) / IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 ohm for values of V OUT between 0V and 280 mV. 3. The dc value of V REF applied to the receiving device is set to V TT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in note 1 and 2. They are used to test drive current capability to ensure V IHmin. plus a noise margin and V ILmax. minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating points along 21 ohm load line to define a convenient current for measurement. OCD Default Setting Table Symbol Description Min. Nominal Max. Unit Notes - Pull-up / Pull down mismatch 0 - 4 Ohms 6 - Output Impedance step size for OCD calibration 0 - 1.5 Ohms 1,2,3 1.5 - 5 V / ns 1,4,5,7,8 SOUT Output Slew Rate 1) Absolute Specification: T OPEN; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V. 2) Impedance measurement condition for output source dc current: VDDQ = 1.7V, V OUT = 1420 mV; (VOUT-VDDQ)/IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V; V OUT = -280mV; VOUT / IOL must be less than 23.4 ohms for values of V OUT between 0V and 280 mV. 3) Mismatch is absolute value between pull-up and pull-down; both are measured at same temperature and voltage. 4) Slew rates measured from V IL(AC) to V IH(AC) with the load specified in Section 8.2. 5) The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. 6) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 0.75 ohms under nominal conditions. 7) DRAM output slew rate specification applies to 533MT/s, 667MT/s, and 800MT/s speed pin. 8) Timing skew due to DRAM output slew rate mis-match between DQS / and associated DQ's is included in tDQSQ and tQHS specification. 59 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Default Output V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS (1) bits A7~A9 = '111'. The driver characteristics evaluation conditions area) Nominal Default 25 (Tcase), VDDQ=1.8V, typical process. b) Minimum TOPER(max), VDDQ=1.7V, slow-slow process. c) Maximum 0 (Tcase), VDDQ=1.9V, fast-fast process 60 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Full Strength Default Pullup Driver Characteristics Minimum Nomal Default low Nomal Default high Maximum (23.4 Ohms) (18 Ohms) (18 Ohms) (12.6 Ohms) 0.0 0.00 0.00 0.00 0.00 0.1 -4.30 -5.65 -5.90 -7.95 0.2 -8.60 -11.30 -11.80 -15.90 0.3 -12.90 -16.50 -16.80 -23.85 0.4 -16.90 -21.20 -22.10 -31.80 0.5 -20.05 -25.00 -27.60 -39.75 0.6 -22.10 -28.30 -32.40 -47.70 0.7 -23.27 -30.90 -36.90 -55.55 0.8 -24.10 -33.00 -40.90 -62.95 0.9 -24.73 -34.50 -44.60 -69.55 1.0 -25.23 -35.50 -47.70 -75.35 1.1 -25.65 -36.10 -50.40 -80.35 1.2 -26.02 -36.60 -52.60 -84.55 1.3 -26.35 -36.90 -54.20 -87.95 1.4 -26.65 -37.10 -55.90 -90.70 1.5 -26.93 -37.40 -57.10 -93.00 1.6 -27.20 -37.60 -58.40 -95.05 1.7 -27.46 -37.70 -59.60 -97.05 1.8 - -37.90 -60.90 -99.05 1.9 - - - -101.05 Voltage (V) The driver characteristics evaluetion conditions are: Nominal Default 25 (Tcase) , VDDQ = 1.8 V, typical process Minimum Toper(max.), VDDQ = 1.7V, slow-slow process Maximum 0 (Tcase). VDDQ = 1.9 V, fast-fast process 61 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM 62 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Full Strength Default Pulldown Driver Characteristics Minimum Nomal Default low Nomal Default high Maximum (23.4 Ohms) (18 Ohms) (18 Ohms) (12.6 Ohms) 0.0 0.00 0.00 0.00 0.00 0.1 4.30 5.65 5.90 7.95 0.2 8.60 11.30 11.80 15.90 0.3 12.90 16.50 16.80 23.85 0.4 16.90 21.20 22.10 31.80 0.5 20.05 25.00 27.60 39.75 0.6 22.10 28.30 32.40 47.70 0.7 23.27 30.90 36.90 55.55 0.8 24.10 33.00 40.90 62.95 0.9 24.73 34.50 44.60 69.55 1.0 25.23 35.50 47.70 75.35 1.1 25.65 36.10 50.40 80.35 1.2 26.02 36.60 52.60 84.55 1.3 26.35 36.90 54.20 87.95 1.4 26.65 37.10 55.90 90.70 1.5 26.93 37.40 57.10 93.00 1.6 27.20 37.60 58.40 95.05 1.7 27.46 37.70 59.60 97.05 1.8 - 37.90 60.90 99.05 1.9 - - - 101.05 Voltage (V) The driver characteristics evaluetion conditions are: Nominal Default 25 (Tcase) , VDDQ = 1.8 V, typical process Minimum Toper(max.), VDDQ = 1.7V, slow-slow process Maximum 0 (Tcase). VDDQ = 1.9 V, fast-fast process 63 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Calibrated Output Driver V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in the Off-Chip Driver (OCD) Impedance Adjustment. The following tables show the data in tabular format suitable for input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real system calibration error needs to be added to these values. It must be understood that these V-I curves are represented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error. Since this a system specific phenomena, it cannot be quantified here. the values in the calibrated tables represent just the DRAM portion of uncertainty while looking at one DQ only. If the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figure. in such a situation, the timing parameters in the specification cannot be guaranteed. It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. If this can't be guaranteed by the system calibration procedure, re-calibration policy and uncertainty with DQ to DQ variation, it is recommend that only the default values to be used. The nominal maximum ad minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. 64 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Full Strength Calibrated Pulldown Driver Characteristics Nominal Minimum Normal Low Nominal Normal High Nominal Maximum (21 Ohms) (18.75 Ohms) (18 ohms) (17.25 Ohms) (15 Ohms) 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 Voltage (V) The driver characteristics evaluation conditions are: Nominal 25 (Tcase) , VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25 (Tcase), VDDQ = 1.8V, any process Nominal Minimum Toper(max), VDDQ = 1.7 V, any process Nominal Maximum 0(Tcase), VDDQ = 1.9 V, any process Full Strength Calibrated Pullup Driver Characteristics Nominal Minimum Normal Low Nominal Normal High Nominal Maximum (21 Ohms) (18.75 Ohms) (18 ohms) (17.25 Ohms) (15 Ohms) 0.2 -9.5 -10.7 -11.4 -11.8 -13.3 0.3 -14.3 -16.0 -16.6 -17.4 -20.0 0.4 -18.7 -21.0 -21.6 -23.0 -27.0 Voltage (V) The driver characteristics evaluation conditions are: Nominal 25 (Tcase) , VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25(Tcase), VDDQ = 1.8V, any process Nominal Minimum Toper(max), VDDQ = 1.7 V, any process Nominal Maximum 0 (Tcase), VDDQ = 1.9 V, any process 65 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Symbol CCK CDCK CI CDI Parameter Input capacitance, CK and Input capacitance delta, CK and Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins -3C/3CI -AC/ACI -BE -BD Units min. max. min. max. min. max. min. max. 1.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 pF - 0.25 - 0.25 - 0.25 - 0.25 pF 1.0 2.0 1.0 1.75 1.0 1.75 1.0 1.75 pF - 0.25 - 0.25 - 0.25 - 0.25 pF 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 pF - 0.5 - 0.5 - 0.5 - 0.5 pF Input/output capacitance, CIO DQ, DM, DQS, Input/output capacitance delta, CDIO DQ, DM, DQS, 66 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Power & Ground Clamp V-I Characteristics Power and Ground clamps are provided on address (A0~A13, BA0, BA1, BA2), , , , WE, CKE, and ODT pins. The V-I characteristics for pins with clamps is shown in the following table Voltage across Minimum Power Minimum Ground clamp (V) Clamp Current (mA) Clamp Current (mA) 0.0 0.0 0.0 0.1 0.0 0.0 0.2 0.0 0.0 0.3 0.0 0.0 0.4 0.0 0.0 0.5 0.0 0.0 0.6 0.0 0.0 0.7 0.0 0.0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0 67 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM IDD Specifications and Measurement Conditions IDD Specifications (VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) Symbol IDD0 IDD1 Parameter/Condition I/O -3C/-3CI -AC/-ACI -BE -BD x8 60 65 75 75 x16 65 70 80 80 x8 75 85 100 100 x16 90 110 130 130 Operating Current Operating Current Unit Notes mA 1,2 mA 1,2 IDD2P Precharge Power-Down Current All 6 6 6 6 mA 1,2 IDD2N Precharge Standby Current All 40 45 50 50 mA 1,2 IDD2Q Precharge Quiet Standby Current All 45 50 55 55 mA 1,2 MRS(12)=0 All 25 30 35 35 mA 1,2 IDD3P Active Power-Down Standby Current MRS(12)=1 All 11 11 11 11 mA 1,2 x8 35 45 55 55 mA 1,2 x16 55 60 70 70 /x8 100 115 130 130 mA 1,2 x16 130 160 180 180 x8 100 120 155 155 mA 1,2 x16 130 190 250 250 /x8 140 155 180 180 mA 1,2 x16 190 200 210 210 All 6 6 6 6 mA 1,2 /x8 200 220 250 250 mA 1,2 x16 230 260 320 320 IDD3N IDD4R IDD4W IDD5 Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current IDD6 Self-Refresh Current for standard products IDD7 Operating Current 68 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM IDD Measurement Conditions (VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W Operating Current - One bank Active - Read - Precharge IOUT = 0 mA; BL = 4, tCK = tCKmin, tRC = tRCmin; tRAS = tRASmin; tRCD = tRCDmin, CL = CLmin.;AL = 0; CKE is HIGH, is HIGH between valid commands;Address bus inputs are SWITCHING,Data bus inputs are SWITCHING; Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.; Other control and address inputs are STABLE, Data Bus inputs are FLOATING. Precharge Standby Current: All banks idle; is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address bus inputs are SWICHTING; Data bus inputs are SWITCHING. Precharge Quiet Standby Current:All banks idle; is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "0"( Fast Power-down Exit); Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "1"( Slow Power-down Exit); Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax.; tRP = tRPmin., CKE is HIGH; is HIGH between valid commands; Other control and address inputs are SWITCHING; Data Bus inputs are SWITCHING. Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin., CKE is HIGH, is HIGH between valid commands; Address inputs are SWITCHING; Data bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.;CKE is HIGH, is HIGH between valid commands; Address inputs are SWITCHING; Data Bus inputs are SWITCHING. IDD5 Auto-Refresh Current: tRC = tRFC(min) which is 8 * tCK for DDR200 at tCK = 10 ns, 10 * tCK for DDR266 at tCK = 7.5 ns; 12 * tCK for DDR333 at tCK = 6ns; 14 * tCK for DDR400 at tCK = 5ns IDD6 Self-Refresh Current: CKE <= 0.2V; external clock off, CK and at 0V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING. IDD7 Operating Bank Interleave Read Current: 1. All bank interleaving reads; IOUT = 0 mA, BL =4, CL = CLmin., AL = tRCDmin. - 1*tCK; tCK = tCKmin., tRC = TRCmin.; tRRD = tRRDmin; tRCD = 1*tCK, CKE = HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTS. 2. Timing pattern: - DDR2 -667 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D - DDR2 -800 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D - DDR2 -1066 6-6-6: A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D 3. Legend : A=Activate, RA=Read with Auto-Precharge, D=DESELECT 1. 2. 3. 4. IDD specifications are tested after the device is properly initialized. IDD parameter are specified with ODT disabled. Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS. Definitions for IDD : LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.); STABLE is defined as inputs are stable at a HIGH or LOW level FLOATING is defined as inputs are VREF = VDDQ / 2 SWITCHING is defined as: Inputs are changing between HIGH and LOW every other clock (once per two clocks) for adress and control signals, and inputs changing between HIGH and LOW every other clock (once per two clocks) for DQ signals not including mask or strobes 5. Timing parameter minimum and maximum values for IDD current measurements are defined in the following table. 69 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM IDD Measurement Conditions (cont'd) For testing the IDD parameters, the following timing parameters are used: Symble -3C/-3CI -AC/-ACI -BE -BD Units Latency CL 5 5 7 6 tCK(avg) Clock Cycle Time tCK 3 2.5 1.875 1.875 ns tRCD 15 12.5 13.125 11.25 ns tRC 60 57.5 58.125 56.25 ns 7.5 7.5 7.5 7.5 10 10 10 10 tRASmin 40 40 40 40 tRASmax 70000 70000 70000 70000 tRP 15 12.5 13.125 11.25 Parameter Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B x8 tRRD command delay x16 ns Active to Precharge Command Precharge Command Period ns ns Refresh parameters Parameter Symbol Component Type 512Mb Unit tRFC All 105 ns Auto-Refresh to Active / Auto-Refresh command period (0Tcase85) 7.8 (85Tcase95) 3.9 (-40Tcase95) 7.8 Standard Grade Average periodic Refresh interval tREFI Industry Grade s s 70 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Electrical Characteristics & AC Timing - Absolute Specification Timing Parameter by Speed Grade (VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V) -3C/-3CI Symbol -AC/-ACI -BE -BD Parameter Units Min. Max. Min. Max. Min. Max. Min. Max. tCK(avg) Clock cycle time, CL=x, (Average) 3000 8000 2500 8000 1875 8000 1875 8000 tCH(avg) CK, high-level width (Average) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK(avg) tCL(avg) CK, low-level width (Average) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK(avg) WL tDQSS Write command to DQS associated clock edge RL-1 DQS latching rising transitions to associated clock edges ps nCK -0.25 0.25 -0.25 0.25 -0.25 0.25 -0.25 0.25 tCK(avg) tDSS DQS falling edge to CK setup time 0.2 - 0.2 - 0.2 - 0.2 - tCK(avg) tDSH DQS falling edge hold time from CK 0.2 - 0.2 - 0.2 - 0.2 - tCK(avg) 0.35 - 0.35 - 0.35 - 0.35 - tCK(avg) tDQSL,H DQS input low (high) pulse width tWPRE Write preamble 0.35 - 0.35 - 0.35 - 0.35 - tCK(avg) tWPST Write postamble 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK(avg) tIS Address and control input setup time 200 - 175 - 125 - 125 - ps tIH Address and control input hold time 275 - 250 - 200 - 200 - ps tIPW Address and control input pulse width (each input) 0.6 - 0.6 - 0.6 - 0.6 - tCK(avg) tDS DQ and DM input setup time differential 100 - 50 - 0 - 0 - ps tDH DQ and DM input hold time differential 175 - 125 - 75 - 75 - ps 71 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM -3C/-3CI Symbol -AC/-ACI -BE -BD Parameter Units Min. Max. Min. Max. Min. Max. Min. Max. 0.35 - 0.35 - 0.35 - 0.35 - tCK(avg) -450 450 -400 400 -350 350 -350 350 ps -400 400 -350 350 -325 325 -325 325 ps - tAC,max - tAC,max - tAC,max - tAC,max ps tLZ(DQS) DQS() low-impedance time from CK / tAC,min tAC,max tAC,min tAC,max tAC,min tAC,max tAC,min tAC,max ps DQ and DM input pulse width tDIPW (each input) tAC DQ output access time from CK / tDQSCK DQS output access time from CK / tHZ Data-out high-impedance time from CK / 2x 2x tLZ(DQ) DQ low-impedance time from CK / tAC,max tAC,min 2x tAC,max tAC,min 2x tAC,max tAC,min tAC,max ps 175 ps - ps 250 ps - ps tAC,min DQS-DQ skew tDQSQ - 240 - 200 - 175 - (for DQS & associated DQ signals) Min tHP Clock half period Min (tCH(avg) - tCL(avg) ) tQHS Data hold skew factor - 340 Data output hold time from DQS - tCL(avg) ) tHP tQH (tCH(avg) Min - tQHS - tCL(avg) ) 300 tHP - (tCH(avg) Min - tCL(avg) ) 250 tHP - tQHS (tCH(avg) tHP - tQHS tQHS tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK(avg) tRPST Read postamble 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK(avg) - ns - ns Active bank A to Active bank B X8 7.5 7.5 tRRD command period tFAW X16 10 X8 37.5 Four Activate Window 10 50 7.5 - 10 35 - X16 7.5 - 10 35 - 45 35 - 45 45 tCCD A to B command period 2 - 2 - 2 - 2 - nCK tWR Write recovery time 15 - 15 - 15 - 15 - ns 72 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM -3C/-3CI Symbol -AC/-ACI -BE -BD Parameter Units Min. Auto-Precharge write recovery Max. WR + tDAL Min. Min. Max. - WR + tnRP - WR + - + precharge time Max. tnRP Min. Max. WR + tnRP - nCK tnRP Internal Write to Read command tWTR 7.5 - 7.5 - 7.5 - 7.5 - ns 7.5 - 7.5 - 7.5 - 7.5 - ns 3 - 3 - 3 - 3 - nCK - tRFC + 10 - tRFC + 10 - - ns delay Internal Read to Precharge tRTP command delay CKE minimum high and low pulse tCKE width Exit Self-Refresh to non-Read tRFC + tXSNR command tXSRD Exit Self-Refresh to Read command tRFC + 10 10 200 - 200 - 200 - 200 - nCK 2 - 2 - 3 - 3 - nCK 2 - 2 - 3 - 3 - nCK 7-AL - 8-AL - 10-AL - 10-AL - nCK 2 2 2 2 2 2 2 2 nCK Exit precharge power-down to any tXP valid command (other than NOP or Deselect) Exit power down to any valid tXARD command (other than NOP or Deselect) Exit active power-down mode to tXARDS Read command (slow exit, lower power) tAOND ODT turn-on delay tAC,max tAON ODT turn-on tAC,min tAC,max tAC,min + 0.7 tAC,max tAC,min tAC,max tAC,min + 0.7 + 2.575 2x 3x tCK(avg) tCK(avg) 2x 3x tAC,min tCK(avg) + tAC,min + tAONPD ODT turn-on (Power-Down mode) tAC,min + + +2 tAC,max + 2 tAC,min tCK(avg) + + 2 ns +2 tAC,max tAC,max +1 +1 1 tAOFD ODT turn-off delay 2.5 2.5 ODT turn-off tAC,min 2.5 2.5 2.5 tAC,max tAC,min 0.6 tAC,max + 1 tAC,max + tAOF ns + 2.575 2.5 tAC,max tAC,min + 0.6 2.5 2.5 tAC,max + tAC,min + 0.6 nCK ns 0.6 73 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM -3C/-3CI Symbol -AC/-ACI -BE -BD Parameter Units Min. Max. Min. 2.5 x Max. Min. 2.5 x Max. Min. 2.5 x Max. 2.5 x tAC,min tCK(avg) + tAC,min tCK(avg) + tAC,min tCK(avg) + tAC,min tCK(avg) + tAOFPD ODT turn-off (Power-Down mode) ns +2 tAC,max + +2 1 tAC,max + +2 1 tAC,max + +2 1 tAC,max + 1 tANPD ODT to power down entry latency 3 - 3 - 4 4 nCK tAXPD ODT power down exit latency 8 - 8 - 11 - 11 - nCK 2 - 2 - 2 - 2 - nCK 0 12 0 12 0 12 0 12 ns 0 12 0 12 0 12 0 12 ns - ns Mode register set command cycle tMRD time MRS command to ODT update tMOD delay tOIT OCD drive mode output delay Minimum time clocks remain ON tDELAY after CKE asynchronously drops LOW tIS + tCK(avg) + tIH tIS + - tCK(avg) + tIH tIS + - tCK(avg) + tIH tIS + - tCK(avg) + tIH 74 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM General Note 1 DDR2 SDRAM AC timing reference load The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally a coaxial transmission line terminated at the tester electronics. This reference load is also used for output slew rate characterization. The output timing reference voltage level for single ended signals is the cross point with VTT. The output timing reference voltage level for differential signals is the cross point of the true (e.g. DQS) and the complement (e.g. ) signal. General Note 2 Slew Rate Measurement Levels a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - ) output slew rate is measured between DQS = - 500mV and DQS - = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b) Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges and from Vref(dc) to VIL(ac),max for falling edges. For differential signals (e.g. CK - ) slew rate for rising edges is measured from CK - = - 250 mV to CK = + 500 mV (+ 250 mV to - 500 mV for falling edges). c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on , or between DQS and for differential strobe. General Note 3 DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as following 75 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM General Note 4 Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, . This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, , must be tied externally to VSS through a 20 to 10 k resistor to insure proper operation. General Note 5 AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions. General Note 6 All voltages are referenced to VSS. General Note 7 These parameters guarantee device behavior, but they are not necessarily tested on each device.. General Note 8 Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 76 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Specific notes for dedicated AC parameters Specific Note 1 User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. Specific Note 2 AL = Additive Latency. Specific Note 3 This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min) have been satisfied. Specific Note 4 A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency. Specific Note 5 Timings are specified with command/address input slew rate of 1.0 V/ns. See Specific Notes on derating for other slew rate values. Specific Note 6 Timings are specified with DQs, DM, and DQS's (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns. See Specific Notes on derating for other slew rate values. Specific Note 7 Timings are specified with CK/ differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode. See Specific Notes on derating for other slew rate values. Specific Note 8 Data setup and hold time derating. Data Setup (tDS) and Hold Time (tDH) Derating Table with differential data strobe DQS, Differential Slew Rate (-3C/-3CI/-AC/-ACI/-ACL/-BE/-BD) 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns DQ Slewrate (V/ns) D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH 1. 2.0 100 45 100 45 100 45 - - - - - - - - - - - - 1.5 67 21 67 21 67 21 79 33 - - - - - - - - - - 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - 0.9 - - -5 -14 -5 -14 7 -2 19 10 31 22 - - - - - - 0.8 - - - - -13 -31 -1 -19 11 -7 23 5 35 17 - - - - 0.7 - - - - - - -10 -42 2 -30 14 -18 26 -6 38 6 - - 0.6 - - - - - - - - -10 -59 2 -47 14 -35 26 -23 38 -11 0.5 - - - - - - - - - - -24 -89 -12 -77 0 -65 12 -53 0.4 - - - - - - - - - - - - -52 -140 -40 -128 -28 -116 All units in ps. 2. For all input signals the total Tds (setup time) and Tdh (hold time) required is calculated by adding the individual datasheet value to the derating value listed in the previous table 77 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Specific Note 9 tIS and tIH (input setup and hold) derating Input Setup (tIS) and Hold (tIH) Time Derating Table CK, Differential Slew Rate (-3C/-3CI/-AC/-ACI/-ACL/-BE/-BD) Units Command/Address Slew rate (V/ns) 2.0 V/ns 1.5 V/ns 1.0 V/ns D tIS D tIH D tIS D tIH D tIS D tIH 4.00 150 94 180 124 210 154 ps 3.50 143 89 173 119 203 149 ps 3.00 133 83 163 113 193 143 ps 2.50 120 75 150 105 180 135 ps 2.00 100 45 130 75 160 105 ps 1.50 67 21 97 51 127 81 ps 1.00 0 0 30 30 60 60 ps 0.90 -5 -14 25 16 55 46 ps 0.80 -13 -31 17 -1 47 29 ps 0.70 -22 -54 8 -24 38 6 ps 0.60 -34 -83 -4 -53 26 -23 ps 0.50 -60 -125 -30 -95 0 -65 ps 0.40 -100 -188 -70 -158 -40 -128 ps 0.30 -168 -292 -138 -262 -108 -232 ps 0.25 -200 -375 -170 -345 -140 -315 ps 0.20 -325 -500 -295 -470 -265 -440 ps 0.15 -517 -708 -487 -678 -457 -648 ps 0.10 -1000 -1125 -970 -1095 -940 -1065 ps Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VIH(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VIL(ac)max, If the actual signal is always earlier than the nominal slew rate line between shaded `dc to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded `dc to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value. Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (dc) max and the first crossing of Vref. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of Vref. If the actual signal is always later than the nominal slew rate line between shaded `dc to Vref region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to Vref region', the slew rate of a tangent line to the actual signal from the dc level to Vref level is used for derating value. 78 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM t S t t H S t H V DDQ V IH(ac) min dc to ac region V IH(dc) min dc to Vref region V REF dc to Vref region V IL(dc) max dc to ac region V IL(ac) max V SS Delta TFS Delta TRH t S t Delta TRS t H S Delta TFH t H V DDQ V IH(ac) min dc to ac region V IH(dc) min dc to Vref region V REF dc to Vref region V IL(dc) max dc to ac region V IL(ac) max V SS Delta TFS VIL(dc)max - VIL(ac)max Setup Slew Rate = Delta TFS VIH(dc)min - VIL(ac)min Setup Slew Rate = Delta TRS VREF - VIL(dc)max Hold Slew Rate = Hold Slew Rate = Delta TRH VIH(dc)min - VREF Delta TFH Delta TRH Delta TRS Delta TFH falling signal Se t u p t an g e n t S l e w= R a t e rising signal Se t u p t a n g e n t l i n e [ V I H ( d c ) mrising i n S l e w= R a t e signal D el t a TR S rising signal H o l dl e S w falling signal H o l dl e S w t an g e n t R a t e= li n e [ V I L ( d c ) mfalling a x signal VI L (a c )m a x D e l t a T FS li n e D e l ta [ R EF - T R H VI L ( a c)m i n V I rising L ( d c)m a x ] signal t a n g e n t l i n e [ V I H ( d c ) m falling i n R a t e= signal D e lt a TF H VR EF] Specific Note 10 The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. Specific Note 11 MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH 79 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces. Specific Note 12 tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. Specific Note 13 tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. Specific Note 14 tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer,round up to the next highest integer. tCK refers to the application clock period. Example: For DDR533 at tCK = 3.75ns with WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. Specific Note 15 The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required. Specific Note 16 ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. Specific Note 17 ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges. Specific Note 18 tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .The following figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. tLZ(DQ) refers to tLZ of the DQ's and tLZ(DQS) refers to tLZ of the (U/L/R)DQS and each treated as single-ended signal. Specific Note 19 tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). The following figure 80 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. Specific Note 20 Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, signals must be monotonic between Vil(dc)max and Vih(dc)min. Specific Note 21 Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied to the device under test. DQS,signals must be monotonic between Vil(dc)max and Vih(dc)min. Specific Note 22 Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. Specific Note 23 Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test. 81 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Specific Note 24 tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency. Specific Note 25 Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. Specific Note 26 Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. Specific Note 27 tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges.CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. Specific Note 28 If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. Specific Note 29 These parameters are measured from a command/address signal (, , , , ,ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. Specific Note 30 These parameters are measured from a data strobe signal ((L/U/R)DQS/) crossing to its respective clock signal (CK/) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. Specific Note 31 These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS/) crossing. 82 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Specific Note 32 For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input clock jitter. Specific Note 33 tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in the mode register set. Specific Note 34 New units, `tCK(avg)' and `nCK', are introduced in DDR2-667 and DDR2-800. Unit `tCK(avg)' represents the actual tCK(avg) of the input clock under operation. Unit `nCK' represents one clock cycle of the input clock, counting the actual clock edges. ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2,even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min. Specific Note 35 Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply. The jitter specified is a random jitter meeting a Gaussian distribution. Input clock jitter spec parameter apply to DDR2-667, DDR2-800 and DDR2-1066 DDR2-667 Parameter DDR2-800 DDR2-1066 Symbol Units min max min max min max tJIT(per) -125 125 -100 100 -90 90 ps tJIT(per,lck) -100 100 -80 80 -80 80 ps tJIT(cc) -250 250 -200 200 -180 180 ps tJIT(cc,lck) -200 200 -160 160 -160 160 ps Cumulative error across 2 cycles tERR(2per) -175 175 -150 150 -132 132 ps Cumulative error across 3 cycles tERR(3per) -225 225 -175 175 -157 157 ps Cumulative error across 4 cycles tERR(4per) -250 250 -200 200 -175 175 ps Cumulative error across 5 cycles tERR(5per) -250 250 -200 200 -188 188 ps tERR(6-10per) -350 350 -300 300 -250 250 ps tERR(11-50per) -450 450 -450 450 -425 425 ps tJIT(duty) -125 125 -100 100 -75 75 ps Clock period jitter Clock period jitter during DLL locking period Cycle to cycle clock period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across n cycles,n = 6 ... 10, inclusive Cumulative error across n cycles,n = 11 ... 50, inclusive Duty cycle jitter 83 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Definitions: - tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window. - tCH(avg) and tCL(avg) tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses. tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses. - tJIT(duty) tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg). tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} where, tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200} tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200} - tJIT(per), tJIT(per,lck) tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing. - tJIT(cc), tJIT(cc,lck) tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of |tCKi+1 - tCKi| tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. 84 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing. - tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per) tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg). Specific Note 36 These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (min and max of SPEC values are to be used for calculations in the table below.) Parameter Symbol min max Units Absolute clock period tCK(abs) tCK(avg),min + tJIT(per),min tCK(avg),max + tJIT(per),max ps tCH(avg),max x tCK(avg),max + Absolute clock HIGH pulse width tCH(abs) tCH(avg),min x tCK(avg),min +tJIT(duty),min ps tJIT(duty),max tCL(avg),min x tCK(avg),min + tCL(avg),max x tCK(avg),max + tJIT(duty),min tJIT(duty),max Absolute clock LOW pulse width tCL(abs) ps Example: For DDR2-667, tCH(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps Specific Note 37 tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = Min ( tCH(abs), tCL(abs) ), where, tCH(abs) is the minimum of the actual instantaneous clock HIGH time; tCL(abs) is the minimum of the actual instantaneous clock LOW time; Specific Note 38 tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers Specific Note 39 tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye 85 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. Specific Note 40 When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps and tERR(610per),max = + 293 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 400 ps - 293 ps = 693 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(6-10per),min = 400 ps + 272 ps = + 672 ps. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ),min(derated) = - 900 ps - 293 ps = - 1193 ps and tLZ(DQ),max(derated)= 450 ps + 272 ps = + 722 ps. (Caution on the min/max usage!) Specific Note 41 When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 ps and tJIT(per),max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 ps = + 2178 ps and tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 93 ps = + 2843 ps. (Caution on the min/max usage!) Specific Note 42 When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 ps and tJIT(duty),max = + 93ps, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 ps = + 928 ps and tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 93 ps = + 1592 ps. (Caution on the min/max usage!) Specific Note 43 When the device is operated with input clock jitter, this parameter needs to be derated by { tJIT(duty),max - tERR(6-10per),max } and { - tJIT(duty),min - tERR(6-10per),min } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps, tERR(610per),max = + 293 ps, tJIT(duty),min = - 106 ps and tJIT(duty),max = + 94 ps, then tAOF,min(derated) = tAOF,min+ { - tJIT(duty),max - tERR(6-10per),max } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and tAOF,max(derated) =tAOF,max + { - tJIT(duty),min - tERR(6-10per),min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps. (Caution on the min/max usage!) Specific Note 44 For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg), average input clock HIGH pulse width of 0.5 relative to tCK(avg). tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtracting 86 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM 0.02 x tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the tAOF,max should be derated by adding 0.02 x tCK(avg) to it. Therefore, we have; tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH(avg),min)] x tCK(avg) tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH(avg),max) - 0.5] x tCK(avg) or tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH(avg),min] x tCK(avg)) tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH(avg),max - 0.5] x tCK(avg)) where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at the DRAM input balls. Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6-10per). However tAC values used in the equations shown above are from the timing parameter table and are not derated. Thus the final derated values for tAOF are; tAOF,min(derated_final) = tAOF,min(derated) + { - tJIT(duty),max - tERR(6-10per),max } tAOF,max(derated_final) = tAOF,max(derated) + { - tJIT(duty),min - tERR(6-10per),min } 87 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Overshoot and Undershoot Specification AC Overshoot / Undershoot Specification for Address and Control Pins Parameter -3C/-3CI -AC/-ACI -BE -BD Units Maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 0.5 V Maximum peak amplitude allowed for undershoot area 0.5 0.5 0.5 0.5 V Maximum overshoot area above VDD 0.8 0.66 0.66 0.66 V-ns Maximum undershoot area below VSS 0.8 0.66 0.66 0.66 V-ns Maximum Amplitude Volts (V) Overshoot Area VDD VSS Undershoot Area Maximum Amplitude Time (ns) AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter -3C/-3CI -AC/-ACI -BE -BD Units Maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 0.5 V Maximum peak amplitude allowed for undershoot area 0.5 0.5 0.5 0.5 V Maximum overshoot area above VDD 0.23 0.23 0.23 0.23 V.ns Maximum undershoot area below VSS 0.23 0.23 0.23 0.23 V.ns Maximum Amplitude Volts (V) Overshoot Area VDDQ VSSQ Maximum Amplitude Undershoot Area Time (ns) 88 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Package Dimensions (x4/x8; 60 balls; BGA Package) 60 Ball BGA 8 .00+/-0.10 Pin A1 Index 6 .40 10.00 +/- 0.10 8 . 00 0.80 0.80 Dia. Min 0.40 Max0.50 0. 10 Max. Min0.10 Min 0.10 0. 40 Max. 0. 25 Min. 1. 20 Max. Unit: Millimeters Note : All dimensions are typical unless otherwise stated 89 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Package Dimensions (X16; 84 balls; BGA Package) 84 Ball BGA 8 .00+/-0.10 Pin A1 Index 6.40 12.50 +/- 0.10 11. 20 0.80 0.80 Dia. Min 0.40 Max0.50 0. 10 Max. 0. 40 Max. 0. 25 Min. 1. 20 Max. Min 0.10 Min 0.10 Unit: Millimeters Note: All dimensions are typical unless otherwise stated. 90 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TU64M8DE / NT5TU32M16DG 512Mb DDR2 SDRAM Revision Log Rev Date Modification 0.1 06/2010 Preliminary Release 0.2 07/2010 Revised Block Diagram Description 0.3 09/2010 Revised Description, Electrical Characteristics, tFAW, the feature of -BE, and ordering information 0.4 09/2010 Revised tRRD 0.5 10/2010 Updated CAS Latency Frequency Table 0.6 11/2010 Revised Refresh Parameter Component Type 1.0 12/2010 Official Release 1.1 02/2011 Revised 60 balls BGA Package Pin Configuration and -BD tCK parameters 1.2 04/2011 Removed x8/1066 Part Number from Ordering Information 1.3 05/2011 Revised Note Description of Operating Temperature Range and Table of Bank Selection for Prechange by Address Bit 1.4 08/2011 Revised the number bit of address bus 1.5 12/2011 Added TC and TOPER relation into the description of Operating Temperature 1.6 12/2011 Revised Self Refresh Exit in the Command Truth Table 1.7 07/2012 Added General Note and Specific Note from the page 75 to the page 87 1.8 02/2013 Modified tRAS. 91 REV 1.8 02/2013 (c) NANYA TECHNOLOGY CORP . All rights reserved NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.