2White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WMS128K8-XXX
September 2002
Rev. 5
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
DC CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol Conditions -15 -17 -20 -25 -35 -45 -55 Units
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 10 10 10 10 10 10 µA
Output Leakage Current ILO CS# = VIH, OE# = VIH, VOUT = GND to VCC 10 10 10 10 10 10 10 µA
Operating Supply Current ICC CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5 150 150 150 150 150 150 150 mA
Standby Current ISB CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 20202015151515mA
Output Low Voltage VOL IOL = 2.1mA, VCC = 4.5 0.4 0.4 0.4 0.4 0.4 0.4 0.4 V
Output High Voltage VOH IOH = -1.0mA, VCC = 4.5 2.4 2.4 2.4 2.4 2.4 2.4 2.4 V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Unit
Operating Temperature TA-55 +125 °C
Storage Temperature TSTG -65 +150 °C
Signal Voltage Relative to GND VG-0.5 VCC+0.5 V
Junction Temperature TJ150 °C
Supply Voltage VCC -0.5 7.0 V
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
Supply Voltage VCC 4.5 5.5 V
Input High Voltage VIH 2.2 VCC + 0.3 V
Input Low Voltage VIL -0.5 +0.8 V
Operating Temp. (Mil.) TA-55 +125 °C
TRUTH TABLE
CS# OE# WE# Mode Data I/O Power
H X X Standby High Z Standby
L L H Read Data Out Active
L X L Write Data In Active
L H H Out Disable High Z Active
CAPACITANCE
TA = +25°C
Parameter
Symbol
Condition Package Speed (ns) Max Unit
Input capacitance CIN
VIN = 0V, f = 1.0MHz
32 Pin CSOJ, DIP, Flat Pack Evolutionary 15 to 55 20 pF
36 Pin Flat Pack and 15 to 25 12 pF
32 Pin CSOJ Revolutionary 35 to 55 20 pF
Output capicitance COUT
VOUT = 0V, f = 1.0MHz
32 Pin CSOJ, DIP, Flat Pack Evolutionary 15 to 55 20 pF
36 Pin Flat Pack and 15 to 55 12 pF
32 Pin CSOJ Revolutionary 35 to 55 20 pF
32 Pin CLCC 15 to 55 15 pF
This parameter is guaranteed by design but not tested.