TSM2N7002ED 1-5 2004/12 rev. B
TSM2N7002ED
50V Dual N-Channel Enhancement Mode MOSFET
VDS = 50V
RDS (on), Vgs @ 10V, Ids @ 250mA = 3
RDS (on), Vgs @ 5V, Ids @ 50mA = 4
Ordering Information
Part No. Packing Package
TSM2N7002EDCU6 T & R (3kpcs/Rell) SOT-363
Features
Dual N-channel in package.
Advanced trench process technology
High density cell design for ultra low on-resistance
High input impedance
High speed switching
No minority carrier storage time
CMOS logic compatible input
No secondary breakdown
Compact and low profile SOT-363 package
Block Diagram
Absolute Maximum Rating (Ta = 25oC unless otherwise noted)
Parameter Symbol Limit Unit
Drain-Source Voltage VDS 50 V
Gate-Source Voltage VGS ± 20 V
Continuous Drain Current ID 250 mA
Pulsed Drain Current IDM 1.0 A
Ta = 25 oC 200 Maximum Power Dissipation
Ta = 75 oC
PD
150
mW
Operating Junction Temperature TJ +150
oC
Operating Junction and Storage Temperature Range TJ, TSTG - 55 to +150 oC
Thermal Performance
Parameter Symbol Limit Unit
Lead Temperature (1/8” from case) TL 5 S
Junction to Ambient Thermal Resistance (PCB mounted) Rθja 625
oC/W
Note: Surface mounted on FR4 board t<=5sec.
Pin assignment:
1. Source (2) 6. Drain (2)
2. Gate (2) 5. Gate (1)
3. Drain (1) 4. Source (1)