Part Number 460EX
Revision 1.19 – June 17, 2009
AMCC Proprietary 1
460EX
PowerPC 460EX Embedded Processor
Prelimin ary Data Sheet
Features
•PowerPC
® 440 processor operating between
600MHz and 1.000GHz with 32KB I-cache and D-
cache and 256KB L2/SRAM with parity checking
• On-chip memory (64KB)
• Floating Point Unit
• Processor Local Bus (PLB) with 128-bit width
• Double Data Rate 2/1 (DDR2/1) Synchronous
DRAM (SDRAM) interface
• One four-channel DMA (Direct Memory Access)
for internal and external peripherals
• One single-channel, high-performance DMA for
internal use
• External 32-bit peripheral bus (EBC) for up to six
devices. Up to 100MHz
• Programmable Interrupt Controller (UIC) with up
to 16 external interrupts
• Programmable Genera l Purpose Timers (GPTs)
• Two PCI Express 1.1 interfaces—one 4-lane and
one 1-lane
• PCI V2.3 interface. Thirty-two bits at up to 66MHz
• Two Ethernet 10/100/1000Mbps half- or full-
duplex interfaces. Operational modes supported
are MII, GMII, RGMII, and SGMII with QoS,
Jumbo frames, interrupt coalescing, and TCP/IP
acceleration
• Up to four serial (UART) ports (16750 compatible)
• USB 2.0 Host/Device OTG and Host interface
• Two IIC interfaces (one with boot parameter read
capability)
• NAND Flash interface
• SPI interface
•SATA controller
• General Purpose I/O (GPIO) interface
• JTAG interface for board level testing
• Boot from PCI memory, NOR Flash on the
external peripheral bus, or NAND Flash on the
NAND Flash interface
• Optional security feature with KASUMI
• Available in RoHS compliant, lead-free package
Description
Designed specifically to address high-end embedded
applications, the PowerPC 460EX (PPC460EX)
provides a high-performance, low-power solution that
interfaces to a wide range of peripherals and
incorporates on-chip power management features.
This chip contains a high-performance RISC
processor, on-chip memory, a floating point unit, a
DDR2/1 SDRAM controller, PCI and PCI Express bus
interfaces, control for external ROM and peripherals,
DMA with scatter/gather support, Ethernet ports, serial
ports, IIC interfaces, SPI interface, USB ports, NAND
Flash interface, SATA interface, an optional security
feature with KASUMI, and general purpose I/O.
Technology: CMOS Cu-08, 90nm.
Package: 35mm, 728-ball thermally and electrically
enhanced plastic ball grid array (TE-EPBGA). RoHS
compliant package available.
Typical power: Less than 5W at 1GHz with DDR2.
Supply voltages required: 3.3V, 2.5V (DDR1,
Ethernet), 1.8V (DDR2), 1.2V.
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
2 AMCC Proprietary
Revision 1.19 – June 17, 2009
Contents
Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PPC460EX Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PowerPC 440 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
L2 Cache/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
On-Chip Memory (OCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Security Function (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PCI Express Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DDR2/1 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DMA 4-Channel Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I2O/DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Ports (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
IIC Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial Peripheral Controller (SPI/SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Universal Serial Bus 2.0 (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Assembly Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DDR2/1 SDRAM Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
PCI Express Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Serial ATA (SATA) Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PCI-E and SATA Reference Clock AC Coupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Revision Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 3
Prelim inary Data Sheet
Figures
Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. PPC460EX Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. 35mm, 728-Ball TE-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 5. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 6. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 7. Setup and Hold Timing Waveforms for RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 8. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 9. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 10. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 11. LVDS PCIe or SATA Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 12. LVPECL PCIe or SATA Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 13. CML PCIe or SATA Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 14. HCSL PCIe or SATA Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
4 AMCC Proprietary
Revision 1.19 – June 17, 2009
Tables
Table 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Recommended Reflow Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. JEDEC Moisture Sensitivity Level and Ball Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 7. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 8. Non-Functional Ball Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 9. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 10. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 11. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 12. 3.3V, 2.5V, and LVDS I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 13. Typical DC Power Supply Requirements Using DDR2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 14. Typical DC Power Supply Requirements Using DDR1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 16. Maxiumum DC Power Supply Requirements Using DDR1 Memory . . . . . . . . . . . . . . . . . . . . . . 78
Table 15. Maxiumum DC Power Supply Requirements Using DDR2 Memory . . . . . . . . . . . . . . . . . . . . . . 78
Table 17. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 18. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 19. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 20. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 21. RGMII I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 22. AC I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 23. DDR I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 24. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 25. DDR SDRAM Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 26. I/O Timing—DDR SDRAM TDS for 200 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 27. I/O Timing—DDR SDRAM TSA, and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 28. I/O Timing—DDR SDRAM Write Timing TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 29. I/O Timing—DDR SDRAM Read Timing TSD and THD for 200MHz . . . . . . . . . . . . . . . . . . . . . . 96
Table 30. PCI Express Transmitter Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 31. PCI Express Receiver Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 32. PCI Express Reference Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 33. SATA Transmitter Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 34. SATA Receiver Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 35. SATA Reference Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 36. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 5
Prelim inary Data Sheet
Ordering and PVR Information
For information on the availability of the following parts, contact your local AMCC sales office. For additional
information on the part number structure see Fi gur e 1.
Each part number contains a revision code. This is the die mask revision number and is included in the part
number for identification purposes only.
The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain
information that uniquely identifies the part. Refer to the PowerPC 460EX/EXr/GT Embedded Processor User’s
Manual for details on accessing these registers.
Figure 1. Orde r Part Numb er Key
Product Name Order Part Number
(see Notes)Package Revision
Level PVR Value JTAG ID
PPC460EX PPC460EX- opA fff(f)T 35mm 728-ball TE-EP BGA A 0x130218A2 0x144101E1
PPC460EX PPC460EX- opB fff(f)T 35mm 728-ball TE-EP BGA B 0x130218A4 0x144101E1
Notes: Characters following the dash (-):
1. o = Security option: S = security feature present, N = no security
2. p = Package type: U = lead-free (RoHS compliant), T = contains lead.
3. A = Chip revision level A, B = Chip revision level B
4. ff f(f) = Processor frequency: = 600 = 600MHz, = 800 = 800MHz, fff f = 1000 = 1GHz
5. T = Case temperature range of −40°C to +85°C.
AMCC Part Number
PPC460EX-SUB1000T
Package
Processor Frequency
Case Temperature Range
Revision Level
Securi ty Fe ature
Note:
The example P/N above contains the security feature, is lead-free, is capable of running at 1GHz, and is shipped
in a tray (tape-and-reel packaging is not available).
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
6 AMCC Proprietary
Revision 1.19 – June 17, 2009
Block Diagram
Figure 2. PPC460EX Functional Block Diagram
The PPC460EX is a system on a chip (SOC).
Processor DCR Bus
32KB
On-chip Peripheral Bus ( O PB) –3 2 bits, 100MHz
GPIO
DMA
Proces sor Local Bus (PL B)–128 bits, 200MH z
External
Bus
Controller
Clock
Control
Reset
Power
Mgmt
JTAG Trace
Timers
MMU
Cntl
OPB
Arb
D-Cache
32KB
I-Cache (4-Ch)
SRAM
Cntl
PPC440
Ethernet
DCRs
ZMIIRGMII
256KB L2 Cache
TAH/QoS
10/100/1000
x2
Bridge Bridge
UART
x4 IIC(x2)
BSC SPI
NAND
Flash
Controller
MAL w/
Int. Coalescing
PCI-Express
Memory
PCI-E1
PCI-E0
Queue
PCI
4 lanes
32-bit
64 + 8
DDR 1 and 2
SDRAM Cntrlr
33/66 MH z
M0 M1 M4 M6
M10
Arb
S3
S4
M2
M3
S1
S3
M5
Low Latency (LL) Segment
High Bandwidth (HB) Segment
Int
Hand
S2 S0
S0
(x1) (x4)
HSS x1/x4
1 lane
HSS x1
OCM
64KB
S2 S7
TRNG/
PKA
S5
M7
S1
HSDMA
Cntl
Bridge
M8
S4
M9
GPT
Security
Engine
FPU
External
16
Interrupts
UIC
PLB-to-AHB
Bridge
AHB Bus–32 bits, 200 MHz Arb
M11
S6
DMA
Cntl USB 2.0
OTG
Cntl
USB 2.0
Host
Cntl
M1
ICM
SATA ULPI SDR
Interface
SGMII
S6
S1
M1
Sn = Slave n
Mn = Master n
w/KASUMI
x2
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 7
Prelim inary Data Sheet
Address Ma ps
The PPC460EX incorporates two address maps. The first is a fixed processor System Memory Address Map. This
address map defines the possible contents of various address regions which the processor can access. The
second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software
running on the PPC460EX processor through the use of mtdcr and mfdcr instructions.
Table 1. System Memory Address Map (Part 1 of 3)
Function Sub Function Start Address End Address Size
Local Memory (LL)1
DDR SDRAM 0000 0000 0000 0000 0000 0003 FFFF FFFF 16GB
SRAM (L2 Cache) 0000 0004 0000 0000 0000 0004 0003 FFFF 256KB
On-Chip Memory (OCM ) 0000 0004 0004 0000 0000 0004 0004 FFFF 64KB
Reserved 0000 0004 0005 0000 0000 0004 000F FFFF 704KB
Internal PLB Interfaces (LL)1
I2O/DMA 0000 0004 0010 0000 0000 0004 0010 FFFF 64KB
I2O Registers 0000 0004 0010 0000 0000 0004 0010 00FF 256B
Reserved 0000 0004 0010 0100 0000 0004 0010 01FF 256B
HSDMA Registers 0000 0004 0010 0200 0000 0004 0010 02FF 256B
Reserved 0000 0004 0010 0300 0000 0004 0010 FFFF 63.25KB
PKA & TRNG (EIPPK P) 0000 0004 0011 0000 0000 0004 0011 FFFF 64KB
Reserved 0000 0004 0012 0000 0000 0004 0017 FFFF 384KB
Security Function (EIP94) 0000 0004 0018 0000 0000 0004 001F FFFF 512KB
Reserved 0000 0004 0020 0000 0000 0004 BFF 7 FFFF ~3GB
Internal AHB Peripherals (LL)
USB 2.0 OTG 0000 0004 BFF8 0000 0000 0004 BFFB FFFF 256KB
Reserved 0000 0004 BFFC 0000 0000 0004 BFFC FFFF 64KB
USB 2.0 Host (OHCI) 0000 0004 BFFD 0000 0000 0004 BFFD 03FF 1KB
USB 2.0 Host (EHCI) 0000 0004 BFFD 0400 0000 0004 BFFD 07FF 1KB
AHBDMA for SAT A 0000 0004 BFFD 0800 0000 0004 BFFD 0BFF 1KB
Reserved 0000 0004 BFFD 0C00 0000 0004 BFFD 0FFF 1KB
SATA 0000 0004 BFFD 1000 0000 0004 BFFD 17FF 2KB
Reserved 0000 0004 BFFD 1800 0000 0004 BFFD 1FFF 2KB
AHB Arbiter 0000 0004 BFFD 2000 0000 0004 BFFD 23FF 1KB
Reserved 0000 0004 BFFD 2400 0000 0004 BFFF FFFF 183KB
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Internal OPB Peripherals (LL)
EBC Memory exce pt Bank 0 60 000 0004 C000 0000 0000 0004 E7FF FFFF 640MB
Reserved 0000 0004 E800 0000 0000 0004 EF5F FFFF 118MB
General Purpose Timer 0000 0004 EF60 0000 0000 0004 EF60 01FF 512B
Reserved 0000 0004 EF60 0200 0000 0004 EF60 02FF 256B
UART0 0000 0004 EF60 0300 0000 0004 EF60 0307 8B
Reserved 0000 0004 EF60 0308 0000 0004 EF60 03FF 248B
UART1 0000 0004 EF60 0400 0000 0004 EF60 0407 8B
Reserved 0000 0004 EF60 0408 0000 0004 EF60 04FF 248B
UART2 0000 0004 EF60 0500 0000 0004 EF60 0507 8B
Reserved 0000 0004 EF60 0508 0000 0004 EF60 05FF 248B
UART3 0000 0004 EF60 0600 0000 0004 EF60 0607 8B
Reserved 0000 0004 EF60 0608 0000 0004 EF60 06FF 248B
IIC0 0000 0004 EF60 0700 0000 0004 EF 60 071F 32B
Reserved 0000 0004 EF60 0720 0000 0004 EF60 07FF 224B
IIC1 0000 0004 EF60 0800 0000 0004 EF 60 081F 32B
Reserved 0000 0004 EF60 0820 0000 0004 EF60 08FF 224B
SPI 0000 0004 EF60 0900 0000 0004 EF 60 090F 16B
Reserved 0000 0004 EF60 0910 0000 0004 EF60 09FF 240B
OPB Arbiter 0000 0004 EF60 0A00 0000 0004 EF60 0A3F 64B
Reserved 0000 0004 EF60 0A40 0000 0004 EF60 0AFF 192B
GPIO0 Controller 0000 0004 EF60 0B00 0000 0004 EF60 0B7F 128B
Reserved 0000 0004 EF60 0B80 0000 0004 EF60 0BFF 128B
GPIO1 Controller 0000 0004 EF60 0C00 0000 0004 EF60 0C7F 128B
Reserved 0000 0004 EF60 0C80 0000 0004 EF60 0CFF 128B
Ethernet PHY ZMII 0000 0004 EF60 0D00 0000 0004 EF60 0D0F 16B
Reserved 0000 0004 EF60 0D10 0000 0004 EF60 0DFF 240B
EMAC0 Controller 0000 0004 EF60 0E00 0000 0004 EF60 0EFF 256B
EMAC1 Controller 0000 0004 EF60 0F00 0000 0004 EF60 0FFF 256B
Reserved 0000 0004 EF60 1000 0000 0004 EF60 12FF 768B
TAHOE0 Accelerator 0000 0004 EF60 1300 0000 0004 EF60 13FF 256B
TAHOE1 Accelerator 0000 0004 EF60 1400 0000 0004 EF60 14FF 256B
RGMII0 Controller 0000 0004 EF60 1500 0000 0004 EF60 150F 16B
Reserved 0000 0004 EF60 1510 0000 0004 FEFF FFFF ~250MB
Boot ROM 2, 3 EBC Memory Bank 0 0000 0004 FF00 0000 0000 0004 FFFF FFFF 16MB
Internal PLB Interfaces (LL) Reserved 0000 0005 0000 0000 0000 0007 FFFF FFFF 12GB
Local Memory Alias (HB) Aliased DDR SDRAM 0000 0008 0000 0000 0000 000B FFFF FFFF 16GB
Table 1. System Memory Address Map (Part 2 of 3)
Function Sub Function Start Address End Address Size
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PCI/PCIE Space (HB)
PCI Express Memory 0000 000C 0000 0000 0000 000C 07FF FFFF 128MB
PCI I/O 0000 000C 0800 0000 0000 000C 0800 FFFF 64KB
PC Express Memory 0000 000C 0801 0000 0000 000C 087F FFFF ~8MB
PCI Extra I/O 0000 000C 0880 0000 0000 000C 0BFF FFFF ~56MB
PCI Express Memory 0000 000C 0C00 0000 0000 000C 0EBF FFFF ~44MB
PCI Configuration Registers 0000 000C 0EC0 0000 0000 000C 0EC0 0007 8B
Reserved 0000 000C 0EC0 0008 0000 000C 0EC7 FFFF ~512KB
PCI Local Registers 0000 000C 0EC8 0000 0000 000C 0EC8 11FF 4.75KB
Reserved 0000 000C 0EC8 1200 0000 000C 0ECF FFFF ~512KB
PCI Special Cycle 0000 000C 0ED0 0000 0000 000C 0ED0 0003 4B
Reserved 0000 000C 0ED0 0004 0000 000C 0FFF FFFF ~19MB
PCI Express Interrupt Handler 0000 000C 1000 0000 0000 000C 1000 00FF 256B
PCI, PCI Express Memory 0000 000C 1000 0100 0000 000C FEFF FFFF ~3.8MB
PCI Boot ROM (PCI Memory) 0000 000C FF00 0000 0000 000C FFFF FFFF 16MB
PCI, PCI Express Memory 0000 000D 0000 0000 0000 000F FFFF FFFF 12GB
Reserved 40000 0010 0000 0000 03FF FFFF FFFF FFFF
Reserved 50400 0000 0000 0000 0FFF FFFF FFFF FFFF
XOR Space (HB) XOR 1000 0000 0000 0000 1FFF FFFF FFFF FFFF
PCI/PCIE Space (HB) PCI, PCI Express Memory 2000 0000 0000 0000 FFFF FFFF FFFF FFFF
Notes:
1. DDR SDRAM, SRAM (L2 Cache) and On-Chip Memory (O CM) can be located anywhere in the Local Memory area of the memory
map.
2. The Boot ROM area of the memory map are intended for use by ROM or Flash-type devices. While locating volatile DDR SDRAM and
SRAM in this region is supported, use of these regions for this purpose is not recommended.
3. When the optional boot from PCI Memory is selected, the PCI Boot ROM address space begins at 0000 000C FF00 0000 (16 MB).
4. Never decoded.
5. Unpredictable results on Read and Write operations.
6. Accessed by means of EBC Peripheral Bank Configuration Registers.
Table 1. System Memory Address Map (Part 3 of 3)
Function Sub Function Start Address End Address Size
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Table 2. DCR Address Map
Function Base Address Start Address End Address Size
Total DCR Address Space1000 3FF 1KW (4KB)1
By function:
Reserved 000 00B 12W
Clocking Power On Reset (CPR) 00 0000 110x 00C 00D 2W
System DCRs (SDR) 00 0000 111x 00E 00F 2W
Memory Controller 00 0001 000x 010 011 2W
External Bus Controller (EBC) 00 0001 001x 012 013 2W
Reserved 014 01F 12W
L2 Cache as SRAM 00 0010 xxxx 020 02F 16W
L2 Controller 00 0011 xxxx 030 03F 16W
Memory Queue 00 010x xxxx 040 04F 16W
Reserved 050 05F 16W
I2O/DMA Controller 00 011x xxxx 060 07F 32W
PLB Arbiter 00 1000 xxxx 080 08F 16W
PLB-to-OPB Bridge 00 1001 xxxx 090 09F 16W
PLB-to-AHB Bridge 00 1010 xxxx 0A0 0AF 16W
On-Chip Memory (OCM) 00 1011 xxxx 0B0 0BF 16W
Universal Interrupt Controller 0 00 1100 xxxx 0C0 0CF 16W
Universal Interrupt Controller 1 00 1101 xxxx 0D0 0DF 16W
Universal Interrupt Controller 2 00 1110 xxxx 0E0 0EF 16W
Universal Interrupt Controller 3 00 1111 xxxx 0F0 0FF 16W
PCI Express 0 01 000x xxxx 100 11F 32W
PCI Express 1 01 001x xxxx 120 13F 32W
Reserved 140 15F 32W
Power Management 01 011x xxxx 160 167 8W
Reserved 168 17F 24W
Ethernet MAL 01 1xxx xxxx 180 1FF 128W
DMA Controller 10 00xx xxxx 200 23F 64W
Reserved 240 3FF 448W
Notes:
1. DCR addresses are 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One
kiloword (1024W) equals 4KB (4096 B).
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Prelim inary Data Sheet
PPC460EX Features
The following sections provide information on the features of the chip.
PowerPC 440 Pr o cess or
The PowerPC 440 processor (in 90nm technology) is designed for high-end applications: RAID controllers, SAN,
iSCSI, routers, switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture
and uses the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features inc l ude:
• Up to 1.000GHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache
– UTLB Word Wide parity on data and tag address parity with exception force
• Three logical regions in D-cache: locked, transient, normal
• D-cache full line flush capability
• 41-bit virtual address, 36-bit (64GB) physical address
• Superscalar, out-of-order execution
• 7-stage pip eli ne
• Three execution pipelines
• Dynamic branch prediction
• Memory management unit
– 64-entry, full associative, unified TLB with optional parity
– Separate instruction and data micro-TLBs
– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
• Debug facilities
– Multiple instruction and data range breakpoints
– Data value compar e
– Single step, branch, and trap events
– Non-invasive real-time trace interface
• 24 DSP instru cti ons
– Single cycle multiply and multiply-accumulate
– 32 x 32 integer multiply
– 16 x 16 -> 32-bit MAC
Floating Point Unit (FPU)
The chip has a built-in super scalar FPU that supports both single- and double-precision operations, and offers
single cycle through put on most instructions.
Features inc l ude:
• Five stages with 2 MFlops/MHz
• Hardware support for IEEE 754
• Single- and double-precision
• Single-cycle throughput on most instructions
• Thirty-two 64-bit floating point registers
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L2 Cache/SRAM
The PPC460EX also provides a 256KB L2 cache between the Processor Local Bus and the processor’s D- and
I-caches. This memory unit can be alternatively programmed to function as 256KB of SRAM.
Features inc l ude:
• Four banks of 64KB each
• Memory cycles supported:
– Single beat read and write, 1 to 16 bytes
– Quadword Read and Write burst for 12-bit master
– Guarded memory accesses on 4KB boundaries
• Sustainable 3.2GB/s peak bandwidth at 200MHz
• Use as an L2 cache improves processor performance and reduces the PLB load
– Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) Processor Local
Bus (PLB) or by software
– Data Array and Tag Array parity
– Unified data and instruction cache
– Four-way set associative
– 36-bit addressing
– Full LRU replacement algorithm
– Write through, look aside
On-Chip Memory (OCM)
The PPC460EX provides 64KB of on-chip memory.
Features inc l ude:
• Up to 128-bit bus width
• 128-bit slave attachment, addressable by any PLB master
• Transfers by PLB slave cycles:
– Single-beat read and write (1 to 8 bytes for 64-bit masters, 1 to 16 bytes for 128-bit masters)
– 4- and 8-word line reads and writes
– Double word read and write burst s for 64-bit masters
– Quadword read and write bursts for 128-bit masters
– Slave-terminated double word and quadword fixed length bursts
– Master-terminated variable length bursts
• Guarded memory access on 4KB boundaries
• Data parity checking
• Data transfers at PLB bus speeds
• Power management
• Use as storage area for DMA descriptors and packet data for processing by Ethernet and Security Function.
Internal Buses
The PowerPC 460EX features four standard internal buses: one Processor Local Bus (PLB), one On-chip
Peripheral Bus (OPB), the Advanced High-performance Bus (AHB), and the Device Control Register bus (DCR).
The high performance, high bandwidth functions such as the PowerPC 440 processor, the DDR SDRAM memory
controller, PCI Express, PCI, and the AHB bridge, connect to the PLB. The OPB hosts lower data rate peripherals.
The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the
processor and the other on-c hip cor es.
The PLB has a Crossbar arbiter that supports data transfer between the PLB master and two slave segments
identified as the Low Latency (LL) and High Bandwidth (HB) segments. The LL segment allows PLB masters CPU
and I2O, that are adversely affected by latency, to communicate with slave devices with minimal latency. The HB
segment allows PLB masters DMA, PCI and PCI Express to exchange large blocks of data with SDRAM, PCI and
PCI Express without interfering with the low latency PLB masters.
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Features inc l ude:
• PLB4 (128-bit)
– 128-bit implementation of the PLB archite cture
– Separate and simultaneous read and write data paths
– 64-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte-en able capabi li ty sup por ting unal ig ned trans fers
– 32- and 64-byte burst transfers
– 200MHz, maximum 12.8GB/s (simultaneous read and write)
– Pro cessor:bus clock ratios of N:1
•AHB
– 32-bit data path
– 32-bit address
– Synchron ous to the PLB
– Up to 200MHz, maximum 800MB/s
•OPB
– 32-bit data path with dynamic sizing for 32-, 16-, and 8-bit width
– 32-bit address
– 100MHz
• DCR
– 32-bit data path
– 10-bit address
Security Function (Optiona l)
The built-in security function is a cryptographic engine attached to the PLB with built-in DMA and interrupt
controllers.
Features inc l ude :
• Federal Information Processing Standard (FIPS) 140-2 design
• Support for an unlimited number of Security Associations (SA)
• Different SA formats for each supported protocol (IPsec/SSL/TLS/sRTP)
• Internet Protocol Security (IPSec) features
– Full packet transforms, Encapsulated Security Payload (ESP) and Authentication Header (AH)
– Complete header and trailer processing (IPv4 and IPv6)
– Multi-mode automatic padding
– "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers
– Extended Sequence Number (ESN) processing for ESP and AH
• Secure Socket Layer (SSL) and Transport Layer Security (TLS) features and Datagram Transport Layer
Security (DTLS) features
– Packet transfor ms
– One-pass hash-then-encrypt for SSL and TLS packet transforms for inbound packet using Stream Cipher
• Secure Real-Time Protocol (sRTP) featur es
– Packet transfor ms
– Roll Over Counter (ROC) removal and TAG insertion
– Variable bypass offset of header length per packet
• Media Access Control Security (MACSec) features
– MSDU (User data) encryption 0, 30, or 50 bytes offset
– Header insertion and removal
– SecTAG header with or without Secure Channel Identifier (SCI) field
– 128-bit key, 96-bit IV (nonce) and 128-bit ICV
– IV from SA record or from input buffer (as part of SecTAG)
– ICV generation and validation
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• SGT features:
– GCM-AES with 128-bit key, 96-bit IV (nonce) and 128-bit ICV
– SecTAG header with or without Secure Channel Identifier (SCI) field
– Replay protection "Strict order Mode" and "Out of Order Mode"
– Header insertion and removal
– ICV generation and validation
• IPsec/SSL security acceleration engine
• DES, 3DES, AES, ARC-4 encryption (no support for hashing of zero length messages)
• MD-5, SHA-1, and SHA-2 (224-, 256-, 384-, and 512-bit) hashing, HMAC encrypt-hash and hash-decrypt
• Public key acceleration (PKA) for RSA, DSA and Diffie-Hellman
• True (TRNG) or pseudo (PRNG) random number generators
– Non-deterministic true random numbers
– Pseudo random numbers with lengths of 8 or 16 bytes
– ANSI X9.17 Annex C compliant using a DES algorithm
• Interrupt controller
– Fifteen programmable, maskable interrupts
– Initiate commands by means of an input interrupt
– Sixteen programmable interrupts indicating completion of certain operations
– All interrupts mapped to one level- or edge-sensitive programmable interrupt output
• DMA controller
– Autonomous, 4-channel
– 1024 words (32 bits/word) per DMA transfer
– Scatter/gather capability with byte aligned addressing
PCI Controller
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is
designed to Version 2.3 of the PCI Specification and supports 32- bit PCI devices.
Reference Specifications:
• PCI Specification Version 2.3
• PCI Bus Power Management Interface Specification Version 1.1
Features inc l ude:
• Frequency to 66MHz
• 32-bit bus
• PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to four external devices, that can be disabled for use with an
external arbiter
• Support for inbound and outbound Message Signaled Interrupts (MSI)
• Simp le messa ge passing capabi li ty
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI bus memory
• Error tracking/status
• Supports initiation of transfers of the following types:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
• Vital Product Data (VPD) support
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PCI Express Controller
There are two independent PCI Express interfaces compliant with PCI Express base specification 1.1. One
interface can be configured as one to four lanes while the other functions as one-lane only. Both can be Root or
Endpoint Ports. The single lane interface shares a High-Speed SERDES with the Serial ATA (SATA) interface.
Features inc l ude:
• Two independent PCI Express interfaces
– One 4 lanes
– One 1 lane
– 2.5 GB/sec full duplex per lane
• Compliant with PCI Express base specification 1.1
• Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)
– Applications compliant with MSI rules are limited to one Endpoint port per PPC460EX
• Power Management
• Supports one virtual channel (VC0) no Traffic Class (TC) filtering
• Maximum Payload block size 512 Bytes
• Supports up to 512 Bytes maximum Read request size
• Reques ts supported:
– up to 4 (x4) or 2 (x1) posted outbound Write requests (memory and messages)
– up to 4 (x4) or 2 (x1) posted inbound Write requests
– up to 4 (x4) or 2 (x1) outbound Read requests outstanding on PCI Express
– up to 4 (x4) or 2 (x1) inbound Read requests outstanding on PCI Express
– Outbound I/O request as a PCI Express Root Port
– Inbound I/O request as a PCI Express Endpoint
• Buffering in each PCI Express port for the following transaction types:
– 2KB Replay buffer: up to 4 in flight transactions
– 2KB (x4) or 1KB (x1) for Outbound posted Writes
– 2KB (x4) or 1KB (x1) for Outbound Reads completion
– 2KB (x4) or 1KB (x1) for Inbound posted Writes
– 2KB (x4) or 1KB (x1) for Inbound Reads completion
• Parity checking on each buffer
• Programmable Outbound Memory (POM) regions: 3 memory, 1 I/O, 1 message, 1 configuration, 1 internal
register
• Programmable Inbound Memory (PIM) regions: 4 memory, 1 I/O, 1 expansion ROM
• INTx Interrupts support (legacy PCI):
– Up to four INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC
– A/B/C/D INTx types generation for Endpoints
• MSI - Message Signaled Interrupts
– MSI generation for Endpoint
– MSI termination for Root Ports
– MSI_X termination for Root Ports
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DDR2/1 SDRAM Memory Controller
The Double Data Rate 2/1 (DDR2/1) SDRAM memory controller supports industry standard 184-pin DIMMs, SO-
DIMMs, and other discrete devices. Global memory timings, address and bank sizes, and memory addressing
modes are programmable. This controller interfaces to the PLB through a Memory Queue (MQ) function that
includes six high-speed 1KB FIFO buffers.
The correct I/O supply voltage must be provided for the two types of DDR devices: DDR1 devices require +2.5V
and DDR2 devices require +1.8V.
Features inc l ude:
• Registered and non-registered industry standard DIMMs
• DDR2 333/400 support
• 64- and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)
• 3.2GB/s peak bandwidth for the 64-bit interface
• 1.6GB/s peak bandwidth for the 32-bit interface
• Four chip (bank) select signals supporting four external banks
• CAS latencies of 2, 3, 4, 5, 6, and 7
• Page mode accesses (up to 32 open pages) with configurable paging policy
• Look-ahead request queue with programmable depth of four commands
• Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current
bank)
• Up to 8GB in four external banks
• Up to two MemClkOut signals
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Sync DRAM configuration by means of mode register and extended mode register set commands
• Power management (self-refresh, suspend, sleep)
• Low Latency and High Bandwidth PLB ports
• Selectable PLB read response (immediate or deferred)
• Programmable Low Latency and High Bandwidth arbitration schemes
• High Bandwidth port has four 1KB read buffers and two 1KB write buffers
• Low Latency port has four 128B read buffers and two 128B write buffers
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Prelim inary Data Sheet
External Peripheral Bus Controller (EBC)
The External Bus Controller (EBC) transfers data between the PLB and external memory or peripheral devices
attached to the external peripheral bus. The EBC allows for direct attachment of memory devices such as ROM
and SRAM, DMA device-paced memory devices, and DMA peripheral devices.
Features inc l ude:
• Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 100MHz operation
• Burst and non-burst devices
• 32-bit byte-addressable data bus
•Data parity
• 27-bit address
• Peripheral Device pacing with external Ready
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
– 256 Wa it States for non-burs t
– 32 Burst Wait States for first access and up to eight Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
• Programmable address mapping
• External DMA Slave Support
Ethernet Controller
Two 10/100/1000 Ethernet ports are supported.
Features inc l ude:
• Compliant with ANSI/IEEE S tandard 802.3 and IEEE 802.3u supplement
• Compliant with IEEE Standard 802.3z (Gigabit Ethernet)
• Two 10/100/1000 interfaces running in full- and half-duplex modes providing:
– One Gigabit Media Independent Interface (GMII)
– One Media Independent Interface (MII)
– Two Reduced Gigabit MII (RGMII)
– Two Serial GMIIs (SGMII)
• Quality of Service (QoS) support
– Support of IEEE 802.1p priority queueing for up to 8 priorities
– Recognizes TCI field in VLAN-tagged frames where the priority field is coded
• Jumbo frame support (9018 bytes)
– Support for Ethernet II formatted frames (RFC894)
– Support for IEEE formatted frames (RFC1042)
– Handles VLAN-tagged frames (IEEE 802.2ac)
• TCP/IP Acceleration Hardware (TAH) support
• Off loads Gigabit Ethe rnet protocol processing from the CPU
• Checksum verification for TCP/UDP/IP headers in the receive path
• Checksum generation for TCP/UDP/IP headers in the transmit path
• TCP segmentation support in the transmit path
• IPv4 and IPv6 sup port
• IPv6 header extension support
• Wake On LAN handling
• 256-bit hash table to filter multicast frames
• DMA capability
• Interrupt coalescence
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DMA 4-Channel Controller
The 4-channel DMA controller provides a DMA interface between the PLB memories and internal and external
peripheral devices.
Features inc l ude:
• Supports the following transfers:
– Memory-to-memory
– Buffered peripheral to memory
– Buffered memory to peripheral
• Scatter/Gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 64-bit addressing
• 128 byte FIFO buffer
• Address increment or decrement
• Suppo rt for:
– Internal and external peripherals
– Memory mapped peripherals
– Peripherals running on slower frequency buses
I2O/DMA Controller
The I2O/DMA controller provides one High Speed DMA (HSDMA) interface to the PLB and support for I2O
messaging. The HSDMA provides single-channel direct memory access support to ease the CPU burden. I2O
manages Message Frame Address (MFA) FIFOs or queues in memory in response to I2O register reads and
writes and transfers message frames.
DMA features include:
• Programmable Command Pointer FIFO and Completion FIFO size (up to 2048 DMA operations queued)
• Separate 512-byte buffering for transmit and receive
– 1.4GB throughput (local read)
– 1.0GB throughput (remote read)
• Simultaneous fill and drain (PLB read/write pipelining)
• Any sourc e PLB addres s to any des tin ati on addre ss
• No memory alignment restrictions on source or destination
• 32-byte command descriptor block
• Maximum transfer size of 16MB
• 64-bit addressing
• Prefetch indicators for PCI buffer management
• Supports initiation of transfer to the following address spaces:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (type 0 and type 1)
– Single beat special cycles
I2O features include:
• I2O pull- and push-messaging methods
• Dynamic message frame size
• Programmable FIFO size (4096 64-bit MFAs maximum)
• 64- and 32-bit MFA sizes
• Three interrupt gathering methods
• Registered MFA prefetch and posting
• 32-bit inbound and outbound doorbell registers
• Four 32-bit scratch pad registers
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Prelim inary Data Sheet
Serial Ports (UART)
The Universal Asynchronous Receiver/Transmitter (UART) interface provides one 8-signal port, or two 4-signal
ports, or four 2-signal ports. The UART performs serial-to-parallel conversion on data received from a peripheral
device or a modem, and parallel-to-serial conversion on data received from the processor.
Features inc l ude:
• Up to four ports in the following combinations:
– One 8-pin (UART0)
– Two 4-pin (UART0 and UART1)
– Four 2-pin (UART0, UART1, UART2, and UART3)
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with 16750 register set
• Complete status reporting capability
• Fully programmable serial-interface characteristics
• Supports DMA using the 4-channel internal DMA function
• 64-byte FIFOs for buffering transmit and receive data
IIC Bus Controller
The Inter-Integrated Circuit (IIC) interface provides a Philips® I2C™ compatible interface operating up to 400 kHz
either as a master, a slave, or both, with a Bootstrap Controller (BSC) included. During chip reset, the Bootstrap
Controller can read configuration data from an IIC-compatible memory device (for example, EEPROM). This data
can be used to replace the default configuration settings provided by the chip.
Features inc l ude:
• Two IIC interfaces
• Support for Philips Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
•8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed VDD IIC interface
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocols
• Programmable error recovery
• Port 0 includes an integrated BSC that supports a serial Bootstrap ROM with default override parameters at
initialization
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20 AMCC Proprietary
Revision 1.19 – June 17, 2009
Serial Peripheral Controller (SPI /SCP)
The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous,
character-oriented (byte) port that allows the exchange of data with other serial devices. The SPI is a master on the
serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.
Features inc l ude:
• Three-wire serial port interface
• Full-duplex synchronous operation
•SPI bus master
• OPB bus slave
• Programmable clock rate divider
• Clock inversion
• Reverse data
• Local data loop back for test
Uni versal Serial Bus 2.0 ( USB)
Two USB 2.0 interfaces provide both Device and Host support. These interfaces are provided as one USB 2.0 On-
The-Go (OTG) controller (Host and Device) and one USB 2.0 Host controller. Both controllers provide support to
an external PHY device through separate ULPI SDR interfaces.
Features inc l ude:
• USB 2.0 Host
– Fully compliant to the following specifications:
• Universal Serial Bus Specification, Revision 2.0
• Enhanc ed Host Controller Interface (EHCI) Specificatio n for USB, Revision 1.0
• Open Host Controller Interface (OHCI) Specification for USB, Revision 1.0a
– One EHCI high speed (480Mbps) Host interface
– One OHCI full/low speed (12Mbps/1.5Mbps) Host interface
– Maximum packet sizes of 1024B for isochronous transfers and 512B for bulk transfers
– Isochronous traffic can have three packets per microframe (196.6 Mbps throughput)
– Data and descriptor prefetch to optimize performance and off load CPU
– 4 KB buffer
• USB 2.0 OTG
– Fully compliant to the following specifications
• Universal Serial Bus Specification, Revision 2.0
• On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a
– Configurable as a Host-only or Device-only controller
– Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transfers
– Maximum packet sizes of 1024B for isochronous transfers and 512B for bulk transfers
– Isochronous traffic can have three packets per microframe (196.6 Mbps throughput)
– Integrated DMA support to optimize performance and off load CPU
– Device support provides six Endpoints (3 IN, 3 OUT)
– 8192-byte FIFO by Endpoint (supports high-bandwidth isochronous transfers, double buffering of 1024-
byte packets)
– FIFOs are not shared between IN and OUT Endpoints
– Two USB 2.0 device Endpoints have DMA dedicated channels
– 16K B buffer
460EX – PPC460EX Embedded Processor
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AMCC Proprietary 21
Prelim inary Data Sheet
Serial ATA (SATA)
The Serial Advanced Technology Attachment (ATA) interface provides an interface to physical storage devices. It
shares the High-Speed SERDES with the PCI-Express interface with 1-Lane.
Features inc l ude:
• Compliant with Serial ATA Revision 2.5 Specification
• Supports SATA 1.5Gbps Generation 1 and 3Gbps Generation 2 speeds
• Supports device hot-plugging
• Supports power management
• Supports BIST loopback modes
• Dedicated DMA controller support to optimize performance and off load CPU
• Separate 512B transmit and receive buffers
NAND Flash Controller
The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND
Flash devices. It provides both direct command, address, and data access to the external device as well as a
memory-mapped linear region that generates data accesses. NAND Flash data is transferred on the peripheral
data bus.
Features inc l ude:
• One to four banks supported on EBC
• Direct interface to:
– Discrete NAND Flash devices (up to four devices)
– S mart Media Card socket (22-pins)
• Device sizes of 4MB and larger supported for read/write access
• (512 + 16)-B or (2K + 64)-B page sizes supported
• Boot from NAND supported with execution of up to 4KB of boot code out of block 0
• ECC generation - hamming code, single-bit correction, double-bit detection (SEC/DED):
– ECC generation assist software with ECC checking of SLC NAND
– No ECC checking supported when booting directly from block 0
• Chip select pins are multiplexed with EBC
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor.
Features inc l ude:
• Time Base Counter (32 b its) driven by the OPB bus cloc k
• Seve n 32-bit compare timer s
General Purp ose IO (GP IO) Contr ol ler
Controller functions and GPIO registers are programmed and accessed by means of memory-mapped OPB bus
master accesses.
Features inc l ude:
• Sixty-four GPIOs multiplexed with other functions. DCRs control whether a GPIO pin acts as a GPIO or is used
for another purpose.
• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,
tri-stated if output bit is 1).
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22 AMCC Proprietary
Revision 1.19 – June 17, 2009
Universal Interrupt Controller (UIC)
Universal Interrupt Controllers (UICs) provide control, status, and communications necessary between the external
and internal sources of interrupts and the on-chip PowerPC processor.
Note: Processor specific interrupts (for example, page faults) do not use UIC resources.
Features inc l ude:
• Sixteen external interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to the on-chip processor
• Programmable interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
JTAG
Features inc l ude:
• IEEE 1149.1 Test Access Port
• JTAG Boundary Scan Description Language (BSDL)
• IBM RISCWatch support
Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use with
this port.
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 23
Prelim inary Data Sheet
Package Diagram
Figure 3. 35mm, 728-Ball TE-PBGA Package
35.0
Gold Gate Release
Corresponds to
PCB
Substrate
Mold
Compound
A01 Ball Location
Top View
Bottom View
Notes:
1. All dimensions are in mm.
2. Packa ge is available with lead or
30 24
A
26
AF
BC
DE
FG
HJ
KL
M
AA
N
PR
TU
VW
Y
AB AC
AD AE
Thermal Balls
01 03 05 07 09 11 13 15 17 19
02 04 06 08 10 12 14 16 18 21 23 25
20 22 24 34
27 29 31 33
28 30 32
AP
AJ
AG
AH
AK AL
AM AN
33.0
1.0
728 x 0.60 ± 0.10 Solder Ball
7.0
2.65 max
0.4 - 0.6
3. Package conforms to JEDEC MS-034.
Part
Lot Number (ZZ ZZZ)
lead-free (RoHS compliant).
Side View
TYP TYP
Logo View
PPC460EX
e1
1YWWBZZZZZ
PPC460EX-nprfff(f)T
®
ccccccc
Number
MMDDQL
Heat Slug
4. Optional solder ball diameter is
0.63 +0.07/
−
0.13.
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
24 AMCC Proprietary
Revision 1.19 – June 17, 2009
Assembly Recommendations
Assembly recommendations from JEDEC standard J-STD-020 should be used unless recommended differently in
the following table.
Table 3. Recommended Reflow Soldering Profile
Profile Feature Sn-Pb Eutectic Assembly
(PPC460EX-STxfff) Pb Free Reflow Assembly
(PPC460EX-SUxfff)
Average ramp-up rate 3°C/second max 3°C/second max
Preheat:
• Temperature Min
• Temperature Max
• Time (min to ma x)
100°C
150°C
60–120 seconds
150°C
200°C
60–120 seconds
Time Maintained Above:
• Temperature
•Time 183°C
60–150 seconds 217°C
60–150 seconds
Peak Temperature 225°C 260°C
Time within 5°C of Actual Peak Temperature 20 seconds max 30 seconds max
Ramp-down Rate 6°C/second max 6°C/second max
Time 25°C to Peak Temperature 6 minut es m ax 8 minutes max
Table 4. JEDEC Moisture Sensitivity Level and Ball Composition
Sn-Pb (PPC460EX-STxfff ) Pb Free (PPC460EX-SUxfff)
MSL Level 3 3
Solder Ball Metallurgy 63Sn/37Pb Sn/4Ag/05Cu
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 25
Prelim inary Data Sheet
Signal Lists
The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the
signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and alternate
signals in brackets. Multiplexed signals appear alphabetically multiple times in the list—once for each signal name
on the ball. The page number listed gives the page in Table 9 on page 64 where the signals in the indicated
interface group begin. In cases where signals in the same interface group (for example, Ethernet) have different
names to distinguish variations in the mode of operation, the names are separated by a comma with the primary
mode name appearing first. In cases where the signals have the same function but are associated with different
ports (for example, UART), the signals are separated by a slash (/). These signals are listed only once, and appear
alphabetically by the primary mode or primary port name.
Alphabetical Signal List
Table 5. Signals Listed Alphabetically (Part 1 of 26)
Signal Name Ball Interface Group P age
AGND L01
Power 73
AGND L02
AGND M04
AGND M06
AGND P03
AGND P04
AGND P06
AGND R01
AGND R02
AGND R06
AGND U01
AGND U04
AGND U05
AGND Y01
AGND Y03
AGND Y05
AGND AA04
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Revision 1.19 – June 17, 2009
AVDD L03
Power 73
AVDD L06
AVDD M03
AVDD M05
AVDD N03
AVDD N06
AVDD P05
AVDD T03
AVDD U02
AVDD U03
AVDD U06
AVDD V03
AVDD V06
AVDD W03
AVDD W06
AVDD Y02
AVDD Y04
AVDD AB04
BA0 AN32
DDR2/1 SDRAM 66BA1 AP31
BA2 AM31
BankSel0 AL28
DDR2/1 SDRAM 66
BankSel1 AP29
BankSel2 AM29
BankSel3 AN29
CAS AL29 DDR2/1 SDRAM 66
ClkEn0 AE29
DDR2/1 SDRAM 66
ClkEn1 AF34
ClkEn2 AE33
ClkEn3 AE31
[DMAAck0]GPIO47[PerAddr06][IRQ14] C31
DMA 69
[DMAAck1]GPIO44[PerCS4][IRQ11] E21
[DMAAck2]GPIO31[PerPar1][IRQ8] A16
[DMAAck3]GPIO36[UART0CTS][UART3Rx] E31
[DMAReq0]GPIO46[PerAddr05][IRQ13] B32
[DMAReq1]GPIO43[PerCS3][NFCE3][IRQ10] A22
[DMAReq2]GPIO30[PerPar0][IRQ7] A20
[DMAReq3]GPIO33[PerPar3][IRQ4] F13
Table 5. Signals Listed Alphabetically (Part 2 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
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AMCC Proprietary 27
Prelim inary Data Sheet
DM0 P31
DDR2/1 SDRAM 66
DM1 U30
DM2 V30
DM3 AB34
DM4 AM25
DM5 AP23
DM6 AN20
DM7 AM17
DM8 AD34
DQS0 P33
DDR2/1 SDRAM 66
DQS0 P32
DQS1 U32
DQS1 U31
DQS2 W31
DQS2 W32
DQS3 AA30
DQS3 AA31
DQS4 AP25
DQS4 AN25
DQS5 AN22
DQS5 AM22
DQS6 AM19
DQS6 AL19
DQS7 AK17
DQS7 AL17
DQS8 AD32
DQS8 AD33
E1OVDD Y14
Power 73
E1OVDD AA15
E1OVDD AD06
E1OVDD AF02
E1OVDD AG05
E1OVDD AJ11
E1OVDD AK02
E1OVDD AK08
E1OVDD AN05
E1OVDD AN09
E2OVDD AK13 Power 73
E2OVDD AN16
Table 5. Signals Listed Alphabetically (Part 3 of 26)
Signal Name Ball Interface Group P age
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Revision 1.19 – June 17, 2009
EAGND AP12 Power 73
EAVDD AP11
ECC0 AC31
DDR2/1 SDRAM 66
ECC1 AC30
ECC2 AE32
ECC3 AE34
ECC4 AC34
ECC5 AC32
ECC6 AD31
ECC7 AD30
[EOT0/TC0]GPIO48[PerAddr07][IRQ15] D30
DMA 69
[EOT1/TC1]GPIO45[PerCS5][IRQ12] D21
[EOT2/TC2]GPIO32[PerPar2][IRQ9] A14
[EOT3/TC3]GPIO37[UART0RTS][UART3Tx] D33
ExtReset F22 External Peripheral 69
FSOURCE0 E17 System 72
Table 5. Signals Listed Alphabetically (Part 4 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
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AMCC Proprietary 29
Prelim inary Data Sheet
GMC0CD, GMC1RxClk AP05
Ethernet 0 67
GMC0CrS, GMC1TxClk AL07
GMC0GTxClk, GMC0TxClk AN06
GMC0RxClk, GMC0RxClk AM07
GMC0RxD0, GMC0RxD0 AL09
GMC0RxD1, GMC0RxD1 AK09
GMC0RxD2, GMC0RxD2 AP08
GMC0RxD3, GMC0RxD3 AJ09
GMC0RxD4, GMC1RxD0 AN08
GMC0RxD5, GMC1RxD1 AL08
GMC0RxD6, GMC1RxD2 AM08
GMC0RxD7, GMC1RxD3 AP07
GMC0RxDV, GMC0RxCtl AL06
GMC0RxEr, GMC1RxCtl AJ10
GMC0TxClk AN04
GMC0TxD0, GMC0TxD0 AM02
GMC0TxD1, GMC0TxD1 AK04
GMC0TxD2, GMC0TxD2 AL02
GMC0TxD3, GMC0TxD3 AL01
GMC0TxD4, GMC1TxD0 AK03
GMC0TxD5, GMC1TxD1 AM01
GMC0TxD6, GMC1TxD2 AH05
GMC0TxD7, GMC1TxD3 AL03
GMC0TxEn, GMC0TxCtl AM05
GMC0TxEr, GMC1TxCtl AJ08
GMCMDClk AJ03
Ethernet 0 67GMCMDIO AK01
GMCRefClk AP09
Table 5. Signals Listed Alphabetically (Part 5 of 26)
Signal Name Ball Interface Group P age
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30 AMCC Proprietary
Revision 1.19 – June 17, 2009
GND A01
Power 73
GND A02
GND A03
GND A33
GND A34
GND B01
GND B02
GND B03
GND B07
GND B12
GND B23
GND B28
GND B33
GND B34
GND C01
GND C02
GND C03
GND C16
GND C32
GND D04
GND D31
GND E05
GND E10
GND E23
GND E25
GND E28
GND E30
GND F06
GND F16
GND F19
GND F29
GND F30
GND F31
GND F32
Table 5. Signals Listed Alphabetically (Part 6 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
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AMCC Proprietary 31
Prelim inary Data Sheet
GND G02
Power 73
GND G31
GND G33
GND H01
GND J01
GND J03
GND J30
GND J32
GND K02
GND K05
GND K06
GND K30
GND M30
GND M33
GND P14
GND P16
GND P19
GND P21
GND R15
GND R16
GND R19
GND R20
GND T14
GND T15
GND T16
GND T17
GND T18
GND T19
GND T20
GND T21
GND T30
GND U16
GND U17
GND U18
GND U19
Table 5. Signals Listed Alphabetically (Part 7 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
32 AMCC Proprietary
Revision 1.19 – June 17, 2009
GND V16
Power 73
GND V17
GND V18
GND V19
GND W14
GND W15
GND W16
GND W17
GND W18
GND W19
GND W20
GND W21
GND W29
GND Y15
GND Y16
GND Y19
GND Y20
GND AA14
GND AA16
GND AA19
GND AA21
GND AC01
GND AC03
GND AC04
GND AC05
GND AC33
GND AD01
GND AE03
GND AE05
GND AE30
GND AF05
GND AF29
GND AF30
GND AG29
GND AH02
GND AH33
Table 5. Signals Listed Alphabetically (Part 8 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 33
Prelim inary Data Sheet
GND AJ06
Power 73
GND AJ13
GND AJ16
GND AJ23
GND AJ25
GND AJ26
GND AJ27
GND AJ29
GND AJ30
GND AJ31
GND AK05
GND AK06
GND AK07
GND AK10
GND AK14
GND AK19
GND AK24
GND AK25
GND AK28
GND AK29
GND AK30
GND AL04
GND AL05
GND AL22
GND AL25
GND AL30
GND AL31
GND AL32
GND AL33
GND AL34
GND AM03
GND AM04
GND AM06
GND AM10
GND AM30
GND AM32
Table 5. Signals Listed Alphabetically (Part 9 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
34 AMCC Proprietary
Revision 1.19 – June 17, 2009
GND AN01
Power 73
GND AN02
GND AN03
GND AN07
GND AN12
GND AN23
GND AN28
GND AN31
GND AN33
GND AN34
GND AP01
GND AP02
GND AP03
GND AP04
GND AP06
GND AP16
GND AP17
GND AP33
GND AP34
Table 5. Signals Listed Alphabetically (Part 10 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 35
Prelim inary Data Sheet
GPIO00[USB2HD0] AG01
System 72
GPIO01[USB2HD1] AD05
GPIO02[USB2HD2] AE04
GPIO03[USB2HD3] AF01
GPIO04[USB2HD4] AE02
GPIO05[USB2HD5] AE01
GPIO06[USB2HD6] AB05
GPIO07[USB2HD7] AD03
GPIO08[USB2DD0] AH04
GPIO09[USB2DD1] AJ05
GPIO10[USB2DD2] AG06
GPIO11[USB2DD3] AJ02
GPIO12[USB2DD4] AJ04
GPIO13[USB2DD5] AH03
GPIO14[USB2DD6] AJ01
GPIO15[USB2DD7] AH01
GPIO16[USB2HStop] AF04
GPIO17[USB2HNext] AG02
GPIO18[USB2HDir] AG04
GPIO19[USB2DStop] AF03
GPIO20[USB2DNext] AG03
GPIO21[USB2DDir] AD04
GPIO22[NFRdyBusy]C24
GPIO23[NFREn]B24
GPIO24[NFWEn]A24
GPIO25[NFCLE] F26
GPIO26[NFALE] A25
GPIO27[IRQ0] D12
GPIO28[IRQ1] E12
GPIO29[IRQ2] F12
GPIO30[PerPar0][DMAReq2][IRQ7] A20
GPIO31[PerPar1][DMAAck2][IRQ8] A16
Table 5. Signals Listed Alphabetically (Part 11 of 26)
Signal Name Ball Interface Group P age
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36 AMCC Proprietary
Revision 1.19 – June 17, 2009
GPIO32[PerPar2][EOT2/TC2][IRQ9] A14
System 72
GPIO33[PerPar3][DMAReq3][IRQ4] F13
GPIO34[UART0DCD][UART1CTS][UART2Tx] E34
GPIO35[UART0DSR][UART1RTS][UART2Rx] E32
GPIO36[UART0CTS][DMAAck3][UART3Rx] E31
GPIO37[UART0RTS][EOT3/TC3][UART3Tx] D33
GPIO38[UART0DTR][UART1Tx][IRQ5] D32
GPIO39[UART0RI][UART1Rx][IRQ6] D34
GPIO40[IRQ3] C12
GPIO41[PerCS1][NFCE1]B22
GPIO42[PerCS2][NFCE2]D25
GPIO43[PerCS3][NFCE3][DMAReq1][IRQ10] A22
GPIO44[PerCS4][DMAAck1][IRQ11] E21
GPIO45[PerCS5][EOT1/TC1][IRQ12] D21
GPIO46[PerAddr05][DMAReq0][IRQ13] B32
GPIO47[PerAddr06][DMAAck0][IRQ14] C31
GPIO48[PerAddr07][EOT0/TC0][IRQ15] D30
GPIO49[TrcBS0] H33
GPIO50[TrcBS1] J34
GPIO51[TrcBS2] H34
GPIO52[TrcES0] L30
GPIO53[TrcES1] L31
GPIO54[TrcES2] K33
GPIO55[TrcES3] L32
GPIO56[TrcES4] K34
GPIO57[TrcTS0] L33
GPIO58[TrcTS1] N29
GPIO59[TrcTS2] M31
GPIO60[TrcTS3] L34
GPIO61[TrcTS4] M32
GPIO62[TrcTS5] M34
GPIO63[TrcTS6] N31
Halt H32 System 72
HISRRst B11 DDR2/1 SDRAM 66
IIC0SClk J31
IIC Peripheral 70
IIC0SData H31
[IIC1SClk]SPIClkOut K31
[IIC1SData]SPIDO G34
Table 5. Signals Listed Alphabetically (Part 12 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 37
Prelim inary Data Sheet
[IRQ0]GPIO27 D12
Interrupt 71
[IRQ1]GPIO28 E12
[IRQ2]GPIO29 F12
[IRQ3]GPIO40 C12
[IRQ4]GPIO33[PerPar3][DMAReq3] F13
[IRQ5]GPIO38[UART0DTR][UART1Tx] D32
[IRQ6]GPIO39[UART0RI][UART1Rx] D34
[IRQ7]GPIO30[PerPar0][DMAReq2] A20
[IRQ8]GPIO31[PerPar1][DMAAck2] A16
[IRQ9]GPIO32[PerPar2][EOT2/TC2] A14
[IRQ10]GPIO43[PerCS3][NFCE3][DMAReq1] A22
[IRQ11]GPIO44[PerCS4][DMAAck1] E21
[IRQ12]GPIO45[PerCS5][EOT1/TC1] D21
[IRQ13]GPIO46[PerAddr05][DMAReq0] B32
[IRQ14]GPIO47[PerAddr06][DMAAck0] C31
[IRQ15]GPIO48[PerAddr07][EOT0/TC0] D30
MemAddr00 AK34
DDR2/1 SDRAM 66
MemAddr01 AJ33
MemAddr02 AJ32
MemAddr03 AJ34
MemAddr04 AH30
MemAddr05 AH31
MemAddr06 AH32
MemAddr07 AG31
MemAddr08 AH34
MemAddr09 AG32
MemAddr10 AG33
MemAddr11 AF31
MemAddr12 AG34
MemAddr13 AC29
MemAddr14 AF32
MemClkOut0 AP27
DDR2/1 SDRAM 66
MemClkOut0 AN27
MemClkOut1 AK31
MemClkOut1 AK32
Table 5. Signals Listed Alphabetically (Part 13 of 26)
Signal Name Ball Interface Group P age
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38 AMCC Proprietary
Revision 1.19 – June 17, 2009
MemData00 P30
DDR2/1 SDRAM 66
MemData01 N34
MemData02 R32
MemData03 R30
MemData04 N33
MemData05 N32
MemData06 P34
MemData07 R31
MemData08 R34
MemData09 T34
MemData10 V34
MemData11 T32
MemData12 R33
MemData13 T31
MemData14 U33
MemData15 U34
MemData16 V32
MemData17 V31
MemData18 Y32
MemData19 W30
MemData20 V33
MemData21 W34
MemData22 Y34
MemData23 Y33
MemData24 AA33
MemData25 AA32
MemData26 AB31
MemData27 Y30
MemData28 AA34
MemData29 Y31
MemData30 AB33
MemData31 AB32
Table 5. Signals Listed Alphabetically (Part 14 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
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AMCC Proprietary 39
Prelim inary Data Sheet
MemData32 AM26
DDR2/1 SDRAM 66
MemData33 AP26
MemData34 AK21
MemData35 AN24
MemData36 AL26
MemData37 AK26
MemData38 AL24
MemData39 AM24
MemData40 AL23
MemData41 AM23
MemData42 AM21
MemData43 AN21
MemData44 AK23
MemData45 AP24
MemData46 AP22
MemData47 AL21
MemData48 AL20
MemData49 AM20
MemData50 AL18
MemData51 AM18
MemData52 AK20
MemData53 AP21
MemData54 AP20
MemData55 AP19
MemData56 AP18
MemData57 AN17
MemData58 AL16
MemData59 AP15
MemData60 AK18
MemData61 AN18
MemData62 AM16
MemData63 AK16
MemDCFdbkD AM33 DDR2/1 SDRAM 66
MemDCFdbkR AM34
MemODT0 AP28
DDR2/1 SDRAM 66
MemODT1 AM27
MemODT2 AM28
MemODT3 AL27
Table 5. Signals Listed Alphabetically (Part 15 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
40 AMCC Proprietary
Revision 1.19 – June 17, 2009
MemVRef1A AJ19
DDR2/1 SDRAM 66
MemVRef1B AB29
MemVRef2A AJ22
MemVRef2B T29
[NFALE]GPIO26 A25
NAND Flash 71
[NFCE0]PerCS0 E24
[NFCE1]GPIO41[PerCS1 B22
[NFCE2]GPIO42[PerCS2]D25
[NFCE3]GPIO43[PerCS3][DMAReq1][IRQ10] A22
[NFCLE]GPIO25 F26
[NFRdyBusy]GPIO22 C24
[NFREn]GPIO23 B24
[NFWEn]GPIO24 A24
OVDD B05
Power 73
OVDD B09
OVDD B16
OVDD B19
OVDD B26
OVDD B30
OVDD E02
OVDD E08
OVDD E13
OVDD E22
OVDD E27
OVDD E33
OVDD F11
OVDD F24
OVDD H05
OVDD H30
OVDD J02
OVDD J33
OVDD L29
OVDD P15
OVDD P20
OVDD R14
OVDD R21
PAVDD T06 Power 73
PAVDD AA05
Table 5. Signals Listed Alphabetically (Part 16 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 41
Prelim inary Data Sheet
PCI0AD00 D11
PCI 64
PCI0AD01 E11
PCI0AD02 B10
PCI0AD03 A10
PCI0AD04 C10
PCI0AD05 F10
PCI0AD06 D10
PCI0AD07 A09
PCI0AD08 D09
PCI0AD09 A08
PCI0AD10 F09
PCI0AD11 B08
PCI0AD12 C08
PCI0AD13 D08
PCI0AD14 A07
PCI0AD15 F08
PCI0AD16 A05
PCI0AD17 A04
PCI0AD18 D05
PCI0AD19 B04
PCI0AD20 D02
PCI0AD21 F04
PCI0AD22 E03
PCI0AD23 D03
PCI0AD24 E01
PCI0AD25 E04
PCI0AD26 G05
PCI0AD27 G04
PCI0AD28 F02
PCI0AD29 H06
PCI0AD30 F01
PCI0AD31 F05
PCI0C/BE0 C09
PCI 64
PCI0C/BE1 C07
PCI0C/BE2 C05
PCI0C/BE3 F03
PCI0Clk K01
PCI 64PCI0DevSel A06
PCI0Frame E06
Table 5. Signals Listed Alphabetically (Part 17 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
42 AMCC Proprietary
Revision 1.19 – June 17, 2009
PCI0Gnt0/Req G03
PCI 64
PCI0Gnt1 H04
PCI0Gnt2 G01
PCI0Gnt3 H03
PCI0IDSel D01
PCI 64
PCI0Int J04
PCI0IRdy C04
PCI0M66En E09
PCI0Par D07
PCI0PErr B06
PCI0Req0/Gnt J06
PCI 64
PCI0Req1 H02
PCI0Req2 K04
PCI0Req3 J05
PCI0Reset K03
PCI 64
PCI0SErr E07
PCI0Stop C06
PCI0TRdy D06
PCIE0AVReg[SATA0AVReg] AA01
PCI Express 0 64
PCIE0CalRN[SATA0CalRN] AB02
PCIE0CalRP[SATA0CalRP] AB01
PCIE0RefClk[SATA0RefClk] AA02
PCIE0RefClk[SATA0RefClk]AA03
PCIE0Rx0[SATA0Rx0] W04
PCIE0Rx0[SATA0Rx0]W05
PCIE0Tx0[SATA0Tx0] W02
PCIE0Tx0[SATA0Tx0]W01
Table 5. Signals Listed Alphabetically (Part 18 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 43
Prelim inary Data Sheet
PCIE1AVReg R05
PCI Express 1 65
PCIE1CalRN P01
PCIE1CalRP P02
PCIE1RefClk R04
PCIE1RefClk R03
PCIE1Rx0 L05
PCIE1Rx0 L04
PCIE1Rx1 N05
PCIE1Rx1 N04
PCIE1Rx2 T04
PCIE1Rx2 T05
PCIE1Rx3 V05
PCIE1Rx3 V04
PCIE1Tx0 M02
PCIE1Tx0 M01
PCIE1Tx1 N02
PCIE1Tx1 N01
PCIE1Tx2 T02
PCIE1Tx2 T01
PCIE1Tx3 V02
PCIE1Tx3 V01
Table 5. Signals Listed Alphabetically (Part 19 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
44 AMCC Proprietary
Revision 1.19 – June 17, 2009
[PerAddr05]GPIO46[DMAReq0][IRQ13] B32
External Peripheral 69
[PerAddr06]GPIO47[DMAAck0][IRQ14] C31
[PerAddr07]GPIO48[EOT0/TC0][IRQ15] D30
PerAddr08 A32
PerAddr09 E29
PerAddr10 C30
PerAddr11 B31
PerAddr12 A30
PerAddr13 A31
PerAddr14 D29
PerAddr15 C29
PerAddr16 A29
PerAddr17 D28
PerAddr18 C28
PerAddr19 B29
PerAddr20 C27
PerAddr21 A28
PerAddr22 D26
PerAddr23 F27
PerAddr24 B27
PerAddr25 D27
PerAddr26 A27
PerAddr27 C26
PerAddr28 A26
PerAddr29 C25
PerAddr30 B25
PerAddr31 D24
PerBLast F25 External Peripheral 69
PerClk F23 Ex tern al Peripheral 69
PerCS0[NFCE0]E24
External Peripheral 69
[PerCS1]GPIO41[NFCE1]B22
[PerCS2]GPIO42[NFCE2]D25
[PerCS3]GPIO43[NFCE3][DMAReq1][IRQ10] A22
[PerCS4]GPIO44[DMAAck1][IRQ11] E21
[PerCS5]GPIO45[EOT1/TC1][IRQ12] D21
Table 5. Signals Listed Alphabetically (Part 20 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 45
Prelim inary Data Sheet
PerData00 C21
External Peripheral 69
PerData01 B21
PerData02 A21
PerData03 E20
PerData04 D20
PerData05 C20
PerData06 D18
PerData07 B20
PerData08 E19
PerData09 D19
PerData10 E18
PerData11 C19
PerData12 A19
PerData13 C18
PerData14 B18
PerData15 A18
PerData16 D17
PerData17 B17
PerData18 A15
PerData19 B15
PerData20 E15
PerData21 C15
PerData22 D16
PerData23 D15
PerData24 E16
PerData25 C14
PerData26 E14
PerData27 D14
PerData28 B14
PerData29 A13
PerData30 B13
PerData31 C13
[PerPar0]GPIO30[DMAReq2][IRQ7] A20
External Peripheral 69
[PerPar1]GPIO31[DMAAck2][IRQ8] A16
[PerPar2]GPIO32[EOT2/TC2][IRQ9] A14
[PerPar3]GPIO33[DMAReq3][IRQ4] F13
PerErr D13 External Peripheral 69
PerOE E26 External Peripheral 69
PerR/W D23 External Peripheral 69
Table 5. Signals Listed Alphabetically (Part 21 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
46 AMCC Proprietary
Revision 1.19 – June 17, 2009
PerReady C17 External Peripheral 69
PerWBE0 C23
External Peripheral 69
PerWBE1 A23
PerWBE2 D22
PerWBE3 C22
RAS AP30 DDR2/1 SDRAM 66
Reserved A17
Other 73
Reserved AL13
Reserved AM13
Reserved AL12
Reserved AM12
Reserved AM15
Reserved AN15
Reserved AP10
Reserved AN10
[SATA0AVReg]PCIE0AVReg AA01
Serial ATA 68
[SATA0CalRN]PCIE0CalRN AB02
[SATA0CalRP]PCIE0CalRP AB01
[SATA0RefClk]PCIE0RefClk AA02
[SATA0RefClk]PCIE0RefClk AA03
[SATA0Rx0]PCIE0Rx0 W04
[SATA0Rx0]PCIE0Rx0 W05
[SATA0Tx0]PCIE0Tx0 W02
[SATA0Tx0]PCIE0Tx0 W01
SGMII0RxClk AK15
Ethernet SGMII 0 68
SGMII0RxClk AL15
SGMII0RxD AN14
SGMII0RxD AP14
SGMII0TxD AM11
SGMII0TxD AN11
SGMII1RxClk AL14
Ethernet SGMII 1 68
SGMII1RxClk AM14
SGMII1RxD AN13
SGMII1RxD AP13
SGMII1TxD AK11
SGMII1TxD AL11
SGMIITxClk AJ12
SGMIITxClk AK12
Table 5. Signals Listed Alphabetically (Part 22 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 47
Prelim inary Data Sheet
SOVDD N30
Power 73
SOVDD T33
SOVDD W33
SOVDD Y21
SOVDD AA20
SOVDD AB30
SOVDD AD29
SOVDD AF 33
SOVDD AG30
SOVDD AJ24
SOVDD AK22
SOVDD AK27
SOVDD AK33
SOVDD AN19
SOVDD AN26
SOVDD AN30
SPAGND A11 Power 73
SPAVDD A12
SPIClkOut[IIC1SClk] K31
Serial Peripheral 71SPIDI K32
SPIDO[IIC1SData] G34
SysClk AD02
System 72SysErr AB03
SysReset AC02
TCK J29
JTAG 72TDI F34
TDO F33
TestEn K29
System 72TherMonA AM09
TherMonB AL10
TmrClk C11 System 72
TMS G32 JTAG 72
[TrcBS0]GPIO49 H33
Trace 72[TrcBS1]GPIO50 J34
[TrcBS2]GPIO51 H34
Table 5. Signals Listed Alphabetically (Part 23 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
48 AMCC Proprietary
Revision 1.19 – June 17, 2009
TrcClk M29
Trace 72
[TrcES0]GPIO52 L30
[TrcES1]GPIO53 L31
[TrcES2]GPIO54 K33
[TrcES3]GPIO55 L32
[TrcES4]GPIO56 K34
[TrcTS0]GPIO57 L33
Trace 72
[TrcTS1]GPIO58 N29
[TrcTS2]GPIO59 M31
[TrcTS3]GPIO60 L34
[TrcTS4]GPIO61 M32
[TrcTS5]GPIO62 M34
[TrcTS6]GPIO63 N31
TRST H29 JTAG 72
UARTSerClk[LeakT est] G30 UART Peripheral 70
[UART0CTS]GPIO36[DMAAck3][UART3Rx] E31
UART Peripheral 70
[UART0DCD]GPIO34[UART1CTS][UART2Tx] E34
[UART0DSR]GPIO35[UART1RTS][UART2Rx] E32
[UART0DTR]GPIO38[UART1Tx][IRQ5] D32
[UART0RI]GPIO39[UART1Rx][IRQ6] D34
[UART0RTS]GPIO37[EOT3/TC3][UART3Tx] D33
UART0Rx C34
UART0Tx C33
[UART1CTS][UART0DCD]GPIO34[UART2Tx] E34
UART Peripheral 70
[UART1RTS][UART0DSR]GPIO35[UART2Rx] E32
[UART1Rx][UART0RI]GPIO39[IRQ6] D34
[UART1Tx][UART0DTR]GPIO38[IRQ5] D32
[UART2Rx][UART0DSR]GPIO35[UART1RTS]E32
[UART2Tx][UART0DCD]GPIO34[UART1CTS]E34
[UART3Rx][UART0CTS]GPIO36[DMAAck3] E31
[UART3Tx][UART0RTS]GPIO37[EOT3/TC3] D33
Table 5. Signals Listed Alphabetically (Part 24 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 49
Prelim inary Data Sheet
USB2DClk AF06 USB 2.0 70
[USB2DD0]GPIO08 AH04
USB 2.0 70
[USB2DD1]GPIO09 AJ05
[USB2DD2]GPIO10 AG06
[USB2DD3]GPIO11 AJ02
[USB2DD4]GPIO12 AJ04
[USB2DD5]GPIO13 AH03
[USB2DD6]GPIO14 AJ01
[USB2DD7]GPIO15 AH01
[USB2DDir]GPIO21 AD04
USB 2.0 70[USB2DNext]GPIO20 AG03
[USB2DStop]GPIO19 AF03
USB2HClk AC06 USB 2.0 Host 71
USB2HClk48 AE06
[USB2HD0]GPIO00 AG01
USB 2.0 Host 71
[USB2HD1]GPIO01 AD05
[USB2HD2]GPIO02 AE04
[USB2HD3]GPIO03 AF01
[USB2HD4]GPIO04 AE02
[USB2HD5]GPIO05 AE01
[USB2HD6]GPIO06 AB05
[USB2HD7]GPIO07 AD03
[USB2HDir]GPIO18 AG04
USB 2.0 Host 71[USB2HNext]GPIO17 AG02
[USB2HStop]GPIO16 AF04
Table 5. Signals Listed Alphabetically (Part 25 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
50 AMCC Proprietary
Revision 1.19 – June 17, 2009
VDD F14
Power 73
VDD F15
VDD F17
VDD F18
VDD F20
VDD F21
VDD P17
VDD P18
VDD P29
VDD R17
VDD R18
VDD R29
VDD U14
VDD U15
VDD U20
VDD U21
VDD U29
VDD V14
VDD V15
VDD V20
VDD V21
VDD V29
VDD Y06
VDD Y17
VDD Y18
VDD Y29
VDD AA06
VDD AA17
VDD AA18
VDD AA29
VDD AB06
VDD AJ14
VDD AJ15
VDD AJ17
VDD AJ18
VDD AJ20
VDD AJ21
WE AP32 DDR2/1 SDRAM 66
Table 5. Signals Listed Alphabetically (Part 26 of 26)
Signal Name Ball Interface Group P age
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 51
Prelim inary Data Sheet
Signals in Ball Assignment Order
In the following table, only the default signal name is shown for each ball. Multiplexed or multifunction signals are
marked with an asterisk (*). To determine what other signals or functions can be programmed to those balls, look
up the default signal name in Table 5 on page 25.
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
52 AMCC Proprietary
Revision 1.19 – June 17, 2009
Table 6. Signals Listed by Ball Assignment (Part 1 of 9)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
A01 GND B01 GND C01 GND D01 PCI0IDSel
A02 GND B02 GND C02 GND D02 PCI0AD20
A03 GND B03 GND C03 GND D03 PCI0AD23
A04 PCI0AD17 B04 PCI0AD19 C04 PCI0IRdy D04 GND
A05 PCI0AD16 B05 OVDD C05 PCI0C/BE2 D05 PCI0AD18
A06 PCI0DevSel B06 PCI0PErr C06 PCI0Stop D06 PCI0TRdy
A07 PCI0AD14 B07 GND C07 PCI0C/BE1 D07 PCI0Par
A08 PCI0AD09 B08 PCI0AD11 C08 PCI0AD12 D08 PCI0AD13
A09 PCI0AD07 B09 OVDD C09 PCI0C/BE0 D09 PCI0AD08
A10 PCI0AD03 B10 PCI0AD02 C10 PCI0AD04 D10 PCI0AD06
A11 SPAGND B11 HISRRst C11 TmrClk D11 PCI0AD00
A12 SPAVDD B12 GND C12 GPIO40 * D12 GPIO27 *
A13 PerData29 B13 PerData30 C13 PerData31 D13 PerErr
A14 GPIO32 * B14 PerData28 C14 PerData25 D14 PerData27
A15 PerData18 B15 PerData19 C15 PerData21 D15 PerData23
A16 GPIO31 * B16 OVDD C16 GND D16 PerData22
A17 Reserved B17 PerData17 C17 PerReady D17 PerData16
A18 PerData15 B18 PerData14 C18 PerData13 D18 PerData06
A19 PerData12 B19 OVDD C19 PerData11 D19 PerData09
A20 GPIO30 * B20 PerData07 C20 PerData05 D20 PerData04
A21 PerData02 B21 PerData01 C21 PerData00 D21 GPIO45 *
A22 GPIO43 * B22 GPIO41 * C22 PerWBE3 D22 PerWBE2
A23 PerWBE1 B23 GND C23 PerWBE0 D23 PerR/W
A24 GPIO24 * B24 GPIO23 * C24 GPIO22 * D24 PerAddr31
A25 GPIO26 * B25 PerAddr30 C25 PerAddr29 D25 GPIO42 *
A26 PerAddr28 B26 OVDD C26 PerAddr27 D26 PerAddr22
A27 PerAddr26 B27 PerAddr24 C27 PerAddr20 D27 PerAddr25
A28 PerAddr21 B28 GND C28 PerAddr18 D28 PerAddr17
A29 PerAddr16 B29 PerAddr19 C29 PerAddr15 D29 PerAddr14
A30 PerAddr12 B30 OVDD C30 PerAddr10 D30 GPIO48 *
A31 PerAddr13 B31 PerAddr11 C31 GPIO47 * D31 GND
A32 PerAddr08 B32 GPIO46 * C32 GND D32 GPIO38 *
A33 GND B33 GND C33 UART0Tx D33 GPIO37 *
A34 GND B34 GND C34 UART0Rx D34 GPIO39 *
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 53
Prelim inary Data Sheet
E01 PCI0AD24 F01 PCI0AD30 G01 PCI0Gnt2 H01 GND
E02 OVDD F02 PCI0AD28 G02 GND H02 PCI0Req1
E03 PCI0AD22 F03 PCI0C/BE3 G03 PCI0Gnt0/Req H03 PCI0Gnt3
E04 PCI0AD25 F04 PCI0AD21 G04 PCI0AD27 H04 PCI0Gnt1
E05 GND F05 PCI0AD31 G05 PCI0AD26 H05 OVDD
E06 PCI0Frame F06 GND G06 No ball H06 PCI0AD29
E07 PCI0SErr F07 No ball G07 No Ball H07 No Ball
E08 OVDD F08 PCI0AD15 G08 No Ball H08 No Ball
E09 PCI0M66En F09 PCI0AD10 G09 No Ball H09 No Ball
E10 GND F10 PCI0AD05 G10 No Ball H10 No Ball
E11 PCI0AD01 F11 OVDD G11 No Ball H11 No Ball
E12 GPIO28 * F12 GPIO29 * G12 No Ball H12 No Ball
E13 OVDD F13 GPIO33 * G13 No Ball H13 No Ball
E14 PerData26 F14 VDD G14 No Ball H14 No Ball
E15 PerData20 F15 VDD G15 No Ball H15 No Ball
E16 PerData24 F16 GND G16 No Ball H16 No Ball
E17 FSOURCE0 F17 VDD G17 No Ball H17 No Ball
E18 PerData10 F18 VDD G18 No Ball H18 No Ball
E19 PerData08 F19 GND G19 No Ball H19 No Ball
E20 PerData03 F20 VDD G20 No Ball H20 No Ball
E21 GPIO44 * F21 VDD G21 No Ball H21 No Ball
E22 OVDD F22 ExtReset G22 No Ball H22 No Ball
E23 GND F23 PerClk G23 No Ball H23 No Ball
E24 PerCS0 F24 OVDD G24 No Ball H24 No Ball
E25 GND F25 PerBLast G25 No Ball H25 No Ball
E26 PerOE F26 GPIO25 * G26 No Ball H26 No Ball
E27 OVDD F27 PerAddr23 G27 No Ball H27 No Ball
E28 GND F28 No ball G28 No Ball H28 No Ball
E29 PerAddr09 F29 GND G29 No ball H29 TRST
E30 GND F30 GND G30 UARTSerClk H30 OVDD
E31 GPIO36 * F31 GND G31 GND H31 IIC0SData
E32 GPIO35 * F32 GND G32 TMS H32 Halt
E33 OVDD F33 TDO G33 GND H33 GPIO49 *
E34 GPIO34 * F34 TDI G34 SPIDO * H34 GPIO51 *
Table 6. Signals Listed by Ball Assignment (Part 2 of 9)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
54 AMCC Proprietary
Revision 1.19 – June 17, 2009
J01 GND K01 PCI0Clk L01 AGND M01 PCIE1Tx0
J02 OVDD K02 GND L02 AGND M02 PCIE1Tx0
J03 GND K03 PCI0Reset L03 AVDD M03 AVDD
J04 PCI0Int K04 PCI0Req2 L04 PCIE1Rx0 M04 AGND
J05 PCI0Req3 K05 GND L05 PCIE1Rx0 M05 AVDD
J06 PCI0Req0/Gnt K06 GND L06 AVDD M06 AGND
J07 No Ball K07 No Ball L07 No Ball M07 No Ball
J08 No Ball K08 No Ball L08 No Ball M08 No Ball
J09 No Ball K09 No Ball L09 No Ball M09 No Ball
J10 No Ball K10 No Ball L10 No Ball M10 No Ball
J11 No Ball K11 No Ball L11 No Ball M11 No Ball
J12 No Ball K12 No Ball L12 No Ball M12 No Ball
J13 No Ball K13 No Ball L13 No Ball M13 No Ball
J14 No Ball K14 No Ball L14 No Ball M14 No Ball
J15 No Ball K15 No Ball L15 No Ball M15 No Ball
J16 No Ball K16 No Ball L16 No Ball M16 No Ball
J17 No Ball K17 No Ball L17 No Ball M17 No Ball
J18 No Ball K18 No Ball L18 No Ball M18 No Ball
J19 No Ball K19 No Ball L19 No Ball M19 No Ball
J20 No Ball K20 No Ball L20 No Ball M20 No Ball
J21 No Ball K21 No Ball L21 No Ball M21 No Ball
J22 No Ball K22 No Ball L22 No Ball M22 No Ball
J23 No Ball K23 No Ball L23 No Ball M23 No Ball
J24 No Ball K24 No Ball L24 No Ball M24 No Ball
J25 No Ball K25 No Ball L25 No Ball M25 No Ball
J26 No Ball K26 No Ball L26 No Ball M26 No Ball
J27 No Ball K27 No Ball L27 No Ball M27 No Ball
J28 No Ball K28 No Ball L28 No Ball M28 No Ball
J29 TCK K29 TestEn L29 OVDD M29 TrcClk
J30 GND K30 GND L30 GP IO52 * M30 GND
J31 I IC0SClk K31 SPIClkOut * L31 GPIO53 * M31 GPIO59 *
J32 GND K32 SPIDI * L32 GPIO55 * M32 GPIO61 *
J33 OVDD K33 GPIO54 * L33 GPIO57 * M33 GND
J34 GPIO50 * K34 GPIO56 * L34 GPIO60 * M34 GPIO62 *
Table 6. Signals Listed by Ball Assignment (Part 3 of 9)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 55
Prelim inary Data Sheet
N01 PCIE1Tx1 P01 PCIE1CalRN R01 AGND T01 PCIE1Tx2
N02 PCIE1Tx1 P02 PCIE1CalRP R02 AGND T02 PCIE1Tx2
N03 AVDD P03 AGND R03 PCIE1RefClk T03 AVDD
N04 PCIE1Rx1 P04 AGND R04 PCIE1RefClk T04 PCIE1Rx2
N05 PCIE1Rx1 P05 AVDD R05 PCIE1AVReg T05 PCIE1Rx2
N06 AVDD P06 AGND R06 AGND T06 PAVDD
N07 No Ba ll P07 No Ball R07 No Ball T07 No Ball
N08 No Ba ll P08 No Ball R08 No Ball T08 No Ball
N09 No Ba ll P09 No Ball R09 No Ball T09 No Ball
N10 No Ba ll P10 No Ball R10 No Ball T10 No Ball
N11 No Ba ll P11 No Ball R11 No Ball T11 No Ball
N12 No Ba ll P12 No Ball R12 No Ball T12 No Ball
N13 No Ba ll P13 No Ball R13 No Ball T13 No Ball
N14No Ball P14GND R14OV
DD T14 GND
N15 No Ball P15 OVDD R15 GND T15 GND
N16No Ball P16GND R16GND T16GND
N17 No Ball P17 VDD R17 VDD T17 GND
N18 No Ball P18 VDD R18 VDD T18 GND
N19No Ball P19GND R19GND T19GND
N20 No Ball P20 OVDD R20 GND T20 GND
N21No Ball P21GND R21OV
DD T21 GND
N22 No Ba ll P22 No Ball R22 No Ball T22 No Ball
N23 No Ba ll P23 No Ball R23 No Ball T23 No Ball
N24 No Ba ll P24 No Ball R24 No Ball T24 No Ball
N25 No Ba ll P25 No Ball R25 No Ball T25 No Ball
N26 No Ba ll P26 No Ball R26 No Ball T26 No Ball
N27 No Ba ll P27 No Ball R27 No Ball T27 No Ball
N28 No Ba ll P28 No Ball R28 No Ball T28 No Ball
N29 GPIO58 * P29 VDD R29 VDD T29 MEMVRef2B
N30 SOVDD P30 MemData00 R30 MemData03 T30 GND
N31 GPIO63 * P31 DM0 R31 MemData07 T31 MemData13
N32 MemData05 P32 DQS0 R32 MemData02 T32 MemData11
N33 MemData04 P33 DQS0 R33 MemData12 T33 SOVDD
N34 MemData01 P34 MemData06 R34 MemData08 T34 MemData09
Table 6. Signals Listed by Ball Assignment (Part 4 of 9)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
56 AMCC Proprietary
Revision 1.19 – June 17, 2009
U01 AGND V01 PCIE1Tx3 W01 PCIE0Tx0 Y01 AGND
U02 AVDD V02 PCIE1Tx3 W02 PCIE0Tx0 Y02 AVDD
U03 AVDD V03 AVDD W03 AVDD Y03 AGND
U04 AGND V04 PCIE1Rx3 W04 PCIE0RX0 Y04 AVDD
U05 AGND V05 PCIE1Rx3 W05 PCIE0RX0 Y05 AGND
U06 AVDD V06 AVDD W06 AVDD Y06 VDD
U07 No Ball V07 No Bal l W07 No Bal l Y07 No Ball
U08 No Ball V08 No Bal l W08 No Bal l Y08 No Ball
U09 No Ball V09 No Bal l W09 No Bal l Y09 No Ball
U10 No Ball V10 No Bal l W10 No Bal l Y10 No Ball
U11 No Ball V11 No Bal l W11 No Bal l Y11 No Ball
U12 No Ball V12 No Bal l W12 No Bal l Y12 No Ball
U13 No Ball V13 No Bal l W13 No Bal l Y13 No Ball
U14 VDD V14 VDD W14 GND Y14 E1OVDD
U15 VDD V15 VDD W15 GND Y15 GND
U16 GND V16 GND W16 GND Y16 GND
U17 GND V17 GND W17 GND Y17 VDD
U18 GND V18 GND W18 GND Y18 VDD
U19 GND V19 GND W19 GND Y19 GND
U20 VDD V20 VDD W20 GND Y20 GND
U21 VDD V21 VDD W21 GND Y21 SOVDD
U22 No Ball V22 No Bal l W22 No Bal l Y22 No Ball
U23 No Ball V23 No Bal l W23 No Bal l Y23 No Ball
U24 No Ball V24 No Bal l W24 No Bal l Y24 No Ball
U25 No Ball V25 No Bal l W25 No Bal l Y25 No Ball
U26 No Ball V26 No Bal l W26 No Bal l Y26 No Ball
U27 No Ball V27 No Bal l W27 No Bal l Y27 No Ball
U28 No Ball V28 No Bal l W28 No Bal l Y28 No Ball
U29 VDD V29 VDD W29 GND Y29 VDD
U30 DM1 V30 DM2 W30 MemData19 Y30 MemData27
U31 DQS1 V31 MemData17 W31 DQS2 Y31 MemData29
U32 DQS1 V32 MemData16 W32 DQS2 Y32 MemData18
U33 MemData14 V33 MemData20 W33 SOVDD Y33 MemData23
U34 MemData15 V34 MemData10 W34 MemData21 Y34 MemData22
Table 6. Signals Listed by Ball Assignment (Part 5 of 9)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
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Revision 1.19 – June 17, 2009
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AA01 PCIE0AVReg AB01 PCIE0CalRP AC01 GND AD01 GND
AA02 PCIE0RefClk AB02 PCIE0CalRN AC02 SysReset AD02 SysClk
AA03 PCIE0RefClk AB03 SysErr AC03 GND AD03 GPIO07 *
AA04AGND AB04AV
DD AC04 GND A D04 GPIO21 *
AA05 PAVDD AB05 GPIO06 * AC05 GND AD05 GPIO01 *
AA06 VDD AB06 VDD AC06 USB2HClk AD06 E1OVDD
AA0 7 No Ba ll AB07 No Ball AC 0 7 No Ball AD07 No Bal l
AA0 8 No Ba ll AB08 No Ball AC 0 8 No Ball AD08 No Bal l
AA0 9 No Ba ll AB09 No Ball AC 0 9 No Ball AD09 No Bal l
AA1 0 No Ba ll AB10 No Ball AC 1 0 No Ball AD10 No Bal l
AA1 1 No Ba ll AB11 No Ball AC 1 1 No Ball AD11 No Bal l
AA1 2 No Ba ll AB12 No Ball AC 1 2 No Ball AD12 No Bal l
AA1 3 No Ba ll AB13 No Ball AC 1 3 No Ball AD13 No Bal l
AA1 4 GND A B14 No Ball AC14 No Ball AD14 No Ba ll
AA15 E1OVDD AB15 No Ball AC 1 5 No Bal l AD15 No Ba l l
AA1 6 GND A B16 No Ball AC16 No Ball AD16 No Ba ll
AA17 VDD AB17 No Ball AC17 No Ball AD17 No Ball
AA18 VDD AB18 No Ball AC18 No Ball AD18 No Ball
AA1 9 GND A B19 No Ball AC19 No Ball AD19 No Ba ll
AA20 SOVDD AB20 No Ball AC20 No Ball AD2 0 No Ball
AA2 1 GND A B21 No Ball AC21 No Ball AD21 No Ba ll
AA2 2 No Ba ll AB22 No Ball AC 2 2 No Ball AD22 No Bal l
AA2 3 No Ba ll AB23 No Ball AC 2 3 No Ball AD23 No Bal l
AA2 4 No Ba ll AB24 No Ball AC 2 4 No Ball AD24 No Bal l
AA2 5 No Ba ll AB25 No Ball AC 2 5 No Ball AD25 No Bal l
AA2 6 No Ba ll AB26 No Ball AC 2 6 No Ball AD26 No Bal l
AA2 7 No Ba ll AB27 No Ball AC 2 7 No Ball AD27 No Bal l
AA2 8 No Ba ll AB28 No Ball AC 2 8 No Ball AD28 No Bal l
AA29 VDD AB29 MemVRef1B AC29 MemAddr13 AD29 SOVDD
AA30DQS3 AB30SOV
DD AC30 ECC1 AD30 ECC7
AA31 DQS3 AB31 MemData26 AC31 ECC0 AD31 ECC6
AA32 MemData25 AB32 MemData31 AC32 ECC5 AD32 DQS8
AA33 MemData24 AB33 MemData30 AC33 GND AD33 DQS8
AA34 MemData28 AB34 DM3 AC34 ECC4 AD34 DM8
Table 6. Signals Listed by Ball Assignment (Part 6 of 9)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
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AE01 GPIO05 * AF01 GPIO03 * AG01 GPIO00 * AH01 GPIO15 *
AE02 GPIO04 * AF02 E1OVDD AG02 GPIO17 * AH02 GND
AE03 GND AF03 GPIO19 * AG03 GPIO20 * A H03 GPIO13 *
AE04 GPIO02 * AF04 GPIO16 * AG04 GPIO18 * AH04 GPIO08 *
AE05 GND AF05 GND AG05 E1OVDD AH05 GMC0TxD6
AE06 USB2HClk48 AF06 USB2DClk AG06 GPIO10 * AH06 No ball
AE0 7 No Ba ll AF07 No Ball A G 0 7 No Ball AH07 No Ba l l
AE0 8 No Ba ll AF08 No Ball A G 0 8 No Ball AH08 No Ba l l
AE0 9 No Ba ll AF09 No Ball A G 0 9 No Ball AH09 No Ba l l
AE1 0 No Ba ll AF10 No Ball A G 1 0 No Ball AH10 No Ba l l
AE1 1 No Ba ll AF11 No Ball A G 1 1 No Ball AH11 No Ba l l
AE1 2 No Ba ll AF12 No Ball A G 1 2 No Ball AH12 No Ba l l
AE1 3 No Ba ll AF13 No Ball A G 1 3 No Ball AH13 No Ba l l
AE1 4 No Ba ll AF14 No Ball A G 1 4 No Ball AH14 No Ba l l
AE1 5 No Ba ll AF15 No Ball A G 1 5 No Ball AH15 No Ba l l
AE1 6 No Ba ll AF16 No Ball A G 1 6 No Ball AH16 No Ba l l
AE1 7 No Ba ll AF17 No Ball A G 1 7 No Ball AH17 No Ba l l
AE1 8 No Ba ll AF18 No Ball A G 1 8 No Ball AH18 No Ba l l
AE1 9 No Ba ll AF19 No Ball A G 1 9 No Ball AH19 No Ba l l
AE2 0 No Ba ll AF20 No Ball A G 2 0 No Ball AH20 No Ba l l
AE2 1 No Ba ll AF21 No Ball A G 2 1 No Ball AH21 No Ba l l
AE2 2 No Ba ll AF22 No Ball A G 2 2 No Ball AH22 No Ba l l
AE2 3 No Ba ll AF23 No Ball A G 2 3 No Ball AH23 No Ba l l
AE2 4 No Ba ll AF24 No Ball A G 2 4 No Ball AH24 No Ba l l
AE2 5 No Ba ll AF25 No Ball A G 2 5 No Ball AH25 No Ba l l
AE2 6 No Ba ll AF26 No Ball A G 2 6 No Ball AH26 No Ba l l
AE2 7 No Ba ll AF27 No Ball A G 2 7 No Ball AH27 No Ba l l
AE2 8 No Ba ll AF28 No Ball A G 2 8 No Ball AH28 No Ba l l
AE29 ClkE n 0 AF29 GND AG 2 9 GN D AH29 No ball
AE30 GND AF30 GND AG30 SOVDD AH30 MemAddr04
AE31 ClkEn3 AF31 MemAddr11 AG31 MemAddr07 AH31 MemAddr05
AE32 ECC2 AF32 MemAddr14 AG32 MemAddr09 AH32 MemAddr06
AE33 ClkEn2 AF33 SOVDD AG33 MemAddr10 AH33 GND
AE34 ECC3 AF34 ClkEn1 AG34 MemAddr12 AH34 MemAddr08
Table 6. Signals Listed by Ball Assignment (Part 7 of 9)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
460EX – PPC460EX Embedded Processor
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Prelim inary Data Sheet
AJ01 GPIO14 * AK01 GMCMDIO * AL01 GMC0TxD3 AM01 GMC0TxD5
AJ02 GPIO11 * AK02 E1OVDD AL02 GMC0TxD2 AM02 GMC0TxD0
AJ03 GMCMDClk * AK03 GMC0TxD4 AL03 GMC0TxD7 AM03 GND
AJ04 GPIO12 * AK04 GMC0TxD1 AL04 GND AM04 GND
AJ05 GPIO09 * AK05 GND AL05 GND AM05 GMC0TxEn
AJ06 GND AK06 GND AL06 GMC0RxDV AM06 GND
AJ07 No ball AK07 GND AL07 GMC0CrS AM07 GMC0RxClk
AJ08 GMC0TxER AK08 E1OVDD AL08 GMC0RxD5 AM08 GMC0RxD6
AJ09 GMC0RxD3 AK09 GMC0RxD1 AL09 GMC0RxD0 AM09 TherMonA
AJ10 GMC0RxER AK10 GND AL10 TherMonB AM10 GND
AJ11 E1OVDD AK11 SGMII1TxD AL11 SGMII1TxD AM11 SGMII0TxD
AJ12 SGMIITxClk AK12 SGMIITxClk AL12 Reserved AM12 Reserved
AJ13 GND AK13 E2OVDD AL13 Reserved AM13 Reserved
AJ14 VDD AK14 GND AL14 SGMII1RxClk AM14 SGMII1RxClk
AJ15 VDD AK15 SGMII0RxClk AL15 SGMII0RxClk AM15 Reserved
AJ16 GND AK16 MemData63 AL16 MemData58 AM16 MemData62
AJ17 VDD AK17 DQS7 AL17 DQS7 AM17 DM7
AJ18 VDD AK18 MemData60 AL18 MemData50 AM18 MemData51
AJ19 MemVRef1A AK19 GND AL19 DQS6 AM19 DQS6
AJ20 VDD AK20 MemData52 AL20 MemData48 AM20 MemData49
AJ21 VDD AK21 MemData34 AL21 MemData47 AM21 MemData42
AJ22 MemVRef2A AK22 SOVDD AL22 GND AM22 DQS5
AJ23 GND AK23 MemData44 AL23 MemData40 AM23 MemData41
AJ24 SOVDD AK24 GND AL24 MemData38 AM24 MemData39
AJ25 GND AK25 GND AL25 GND AM25 DM4
AJ26 GND AK26 MemData37 AL26 MemData36 AM26 MemData32
AJ27 GND AK27 SOVDD AL27 MemODT3 AM27 MemODT1
AJ28 No ball AK28 GND AL28 BankSel0 AM28 MemODT2
AJ29 GND AK29 GND AL29 CAS AM29 BankSel2
AJ30 GND AK30 GND AL30 GND AM30 GND
AJ31 GND AK31 MemClkOut1 AL31 GND AM31 BA2
AJ32 MemAddr02 AK32 MemClkOut1 AL32 GND AM32 GND
AJ33 MemAddr01 AK33 SOVDD AL33 GND AM33 MemDCFdbkD
AJ34 MemAddr03 AK34 MemAddr00 AL34 GND AM34 MemDCFdbkR
Table 6. Signals Listed by Ball Assignment (Part 8 of 9)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
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AN01 GND AP01 GND
AN02 GND AP02 GND
AN03 GND AP03 GND
AN04 GMC0TxClk AP04 GND
AN05 E1OVDD AP05 GMC0CD
AN06 GMC0GTxClk AP06 GND
AN07 GND AP07 GMC0RxD7
AN08 GMC0RxD4 AP08 GMC0RxD2
AN09 E1OVDD AP09 GMCRefClk
AN10 Reserved AP10 Reserved
AN11 SGMII0TxD AP11 EAVDD
AN12 GND AP12 EAGND
AN13 SGMII1RxD AP13 SGMII1RxD
AN14 SGMII0RxD AP14 SGMII0RxD
AN15 Reserved AP15 MemData59
AN16 E2OVDD AP16 GND
AN17 MemData57 AP17 GND
AN18 MemData61 AP18 MemData56
AN19 SOVDD AP19 MemData55
AN20 DM6 AP20 MemData54
AN21 MemData43 AP21 MemData53
AN22 DQS5 AP22 MemData46
AN23 GND AP23 DM5
AN24 MemData35 AP24 MemData45
AN25 DQS4 AP25 DQS4
AN26 SOVDD AP26 MemData33
AN27 MemClkOut0 AP27 MemClkOut0
AN28 GND AP28 MemODT0
AN29 BankSel3 AP29 BankSel1
AN30 SOVDD AP30 RAS
AN31 GND AP31 BA1
AN32 BA0 AP32 WE
AN33 GND AP33 GND
AN34 GND AP34 GND
Table 6. Signals Listed by Ball Assignment (Part 9 of 9)
Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name
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Prelim inary Data Sheet
Signal Descriptions
The PPC460EX embedded controller is packaged in a 728-ball thermally enhanced plastic ball grid array (TE-
PBGA). The following tables describe the package level pin-out.
In the table Table 9 on page 64, each I/O signal is listed along with a short description of its function. Active-low
signals (for example, RAS) are mar ked wit h an ov erli ne. Pl ease see Table 5 on page 25 for the pin (ball) number to
which each signal is assigned.
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases,
the signal names shown in the following table are not accompanied by signal names that might share the same pin.
If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in Table 5 on
page 25. It is expected that in any single application a particular pin will always be programmed to serve the same
function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be
possible.
Note: Signals multiplexed with GPIO default to GPIO receivers and float after reset. Initialization software must
configure the GPIO registers for the desired function as described in the GPIO section of the user’s manual. Any of
these signals requiring a particular state prior to running initialization code must be terminated with pull-ups or
pull-downs.
Table 7. Pin Summary
Grou p No. of Pins
Total Signal Pins 430
VDD 37
OVDD 23
SOVDD 16
E1OVDD 10
E2OVDD 2
GND 160
PAVDD 2
AVDD 18
AGND 17
EAVDD 1
EAGND 1
SPAVDD 1
SPAGND 1
Total Power Pins 289
Reserved 9
Total Pins 728
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Multipurpose Signals
In addition to multiplexing, some pins such as those carrying the EOTx/TCx signals are also multipurpose. Control
of which function a multipurpose pin has is determined by direction, register settings, and so on. Both functions are
shown separated by a slash (/).
Multimode Signals
In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin
has multiple signal names assigned to distinguish different modes of operation, all of the names are shown
separated by a comma.
Strapping Pins
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 102). Note that
these are not multiple xed pins sinc e the function of the pins is not progra mmab le.
Reserved Pins
The balls marked Reserved on this chip are not functional. However, some of the reserved balls cannot be left
unconnected. Connect the balls shown in the following table as indicated:
Unused Interfaces
The following describes how to terminate the PCI, PCI Express, SATA, and GPIO signals that might not be used.
PCI:
When the PCI bridge is unused, configure the PCI controller to park on the bus by pulling the PCIReq0/GNT signal
low. Parking forces the PLB4 to PCI bridge to actively drive PCI0AD0:31 and PCI0C0:3/BE0:3 greatly reducing the
number of termination resistors required. The remaining PCI control signals must be terminated as follows:
• Disable the internal PCI arbiter. (See the Bootstrap Operation chapter in the user’s manual. Boot Options A-F
automatically disable the PCI Arbiter.)
•PCI0SErr
- Pull up through a 3kΩ resistor to +3.3V
• PCI0TRDY - Pull up through a 3kΩ resistor to +3.3V
•PCI0Stop
- Pull up through a 3kΩ resistor to +3.3V.
• PCI0Req0/Gnt - Pull down thro ugh a 1kΩ resistor to GND.
• PCI0Req1:3 - Individu all y pull up each signal throug h 3kΩ resistors to +3. 3V.
• PCI0Clk - Requires a clock. The frequency must be between 1MHz and 66MHz.
PCI-E/SATA:
When the PCI Express 0/SATA interface is unused, terminate as follows:
• PCIE0AVReg[SATA0AVReg] - Leave unconnected.
• PCIE0CalRN[SATA0CalRN] - Leave unconnected.
• PCIE0CalRP[SATA0CalRP] - Leave unconnected.
• PCIE0RefClk[SATA0RefClk] - Pull down through a 1kΩ resistor to GND.
•PCIE0RefClk
[SATA0RefClk] - Pull down through a 1kΩ resistor to GND.
• PCIE0Rx0[SATA0Rx0] - Pull down through a 1kΩ resistor to GND.
Table 8. Non-Functional Ball Connections
Ball Connection
AM15 1kΩ to GND
AN15 1kΩ to GND
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•PCIE0Rx0[SATA0Rx0] - Pull down through a 1kΩ resistor to GND.
• PCIE0Tx0[SATA0Tx0] - Leave unconnected.
•PCIE0Tx0
[SATA0Tx0] - Leave unconnected .
When the PCI Express 1 interface is unused terminate as follows:
• PCIE1AVR eg - Leave unconnected .
• PCIE1CalRN - Leave unconnected.
• PCIE1CalRP - Leave unconnected.
• PCIE1RefClk - Pull-down through a 1kΩ resistor to GND.
•PCIE1RefClk
- Pull-down through a 1kΩ resistor to GND.
• PCIE1Rx0:3 - Individually pull-down each signal through a 1kΩ resistor to GND.
•PCIE1Rx0:3
- Individually pull-down each signal through a 1kΩ resistor to GND.
• PCIE1Tx0:3 - Leave unconnected.
•PCIE1Tx0:3
- Leave unconnected.
Signals Multiplexed with GPIO:
By default after reset, signals shared with GPIO pins are configured as GPIO receivers. Termination however, is
not needed if the GPIO during initialization are configured as outputs. To configure as drivers, set and clear the
appropriate bits in the GPIOn_ODR, GPIOn_TCR and GPIOn_OR registers as described in the GPIO chapter of
the user’s manual.
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Table 9. Signal Functional Description (Part 1 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OVDD or 8.2kΩ for PCI to OVDD or equivalent.
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OVDD or equivalent.
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OVDD) or pull-down (recommended value is 1kΩ to
GND) required
Signal Name Description I/O Type Notes
PCI Inter fac e
PCIAD00:31 Address/Data bus (bidirectional). I/O 3.3V PCI
PCIC0:3/BE0:3 PCI Command/Byte Enables.I /O 3.3V PCI
PCI0Clk Provides timing to the PCI interface for PCI transactions.
Note: A clock is required even when the PCI interface is not
used. The frequency must be between 1MHz and 66MHz. I 3.3V PCI 1
PCI0DevSel Indicates the driving device has decoded its address as the
target of the current access.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.) I/O 3.3V PC I 4
PCI0Frame Driven by the current master to indicate beginning and duration
of an access.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.) I/O 3.3V PC I 4
PCI0IRdy Indicates initiating agent’s ability to complete the current data
phase of the transaction.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.) I/O 3.3V PC I 4
PCI0TRdy Indicates the target agent’s ability to complete the current data
phase of the transaction.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.) I/O 3.3V PC I 4
PCI0Stop Indicates the current target is requesting the master to stop the
current transaction.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.) I/O 3.3V PC I 4
PCI0PErr Reports data parity errors during all PCI transactions except a
Special Cycle.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.) I/O 3.3V PC I 4
PCI0SErr Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.) I/O 3.3V PC I 4
PCI0Req0/Gnt
Indicates to the PCI arbiter that the specified agent wishes t o use
the bus. When the internal arbiter is enabled, input is Req0.
When internal arbiter is disabled, input is Gnt.
(PCI 2.2 specification requires an 8.2KΩ pull-up on host system.)
I 3 .3V PCI 2
PCI0Req1:3 An indication to the PCI arbiter that the specified agent wishes to
use the bus. Used only when internal PCI arbiter enabled. I 3.3V PCI 2
PCI0Gnt0/Req Indicates that the specified agent is granted access to the bus.
When the internal arbiter is enabled, output is Gnt0. When the
internal arbiter is disabled, output is Req. O 3.3V PCI
PCI0Gnt1:3 Indicates that the specified agent is granted access to the bus.
Used only when internal PCI arbiter enabled. O 3.3V PCI
PCI0IDSel Used as a chip select during configuration read and write
transactions. I 3.3V PCI 5
PCI0INT Level sensitive PCI interrupt. O 3.3V PCI
PCI0M66En Capable of 66MHz operation. I 3.3V PCI 5
PCI0Par Even parity across PCIAD00:31 and PCIC0:3/BE0:3 buses. I/O 3.3V PCI
460EX – PPC460EX Embedded Processor
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PCI0Reset Brings PCI device registers and logic to a consistent state. O 3.3V PCI
PCI Express Interface (n = 0 and 1)
PCIEnRefClk
PCIEnRefClk
Reference Clock: 100MHz differential pair.
Note: AC coupling required. See “PCI-E and SATA Reference
Clock AC Coupling Recommendations” on page 100. I2.5V LVDS
Rcvr w/term
PCIEnAVReg Analog obvservation point for manufacturing test of internal
voltage regulator.
Note: For normal operation, do not terminate. na Analog
PCIEnCalRN
PCIEnCalRP Connect a 1.37kΩ ± 1% external calibration resistor between
these two pins. na Analog
PCIEnRx0:3
PCIEnRx0:3
Differential receive signal pairs.
PCIE0 is a single-channel (Rx0 only) interface.
PCIE1 is a four-channel (Rx0:3) interface.
Lane 0 is the LSB.
I2.5V LVDS
Rcvr w/term
PCIEnTx0:3
PCIEnTx0:3
Differential transmit signal pairs.
PCIE0 is a single-channel (Tx0 only) interface.
PCIE1 is a four-channel (Tx0:3) interface.
Lane 0 is theLSB.
Note: AC couple only.
O2.5V LVDS
Drvr w/term
Table 9. Signal Functional Description (Part 2 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OVDD or 8.2kΩ for PCI to OVDD or equivalent.
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OVDD or equivalent.
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OVDD) or pull-down (recommended value is 1kΩ to
GND) required
Signal Name Description I/O Type Notes
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66 AMCC Proprietary
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DD R 2/1 SD RAM Interf ac e
BA0:2 Bank Address supporting up to eight internal banks. O 2.5V (1.8V)
SSTL2 Dr/Rcv
BankSel0:3 Selects up to four external DDR SDRAM banks (a.k.a. ranks). O 2.5V (1.8V)
SSTL2 Dr/Rcv
CAS Column Address Strobe. O 2.5V (1.8V)
SSTL2 Dr/Rcv
ClkEn0:3 Clock Enable. O 2.5V (1.8V)
SSTL2 Dr/Rcv
DM0:7
DM8 Memory write data byte lane masks. DM8 is the byte lane mask
for the ECC byte lane. O2.5V (1.8V)
SSTL2 Dr/Rcv
DQS0:7
DQS0:7
DQS8
DQS8
Differential byte lane data strobe.
Differential byte lane data strobe for ECC. I/O 2.5V (1.8V)
SSTL2 Diff
Dr/Rcv
ECC0:7 ECC check bits 0:7. I/O 2.5V (1.8V)
SSTL2 Dr/Rcv
MemAddr00:14 Memory address bus.
MemAddr14 is the most significant bit (msb). O2.5V (1.8V)
SSTL2 Dr/Rcv
MemData00:63 Mem ory data bus (MemData32:6 3 available for DDR2 only).
MemData00 is the most significant bit (msb). I/O 2.5V (1.8V)
SSTL2 Dr/Rcv
MemClkOut0:1
MemClkOut0:1 Subsystem clock outputs. O 2.5V (1.8V)
SSTL2 Dr/Rcv
Diff Driver
MemODT0:3 DDR2 On-die termination enable (not used with DDR1). O 2.5V (1.8V)
SSTL2 Dr/Rcv
RAS Row Address Strobe. O 2.5V (1.8V)
SSTL2 Dr/Rcv
WE Write Enable. O 2.5V (1.8V)
SSTL2 Dr/Rcv
MemVRef1A:B Memory voltage reference 1, A and B input. I Volt ref receiver
(1.25V or 0.9V)
MemVRef2A:B Memory voltage reference 2, A and B input. I Volt ref driver
(1.25V or 0.9V)
MemDCFdbkD
Feedback driver for I/O timing measurements.
Note: Connect directly to MemDCFdbkR. Use the shortest trace
length possible. Do not include series termination or parallel
termination to Vtt.
O2.5V (1.8V)
SSTL2 Dr/Rcv
MemDCFdbkR Feedback receiver. Connect externally to MemDCFdbkD. I 2.5V (1.8V)
SSTL2 Dr/Rcv
HISRRst SDRAM hardware initiated self-refresh rese t control. I 3.3V LVTTL 1, 2
Table 9. Signal Functional Description (Part 3 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OVDD or 8.2kΩ for PCI to OVDD or equivalent.
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OVDD or equivalent.
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OVDD) or pull-down (recommended value is 1kΩ to
GND) required
Signal Name Description I/O Type Notes
460EX – PPC460EX Embedded Processor
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Prelim inary Data Sheet
Ethernet 0 Interface
GMCMD Clk GMII, MII, RGMII: Management data clock. O 3.3V tolerant
2.5V CMOS
GMCMDIO GMII, MII, RGMII: Transfer command and status information
between MII and PHY. I/O 3.3V tolerant
2.5V CMOS
GMCRefClk GMII, SGMII, RGMII: 125MHz reference clock for
10/100/1000Mbps. I3.3V tolerant
2.5V CMOS 1, 5
GMC0GTxClk,
GMC0TxClk GMII 0: Transmit clock for 1000Mbps.
RGMII 0: Transmit clock for 1000Mbps. O3.3V tolerant
2.5V CMOS
GMC0TxClk GMII/MII 0: Transmit clock for 10/100Mbps. I 3.3V tolerant
2.5V CMOS 1, 5
GMC0TxD1:0,
GMC0TxD1:0 GMII/MII 0: Transmit data.
RGMII 0: Transmit data. O3.3V tolerant
2.5V CMOS
GMC0TxD3:2,
GMC0TxD3:2 GMII/MII 0: Transmit data.
RGMII 0: Transmit data. O3.3V tolerant
2.5V CMOS
GMC0TxD7:4,
GMC1TxD3:0 GMII 0: Transmit data.
RGMII 1: Transmit data. O3.3V tolerant
2.5V CMOS
GMC0TxEn,
GMC0TxCtl GMII/MII 0: Transmit enable.
RGMII 0: Transmit control. O3.3V tolerant
2.5V CMOS
GMC0TxEr,
GMC1TxCtl GMII/MII 0: Transmit error.
RGMII 1: Transmit control. O3.3V tolerant
2.5V CMOS
GMC0CD,
GMC1RxClk GMII/MII 0: Collision detection.
RGMII 1: Receive clock. I3.3V tolerant
2.5V CMOS 1, 5
GMC0CrS,
GMC1GTxClk GMII/MII 0: Carrier sense.
RGMII 1: Transmit clock for 1000 Mbps. I/O 3.3V tolerant
2.5V CMOS
GMC0RxClk,
GMC0RxClk GMII/MII 0: Receive clock.
RGMII 0: Receive clock. I3.3V tolerant
2.5V CMOS 1, 5
GMC0RxD1:0,
GMC0RxD1:0 GMII/MII 0: Receive data.
RGMII 0: Receive data. I3.3V tolerant
2.5V CMOS 5
GMC0RxD3:2,
GMC0RxD3:2 GMII/MII 0: Receive data.
RGMII 0: Receive data. I3.3V tolerant
2.5V CMOS 5
GMC0RxD7:4,
GMC1RxD3:0 GMII/MII 0: Receive data.
RGMII 1: Receive data. I3.3V tolerant
2.5V CMOS 5
GMC0RxDV,
GMC0RxCtl GMII/MII 0: Receive data valid.
RGMII 0: Receive control. I3.3V tolerant
2.5V CMOS 5
GMC0RxEr,
GMC1RxCtl GMII/MII 0: Receive error.
RGMII 1: Receive control. I3.3V tolerant
2.5V CMOS 5
Table 9. Signal Functional Description (Part 4 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OVDD or 8.2kΩ for PCI to OVDD or equivalent.
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OVDD or equivalent.
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OVDD) or pull-down (recommended value is 1kΩ to
GND) required
Signal Name Description I/O Type Notes
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
68 AMCC Proprietary
Revision 1.19 – June 17, 2009
Eth e r net SGMI I Gi gabi t Inter fa c e
SGMIITxClk
SGMIITxClk Differential transmit clock: Common 625MHz to PHYs. O 1.8V LVDS
Drvr w/term
SGMII0:1RxClk
SGMII0:1RxClk
Differential receive clock: 625MHz from PHY. The differential
receiver clock is required for SGMII. Clock recovery from the
differential SGMII0:2RxD signals is not supported. I1.8V LVDS
Rcvr w/term
SGMII0:1RxD
SGMII0:1RxD Differential receive data. I 1.8V LVDS
Rcvr w/term
SGMII0:1TxD
SGMII0:1TxD Differential transmit data. O 1.8V LVDS
Drvr w/term
SATA Interface
SATA0RefClk
SATA0RefClk
Reference Clock: 100 MHz differential clock pair.
Note: AC coupling required. See “PCI-E and SATA Reference
Clock AC Coupling Recommendations” on page 100. I2.5V LVDS
Rcvr w/term
SATA0Rx0
SATA0Rx0 Data Receive differential signals.
Note: Must be AC coupled. I2.5V LVDS
Rcvr w/term
SATA0Tx0
SATA0Tx0 Data Transmit differential signals.
Note: Must be AC coupled. O2.5V LVDS
Drvr w/term
SATA0AVReg Analog obvservation point for manufacturing test of internal
voltage regulator.
Note: For normal operation, do not terminate. na Analog
SATA0CalRP
SATA0CalRN Connect a 1.37kΩ ± 1% external calibration resistor between
these two pins. na Analog
Table 9. Signal Functional Description (Part 5 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OVDD or 8.2kΩ for PCI to OVDD or equivalent.
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OVDD or equivalent.
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OVDD) or pull-down (recommended value is 1kΩ to
GND) required
Signal Name Description I/O Type Notes
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 69
Prelim inary Data Sheet
DMA Interface
DMAAck0:3 External peripheral DMA acknowledge.
Used by the PPC460EX to indicate that data transfers have
occurred. O3.3V LVTTL
DMAReq0:3 External peripheral DMA request.
Used by slave peripherals to indicate they are prepared to
transfer data. I3.3V LVTTL 5
EOT0:3/TC0:3 End Of Transfer/Terminal Count. I/O 3.3V LVTTL 5
External Peripheral Interface
PerAddr05:31 Peripheral address bus used by the PPC460EX.
PerAddr05 is the most significant bit (msb) on this bus. I/O 3.3V LVTTL
PerData00:31 Peripheral data bus used by the PPC460EX.
PerData00 is the most significant bit (msb) on this bus. I/O 3.3V LVTT L
PerPar0:3 Peripheral data bus parity used by the PPC460EX. I/O 3.3V LVTTL
PerBLast Last burst transfer.
Used by either the peripheral controller or DMA controller to
indicates the last transfer of a memory access. I/O 3.3V L VTTL
PerCS0:5 External peripheral device select. O 3.3V LVTTL
PerOE
Output enable.
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC460EX is the
bus master, it enables the selec ted device to drive the bus.
O3.3V LVTTL
PerReady Used by a peripheral slave to indicate it is ready to transfer data. I 3.3V LVTTL
Rcvr 1, 2
PerR/W
Read/Write.
Used by the PPC460EX as an output by either the peripheral
controller or DMA controller depending upon the type of transfer
involved. High indicates a read from memory, low indicates a
write to memory.
I/O 3.3V LVTTL
PerWBE0:3 External peripheral data bus byte enables. I/O 3.3V LVTTL
PerErr External Error. Used as an input to record external slave
peripheral errors. I3.3V LVTTL
Rcvr 1, 5
ExtReset Peripheral Reset. Used by syn chronous peripheral slaves.
Note: The state of any external signals or clocks cannot be
guaranteed until the ExtReset signal has been de-asserted. O3.3V LVTTL
PerClk Peripheral Clock. Used by synchronous peripheral slaves. O 3. 3V LVTTL
Table 9. Signal Functional Description (Part 6 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OVDD or 8.2kΩ for PCI to OVDD or equivalent.
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OVDD or equivalent.
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OVDD) or pull-down (recommended value is 1kΩ to
GND) required
Signal Name Description I/O Type Notes
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
70 AMCC Proprietary
Revision 1.19 – June 17, 2009
UART Peripheral Interface
The UART interface can be configured as follows:
1. One 8-pin, where n = 0
2. Two 4-pin, where n = 0 & 1
3. Four 2-pin, where n = 0 & 1 & 2 & 3
UARTSerClk This input provides an alternative to the internally generated
serial clock. It is used in cases where the allowable internally
generated clock rates are not satisfactory. I3.3V LVTTL
w/pull-up 1
UARTnRx Receive data. I 3.3V LVTTL
UARTnTx Transmit data. O 3. 3V LVTTL
UARTnDCD Data Carrier Detect. I 3.3V LVTTL 6
UARTnDSR Data Set Ready. I 3.3V LVTTL 6
UARTnCTS Clear To Send. I 3.3V LVTTL 6
UARTnDTR Data Terminal Ready. O 3.3V LVTTL
UARTnRTS Request To Send. O 3.3V LVTTL
UARTnRI Ring Indicator. I 3.3V LVTTL
IIC Peripheral Interface (n = 0 and 1)
IICnSClk IIC0 Serial Clock. I/O 3.3V LVTTL 1, 2
IICnSData IIC0 Serial Data. I/O 3.3V LVTTL 2
USB 2.0 OTG (Device or Host) Interface
USB2DD7:0 B idirectional Device data bus. I/O 3.3V tolerant
2.5V CMOS
USB2D Dir Transfer direction. PHY has data to transfer. I 3.3V tolerant
2.5V CMOS 1
USB2DNext Next transfer. Input signal from the PHY:
Receiving—ready to accept the next data transfer.
Transmitting—a new byte is ready to send. I3.3V tolerant
2.5V CMOS 1
USB2DStop Stop transfer. Output signal to the PHY:
Receiving—stop transferring data.
Transmitting—the last byte of data has been sent. O3.3V tolerant
2.5V CMOS
USB2DClk USB 2.0 OTG clock—60MHz. I 3.3V tolerant
2.5V CMOS 1, 5
Table 9. Signal Functional Description (Part 7 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OVDD or 8.2kΩ for PCI to OVDD or equivalent.
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OVDD or equivalent.
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OVDD) or pull-down (recommended value is 1kΩ to
GND) required
Signal Name Description I/O Type Notes
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 71
Prelim inary Data Sheet
USB 2.0 Host Interface
USB2H D7:0 Bidirectional Host data bus. I/O 3.3V tolerant
2.5V CMOS
USB2H Dir Transfer direction. PHY has data to transfer. I 3.3V tolerant
2.5V CMOS 1
USB2HNext Next transfer. Input signal from the PHY:
Receiving—ready to accept the next data transfer.
Transmitting—a new byte is ready to send. I3.3V tolerant
2.5V CMOS 1, 5
USB2HStop Stop transfer. Output signal to the PHY:
Receiving—stop transferring data.
Transmitting—the last byte of data has been sent. O3.3V tolerant
2.5V CMOS
USB2HClk USB 2.0 Host clock—60MHz. I 3.3V tolerant
2.5V CMOS 1, 5
USB2HClk48 USB 2.0 Host clock—48MHz. I 3.3V tolerant
2.5V CMOS 1, 5
NAND Flash Interface
NFALE Address Latch Enable. O 3. 3V LVTTL
NFCLE Command Latch Enable.
Latches operational commands into the NAND Flash. O3.3V LVTTL
NFRdyBusy Ready/Busy.
Indicates status of device during program erase or page read.
This signal is wire-OR connected from all NAND Flash devices. I3.3V LVTTL
NFREn Read Enable.
Data is latched on the rising edge. O3.3V LVTTL
NFWEn Write Enable.
Data is latched on the rising edge. O3.3V LVTTL
NFCE0:3 Chip enable. O 3.3V LVTTL
Serial Peripheral Interface
SPIClkOut Clock output. O 3.3V LVTTL 1
SPIDI Data input. I 3.3V LVTTL
w/pull-up 2
SPIDO Data output. O 3.3V LVTTL
Interrupts Interface
IRQ0:15 External interrupt requests 0 through 15. I 3.3V LVTTL 1, 5
Table 9. Signal Functional Description (Part 8 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OVDD or 8.2kΩ for PCI to OVDD or equivalent.
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OVDD or equivalent.
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OVDD) or pull-down (recommended value is 1kΩ to
GND) required
Signal Name Description I/O Type Notes
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
72 AMCC Proprietary
Revision 1.19 – June 17, 2009
JTAG Interface
TCK Test Clock. I 3.3V LVTTL
w/pull-up 1
TDI Test D a ta In. I 3.3V LVTTL
w/pull-up
TDO Test D a ta Out. O 3.3V LV TTL
TMS Test Mode Select. I 3.3V LVTTL
w/pull-up
TRST Test Reset. During chip power-up, this signal must be low from
the start of VDD ramp-up until at least 32 SysClk cycles after VDD
is stable in order to initialize the JTAG controller. I3.3V LVTTL
w/pull-up 5
System Interface
SysClk Main system clock input. I 3.3V tolerant
2.5V CMOS 1
SysErr Set to 1 when a machine check is generated. O 3.3V tolerant
2.5V CMOS
SysReset Main system reset. External logic can drive this pin low (minimum
of 32 SysClk cycles) to initiate a system reset. A system reset
can also be initiated by software. I 3.3V tolerant
2.5V CMOS 1, 2
TmrClk Processor timer external input clock. I 3.3V LVTTL
w/pull-up 1
Halt Halt from external debugger. I 3.3V LVTTL
w/pull-up 1
FSOURCE0 Reserved, Manufacturing Test Signal
Must connect to GND (no pull-down resistor required). IN/A
TestEn Test enable.
Note: Do not connect for normal operation. I3.3V LVTTL
w/pull-down
GPIO00:21 General purpose I/O. I/O 3.3V tolerant
2.5V CMOS
GPIO22:63 General purpose I/O. I/O 3.3V LVTTL
TherMonA
TherMonB On-chip thermal monitor (P diffusion).
On-chip thermal monitor (N diffusion). I
OThermal
monitor
Trace Interface
TrcBS0:2 Trace branch execution status. O 3. 3V LVTTL
TrcClk Trace data capture clock; runs at 1/4 the frequency of the
processor. O3.3V LVTTL
TrcES0:4 Trace Execution Status is presented every fourth processor clock
cycle. O3.3V LVTTL
TrcTS0:6 Additional information on trace execution and branch status. O 3.3V LVTTL
Table 9. Signal Functional Description (Part 9 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OVDD or 8.2kΩ for PCI to OVDD or equivalent.
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OVDD or equivalent.
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OVDD) or pull-down (recommended value is 1kΩ to
GND) required
Signal Name Description I/O Type Notes
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 73
Prelim inary Data Sheet
Other
Reserved
To avoid noise pickup problems, some of these balls must be
connected in the board design as shown Table 8 on page 62.
Otherwise, do not connect voltage, ground, or any signals to
these pins.
na na
Power
VDD +1.25V—Logic voltage. na na
OVDD +3.3V—I/O voltage (except DDR SDRAM, Ethernet, and USB). na na
SOVDD +1.8V (DDR2) or +2.5V (DDR1)—I/O voltage for DDR SDRAM. na na
E1OVDD +2.5V—I/O voltage for Ethernet (except SGMII) and USB. na na
E2OVDD +1.8V—I/O Ethernet (SGMII). na na
GND Ground for logic and I/O voltages. na na
AVDD +1.25V—PCI-Express SerDes Analog Supply. na na
PAVDD +2.5V—PCI-Express SerDes PLL Analog Supply. na na
AGND Ground for AVDD and PAVDD.nana
EAVDD +2.5V—Filtered analog voltage for Ethernet PLLs. na na
EAGND Ground for EAVDD.nana
SPAVDD +2.5V—Filtered analog voltage for system PLL. na na
SPAGND Ground for SPAVDD.nana
Table 9. Signal Functional Description (Part 10 of 10)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OVDD or 8.2kΩ for PCI to OVDD or equivalent.
3. Must pull down (recommended value is 1kΩ to GND)
4. If not used, must pull up (recommended value is 3kΩ for LVTTL or 8.2kΩ for PCI to OVDD or equivalent.
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to OVDD) or pull-down (recommended value is 1kΩ to
GND) required
Signal Name Description I/O Type Notes
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
74 AMCC Proprietary
Revision 1.19 – June 17, 2009
Device Charact eristics
Table 10. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic Symbol Value Unit Notes
Internal logic supply voltage VDD 0 to + 1 .6 V
I/O supply voltage OVDD 0 to + 3 .6 V
Ethernet I/O and USB supply voltage E1OVDD 0 to +2.7 V
Ethernet SGMII supply voltage E2OVDD 0 to +1.9 V
DDR2 (DDR1) SDRAM I/O supply voltage SOVDD 0 to + 1 .9 (+ 2 .7V) V
PCI-Express SerDes analog supply voltage AVDD 0 to + 1 .6 V 1
System PLL analog supply voltage SPAVDD 0 to +2 .7 V 1
Ethernet PLL analog supply voltage EAVDD 0 to +2.7 V 1
PCI-Express SerDes PLL analog supply voltage PAVDD 0 to +2 .7 V 1
Storage Temperature Range TSTG −55 to +150 °C
Case temperature under bias TC−40 to +120 °C2
Notes:
1. The analog voltages (AVDD, EAVDD, SPAVDD, and PAVDD) used for the on-chip functions can be derived from the logic voltages, but
must be filtered before entering the PPC460EX. A separate filter for each analog voltage, as shown below, is recommended:
2. This value is not a specification of the operational temperature range; it is a stress rating only.
VDD
C
AVDD
L
AVDD L – SMT ferrite bead chip, Murata BLM18AG121SN1 D
C – 0.1μF cerami c
EAVDD, SPAVDD, and PAVDD
L – SMT ferrite bead chip, Murata BLM15AG102SN1
C – 1μF ceramic
AGND
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 75
Prelim inary Data Sheet
Table 11. Recommended DC Operating Conditions (Part 1 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditi ons can affe ct dev ic e reli abi lit y.
Parameter Symbol Minimum Typical Maximum Unit Notes
Logic Supply Voltage VDD +1.2 +1.25 +1.3 V 4
I/O Supply Voltage OVDD +3.15 +3.3 +3.45 V 4
Ethernet 1 I/O Supply Voltage E1OVDD +2.4 +2.5 +2.6 V 4
Ethernet 2 I/O Supply Voltage (SGMII) E2OVDD +1.7 +1.8 +1.9 V 4
DDR2 (DDR1) SDRAM I/O Supply Voltage SOVDD +1.7 (+2.4) +1.8 (+2.5) +1.9 (+2.6) V 4
PCI-Express SerDes analog Supply Voltage AVDD +1.2 +1.25 +1.3 V 3
System PLL Analog Supply Voltage SPAVDD +2.4 +2.5 +2.6 V 3
Ethernet PLL analog supply voltage EAVDD +2.4 +2.5 +2.6 V 3
PCI-Express SerDes PLL analog supply voltage PAVDD +2.4 +2.5 +2.6 V 3
DDR2 (DDR1) SDRAM Reference Voltage SVREF 0.49SOVDD 0.50SOVDD 0.51SOVDD V3
Input Logic High 3.3V LVTTL and PCI
VIH
+2.0 +3.6 V 1
Input Logic High 2.5V CMOS, 3.3V tolerant +1.7 +3.6 V
Input Logic High 1.8V DDR2 (2.5V DDR1) SVREF + 0.125
(0.15) 2.2 (3.0) V 2
Input Logic High (1.8V SGMII) +1.1 +2.2 V
Input Logic Low 3.3V LVTTL and PCI
VIL
0+0.8 V 1
Input Logic Low 2.5V CMOS 0 +0.7 V
Input Logic Low 1.8V DDR2 (2.5V DDR1) −0.3 (−0.3) SVREF − 0.125
(0.18) V2
Input Logic Low (1.8V SGMII) +0.3 +0.8 V
Output Logic High 3.3V LVTTL and PCI
VOH
+2.4 +3.6 V 1
Output Logic High 2.5V CMOS +2.0 +2.7 V
Output Logic High 1.8V DDR2 (2.5V DDR1) SOVDD − 0.95
(+1.95) SOVDD V
Output Logic High (1.8V SGMII) +1.23 +1.385 +1.534 V
Output Logic Low 3.3V LVTTL and PCI
VOL
0+0.4 V 1
Output Logic Low 2.5V CMOS 0 +0.4 V
Output Logic Low 1.8V DDR2 (2.5V DDR1) 0 +0.45 V
Output Logic Low (1.8V SGMII) +0.841 +0.961 +1.081 V
Input Leakage Current (no pull-up or pull-down) IIL1 00
μA
Input Leakage Current for pull-down IIL2 0 (LPDL) 200 (MPUL) μA5
Input Leakage Current for pull-up IIL3 −150 (LPDL) 0 (MPUL) μA5
460EX – PPC460EX Embedded Processor Preliminary Data Sheet
76 AMCC Proprietary
Revision 1.19 – June 17, 2009
Power Supply Sequencing
All the PPC460EX I/O designs are power supply sequence independent. There is no requirement that the power
supplies power up in any particular order. The following items are power sequence considerations:
• Logic power (VDD) is applied before the I/O supply voltages: The I/Os include internal supply sequencing
circuitry which ensures the output of the receiver connected to internal chip logic is 0 until the I/O power is
applied. When the logic power is on and the I/O power supplies are off, the I/O logic connected to the
associated ball neither sinks or sources significant current unless influenced by an internal pull-up or pull-down
resistor. While the I/O supply is ramping, the state of the I/O ball is not predictable. This power sequence is not
destructive to the I/Os or internal logic and does not cause any functional problems.
• I/O power is applied before the logic power is applied: The output driver (connected the balls) comes up in an
unknown state (driving 1, driving 0, or tri-state) until the internal logic voltage is stable within normal operating
range. This power sequence is not destructive to the I/Os or internal logic and does not cause any functional
problems.
Input Max Allowable Overshoot 2.5V CMOS VIMAO25 +3.9 V
Input Max Allowable Overshoot 3.3V LVTTL VIMAO33 +3.9 V
Input Max Allowable Undershoot 2.5V CMOS VIMAU25 −0.6 V
Input Max Allowable Undershoot 3.3V LVTTL VIMAU33 −0.6 V
Output Max Allowable Overshoot 2.5V CMOS VOMAO25 +3.9 V
Output Max Allowable Overshoot 3.3V LVTTL VOMAO33 +3.9 V
Output Max Allowable Undershoot 2.5V CMOS VOMAU25 −0.6 V
Output Max Allowable Undershoot 3.3V LVTTL VOMAU33 −0.6 V
Case Temperature TC−40 +85 °C6
Notes:
1. PCI drivers meet PCI specifications.
2. SVREF = SOVDD/2 . SOVDD = +1.8V for DDR2 memory or +2.5V for DDR1 memory.
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltages, but must be filtered before entering the
PPC460EX. See “Absolute Maximum Ratings” on page 74.
4. LPDL is least positive down level; MPUL is most positive up level.
5. Case temperature, TC, is measured at top center of case surface with device soldered to a circuit board.
Table 12. 3.3V, 2.5V, and LVDS I/O Characteristics
Interfaces I/O Output Impedance
(Ω)Input Capacitance
(pF)
Ethernet (MII, RGMII), SysClk, SysE rr, GPI O00:21 3.3V tolerant 2.5V CMOS 50 5.7
Ethernet (SGMII) 1.8V LVDS - 5.0
DMA, NAND Flash External Peripheral, UART, USB, Interrupt,
JTAG, TmrClk, Halt , GPIO22:63, Trace 3.3V LVTTL 50 5. 2
IIC, SPI 3.3V LVTTL 35 5.2
PCI 3.3V - 5.7
Table 11. Recommended DC Operating Conditions (Part 2 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditi ons can affe ct dev ic e reli abi lit y.
Parameter Symbol Minimum Typical Maximum Unit Notes
460EX – PPC460EX Embedded Processor
Revision 1.19 – June 17, 2009
AMCC Proprietary 77
Prelim inary Data Sheet
• External voltage should not be applied to the chip I/O balls before the associated I/O power supply voltage is
applied to the chip.
• A chip power-down cycle must complete (all I/O supply voltages and VDD are below +0.4V) before a new
power-up cycle is started
• During a power-up cycle, SysReset and TRST inputs should be asserted low. SysReset and TRST should
remain asserted until SysClock is stable and at least 32 SysClock times after all power supplies are stable
within normal operating range. Failure to follow this reset sequence during the power-up cycle can result in
unpredictable operation of the chip.
Power Specifications
The following tables contain measured power numbers. The measurement conditions are listed as Notes below
each table.
Table 13. Typical DC Power Supply Requirements Using DDR2 Memory
Frequency ( MHz ) +1.25V Suppl y
(VDD+AVDD)+1.8V Sup pl y
(SOVDD+E2OVDD)
+2.5V Su pply
(E1OVDD+EAVDD+
SPAVDD+PAVDD)
+3.3V Suppl y
(OVDD)Total Unit Notes
600 2.90 0.33 0.31 0.37 3.91 W 1
800 3.06 0.34 0.31 0.37 4.08 W 1
1000 3.83 0.34 0.31 0.38 4.86 W 1
Notes:
1. Measured at TC = +85°C, using a typical process part for each speed grade, while running Linux and test applications that exercise
each function with representative traffic (RGMII Ethernet).
2. 600MHz, 800MHz, and 1000MHz parts use a nominal voltage of VDD = +1.25V, DDR2 running at 400MHz, and the PLB running at
200MHz.
Table 14. Typical DC Power Supply Requirements Using DDR1 Memory
Freque nc y (MHz) +1.25V Supply
(VDD+AVDD)+1.8V Suppl y
(E2OVDD)
+2.5V Supply
(E1OVDD+EAVDD+
SPAVDD+PAVDD
+SOVDD)
+3.3V Su pply
(OVDD)Total Unit Notes
600 2.90 0.01 1.18 0.37 4.46 W 1
800 3.06 0.01 1.18 0.37 4.63 W 1
1000 3.83 0.01 1.18 0.38 5.39 W 1
Notes:
1. Estimated and based on a nominal voltage of VDD = +1.25V, TC = 85°C, while running Linux and a test application t hat exercises each
function with representative traffic (RGMII Ethernet).
2. 600MHz, 800MHz, and 1000 MHz parts use a maximum voltage of VDD = +1.30V.
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Table 15. Maxiumum DC Power Supply Requirements Using DDR2 Memory
Frequency ( MHz ) +1.25V Suppl y
(VDD+AVDD)+1.8V Sup pl y
(SOVDD+E2OVDD)
+2.5V Su pply
(E1OVDD+EAVDD+
SPAVDD+PAVDD)
+3.3V Suppl y
(OVDD)Total Unit Notes
600 7.35 0.39 0.34 0.83 8.91 W 1, 2
800 7.66 0.39 0.34 0.83 9.22 W 1, 2
1000 7.87 0.39 0.34 0.85 9.45 W 1, 2
Notes:
1. Measured at TC = +85°C, using a a best-case process (worst case power) part, while running Linux and test applications that exercise
each function with representative traffic (RGMII Ethernet).
2. 600MHz, 800MHz, and 1000MHz parts use a nominal voltage of VDD = +1.30V, DDR2 running at 400MHz, and the PLB running at
200MHz.
Table 16. Maxiumum DC Power Supply Requirements Using DDR1 Memory
Frequency (MHz) +1.25V Supply
(VDD+AVDD)+1 .8V Suppl y
(E2OVDD)
+2.5V Supply
(E1OVDD+EAVDD+
SPAVDD+PAVDD+
SOVDD)
+3.3V Su pply
(OVDD)Total Unit Notes
600 7.35 0.01 1.22 0.83 9.41 W 1, 2
800 7.66 0.01 1.22 0.83 9.72 W 1, 2
1000 7.87 0.01 1.25 0.85 9.98 W 1, 2
Notes:
1. Measured at TC = +85°C, using a a best-case process (worst case power) part, while running Linux and test applications that exercise
each function with representative traffic (RGMII Ethernet).
2. 600MHz, 800MHz, and 1000MHz parts use a nominal voltage of VDD = +1.30V, DDR2 running at 400MHz, and the PLB running at
200MHz.
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Table 17. DC Power Supply Loads
Parameter Symbol Typical 4Maximum 3, 5Unit Notes
VDD (+1.25V) active operating current IDD 3065 6055 mA
OVDD (+3.3V) active operating current IODD 115 250 mA
E1OVDD (+2.5V) active operating current IE1ODD 124 132 mA
E2OVDD (+1.8V) active operating current IE2ODD 350mA
SOVDD (+1.8V) DDR2 active operating current 2ISODD2 210 300 mA
SOVDD (+2.5V) DDR1 active operating current 2ISODD1 376 450 mA
AVDD (+1.25V) input current 1IADD 45mA1
EAVDD (+2.5V) active operating current 1IEADD 12mA1
PAVDD (+2.5V) active operating current 1IUADD 12mA1
SPAVDD (+2.5V) active operating current 1IUADD 12mA1
Notes:
1. See “Absolute Maximum Ratings” on page 74 for filter recommendations.
2. SOVDD will be either +2.5V or +1.8V but not both.
3. The maximum current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many
factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case
temperature, and the power supply voltages. Your specific application can produce significantly different results. VDD (logic) current and
power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI, Ethernet, and so on).
OVDD (I/O) current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.
4. Typical current is estimated at 1.000GHz with VDD = +1.25V, OVDD = +3.3V, E1OVDD = +2.5V, SOVDD = +2.5V (DDR1) or +1.8V
(DDR2), and TC = +85°C with a typical process.
5. Maximum current is estimated at 1.000GHz with VDD = +1.3V, OVDD = +3.45V, E1OVDD = +2.6V, SOVDD = +2.6V (DDR1) or +1.9V
(DDR2), and TC = +85°C, and best-case process (which drives worst-case power).
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Package Thermal Specifications
Heat Sink
The following heat sink was used in the above thermal analysis:
35W x 35L x 15H (mm)
Base thickness = 1.5mm
Fin height = 13.5mm
Fin thickness = 1.0mm
Number of Fins: 11 aluminum
Tab le 18. Pac kage Thermal Spec i fic ations
Thermal resistance v alues for the TE-PBGA package in a convection environment ar e as follows:
Parameter Symbol
Airflow
ft/min
(m/sec) Unit Notes
0
(0) 100
(0.51) 200
(1.02) 300
(1.53 400
(2.04) 600
(2.55)
Junction-to-ambient thermal resistance
without heat sink θJA 13.1 11.7 10.9 10.5 10.3 10 3
Junction-to-ambient thermal resistance
with heat sink θJA 10.3 7.3 6.1 5.6 5.4 5.1 3, 6
Resistance Value
Junction-to-case thermal resistance θJC 3.5 °C/W 3
Junction-to-board thermal resistance θJB 7.3 °C/W 3
Notes:
1. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.
2. TA = TC − P×θCA, where TA is ambient temperature and P is power consumption.
3. TCMax = TJMax − P×θJC, where TJMax is maximum junction temperature (+ 125°C) and P is power consumption.
4. The preceding equations assume that the chip is mounted on a board with at least one signal and two power planes.
5. Values in the table were achieved using a JEDEC standard board with the following characteristics: 114.5mm x 101.6mm x 1.6mm, 4
layers. The board has 100 thermal vias (same as the number of thermal balls on the TE-PBGA package).
6. Values for an attached heat sink were achieved with a 35mm x 35mm x 15mm unit (see Thermal Management below), attached with a
0.1mm thickness of adhesive having a thermal conductivity of 1.3W/mK.
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Thermal Monitor
Thermal monitoring of the chip is accomplished using the PNP transistor (β ≈ 2) provided on the chip. The collector
of the transistor is connected to ground (GND). The emitter (TherMonA) and base (TherMonB) are connected to
chip pins. A voltage measurement (VBE1 and VBE2) across the TherMonA and TherMonB pins at the two current
valu es I1 and I2 prov id es the chip temp er atu re in °K according to the equation:
T = (q/nk)(VBE2−VBE1)/ln(I2/I1) °K where q = 1.602 176 53×10-19, n = 0.99 ± 0.05, and k = 1.380 6505×10-23.
Note: VBE2 and VBE1 should be specified in volts. I1 and I2 can be any units of measure provided they are the
same. The small values require precision measurement and current sources.
TherMonA
TherMonB
PPC460EX
I1, I2 (Max = 3 00μA)
E
BVBE1, VBE2
Note: The bias voltage VEB should be bet ween +0.5V and +0.7V.
C
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Clocking Specifications
Table 19. Clocking Specifications
Symbol Parameter Min Max Units Notes
SysClk Input
FCFrequency 66.66 100 MHz 1
TCPeriod 10 15 ns
TCS Edge stability (cycle-to-cycle jitter) – ±0.1 ns 2
TCH High time 40% of nominal period 60% of nominal period ns
TCL Low time 40% of nominal period 60% of nominal period ns
Note: Input rising and falling edge slew rate ≥ 1V/ns 3
PLL VCO
FCFrequency 600 2000 MHz
TCPeriod 0.50 1.66 ns
Processor (CPU) Clock
FCFrequency 400 1000 MHz 4
TCPeriod 1.00 2.5 ns
MemClkOut and PLB Cloc k
FCFrequency 133.33 200 MHz
TCPeriod 5 7.5 ns
TCH High time 45% of nominal period 55% of nominal period ns
OPB Clock
FCFrequency 66.66 100 MHz 5
TCPeriod 10 15 ns
AHB Clock
FCFrequency 66.66 200 MHz
TCPeriod 5 15 ns
Notes:
1. SysClk supports spread spectrum clocking with a -1% down-spread and a 40 kHz or less modulation frequency. For a 66.66 MHz
minimum SysClk, the modulation frequency range 66.00 MHz to 66.66 MHz is supported.
2. The modulation frequency of the input jitter should be lower than 100 kHz (to allow the PLL to track the jitter) or higher than 20 MHz (to
allow the PLL to filter the jitter). Within the frequency range 100 kHz to 20 MHz, the cycle to cycle jitter must be +/- 100 ps or less.
3. Slew rate is measured between 0.7V and 1.7V.
4. The max imum suppor ted proces sor clock frequency for any part is specified in the part number (see “Ordering and PVR Information”
on page 5).
5. In order to support a 1-Gbps Ethernet data rate, the minimum OPB clock frequency is 66.66 MHz. If the Ethernet application is limite d
to 100 Mbps, the minimum OPB clock frequency is 33.33 MHz.
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Figure 4. Timing Waveform
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC460EX. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracki ng sk ew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC460EX the following conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC460EX with one or more internal clocks at their maximum supported frequency, the SSCG can only lower
the frequency.
• The maximum frequency deviation of SysClk cannot exceed −1%, and the modulation frequency cannot
exceed 40kHz. In some cases, on-board PPC460EX peripherals impose more stringent requirements.
• For the PCI Express Reference Clock, the maximum spread spectrum is −0.5%, modulated between 30kHz
and 33kHz. The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million
(ppm) of each other at all times. This is specified to allow bit rate clock sources with a ± 300ppm tolerance.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that
the connected device is running at precise baud rates.
2. Ethernet operation is unaffected.
3. IIC operation is unaffected.
Important: It is up to the system designer to ensure that any SSCG used with the PPC460EX meets the above
requirements and does not adversely affect other aspects of the system.
TCL
TCH
TC
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Table 20. Peripheral Interface Clock Timings (Part 1 of 2)
Parameter Minimum Maximum Units Notes
PCI0Clk frequency – 66.66 MHz
PCI0Clk period 15 – ns
PCI0Clk high time 40% of nominal period 60% of nominal period ns
PCI0Clk low time 40% of nominal period 60% of nominal period ns
GMCMDClk frequency – 2.5 MHz
GMCMDClk period 400 – ns
GMCMDClk high time 160 – ns
GMCMDClk low time 160 – ns
GMCGTxClk frequency 2.5 125 MHz
GMCGTxClk period 8 400 ns
GMCnTxClk frequency 2.5 25 MHz
GMCnTxClk period 40 400 ns
GMCnTxClk high time 35% of nominal period – ns
GMCnTxClk low time 35% of nominal period – ns
GMCnRxClk frequency 2.5 25 MHz
GMCnRxClk period 40 400 ns
GMCnRxClk high time 35% of nominal period – ns
GMCnRxClk low time 35% of nominal period – ns
GMCRefClk frequency 125 125 MHz
GMCRefClk period 8 8 ns
GMCRefClk high time 40% of nominal period 60% of nominal period ns 2
GMCRefClk low time 40% of nominal period 60% of nominal period ns 2
GMCRefClk rise time – 1 ns 4
SGMIIRxClk frequency 625 625 M Hz
PerClk frequency 33 100 MHz
PerClk period 10 30 ns
PerClk high time 50% of nominal period 66% of nominal period ns
PerClk low time 33% of nominal period 50% of nominal period ns
SPIClkOut frequency (OPB Fc) / 1024 (OPB Fc) / 4 MHz
IICSClk frequency – 400 kHz
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TmrClk frequency – 100 MHz
TmrClk period 10 – ns
TmrClk high time 40% of nominal period 60% of nominal period ns
TmrClk low time 40% of nominal period 60% of nominal period ns
TrcClk frequency 100 300 MHz 3
UARTSerClk frequency – 1000/(2TOPB1 + 2ns) MHz 1
UARTSerClk period 2TOPB1 + 2 –ns1
UARTSerClk high time TOPB1 + 1–ns1
UARTSerClk low time TOPB1 + 1 –ns1
USB2DClk frequency 60 60 MHz
USB2DClk period 16.66 16.66 ns
USB2DClk high time 40% of nominal period 60% of nominal period ns
USB2DClk low time 40% of nominal period 60% of nominal period ns
USB2HClk frequency 60 60 MHz
USB2HClk period 16.66 16.66 ns
USB2HClk high time 40% of nominal period 60% of nominal period ns
USB2HClk low time 40% of nominal period 60% of nominal period ns
USB2HClk48 frequency 48 48 M Hz
USB2HClk48 period 20.8 20.8 ns
USB2HClk48 high time 40% of nominal period 60% of nominal period ns
USB2HClk48 low time 40% of nominal period 60% of nominal period ns
Notes:
1. TOPB is the period in ns of the OPB clock. The minimum OPB clock frequency is Ethernet application dependant (see Table 19 on
page 82). The maximum OPB clock frequency is 100 MHz.
2. An internal PLL improves this duty cycle to a worst case of 48% minimum, 52% maximum.
3. TrcClk is 1/4 CPU Clk. The maximum Trc Clk supported by most instruction trace probes is 200MHz.
4. The rise time for GMCRefClk is measured between 0.7V and 1.7V.
Table 20. Peripheral Interface Clock Timings (Part 2 of 2)
Parameter Minimum Maximum Units Notes
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I/O Specifications
Figure 5. Input Setup and Hold Waveform
Figure 6. Output Delay and Float Timing Waveform
Clock
TIS TIH
min min
Inputs
Valid
Valid
Clock
Outputs
Valid
TOH min
TOVmax
TOVmax
TOH min
TOVmax
TOHmin
Float (High- Z)
High (Drive)
Low (D r i ve)
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RGMII Timing
Figure 7. Setup and Hold Timing Waveforms for RGMII Signals
Test Conditions
AC specifications are characterized with VDD = +1.20V, OVDD = +3.15V,
E1OVDD = +2.4V, TC = +85°C and a 50pF test load as shown in the figure to the right.
Tab le 21. RGMII I/O Timing
Signal
Input (ns) Output (ns) Ou tp ut Current (mA)
Clock Notes
TskewR
(min) TskewR
(max) TskewT
(min) TskewT
(max) I/O H
(min) I/O L
(min)
GMCnRxClk ––––n/an/a –
GMCnRxD0:3 1.0 2.8 n/a n/a n/a n/a GMCnRxClk 1
GMCnRxCtl 1.0 2.8 n/a n/a n/a n/a GMCnRxClk 1
GMCnTxClk v – – – 5.51 7.23 –
GMCnTxD0:3 n/a n/a -0.5 0.5 5.51 7.23 GMCnTxClk
GMCnTxCtl n/a n/a -0.5 0.5 5.51 7.23 GMCnTxClk
Notes:
1. Assumes GMCnRxClk is delayed either on the board or by the PHY to ensure adequate timing margin.
GMCnTxClk
GMCnRxClk
GMCnTxD/Ctl Valid Valid
TskewT
GMCnRxD/Ctl Valid Valid
TskewR
Output
Pin
50pF
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Table 22. AC I/O Specifications (Part 1 of 3)
Notes:
1. SGMII PHY recovers the SGMII Tx clock from the SGMII TxD0:1.
2. TDO timing is referenced to the falling edge of TCK.
Signal Input (ns) Output (ns) Output Current (mA) Clock Notes
Setup Time
(TIS min) Hold Time
(TIH min) Valid Delay
(TOV max) Hold Time
(TOH min) I/O H
(minimum) I/O L
(minimum)
PCI Interfa c e
PCI0Reset na na na na 0.5 1.5 async
PCI0AD00:31 2.5 0 6 2 0.5 1.5 PCI0Clk
PCI0C0:3/BE0:3 2.4 0 6 2 0.5 1.5 PCI0Clk
PCI0Par 2.8 0 5.4 2 0.5 1.5 PCI0Clk
PCI0Frame 2.8 0 6 2 0.5 1.5 PCI0Clk
PCI0DevSel 2.1 0 6 2 0.5 1.5 PCI0Clk
PCI0IRDY 2.7 0 6 2 0.5 1.5 PCI0Clk
PCI0TRDY 2.5 0 6 2 0.5 1.5 PCI0Clk
PCI0Stop 2.5 0 6 2 0.5 1.5 PCI0Clk
PCI0PErr 2.4 0 6 2 0.5 1.5 PCI0Clk
PCI0SErr 2.1 0 6 2 0.5 1.5 PCI0Clk
PCI0IDSel 2.2 0 na na na na PCI0Clk
PCI0Req0:3 3 0 na na na na PCI0Clk
PCI0Gnt0:3 na na 6 2 0.5 1.5 PCI0Clk
PCI0INT na na 5.8 2 0.5 1.5 async
Ethernet MII Interface
GMCMDClk na na na na 5.51 7.23
GMCMDIO 10 0 30 10 5.51 7.23 GMCMDClk
GMC0TxClk na na na na 5.51 7.23
GMC0TxD3:0 na na 7 1 5.51 7.23 GMC0TxClk
GMC0TxEn na na 6 1 5.51 7.23 GMC0TxClk
GMC0TxEr na na 6 1 5.51 7.23 GMC0TxClk
GMC0CD 10 10 na na na na GMC0RxClk
GMC0CrS 10 10 na na na na GMC0RxClk
GMC0RxD3:0 6 10 na na na na GMC0RxClk
GMC0RxDV 5 10 na na na na GMC0RxClk
GMC0RxEr 6 10 na na na na GMC0RxClk
Ether n e t GMII In te r fa c e
GMCMDClk na na na na 5.51 7.23
GMCMDIO 10 0 30 10 5.51 7.23 GMCMDClk
GMC0GTxClk na na na na 5.51 7.23
GMC0TxD7:0 na na 2.3 2 5.51 7.23 GMC0GTxClk
GMC0TxEn na na 2.3 2 5.51 7.23 GMC0GTxClk
GMC0TxEr na na 2.2 2 5.51 7.23 GMC0GTxClk
GMC0CD 2 0 na na na na GMC0RxClk
GMC0CrS 2 0 na na na na GMC0RxClk
GMC0RxD7:0 2 0 na na na na GMC0RxClk
GMC0RxDV 1.9 0 na na na na GMC0RxClk
GMC0RxEr 1.9 0 na na na na GMC0RxClk
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Ethern et SG MI I In ter face
SGMII0:1RxD
SGMII0:1RxD 0.1 0.1 na na na na SGMII0RxClk
SGMII0:1TxD
SGMII0:1TxD na na na na 3.35 3.35 SGMII0TxClk 1
Internal Peripheral Interface
IIC0:1SClk na na na na 15.75 10.46
IIC0:1SData 5 1.5 5 0 15.75 10.46 IIC0:1SClk
SCPClkOut na na na na 15.75 10.46
SPIDI 5 1.5 na na na na SCPClkOut
SPIDO na na 7 0 15.75 10.46 SCPClkOut
UARTnDCD na na na na na na UARTSerClk
UARTnDSR na na na na na na UARTSerClk
UARTnCTS na na na na na na UARTSerClk
UARTnRTS na na na na 11.08 7.37 UARTSerClk
UARTnDTR na na na na 11.08 7.37 UARTSerClk
UARTnRI na na na na na na UARTSerClk
UARTnRx na na na na na na UARTSerClk
UARTnTx na na na na 11.08 7.37 UARTSerClk
USB2DD7:0 4.9 0 6 2 5.51 7.23 USB2HClk
USB2DDir 4.9 0 na na na na USB2HClk
USB2DNext 4.9 0 na na na na USB2HClk
USB2DStop na na 7 2 5.51 7.23 USB2HClk
USB2HD7:0 5 0 6 2 5.51 7.23 USB2HClk
USB2HDir 4.9 0 na na na na USB2HClk
USB2HNext 4.9 0 na na na na USB2HClk
USB2HStop na na 7 2 5.51 7.23 USB2HClk
Interrupts Interface
IRQ0:15 na na na na na na
JTAG Interface
TCK nananananana
TDI 2 5.5 na na na na TCK
TDO na na 9.5 1 11.08 7.37 TCK 2
TMS 25.5nanananaTCK
TRST na na na na na na async
System Interface
SysReset na na na na na na async
SysErr na na na na 11.08 7.37 async
Halt na na na na na na async
Trace Interface
TrcClk na na na na 11.08 7.37
TrcBS0:2 na na 1.5 1 11.08 7.37 TrcClk
TrcES0:4 na na 1.6 1 11.08 7.37 TrcClk
TrcTS0:6 na na 1.7 1 11.08 7.37 TrcClk
Table 22. AC I/O Specifications (Part 2 of 3)
Notes:
1. SGMII PHY recovers the SGMII Tx clock from the SGMII TxD0:1.
2. TDO timing is referenced to the falling edge of TCK.
Signal Input (ns) Output (ns) Output Current (mA) Clock Notes
Setup Time
(TIS min) Hold Time
(TIH min) Valid Delay
(TOV max) Hold Time
(TOH min) I/O H
(minimum) I/O L
(minimum)
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External Slave Peripheral Interface
DMAReq0:3 4 1 na na na na PerClk
DMAAck0:3 na na 5.3 1 11.08 7.37 PerClk
EOT0:3/TC0:3 4 1 5.3 1 11.08 7.37 PerClk
PerClk na na na na 11.08 7.37
PerAddr02:31 na na 4.5 1 11.08 7.37 PerClk
PerData00:31 2 1 4.9 1 11.08 7.37 PerClk
PerPar0:3 2 1 4.9 1 11.08 7.37 PerClk
PerWBE0:3 na na 4.8 1 11.08 7.37 PerClk
PerCS0:5 na na 5.3 1 11.08 7.37 PerClk
PerR/W na na 4.5 1 11.08 7.37 PerClk
PerOE na na 4.5 1 11.08 7.37 PerClk
PerReady 2 1 na na na na PerClk
PerBLast na na 4.5 1 11.08 7.37 PerClk
PerErr 2 1 na na na na PerClk
ExtReset na na na na 11.08 7.37 async
NAND Flash Interface
NFCE0:3 na na 4.7 1 11.08 7.37 PerClk
NFCLE na na 5.3 1 11.08 7.37 PerClk
NFALE na na 5.3 1 11.08 7.37 PerClk
NFREn na na 5.3 1 11.08 7.37 PerClk
NFWEn na na 5.3 1 11.08 7.37 PerClk
NFRdyBusy 2 1 na na na na PerClk
Table 22. AC I/O Specifications (Part 3 of 3)
Notes:
1. SGMII PHY recovers the SGMII Tx clock from the SGMII TxD0:1.
2. TDO timing is referenced to the falling edge of TCK.
Signal Input (ns) Output (ns) Output Current (mA) Clock Notes
Setup Time
(TIS min) Hold Time
(TIH min) Valid Delay
(TOV max) Hold Time
(TOH min) I/O H
(minimum) I/O L
(minimum)
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DDR2/1 SDRAM Interface Specifications
The DDR SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut from
the PLB clock. The PLB clock is an internal signal that cannot be directly observed.
Note: MemClkOut can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR
programming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific
application and requires a thorough understanding of the memory system in general (refer to the DDR
SDRAM Controller chapter in the Power PC 460E X /EX r/G T Em bedd ed Proc es so r Use r’s Manual ).
The signals are terminated as indicated in Figure 8 for the DDR timing data in the following sections.
Programmable Timing
When initializing the DDR controller at boot time, calibration of various programmable delays is required. The
following parameters ar e programmable:
• The internal delay of the DQS signals on a read is programmable. A single programmable delay globally
affects all of the DQS signals.
• The internal delay of the feedback signal on a read is programmable. The DDR controller drives and receives a
pulse at the beginning of each read burst. The feedback pulse is driven and received by MemDCFbdkD and
MemDCFbdkR. This pulse is used to adjust the sample cycle.
• The phase between the internal PLB clock and MemClkOut is programmable.
• The phase between the MemClkOut and the write DM, DQS, and data signals is programmable.
Board Layout Recommendations
The paths (traces) for the data and the associated data strobe signal should be routed with the same length
between PPC460EX and the SDRAM devices, allowing the rising and falling edges of the strobe to arrive at the
capture logic at the same time the data is in transition. Board designs must meet of the following criteria:
• Skew between the signals within any byte lane (8 DQ, 1 DQS, and 1 DM) should not exceed 50ps.
For example, traces that average 3.00in. and 167ps/in., and meet the maximum 50ps skew requirement, have a
maximum length difference of 0.3in. and are between 2.85in. and 3.15in.
Clocking
Clocking skew to all DRAMs must be minimized. The maximum recommended flight-time skew between clocks for
different memory chips is 10ps. Because of the stringent requirements on DDR device clock inputs, it is expected
that board designers use some type of external PLL suitable to redrive the clock to the DDR SDRAMs when more
than two memory clocks are needed.. In such a system, the PLL acts as a zero-delay insertion buffer.
The PPC460EX (PPC460GT) has two identical memory clocks, MemClkOut0:1, eliminating the need to redrive the
memory clock for some board designs. Designs using a single registered DIMM or a single rank of directly attached
32-bit memory (2 x16 memory chips) does not require redriven clocks.
Feedback Signal
There are two options for handling the trace between the feedback driver and receiver, MemDCFbdkD to
MemDCFbdkR.
1. The feedback trace can be length matched to the round-trip delay measured from the rising edge of
MemClkOut0:1 to the resulting input DQS on a read operation. Matching the feedback trace to the round-trip
delay, however, can negatively affect the sample cycle used by the DDR controller during reads. For this
reason, matching the trace length is not recommended for typical applications. Even when trace lengths are
matched to the round trip delay, software calibration of the feedback delay is still required.
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2. The feedback trace can be made as short as possible such that MemDCFbdkD to MemDCFbdkR are directly
connected to one another. When using a short trace, software must calibrate the feedback timing using
MCIF0_RFDC[RFFD] . This method works well as long as the round trip flight time is less than half of a
MemClkOut cycle.
DDR I/O Characteristics
The DDR I/O operate as either 2.5V (SSTL2_25) DDR1 or 1.8V (SSTL_18) DDR2 receiver/drivers. The following
table lists the ODT termination supported, output driver impedance and input receiver capacitance.
Tab le 23. DDR I/O Characteristics
Signals DDR2 ODT (Ω) Output Impedance (Ω) Input Capacitance (pF)
MemData00:63, ECC0:7, MemDCFdbkD, MemDCFdbkR,
MemAddr00:14, BA0:2, BankSel0:3, RAS, CAS, WE ,
ClkEn0:3, DM0:8, MemODT0:3 75 36 6.4
DQS0:8/ DQS0:8 75 18 or 36 6.4
MemClkOut0:1 / MemClkOut0:1 – 18 or 36 6.4
Notes:
1. The output impedance (drive strength) for DQS0:8/ DQS0:8 and MemClkOut0:1/MemClkOut0:1 is programmable.
2. The 75-ohm internal termination for MemData00:63, DQS0:8/DQS0:8, and DM0:8 can be statically or dynamically enabled.
3. The 75-ohm internal termination is statically enabled for MemDCFdbkD, MemDCF dbkR, MemA ddr00:14, BA0:2, B ankS el0:3, RAS,
CAS, WE, ClkEn0:3, and MemODT0:3.
Table 24. DDR SDRAM Output Driver Specifications
Signal Path Output Current (mA)
I/O H (maximum) I/O L (maximum)
MemData00:63 10 10
ECC0:7 10 10
DM0:8 10 10
MemClkOut 10 10
MemAddr00:14 10 10
BA0:2 10 10
RAS 10 10
CAS 10 10
WE 10 10
BankSel0:310 10
ClkEn0:3 10 10
DQS0:8/ DQS0:8 10 10
MemODT0:3 10 10
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DDR SDRAM Timing Conditions
The following timing values are generated by means of simulation and includes logic, driver, package RLC, and
lengths. Values are calculated over best case and worst case processes with speed, junction temperature, and
voltage as follows:
Figure 8. DDR SDRAM Simulation Signal Termination Model
DDR SDRAM Write Operation
The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes.
Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and
maximum values are measured under worst case conditions. The timing numbers in the following sections are
obtained using a simulation that assumes a model as shown in Figure 8.
Table 25. DDR SDRAM Operation Conditions
Case Process Speed Case Temperature (°C) SOVDD for DDR1 (V) SOVDD for DDR2 (V)
Best Fast −40 +2.4 +1.9
Worst Slow +85 +2.6 +1.7
10pF
10pF
MemClkOut
MemClkOut
120Ω
50
Ω
30pF
Addr/Ctrl/Data/DQS/DM (DDR1)
VTT = SOV DD/2
PPC460EX
Addr/Ctrl (DDR2)
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, in cl uding the type of mem or y used and the board layo ut .
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The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 9. DDR SDRAM Write Cycle Timing
Note: The timing data in the following tables is based on simulation runs using Einstimer.
Table 26. I/O Timing—DDR SDRAM TDS for 200 MHz
Notes:
1. All of the DQS signals are referenced to MemClkOut.
2. MemClkOut frequency is 200MHz.
Signal Name TDS (ns)
Minimum Maximum
DQS0:8/ DQS0:8 4.9 5.1
DQS
MemData
PLB Clk
MemClkOut
Addr/Cmd
TSA THA
TDS
TSD
THD
TSD
THD
TSA = Setup time for addr ess and command signal s t o M em C lkOut
THA = Hold time for a ddr ess and com m and signals from M em C lkO ut
TDS = Delay from rising/falling edge of clock to the rising/falling edge of DQS
TSD = Setup tim e fo r da ta signals (minim um time data is valid before rising/falling edge of DSQ)
THD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
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Table 27. I/O Timing—DDR SDRAM TSA, and THA
Notes:
1. The timing values in this table apply to MemClkOut frequency of 200MHz.
2. TSA and THA are referenced to MemClkOut rising edge.
3. DDR1 is supported up to 200MHz. (400Mbps data rate).
Signal Name TSA (ns) THA (ns)
Minimum Minimum
MemAddr00:14 1.08 1.18
BA0:2 1.17 1.19
BankSel0:3 1.12 1.15
ClkEn0:3 1.11 1.15
CAS 1.16 1.14
RAS 1.17 1.13
WE 1.17 1.17
Table 28. I/O Timing—DDR SDRAM Write Timing TSD and THD
Notes:
1. TSD and THD are measured under worst case conditio ns.
2. The timing values in this table apply to MemClkOut frequency of 200MHz.
3. The timing values in this table include 1/4 of a cycle at 200MHz.
4. To obtain adjusted TSD and THD values for clock frequencies less than 200MHz, subtract 1.5ns from the values in the table
and add 1/4 of the cycle time for the lower clock frequency (for example, TSD − 1.5 + 0.25TCYC).
5. DDR1 is supported up to 200MHz. (400Mbps data rate).
Signal Names Reference Signal TSD (ns) THD (ns)
MemData00:07, DM0 DQS0 0.96 0.995
MemData08:15, DM1 DQS1 0.97 0.990
MemData16:23, DM2 DQS2 0.98 0.980
MemData24:31, DM3 DQS3 0.98 0.980
MemData32:39, DM4 DQS4 0.98 0.980
MemData40:47, DM5 DQS5 0.97 0.983
MemData48:55, DM6 DQS6 0.96 0.982
MemData56:63, DM7 DQS7 0.96 0.985
ECC0:7, DM8 DQS8 0 .9 6 0.980
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DDR SDRAM Read Operation
The read of the incoming data from the SDRAM is done on the rising and falling edges of the differential DQS
signal. The data must be centered to these edges for correct operation.
DDR SDRAM Read Cycle Timing
The following diagram illustrates the relationship of the signals involved with a DDR read operation.
Figure 10. DDR SDRAM Memory Data and DQS
Table 29. I/O Timing—DDR SDRAM Read Timing TSD and THD for 200MHz
1. TSD and THD are measured under worst case conditio ns.
2. MemClkOut frequency is 200MHz.
3. The time values in this table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25ns).
4. To obtain adjusted TSD and THD values fo r lo w er clo ck f requ enc ie s, subtract 0.75ns from the v alu es i n t he table and add 1/4
of the cycle time for the lower clock frequency (e.g., TSD − 1.25 + 0.25TCYC).
5. DDR1 is supported up to 200MHz. (400Mbps data rate).
Signal Names Reference Signal Read Data vs DQS Set up
TSD (ns) Read Data vs DQS Hold
THD (ns)
MemData00:07 DQS0 0.393 0.311
MemData08:15 DQS1 0.388 0.314
MemData16:23 DQS2 0.397 0.307
MemData24:31 DQS3 0.396 0.309
MemData32:39 DQS4 0.394 0.291
MemData40:47 DQS5 0.395 0.291
MemData48:55 DQS6 0.393 0.295
MemData56:63 DQS7 0.394 0.308
ECC0:7 DQS8 0.389 0.306
DQS
MemData
TSD
THD
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PCI Express Interface Specification
The followi ng tables conta in the PCI Expr es s int erf ace spec if icati on .
Tab le 30. PCI Ex pr ess Tran sm itte r Spe cifi ca tion
Parameter Minimum Maximum Units Notes
Unit Interval (UI) 400 400 ps
Differential Tx peak-to-peak voltage swing 800 1200 m V ppd
Low power differential Tx peak-to-peak voltage swing 400 – mV ppd
Tx de-emphasis level ratio −3.0 −4.0 dB
Minimum Tx eye width 0.75 – UI
Maximum time between the jitter median and maximum
deviation from the median – 0.125 UI
Transmitter rise and fall time 0.125 – UI
Maximum Tx PLL bandwidth – 22 MHz
Minimum Tx PLL BW for 3dB peaking 1.5 – MHz
PCIEnTx/PC IEnTx Tx output rise/fall time 50 – ps
Tx AC common mode voltage – 20 mV
Absolute delta of DC common mode voltage during L0 and
Electrical Idle 0 100 mV
Absolute delta of DC common mode voltage between PCIEnTx
and PCIEnTx 025mV
Electrical Idle differential peak output voltage 0 20 mV
Amount of voltage change allowed during receiver detection - 600 mV
Tx DC common mode voltage 0 3600 mV
Tx short-circuit current limit – 90 mA
Minimum time spent in Electrical Idle 50 – UI
Maximum time to transition to a valid Electrical Idle after sending
an Electrical Idle Ordered-Set –20UI
Maximum transition time to valid differential signaling after
leaving Electrical Idle –20UI
Tx differential return loss −10 – dB
Tx common mode return loss −6–dB
Tx DC differential impedance 80 120 Ω
Lane-to-Lane output skew – 1300 ps
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Tab le 31. PCI Ex pres s Rec eiv er Spec i fic ation
Parameter Minimum Maximum Units Notes
Unit Interval (UI) 400 400 ps
Frequency offset between transmit and receive clocks −300 +300 ppm
Differential Rx peak-to-peak voltage 175 1200 mV
Rx AC common mode voltage – 150 m V
Receiver eye time opening 0.4 – UI
Maximum time delta between median and deviation from median – 0.3 UI
Total jitter tolerance 0.6 – UI
Rx differential return loss −10 – dB
Rx common mode return loss −6–dB
Rx DC differential impedance 80 120 Ω
Rx DC common mode impedance 40 60 Ω
Rx DC common mode impedance during reset or power down 200 – kΩ
Electrical Idle detect threshold 65 175 mV
Unexpected Electrical Idle enter detect threshold integration time – 10 ms
Lane-to-Lane output skew – 20 ns
Tab le 32. PCI Ex pres s Refer en ce Clock Spec ific ati on
Parameter Minimum Maximum Units Notes
Reference clock frequency 100 100 MHz 1
Accuracy −300 +300 ppm
Duty cycle 45 55 %
Peak-to-peak jitter for 1E-6 BER (1 x 10-6 bit error rate) –86ps3
Peak-to-peak jitter for 1E-6 BER (1 x 10-12 bit error rate) – 108 ps 3
Spread Spectrum Clock (S SC) frequency 30 33 kHz 2
Differential signal amplitude 200 1600 mV
Notes:
1. The reference clock frequency specification does not include ±300ppm frequency offset specification.
2. The data rate can be modulated from +0% to −0.5% of the nominal data rate frequency, at a modulation rate in the range not exceeding
30kHz–33kHz. The ±300ppm requirement remains which requires the two comm uncicating ports to be modulated so that they never
exceed a total of 600ppm difference. For most implementations, this requires that both ports have the same bit rate clock source when
the data is modulated with an SSC.
3. 1E-6 is the probability that the j itter is greater than 86ps peak-to-peak. 1E-12 is the probability that the jitt er is greater than 108ps peak-
to-peak.
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Serial ATA (SATA) Interface Specification
The following tables contain the SATA interface specification.
Tab le 33. SATA Transmitter Specifi c ati on
Parameter Minimum Maximum Units Notes
Unit Interval (UI) 333.3 6 66.6 ps
Differential Tx peak-to-peak voltage swing 400 1600 m V ppd
SATA0Tx/SATA0Tx Tx output rise/fall time 67 – ps
Tx short-circuit current limit – 90 mA
Tx differential return loss −10 – dB
Tx common mode return loss −6–dB
Tx DC differential impedance 85 115 Ω
Tx DC single-ended impedance 40 – Ω
Tx OOB transmission voltage – 200 mV ppd
Table 34. SATA Receiver Specification
Parameter Minimum Maximum Units Notes
Unit Interval (UI) 333.3 6 66.6 ps
Frequency offset between transmit and receive clocks −5350 +350 ppm
Differential Rx peak-to-peak voltage 240 – mV
Total jitter tolerance 0. 65 – UI
Rx differential return loss −10 – dB
Rx common mode return loss −6–dB
Rx DC differential impedance 85 115 Ω
Rx DC common mode impedance 40 – Ω
Rx OOB voltage detection threshold – 240 mV
Tab le 35. SATA Referenc e Clock Sp eci fi ca tio n
Parameter Minimum Maximum Units Notes
Reference clock frequency 100 120 MHz 1, 3
Accuracy −350 +350 ppm
Duty cycle 45 55 %
Cycle-to-cycle jitter – 150 ps p-p
Total jitter 1kHz–1MHz – 100 ps p-p
Total jitter 1MHz–20MHz – 40 ps p-p
Total jitter >20MHz – 100 ps p-p
Spread Spectrum Clock (S SC) frequency 30 33 kHz 2
Spread Spectrum Clock (S SC) variatio n 0 5000 ppm 2
Notes:
1. The reference clock frequency specification does not include 5700ppm frequency offset specification.
2. The data rate can be modulated from +0% to −0.5% of the nominal data rate frequency, at a modulation rate in the range not exceeding
30kHz–33kHz. The ±350ppm requirement remains which requires the two communcicating ports to be modulated so that they never
exceed a total of 700ppm difference. For most implementations, this requires that both ports have the same bit rate clock source when
the data is modulated with an SSC.
3. Only 100MHz or 120MHz is supported.
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PCI-E and SATA Reference Clock AC Coupling Recommendations
AC coupling is recommended for the PCIe and SATA reference clock. The following figures illustrate how to
implement AC coupling for the most common differential reference clocks.
Note: C1 and C2 may be any value from 0.01µF to 0.1µF as long as C1 equals C2. All components should be in a
0603 or smaller package and should be placed to minimize the stub length to the traces.
Figure 11. LVDS PCIe or SATA Reference Clock
Figure 12. LVPECL PCIe or SATA Reference Clock
C1
C2
LVDS PCIe or SATA RefClk receive
r
PCIEnRefClk/
PCIEnRefClk/
with internal biasingcloc k driver
R1=100Ω
C1= C2= 0.01µF to 0.1µF
SATA0RefClk
SATA0RefClk
C1
C2
LVPECL PCIe or SATA RefClk receive
r
with internal biasingcloc k driver
R2=82Ω
R1=130Ω
R3=130Ω
R4=82Ω
3.3V
3.3V
C1=C2=0.01µF to 0.1µF
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Figure 13. CML PCIe or SATA Reference Clock
Figure 14. HCSL PCIe or SATA Reference Clock
C1
C2
CML PCIe or SATA RefClk receive
r
with internal biasingcloc k driver
C1
C2
HCSL PCIe or SATA RefClk receive
r
with internal biasingcloc k driver
R2=50Ω
R1=33Ω
R3=33Ω
R4=50Ω
3.3V
3.3V
C1=C2=0.01µF to 0.1µF
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Boot Configuration
The PPC460EX supports several configurable boot parameters that must be initialized prior to booting. These
parameters are configured by one of several default boot options or programmed by data read from an IIC serial
EEPROM (see “Serial EEPROM” below). Strap signals sampled during reset select which method is used to
initialize the boot parameters (see “Strapping” below).
Strapping
The Bootstrap Controller selects the boot options based on the state of the strap signals during reset. The strap
signals are sampled on the rising edge of SysClk while SysReset is driven low. They must not change state until
after SysR es et is driven high in order to guarantee the correct boot option is selected.
These pins are used for strap functions only during reset. Following reset, they are used for normal functions. The
signal names assigned to the pins for normal operation are shown in parentheses following the pin number.
The following table lists the strapping pins along with their functions and boot strap options:
Serial EEPROM
Boot Options G and H enable the Bootstrap Controller to read 16 bytes of configuration data from a serial
EEPROM attached to the IIC0 bus after SysReset deasserts. The Bootstrap Controller stores the data in the
SDR0_SDSTP0:3 registers.
Note: The IIC serial EEPROM must have a one-byte base address. Multi-byte base addresses are not supported.
The initialization settings and their default values are covered in detail in the PowerPC 460EX/EXr/GT Embedded
Processor User’s Manual User’s Manual.
Table 36. Strapping Pin Assignments
Function Boot Option
Strapping Pins
E31
(UART0CTS)E34
(UART0DCD)E32
(UART0DSR)
Serial device is disabled. Each of the six options (A–
F) is a combination of boot source, boot-source
width, and clock frequency specifications. Refer to
the PPC460EX Embedded Processor User’s Manual
for details.
A000
B001
C010
D011
E100
F101
Serial device is enabled. Boot Option G and H
enable the Bootstrap Controller to program boot
parameters using data read from an IIC serial
EEPROM. Option G and H support different IIC
addresses.
G (0xA8) 1 1 0
H (0xA4) 1 1 1
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Revision Log
Date Version Contents of Modification
04/20/2007 1.00 Initial creation of document.
05/17/2007 1.00 Update to initial creation of document.
07/18/2007 1.01 Update to initial creation of document.
08/03/2007 1.02 Update to initial creation of document.
Eliminate SRIO, EMB, second RGM II, SMII, third and forth EMACs.
10/01/2007 1.03
Change GPIOs to alternate to default signals.
Add thermal monitor diagram.
Corrected signal-to-pin (ball) assignments for nine pins.
Misc. updates and corrections.
10/17/2007 1.04
Change all occurrences of PerDataPar to PerPar.
Swap signals assigned to balls A20 and E19.
Add updates from 460EX development which include changing the nine signal-to-pin changes
made for 1.03 back to their original state.
Restore TBI and RTBI to Features on first page.
Correct ActiveLow indication on some SATA and PCIE signals.
10/18/2007 1.05 Correct ActiveLow indication on some SATA and PCIE signals.
Remove all GMC1xxxx signals.
Remove all TBI and RTBI signals.
12/21/2007 1.06
Add missing GMC1RxCtl signal to pin AJ10.
Update I/O timing.
Change PCIE calibration resistor from 1k to 1.37k.
Add RMII signals.
01/14/2008 1.07 Misc. updates.
Change maximum case temperature from +105°C to +85°C.
02/11/2008 1.08 Correct typograhical errors.
Correct DDR SDRAM Read Data Path diagram.
Update PCIEnRefClk signal description.
04/14/2008 1.09
Add block diagram from R/C engineering specification.
Reference 802.3 Ethernet spec for GMCMDIO timing.
Add KASUMI support to security.
Change document status from Advanced to Preliminary and remove Confidential status.
Update block diagram.
Add power estimates.
Flag SGMIIRefClk signals as not to be used.
Update Contents to include L2 Cache/SRAM.
05/05/2008 1.10 Delete SAVDD voltage from analog voltage filter diagram (Doc Issue 503).
Change Thermal Monitor parameters (Doc Issue 504).
Misc. changes including Doc Issues 512, 524, and 526.
05/29/2008 1.11 Doc Issue 455. Add power sequence information.
07/17/2008 1.12 Doc Issues 530, 532, 536, 550. Update JTAG timing.
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09/26/2008 1.13
Doc Issue 572. Update SysReset signal functional description.
Security is no longer optional. Remove non-security part numbers.
Doc Issue 589. PCI-E and SATA I/O specifications. Timing, power, and other misc. updates.
New RGMII wave forms.
Update Security features list.
Doc Issue 595. Add pull-up and pull-down resistor values.
Additional processor speed of 1.066GHz.
New power values for 1.066GHz and lower speeds.
Change bootstrap description.
11/14/2008 1.14
Doc Issue 4816. Change SysReset I/O designation.
Doc Issue 4892. PCI clock required even when PCI is unused
Doc Issue 4933. Change SATARefClk frequency range.
Doc Issue 4960. Remove all references to SMII and RMII.
Doc Issue 5031. PCI signal termination recommendation.
Doc Issue 5032. Change PCI Express reference clock to 100MHz .
Doc Issue 5045. Remove length constraint from DDR layout recommendation .
Doc Issue 5205. Correct SysReset signal description.
12/18/2008 1.15 For Rev.A parts, removed 1066MHz CPU and 266MHz PLB/Memclk.
1/16/2009 1.16
Doc Issue 5220:
• In Table 9, updated description for SysReset; changed “32 cycles” to “32 SysClk cycles”.
Doc Issue 5440:
• In Table 19, updated OPB Clock minimum frequency and maximum period, and added note.
• In Table 20, updated SPIClkOut minimum and maximum frequency, and updated Note 1.
2/27/2009 1.17
Added Revision B, Rev.B PVR, and No Security part number.
Marked security as optional.
Clarified signal names in Table 24, Table 26, and Table 27.
Doc Issue 5857:
• In Table 19, added notes regarding SysClk jitter and slew rate.
Doc Issue 5885:
• In Table 23, corrected errors: All of the signals with the exception of the MemClkOut signals
have 75-ohm internal termination.
Doc Issue 5973:
• In Table 19, added note indicating the spread spectrum modulation range when SysClk is
66.66MHz.
4/30/09 1.18
Updated Table 17, DC Power Supply Loads.
Doc Issue 6180:
• Added requirement for AC coupling on PCIEnRefClk and SATA0RefClk in Table 9.
• Added section “PCI-E and SATA Reference Clock AC Coupling Recommendations” on
page 100.
Doc Issue 6361:
• Changed CGM to GCM under “Security Function (Optional)” on page 13.
6/17/09 1.19
Removed iSCSI CRC32 function from I2O/DMA.
Added FSOURCE0 to signal list. This signal should be tied to ground if the SDR0_ECID0:3
(electronic chip ID) registers need to be read.
Updated GMCMDIO TOV specification.
Date Version Contents of Modification
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Printed in the United States of America, June 17, 2009
The following are trademarks of AMCC Corporation in the United States, or other countries, or both:
AMCC
Other company, product, and service names may be trademarks or service marks of others.
Preliminary Edition (June 17, 2009)
This document contains information on a new product under development by AMCC.
AMCC reserves the right to change or discontinue this product without notice.
This document is a preliminary edition of the PowerPC 460EX data sheet. Make sure you are using the correct
edition for the level of the produ ct.
While the information contained herein is believed to be accurate, such information is preliminary, and should not
be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness
are made.
The information contained in this document is subject to change or withdrawal at any time without notice
and is being provided on an "AS IS" basis without warranty or indemnity of any kind, whether express or
implied, including without limitation, the implied warranties of non-infringement, merchantability, or
fitness for a p articular purpose. Any products, services, or programs discussed in this document are sold
or licensed under AMCC’s standard terms and conditions, copies of which may be obtained from your
local AMCC representative. Nothing in this document shall operate as an expressed or implied license or
indemnity under the intellectual property rights of AMCC or third parties.
Without limiting the generality of the foregoing, any performance data contained in this document was
determined in a specific or controlled environment and not submitted to any formal AMCC test. Therefore,
the results obtained in other operating environments may vary significantly. Under no circumstances will
AMCC be liable for any damages whatsoever arising out of or resulting from any use of the document or
the information contained herein.
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