July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Am29LV116D
Data Sheet
Publication Number 21359 Revision EAmendment +1 Issue Date November 7, 2000
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be rev is ed by subsequent ver si ons or modificat ions due to changes in technical specif ic ations. Publicati on# 21359 Rev: EAmendment/+1
Issue Date: November 7, 2 000
Am29LV116D
16 Megabit (2 M x 8-Bit)
CMOS 3.0 Volt-onl y Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
— 2.7 to 3.6 volt read and write operations for
battery-powered applications
■Manufactured on 0.23 µm process technology
— Compatible with and replaces Am29LV116B
device
■High performan c e
— Access times as fast as 70 ns
■Ultra low power consumption (typical values at
5MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 15 mA program/erase current
■Flexible sector arch itecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kby te, and
thir ty-one 64 Kbyte sectors
— Supports ful l chip erase
— Sector Protection features:
A hardware method of locking a sector to prev ent
any program or erase operations within that sector
Sectors can be locked in-system or vi a
programming equipment
Temporary Sector Unprotect f eature allo ws code
changes in prev iously locked sectors
■Unlock Bypass Pro gra m Co mmand
— Reduces ov erall prog ramming time when issuing
multiple program command sequences
■Top or bottom boot block configurations
available
■Embe dded Algorithms
— Embedded Erase algorithm automatically
preprogr ams and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specif ied addresses
■Minimum 1,000,000 wr ite cycle guarantee
per sector
■20-year data retention at 125°C
— Reliable operation for the life of the system
■Package option
— 40-pin TSOP
■CFI (Common Flash Interface) compliant
— Provides de vice-specific information to the
system, allow ing host software to easily
reconfigure for different Flash dev ices
■Compatibility with JEDEC standards
— Pinout and software compatible with single-
pow er supply Flash
— Superior inadvertent write protection
■Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
■Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■Erase Suspend/Erase Resume
— Suspends an er ase operation to read d ata from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■Hardware reset pin (RESET#)
— Hardware method to res et the device to reading
array data
2 Am29LV116D
GENERAL DESCRIPTION
The Am29LV116D is a 16 Mbit, 3.0 Volt-only Flash
memory organized as 2,097,152 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)
data appears on DQ7–DQ0. All read, program, and
erase operations are accomplished using only a single
power supply. The device can also be programmed in
standard EPROM programmers.
The standard de vice offers access times of 70, 90, and
120 ns, allowing high speed microprocessors to
operate wit hout wait st ates. To eliminate bus cont ention
the device has separate chip enable (CE#), write
enable ( WE#) and output enable (OE#) controls.
The de vice requires only a single 3. 0 v o lt po wer sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The de vice is entirely command set compatib le with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the er ase and programming circuitry. Write cycles
also internally latch addresses and data neede d f or the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms t he arra y (if it is not already progr ammed)
bef ore ex ecuting the e rase operation. During er ase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the de v ice is ready to read arr ay data
or accept another command.
The sector erase ar chitecture a llo ws memory se ctor s
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure . True bac kg round er ase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading arr a y data. The RESET# pin ma y be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The de vice off ers tw o power-sav ing features . When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also plac e the de v ice into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a se ct or simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron injec-
tion.
Am29LV116D 3
TABLE OF CONTENTS
Product Selecto r Guide . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .7
Standard Products ....................................................................7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .8
Table 1. Am29LV116D Device Bus Operations ................................8
Requirements for Reading Array Data ......... ............... .............8
Writing Commands/Command Sequence s ..... .. .. ...... ....... .. .. .. ..8
Program and Erase Operation Status ......................................9
Standby Mode ............................ .......................... ....................9
Automatic Sleep Mode .............. .......................... ...... .. .. ....... .. ..9
RESET#: Hardware Reset Pin .................................................9
Output Disable Mode ................................................................9
Table 2. Am29LV116D T Top Boo t Sector Address Table ..............10
Table 3. Am29LV116D B Bottom Boot Sector Address Table .........11
Autoselect Mode ............ ................... ......................................12
Table 4. Am29LV116D A utoselect Codes (High Voltage Method) ..12
Sector Protection/Unprotection ...............................................12
Temporary Sector Unprotect ..................................................12
Figure 1. In-System Sector Pro tect/Unprotect Algorithms.............. 13
Figure 2. Temporary Sector Unprotect Operation ........................... 14
Hardware Data Protection ......................................................14
Low V
CC
Write Inhibit ..............................................................14
Write Pulse “Glitch” Protection ...............................................14
Logical Inhibit ..........................................................................14
Power-Up Write Inhibit ............................................................14
Common Flash Memory Interface (CFI). . . . . . . 14
Table 5. CFI Query Identification String ..........................................15
Table 6. System Interface String .....................................................15
Table 7. Device Geometry Definition ..............................................16
Table 8. Primary Vendor-Specific Extended Query ........................16
Command Definitions . . . . . . . . . . . . . . . . . . . . . .17
Reading Array Data ................................................................17
Reset Command .......... ............... ............................... .............17
Autoselect Command Sequence ................ ............... .............17
Byte Program Command Sequence ...... ..... ............... .............17
Unlock Bypass Command Sequence ................................. ....18
Figure 3. Program Operation .......................................................... 18
Chip Erase Command Sequence ...........................................18
Sector Erase Command Sequence ........................................19
Erase Suspend/Erase Resume Commands ......... .. ....... ....... ..19
Figure 4. Erase Operation............................................................... 20
Command Definitions .............................................................21
Table 9. Am29LV116D Com man d Definitions ...............................2 1
Write Operation Status . . . . . . . . . . . . . . . . . . . . .22
DQ 7 : Da t a# P o ll i n g ... ....... .. ... ....... .. .. ........ .. ....... .. ... ....... .. ... .....22
Figure 5. Data# Polling Algorithm ................................................... 22
RY/BY#: Ready/Busy# ...........................................................23
DQ6: Toggle Bit I ....................................................................23
DQ2: Toggle Bit II ...................................................................23
Reading Toggle Bits DQ6/DQ2 ...............................................23
DQ5: Exceeded Timing Limits ................................................24
DQ3: Sector Erase Timer .......................................................24
Figure 6. Toggle Bit Algorithm........................................................ 24
Table 10 . Write Operation Status ................................................... 25
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 26
Figure 7. Maximum Negative Overshoot Waveform............ ....... .. . 26
Figure 8. Maximum Positive Overshoot Waveform........................ 26
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 26
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
CMOS C ompat ib l e .... ....... ... .. ....... .. ... ....... .. ....... ... .. ....... ... .. .....27
Zero Power Flash ...................................................................28
Figure 9. I
CC1
Current vs. Time (Showing Active and
Auto ma tic Sleep Currents)............................................................. 28
Figure 10. Typical I
CC1
vs. Frequency........................................... 28
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. Test Setup ..................................................................... 29
Table 11 . Test Specifications ......................................................... 29
Key to Switching Waveforms ..................................................29
Figure 12. Input Waveforms and Measurement Levels ................. 29
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30
Read Opera tions .................................... ............................... .30
Figure 13. Read Operations Tim ings ....... ....................... ............... 30
Hardware Reset (RESET#) ................... ........................ .........31
Figure 14. RESET# Timings .......................................................... 31
Erase/Program Operations .....................................................32
Figure 15. Program Operation Timings.......................................... 33
Figure 16. Chip/Sector Erase Operation Timings .......................... 33
Figure 17. Data# Polling Timings (Dur ing Embedded Algorithms). 34
Figure 18. Toggle Bit Timings (During Embedded Algorithms)...... 34
Figure 19. DQ2 vs. DQ6................................................................. 35
Temporary Sector Unprotect ..................................................35
Figure 20. Temporary Sector Unprotect Timing Diagram .............. 35
Figure 21. Sector Protect/Unprotect Timing Diagram.................... 36
Figure 22. Alternate CE# Controlled Write Operation Timings ...... 38
Erase and Programming Performance . . . . . . . 39
Latchup C haracteristics. . . . . . . . . . . . . . . . . . . . 39
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 39
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
TS 040—40-Pin Standard TSOP ............................................40
TSR040—40-Pin Reverse TSOP ...........................................41
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision A (October 1997) .....................................................42
Revision B (October 1997) .....................................................42
Revision C (December 1997) ................. ............................... .42
Revision C+1 (January 1998) ......... .......... .......... ....................42
Revision C+2 (March 1998) ............ .......................... ...... .. ......42
Revision C+3 (August 1998) ...................................................42
Revision D (January 1999) ....... .......................... ....................42
Revision E (February 2, 2000) ................................................42
Revision E+1 (November 7, 2000) .........................................42
4 Am29LV116D
PRODUCT SELECTOR GUIDE
Note: See “AC Ch aracte r ist ics ” for full specifications.
BLOCK DIAGRAM
Family Part Number Am29LV116D
Speed Options VCC = 2.7–3.6 V -70 -90 -120
Max access time, ns (tACC)7090120
Max CE# access time, ns (tCE)7090120
Max OE# access time, ns (tOE) 303550
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
CE#
OE#
STB
STB
DQ0
–
DQ7
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A20
Am29LV116D 5
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
17
18
19
20
9
10
11
12
13
14
15
40
25
39
38
37
36
35
34
33
32
31
30
29
28
27
26
24
23
22
21
A16
A5
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A4
A3
A2
A1
A17
DQ0
VSS
A20
A19
A10
DQ7
DQ6
DQ5
OE#
VSS
CE#
A0
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
1
16
2
3
4
5
6
7
8
17
18
19
20
9
10
11
12
13
14
15
40
25
39
38
37
36
35
34
33
32
31
30
29
28
27
26
24
23
22
21
A16
A5
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A4
A3
A2
A1
A17
DQ0
VSS
A20
A19
A10
DQ7
DQ6
DQ5
OE#
VSS
CE#
A0
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
40-Pin Reverse TSOP
40-Pin Standard TSOP
6 Am29LV116D
PIN CONFIGURATION
A0–A20 = 21 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy output
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and vo ltage s upply toler anc es)
VSS = De vice ground
NC = Pin not connected internally
LOGIC SYMBOL
21 8
DQ0–DQ7
A0–A20
CE#
OE#
WE#
RESET#
RY/BY#
Am29LV116D 7
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is form ed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this de vice. Consult the local AMD sales
office to confirm a vailability of specific v alid combinations and
to check on newly released combinations.
Am29LV116D T -70 E C
TEMPERATURE RANGE
C=Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
E = 40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)
F = 40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom S ector
DEVICE NUMBER/DESCRIPTION
Am29LV116D
16 Megabit (2 M x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program and Erase
Valid Combinations
Am29LV116DT-70,
Am29LV116DB-70
EC, EI, FC, FI
Am29LV116DT-90,
Am29LV116DB-90
Am29LV116DT-120,
Am29LV116DB-120
8 Am29LV116D
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The regi st er is composed of latches that stor e the
commands, along with the address and data infor ma-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV116D Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0
±
0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Note: The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates arra y data to the output pins. WE# should
remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the pow er transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produc e valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. ICC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V IL, and OE # to VIH.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase oper at ion can er ase one sect or, multiple s ec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies . A “sector ad-
dress” consists of t he ad dress b its requ ired to uni quely
select a sector. The “Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
Operation CE# OE# WE# RESET# Addresses DQ0–DQ7
Read L L H H AIN DOUT
Write L H L H AIN DIN
Standby VCC ±
0.3 V XX VCC ±
0.3 V X High-Z
Output Disable L H H H X High-Z
Reset X X X L X High-Z
Sector Protect (See Note) L H L VID Sector Addresses,
A6 = L, A1 = H, A0 = L DIN, DOUT
Sector Unprotect (See Note) L H L VID Sector Addresses
A6 = H, A1 = H, A0 = L DIN, DOUT
Temporary Sector Unprotect X X X VID AIN DIN
Am29LV116D 9
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections f or more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or prog ram oper ation, th e system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. St andard read cycle timings and I CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to t he device ,
it can place the device in the standby mode. In this
mode, current co nsumption is g reat ly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are he ld at VIH, b ut not within
VCC ± 0.3 V, the de vice will be in t he standby mode , b ut
the standby current will be greater . The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
The device also enters the standby mode when the RE-
SET# pin is dr iven low. Refer to the nex t section, “RE-
SET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energ y consumption. The dev ice automatic ally enables
this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# cont rol signals. Standard addres s
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC5 in the DC
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin p rovides a hard ware method of reset-
ting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the de vice is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
dra ws CMOS standby current (ICC4). If RESET# is held
at VIL b ut not within VSS±0.3 V, the standb y current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up f i rm-
ware from the Flash memory.
If RESET# is ass erted during a progr am or er ase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor R Y/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the de vice is
disabled. The output pins are plac ed in the h igh imped-
ance state.
10 Am29LV116D
Table 2. A m29LV 116DT Top Boot Sector Address Table
Sector A20 A19 A18 A17 A16 A15 A14 A13 Sector Size
(Kbytes) Address Range
(in hexadecima l)
SA000000XXX 64 000000–00FFFF
SA100001XXX 64 010000–01FFFF
SA200010XXX 64 020000–02FFFF
SA300011XXX 64 030000–03FFFF
SA400100XXX 64 040000–04FFFF
SA500101XXX 64 050000–05FFFF
SA600110XXX 64 060000–06FFFF
SA700111XXX 64 070000–07FFFF
SA801000XXX 64 080000–08FFFF
SA901001XXX 64 090000–09FFFF
SA1001010XXX 64 0A0000–0AFFFF
SA1101011XXX 64 0B0000–0BFFFF
SA1201100XXX 64 0C0000–0CFFFF
SA1301101XXX 64 0D0000–0DFFFF
SA1401110XXX 64 0E0000–0EFFFF
SA1501111XXX 64 0F0000–0FFFFF
SA1610000XXX 64 100000–10FFFF
SA1710001XXX 64 110000–11FFFF
SA1810010XXX 64 120000–12FFFF
SA1910011XXX 64 130000–13FFFF
SA2010100XXX 64 140000–14FFFF
SA2110101XXX 64 150000–15FFFF
SA2210110XXX 64 160000–16FFFF
SA2310111XXX 64 170000–17FFFF
SA2411000XXX 64 180000–18FFFF
SA2511001XXX 64 190000–19FFFF
SA2611010XXX 64 1A0000–1AFFFF
SA2711011XXX 64 1B0000–1BFFFF
SA2811100XXX 64 1C0000–1CFFFF
SA2911101XXX 64 1D0000–1DFFFF
SA3011110XXX 64 1E0000–1EFFFF
SA31111110XX 32 1F0000–1F7FFF
SA3211111100 8 1F8000–1F9FFF
SA3311111101 8 1FA000–1FBFFF
SA341111111X 16 1FC000–1FFFFF
Am29LV116D 11
Tab le 3. Am29LV116DB Bottom Boot Sector Address Table
Sector A20 A19 A18 A17 A16 A15 A14 A13 Sector Size
(Kbytes) Address Range
(in hexadecimal)
SA0 0000000X 16 000000–003FFF
SA1 00000010 8 004000–005FFF
SA2 00000011 8 006000–007FFF
SA3 0 0 0 0 0 1 X X 32 008000–00FFFF
SA4 0 0 0 0 1 X X X 64 010000–01FFFF
SA5 0 0 0 1 0 X X X 64 020000–02FFFF
SA6 0 0 0 1 1 X X X 64 030000–03FFFF
SA7 0 0 1 0 0 X X X 64 040000–04FFFF
SA8 0 0 1 0 1 X X X 64 050000–05FFFF
SA9 0 0 1 1 0 X X X 64 060000–06FFFF
SA10 0 0 1 1 1 X X X 64 070000–07FFFF
SA11 0 1 0 0 0 X X X 64 080000–08FFFF
SA12 0 1 0 0 1 X X X 64 090000–09FFFF
SA13 0 1 0 1 0 X X X 64 0A0000–0AFFFF
SA14 0 1 0 1 1 X X X 64 0B0000–0BFFFF
SA15 0 1 1 0 0 X X X 64 0C0000–0CFFFF
SA16 0 1 1 0 1 X X X 64 0D0000–0DFFFF
SA17 0 1 1 1 0 X X X 64 0E0000–0EFFFF
SA18 0 1 1 1 1 X X X 64 0F0000–0FFFFF
SA19 1 0 0 0 0 X X X 64 100000–10FFFF
SA20 1 0 0 0 1 X X X 64 110000–11FFFF
SA21 1 0 0 1 0 X X X 64 120000–12FFFF
SA22 1 0 0 1 1 X X X 64 130000–13FFFF
SA23 1 0 1 0 0 X X X 64 140000–14FFFF
SA24 1 0 1 0 1 X X X 64 150000–15FFFF
SA25 1 0 1 1 0 X X X 64 160000–16FFFF
SA26 1 0 1 1 1 X X X 64 170000–17FFFF
SA27 1 1 0 0 0 X X X 64 180000–18FFFF
SA28 1 1 0 0 1 X X X 64 190000–19FFFF
SA29 1 1 0 1 0 X X X 64 1A0000–1AFFFF
SA30 1 1 0 1 1 X X X 64 1B0000–1BFFFF
SA31 1 1 1 0 0 X X X 64 1C0000–1CFFFF
SA32 1 1 1 0 1 X X X 64 1D0000–1DFFFF
SA33 1 1 1 1 0 X X X 64 1E0000–1EFFFF
SA34 1 1 1 1 1 X X X 64 1F0000–1FFFFF
12 Am29LV116D
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended f or programming equipment
to automatically match a de vice to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as show n in
Table 4. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don’t ca re.
When all necessary bits ha ve been set as require d, the
programming equipment may then read the corre-
sponding identifier code on DQ7-DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 9. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
Tab le 4. Am29LV116D Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
progr am and er ase opera tions in an y sect or. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 1 shows the algo-
rithms and Figure 21 shows the timing diagram. This
method uses standard microprocessor bus cycle tim-
ing. For s ector unprotect, all unprotected sectors must
first be prote cted prior to the firs t sector unprotec t write
cycle.
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written f or earlier 3.0 v olt-only AMD flash de vi ces. Pub-
lication number 21586 contains further details; contact
an AMD representative to request a copy.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details .
It is possib le to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-s ystem. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, for merly protected
sectors can be prog r ammed or er ased b y selec ting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 20 shows the timing diagrams, for this feature.
Description CE# OE# WE#
A20
to
A13
A12
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID XLXLL 01h
Device ID: Am29LV116D
(Top Boot Block) LLHXXV
ID XLXLH C7h
Device ID: Am29LV116D
(Bottom Boot Block) LLHXXV
ID XLXLH 4Ch
Sector Protection Verification L L H SA X VID XLXHL
01h
(protected)
00h
(unprotected)
Am29LV116D 13
Figure 1. I n-Sys tem Sector Protect/Unprotect Algori thms
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Data = 00h?
Last sector
verified?
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
14 Am29LV116D
Figure 2. Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 9 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system lev el signals during VCC power-up and
power-down trans itions, or from system noise.
Low V CC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-do wn. The command register and
all internal program/er ase circuits are disabled, and the
dev ice resets . Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical In hibit
Write cycles are inhibited by holding an y one of OE# =
VIL, CE# = VIH or W E# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up , the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
dev ices. Soft ware support can t hen be devi ce-indepen-
dent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families.
Flash vendors can standardize their existing interf aces
for long-term compatibility.
This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h, an y time the device is ready to read ar ra y
data. The system can read CFI information at the
addresses given in Tables 5–8. To terminate reading
CFI data, the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The
system must write the reset command to return the
device to the autoselect mode.
For fur ther information, please refer to the CFI Specifi-
cation and CFI Pub licatio n 100, a vailable via the W orld
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD represen-
tative for copies of these documents.
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Am29LV116D 15
Table 5. CFI Query Identification String
Addresses Data Description
10h
11h
12h
51h
52h
59h Query Unique ASCII string “QRY”
13h
14h 02h
00h Primary OEM Command Set
15h
16h 40h
00h Address for Primary Extended Table
17h
18h 00h
00h Alternate OEM Command Set (00h = none exists)
19h
1Ah 00h
00h Address for Alternate OEM Extended Table (00h = none exists)
Table 6. System Interface String
Addresses Data Description
1Bh 27h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 36h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 00h VPP Min. voltage (00h = no VPP pin present)
1Eh 00h VPP Max. voltage (00h = no VPP pin present)
1Fh 04h Typical timeout per single byte/word write 2N µs
20h 00h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 0Ah Typical timeout per individual block erase 2N ms
22h 00h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 05h Max. timeout for byte/word write 2N times typical
24h 00h Max. timeout for buffer write 2N times typical
25h 04h Max. timeout per individual block erase 2N times typical
26h 00h Max. timeout for full chip erase 2N times typical (00h = not supported)
16 Am29LV116D
Table 7. Device Geometry Definition
Addresses Data Description
27h 15h Device Size = 2N byte
28h
29h 00h
00h Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh 00h
00h Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch 04h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
00h
00h
40h
00h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
01h
00h
20h
00h
Erase Block Region 2 Information
35h
36h
37h
38h
00h
00h
80h
00h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
1Eh
00h
00h
01h
Erase Block Region 4 Information
Table 8. Primary Vendor-Specific Extended Query
Addresses Data Description
40h
41h
42h
50h
52h
49h Query-unique ASCII string “PRI”
43h 31h Major version number, ASCII
44h 30h Minor version number, ASCII
45h 00h Address Sensitive Unlock
0 = Required, 1 = Not Required
46h 02h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 01h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 01h Sector Temporary Unprotect: 00 = Not Supported, 01 = Supported
49h 04h Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah 00h Simultaneous Operation: 00 = Not Supported, 01 = Supported
4Bh 00h Burst Mode Type: 00 = Not Supported, 01 = Supported
4Ch 00h Page Mode Type: 00 = Not Supported, 01 = 4 Word Page,
02 = 8 Word Page
Am29LV116D 17
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates de vice op-
erations. Table 9 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the i mproper sequence resets
the device to reading arr ay data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Charac teristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a progr amming operation in the Erase
Suspend mode, th e system ma y once again read array
data with the same exception. See “Erase Sus-
pend/Erase Resume Commands” for more information
on this mode.
The system
must
issue the reset command to re-en-
abl e the de vice f or reading arr ay data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” se ctio n , next.
See also “Requirements for Reading Arra y Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the aut oselect mode , the re set command
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command retur ns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the man uf acturer and devices codes ,
and determine whether or not a sector is protected.
Table 9 shows the address and data requirements. This
method is an alternativ e to that shown in Table 4, which
is intended for PROM programmers and requires VID
on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to Tables 2
and 3 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading arra y data.
Byte Program Command Sequence
The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write cy-
cles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
syst em is
not
required to p rovide further controls or tim-
ings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table
9 shows the address and data requirements for the
byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-
18 Am29LV116D
quence should be re initiated onc e the device has reset
to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. At tempting to do so ma y halt
the operation and set DQ5 to “1,” or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. Howe ver , a succeeding read will show that the
data is still “0”. Only erase operations can con vert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gr am byte s to the de vice f ast er than using the standard
program command sequenc e. The unlock b ypass com-
mand sequence is initiated by first writing two unlock
cycles. This is f ollo wed b y a third write cycle containing
the unloc k by pass command, 20h. The de vice then en-
ters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is required
to program in this mode. The first cycle in this se-
quence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time . Table 9 shows the r equirements f or the com-
mand sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t cares for both cycles. The device then returns to
reading array data.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams
Note: See Table 9 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six b us cycle ope ra tion. The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogr am prior to er ase. The Embedded Erase algo-
rithm automatically preprogr ams and verifies the entire
memor y for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 9 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Not e that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data int egrity.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Am29LV116D 19
The system can determine the status of the eras e op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 9 shows the address and data
requirements f or the sector eras e command sequence.
The device does
not
require the system to preprogram
the memory p rior to erase. The Embedded Eras e algo-
rithm automatically progr ams and verifies the sector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is writt en, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may b e written. Loading the sector erase buffer
ma y be done in any sequence , and the nu mber of sec-
tors ma y be from one sector to a ll sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is v alid. All oth er commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
dev ice returns to reading arr a y dat a and addr esses are
no longer latched. The system can determine the sta-
tus of the e rase operat ion b y using DQ7, DQ6, DQ2, or
R Y/BY#. ( Refer to “Write Ope ration St atus” f or inf orma-
tion on these status bits.)
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section f or par amet ers , and to
Figure 16 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend co mmand allo ws the s yste m to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the time-out period 50 µs
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspe nd command during the
Sector Erase time-out immediately terminates the
time-out period an d sus pends t he er ase oper at ion. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
When the Erase Suspend command is written during a
sector erase oper ation, the devi ce requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not select ed for er asure . (The devic e “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is com-
plete, the system c an once again r ead arra y d ata within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
20 Am29LV116D
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operat ion. See “Autoselect Command Sequence”
for more inf ormation.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase oper ation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Notes:
1. See Table 9 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Am29LV116D 21
Command Definitions
Table 9. Am29LV116D Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# or CE#
pulse.
PD = Data to be programmed at location PA. Data is latched
on the rising edge of WE# or CE# pulse.
SA = Address of the sector to be erased or verified. Address
bits A20–A13 uniquely select any sector.
Notes:
1. See Table 1 for descriptions of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus
cycles are write operations.
4. Address bits A20–A11 are don’t care for unlock and
command cycles, except when PA or SA is required.
5. No unlock or command cycles required when device is in
read mode.
6. The Reset command is required to return to the read
mode when the device is in the autoselect mode or if DQ5
goes high.
7. The fourth cycle of the autoselect command sequence is
a read cycle.
8. The data is 00h for an unprotected sector and 01h for a
protected sector.
9. Command is valid when device is ready to read array data
or when device is in autoselect mode.
10. The Unlock Bypass command is required prior to the
Unlock Bypass Program command.
11. The Unlock Bypass Reset command is required to return
to reading array data when the device is in the Unlock
Bypass mode.
12. The system may read and program functions in non-
erasing sectors, or enter the autoselect mode, when in the
Erase Suspend mode. The Erase Suspend command is
valid only during a sector erase operation.
13. The Erase Resume command is valid only during the
Erase Suspend mode.
Command Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–4)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Autoselect (Note 7)
Manufacturer ID 4 555 AA 2AA 55 555 90 X0 0 01
Device ID,
Top Boot Block 4 555 AA 2AA 55 555 90 X01 C7
Device ID,
Bottom Boot Block 4C
Sector Protect
Verify (Note 8) 4 555 AA 2AA 55 555 90 SA
X02 00
01
CFI Query (Note 9) 1 55 98
Byte Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program
(Note 10) 2 XXX A0 PA PD
Unlock Bypass Reset
(Note 11) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 5 55 AA 2AA 5 5 55 5 80 555 A A 2AA 55 SA 30
Erase Suspend (Note 12) 1 XXX B0
Erase Resume (Note 13) 1 XXX 30
22 Am29LV116D
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 10 and the following subsections
describe the funct ions of these bits . DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Algorithm is in progress or
completed, or whether t he device is in Erase Sus pend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se-
quence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the dev ice returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When t he Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous t o the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an er ase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro x imately 100 µs , the n the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid dat a at DQ7–
DQ0 on the
following
read cycles . This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted lo w. Figure 17, Data#
Polling Timings (Dur ing Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
Table 10 shows the outputs for Dat a# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
Am29LV116D 23
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC. (The R Y/BY# pin is not av ailable
on the 44-pin SO package.)
If the outpu t is low (Busy ), the de vice is activ ely er asing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the devic e is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Tab le 10 shows the output s f or RY/BY#. Figures 13, 15
and 16 shows RY/BY# for reset, program, and erase
operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Er ase algorithm is in prog ress or complete ,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle (The syst em may use eit her OE# or CE#
to control t he r ead cy cles). When the oper at ion is c om-
plete, DQ6 stops toggling.
After an er ase command sequence is written, if all sec-
tors selected f or er asing are protected , DQ6 toggles f or
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the de vice is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 10 shows the outputs f or Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm in flowchart form,
and the section “Reading Toggle Bits DQ6/DQ2” ex-
plains the algorithm. Figure 18 in the “AC C haracteris-
tics” section shows the toggle bit timing diagrams.
Figure 19 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a par ticular sector is actively erasing
(that is , the Embedded Er ase algo rithm is in progr ess),
or whether that sector is erase-suspended. Toggle Bit
II is valid afte r the rising edge of the final WE# pu lse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 10 to compare out-
puts for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 18 shows the toggle bit timing dia-
gram. Figure 19 shows the differences between DQ2
and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store th e v alue of the t oggle bit
after the first read. After the second read, the system
would compare the new v alue of the toggle bit with the
first. I f the toggle bit is no t toggling, the de vice has com-
pleted the prog ram or er ase operation. The system can
read array data on DQ7–DQ0 on the f ollo wing read cy-
cle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
24 Am29LV116D
must write the reset command to return to reading
array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is togglin g and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successiv e read cycles , de-
termining the stat us as described in the pre vious para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it re turns to determine
the status of the operation (top of Figure 6).
Table 10 shows the outputs f or Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm. Figure 18 in the
“AC Char acteristics” section sho ws the toggle bit timing
diagrams. Figure 19 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the prog ram or er ase cycle w as
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is pre viously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector er ase com-
mand. When the time-out is complete, DQ3 switches
from “0” to “1.” If the time between additional sector
erase commands from the system can be assumed to
be less than 50 µs, the system need not monitor DQ3.
See also the “S ector Er as e Command Sequence” sec-
tion.
After the sector erase command sequence is written,
the system should re ad the s tatus on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence , and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other th an Er ase Su spend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the s ystem softw are should chec k the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 10 sho ws the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 6. Toggle Bit Algorithm
(Note 1)
(Notes
1, 2)
Am29LV116D 25
Table 10. W rite Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status inf ormation. Ref er to the appropriate subsection for further details.
Operation DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) RY/BY#
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Erase
Suspend
Mode
Reading within Erase
Suspended Sector 1 No toggle 0 N/A Toggle 1
Reading within Non-Erase
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
26 Am29LV116D
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperat ure
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, and
RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may o vershoot VSS to
–2.0 V for periods of up to 20 ns. See Figure 7. Maximum
DC voltage on input or I/O pins is
V
CC +0.5 V. During
voltage transitions, input or I/O pins may overshoot to VCC
+2.0 V for periods up to 20 ns. See Figure 8.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may o vershoot VSS to –2.0 V for periods of up to
20 ns. See Figure 7. Maximum DC input voltage on pin A9
is +12.5 V which may overshoot to 14.0 V for periods up
to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperat ure (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperat ure (TA) . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . .+2.7 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figure 7. Maximum Negative
Overshoot Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 8. Maximum Positive
Overshoot Waveform
Am29LV116D 27
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC = 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(Notes 1, 2) CE# = VIL, OE# = VIH 5 MH z 9 16 mA
1 MHz 2 4
ICC2 VCC Active Write Current
(Notes 2, 3, 4) CE# = VIL, OE# = VIH 15 30 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC±0.3 V 0.2 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA
ICC5 Automatic Sleep Mode
(Notes 2, 5) VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V 0.2 5 µA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VID Voltage for Autoselect and
Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4
VLKO Low VCC Lock-Out Voltage
(Note 4) 2.3 2.5 V
28 Am29LV116D
DC CHARACTERISTICS (Continued)
Zero Power Flash
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
25
20
15
10
5
00 500 1000 1500 2000 2500 3000 3500 4000
Supply Current in mA
Time in ns
10
8
2
0
12345
Frequency in MHz
Supply Current in mA
Note: T = 25
°
C
Figure 10. Typical ICC1 vs. Frequency
2.7 V
3.6 V
4
6
Am29LV116D 29
TEST CONDITIONS
Table 11. Test Specifications
Key to Switching Waveforms
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Test
Figure 11. Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition -70 -90, -120 Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig cap aci tan ce) 30 100 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement
reference levels 1.5 V
Output timing measurement
reference levels 1.5 V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput
Figure 12. Input Waveforms and Measurement Levels
30 Am29LV116D
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 11 for test specifications.
Parameter
Description
Speed Option
JEDEC Std Test Setup - 7 0 -90 -12 0 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 70 90 120 ns
tAVQV tACC Address to Output Delay CE# = VIL
OE# = VIL Max 70 90 120 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 120 ns
tGLQV tOE Output Enable to Output Delay Max 30 35 50 ns
tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 25 30 30 ns
tGHQZ tDF Output Enable to Output High Z (Note 1) Max 25 30 30 ns
tOEH Output Enable
Hold Time (Note 1)
Read Min 0 ns
Toggle and
Data# Polling Min 10 ns
tAXQX tOH Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1) Min 0 ns
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
RY/BY#
RESET#
tDF
tOH
Figure 13. Read Operations Timings
Am29LV116D 31
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100 % test ed.
Parameter
Description All Speed OptionsJEDEC Std Test Setup Unit
tREADY RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note) Max 20 µs
tREADY RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH RESET# High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 14. RESET# Timings
32 Am29LV116D
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter Speed Options
JEDEC Std Description -70 -90 -120 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min 45 45 50 ns
tDVWH tDS Data Setup Time Min 35 45 50 ns
tWHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time (Note 1) Min 0 ns
tGHWL tGHWL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 35 50 ns
tWHWL tWPH Write Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Recovery Time from RY/BY# Min 0 ns
tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns
Am29LV116D 33
AC CHARACTERISTICS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 15. Program Operation Timings
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
Figure 16. Chip/Sector Erase Operation Timings
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h PA PA
Read Status Data (last two cycles)
A0h
t
CS
Status D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
t
BUSY
t
CH
PA
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh SA
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
t
RB
t
BUSY
34 Am29LV116D
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
RY/BY#
tBUSY
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 17. Data# P olling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
t
OE
DQ6/DQ2
RY/BY#
t
BUSY
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
t
ACC
t
RC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 18. Toggle Bit Timings (During Embedded Algorithms)
Am29LV116D 35
AC CHARACTERISTICS
Temporary Sector Unprotect
Note: Not 100 % test ed.
Parameter
All Speed OptionsJEDEC Std Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET# Setup Time for Temporary Sector
Unprotect Min 4 µs
Note: The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 19. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
RESET#
tVIDR
12 V
0 or 3 V
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
Figure 20. Temporary Sector Unprotect Timing Diagram
36 Am29LV116D
AC CHARACTERISTICS
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
RESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector Protect/Unprotect Verify
V
ID
V
IH
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 21. Sector Protect/Unprotect Timing Diagram
Am29LV116D 37
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter Spe ed Opt ion s
JEDEC Std Description -70 -90 -120 Unit
tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 45 50 ns
tDVEH tDS Data Setup Time Min 35 45 50 ns
tEHDX tDH Data Hold Time Min 0 ns
tOES Output Enable Setup Time Min 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Setup Time Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# Pulse Width Min 35 35 50 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec
38 Am29LV116D
AC CHARACTERISTICS
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase PA for program
SA for sector erase
555 for chip erase
tBUSY
Note: PA = program address , PD = program data, DQ7# = complement of the data written to the de vice, DOUT = data written to
the device. Figure indicates the last two bus cycles of the command sequence.
Figure 22. Alternate CE# Controlled Write Operation Timings
Am29LV116D 39
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four- or two-bus-cycle sequence for the program command. See
Table 9 for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles per sector.
LATCHUP CHARACTERISTICS
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.7 15 s Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time 25 s
Byte Programming Time 9 300 µs Excludes system level
overhead (Note 5)
Chip Programming Time (Note 3) 18 54 s
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE #, and RESE T#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1. 0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C 10 Years
125°C 20 Years
40 Am29LV116D
PH YS ICAL DIMENSIONS *
TS 040—40-Pin Standard TSOP
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
Am29LV116D 41
PH YS ICAL DIMENSIONS
TSR040—40-Pin Reverse TSOP
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Dwg rev AA; 10/99
42 Am29LV116D
REVISION SUMMARY
Revision A (October 1997)
First release.
Revision B (October 1997)
Global
Deleted SO package from data sheet.
Revision C (December 1997)
Alternate CE# Controlled Erase/Program
Operations
Changed tCP from 45 to 35 ns on 80R and 90 speed
options.
Revision C+1 (January 1998)
Global
Changed data sheet status to Preliminary.
Reset Command
Deleted the last paragraph in this section.
Revision C+2 (March 1998)
Figure 2, In-System Sector Protect/U nprotect
Algorithms (0.35 µm devices)
In the sector protect algorithm, added a “Reset
PLSCNT=1” box in the pa th from “Pr otect ano ther sec-
tor?” back to setting up the next sector address.
AC Characteristics
Erase/Program Operations; Alternate CE# Controlled
Erase/Program Operations:
Corrected the notes refer-
ence for tWHWH1 and tWHWH2. These parameters are
100% tested. Corrected the note reference for tVCS.
This parameter is not 100% tested.
Temporary Sector Unprotect Table
Added note reference for tVIDR. This parameter is not
100% tested.
Figure 21, Sector Protect/Unprotect Timing
Diagram
A valid address is not required for the first write cycle;
only the data 60h.
Erase and Programming Performance
In Note 2, the worst case endurance is now 1 million
cycles.
Revision C+3 (August 1998)
Global
Added 70R speed option, changed 80R speed option
to 80.
Distinctive Characteri stics
Changed process technology to 0.32 µm.
Table 9, Command Definitions
The CFI Query command is now included in the table.
DC Chara cterist ics
Moved VCCmax test c ondition for ICC specifications to
notes.
Figure 21, Sector Protect/Unprotect Timing
Diagram
Changed timing specifications in diagram to match
those in the figure of In-System Sector Protect/Unpro-
tect Algorithms.
Revision D (January 1999)
Distinctive Characteri stics
Added “20-year dat a retention at 125°C” bullet.
Revision E (February 2, 2000)
Global
The process technology has changed to 0.23 µm, and
is indicated in the part number by t he “D” suffix. The 70
ns speed option is now offered in the full voltage range
instead of the regulated voltage range. The 70 ns
dev ices are also now av ailab le in the industrial temper-
ature range. The extended temperature range is no
longer available. The 80 ns speed option has been
deleted. All other parameters and functions remain
unchanged.
AC Characteristics—Figure 15. Program
Operations Timing and Figure 16. Chip/Sector
Erase Operations
Deleted tGHWL and changed OE# waveform to star t at
high.
Physi cal Dimensions
Replaced figures with more detailed illustrations.
Revision E+1 (November 7, 2000)
Global
Added table of contents. Deleted burn-in option in
ordering information section.
Am29LV116D 43
Trademarks
Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
