PIC16F630T-C/SL - Microchip Technology

PIC16F630/676

Data Sheet

14-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

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PIC16F630/676

High Performance RISC CPU:

• Only 35 instructions to learn

- All single-cycle instructions except branches

• Operati ng spe ed:

- DC - 20 MHz oscillator/clock input

- DC - 200 ns instruction cycle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect, and Relative Addressing modes

Special Microcontroller Features:

• Internal and external oscil la tor opti ons

- Precision Internal 4 MHz oscillator factory

calibrated to ±1%

- External Oscillator support for crystals and

resonators

-5μs wake-up from SLEEP, 3.0V, typical

• Power saving SLEEP mode

• Wide operating voltage range - 2.0V to 5.5V

• Industri al and Extend ed tem pera t ure range

• Low power Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Brown-out Detect (BOD)

• Watchdog Timer (WDT) with independent

oscilla tor for reliable operation

• Multiplexed MCLR/Input-pin

• Interrupt-on-pin change

• Individual programmable weak pull-ups

• Programmable code protection

• High Endurance FLASH/EEPROM Cell

- 100,000 write FLASH endurance

- 1,000,000 write EEPROM endurance

- FLASH/Data EEPROM Retention: > 40 years

Low Power Features:

• Standby Current:

- 1 nA @ 2.0V, typical

• Operating Current:

-8.5μA @ 32 kHz, 2.0V, typical

-100μA @ 1 MHz, 2.0V, typic al

• Watchdog Timer Current

- 300 nA @ 2.0V, typical

• Timer1 oscillator current:

-4μA @ 32 kHz, 2.0V, typical

Peripheral Feat ures:

• 12 I/O pins with individual direction contr ol

• High current sink/source for direct LED drive

• Analog comparator module with:

- One analog comparator

- Programmable on-chip comparator voltage

reference (CVREF) module

- Programmable input multiplexing from device

inputs

- Comparator output is externally accessible

• Analog-to-Digital Converter module (PIC16F676):

- 10-bit resolution

- Programmable 8-channel input

- Voltage reference input

• Timer0: 8-bit timer/counter with 8-bit

progra mmab le pres caler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator, if INTOSC mode

selected

• In-Circuit Serial ProgrammingTM (ICSPTM) via

two pins

Device

Program

Memory Dat a Memory I/O 10-bit A/D

(ch) Comparators Timers

8/16-bit

FLASH

(words) SRAM

(bytes) EEPROM

(bytes)

PIC16F630 1024 64 128 12 – 1 1/1

PIC16F676 1024 64 128 12 8 1 1/1

14-Pin, Flash-Based 8-Bit CMOS Microcontroller

PIC16F630/676

Pin Diagrams

14-pin PDIP, SOIC, TSSOP

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/T1G/OSC2/AN3/CLKOUT

RA3/MCLR/VPP

RC5

RC4

RC3/AN7

VSS

RA0/AN0/CIN+/ICSPDAT

RA1/AN1/CIN-/VREF/ICSPCLK

RA2/AN2/COUT/T0CKI/INT

RC0/AN4

RC1/AN5

RC2/AN6

PIC16F676

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RC5

RC4

RC3

VSS

RA0/CIN+/ICSPDAT

RA1/CIN-/ICSPCLK

RA2/COUT/T0CKI/INT

RC0

RC1

RC2

PIC16F630

PIC16F630/676

Table of Contents

1.0 Device Overview ......................... ........................... ..................... ........................... ..................................................................... 5

2.0 Memory Org anization .................. ........................... ........................... ............................ .............................................................. 7

3.0 Ports A and C ................................ .. .... .. .. ....... .. .... .. .. .... .. ....... .. .. .... .. .. ....... .. .... .. .. .... .. ................................................................. 19

4.0 Timer0 Module .............................. .. .. .... .. .. ....... .. .. .... .. .. .. ....... .. .... .. .. .. ....... .. .. .... .. .. .. ....... ............................................................ 29

5.0 Timer1 Module with Gate Control................... .... .. .. .. .... .. ..... .... .. .. .... .. .. ....... .. .. .. .... .. .. ....... .. .. .... ................................................. 32

6.0 Comparat or Module .................................................................................................................................................................. 37

7.0 Analog-to-Digital Converter (A/D) Module (PIC16F676 only) .................... .... .... .. .... ......... .. .... .. .... ......... ................................... 43

8.0 Data EEPROM Memory............................................................................................................................................................ 49

9.0 Special Features of the CPU .................................................................................................................................................... 53

10.0 Instruction Set Summary ........................................................................................................................................................... 71

11.0 Development Support ....................... .. .. .... ....... .. .. .... .. .... ....... .. .. .... .. .... ..... .... .. .... .. .. ....... .... ........................................................ 79

12.0 Electrical Spec ifications .......... ..................... .............. ..................... ............... ........................................................................... 83

13.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 105

14.0 Packaging Information ............................................................................................................................................................ 115

Appendix A: Data Sheet Revision History ........................ .... .... ......... .... .. .... ......... .... .... .... ......... .... .................................................... 119

Appendix B: Device Differences ....................................................................................................................................................... 119

Appendix C: Device Migrations ............... .. .. .... .. ......... .. .. .... .. .... ....... .. .... .. .... .. ....... .... .. .... .. ....... .. ........................................................ 120

Appendix D: Migrating from other PIC® Devices .............................................................................................................................. 120

Index ................................................................................................................................................................................................. 121

On-Line Support ......................... .... ......... .. .... .... .. ......... .. .... .... .. ......... .... .. .... ....... .... .... .. .... ................................................................. 125

Systems Information and Upgrade Hot Line ..................................................................................................................................... 125

Reader Response ............................................................................................................................................................................. 126

Product Identification System ........................................................................................................................................................... 127

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Customer Noti fic atio n Syst em

PIC16F630/676

NOTES:

PIC16F630/676

1.0 DEVICE OVERVIEW

This do cu me n t conta i ns dev ic e spec if i c in f orm at i on fo r

the PIC16F630/676. Additional information may be

found in the PIC® Mid-Range Reference Manual

(DS33023), which may be obtained from your local

Microchip Sales Representative or downloaded from

the Microchip web site. The Reference Manual should

be conside red a com pleme nta ry do cume nt to thi s Da ta

Sheet and is highly recommended reading for a better

understanding o f the dev ic e arc hi tec ture a nd o pera t io n

of the peripheral modules.

The PIC16F630 and PIC16F676 devices are covered

by this Data Sheet. They are identical, except the

PIC16F676 has a 10-bit A/D converter. They come in

14-pin PDIP, SOIC and TSSOP packages. Figure 1-1

shows a blo ck dia gram of th e PIC16F630 /676 de vices .

Table 1-1 shows the pinout description.

FIGURE 1-1: PIC16F63 0/676 BLOCK DIAGRAM

FLASH

Program

Memory

13 Data Bus 8

Program

Bus

Instruction reg

Progra m Counter

RAM

File

Registers

Direct Addr 7

RAM Addr 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

PORTA

8-Level Stack 64

1K x 14

bytes

(13-bit)

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR VSS

Brown-out

Detect

Analog

Timer0 Timer1

DATA

EEPROM

128 bytes

EEDATA

EEADDR

RA0

RA1

RA2

RA3

RA4

RA5

Comparator

Analog to Digital Converter

(PIC16F676 only)

AN0 AN1AN2 AN3 CIN- CIN+ COUT

T0CKI

INT

T1CKI

Configuration

Internal

Oscillator

VREF

and reference

T1G

PORTC RC0

RC1

RC2

RC3

RC4

RC5

AN4 AN5 AN6AN7

VDD

PIC16F630/676

TABLE 1-1: PIC16F630/676 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/AN0/CIN+/ICSPDAT RA0 TTL CMOS Bi-directional I/O w/ programmable pull-up and

Interrupt-on-change

AN0 AN —A/D Channel 0 input

CIN+ AN Comparator input

ICSPDAT TTL CMOS Serial Programming Data I/O

RA1/AN1/CIN-/VREF/

ICSPCLK RA1 TTL CMOS Bi-directional I/O w/ programmable pull-up and

Interrupt-on-change

AN1 AN —A/D Channel 1 input

CIN- AN — Comparator input

VREF AN —External Voltage reference

ICSPCLK ST — Serial Programming Clock

RA2/AN2/COUT/T0CKI/INT RA2 ST CMOS Bi-directional I/O w/ programmable pull-up and

Interrupt-on-change

AN2 AN —A/D Channel 2 input

COUT — CMOS Compara tor outp ut

T0CKI ST — Timer0 clock input

INT ST — External Interrupt

RA3/MCLR/VPP RA3 TTL — Input port with Interrupt-on-change

MCLR ST — Master Clear

VPP HV — Programming voltage

RA4/T1G/AN3/OSC2/

CLKOUT RA4 TTL CMOS Bi-directional I/O w/ programmable pull-up and

Interrupt-on-change

T1G ST — Timer1 gate

AN3 AN3 —A/D Channel 3 input

OSC2 — XTAL Crystal/Resonator

CLKOUT — CMOS FOSC/4 output

RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS Bi-directional I/O w/ programmable pull-up and

Interrupt-on-change

T1CK I ST — Timer1 clock

OSC1 XTAL — Crystal/Resonator

CLKIN ST — External clock input/RC oscillator co nnection

RC0/AN4 RC0 TTL CMOS Bi-directional I/O

AN4 AN4 —A/D Channel 4 input

RC1/AN5 RC1 TTL CMOS Bi-directional I/O

AN5 AN5 —A/D Channel 5 input

RC2/AN6 RC2 TTL CMOS Bi-directional I/O

AN6 AN6 —A/D Channel 6 input

RC3/AN7 RC3 TTL CMOS Bi-directional I/O

AN7 AN7 —A/D Channel 7 input

RC4 RC4 TTL CMOS Bi-directional I/O

RC5 RC5 TTL CMOS Bi-directional I/O

VSS VSS Power — Ground reference

VDD VDD Power — Positive supply

Legend: Shade = PIC16F676 only

TTL = TTL input buffer

ST = Schmitt Trigger input buffer

PIC16F630/676

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16F630/676 devices have a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. Only the first 1K x 14 (0000h - 03FFh)

for the PIC16F630/676 devices is physically imple-

mented. Accessing a location above these boundaries

will c ause a wra p around withi n the firs t 1K x 14 sp ac e.

The RESET vector is at 0000h and the interrupt vector

is at 0004h (see Figure 2-1).

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F630/676

2.2 Data Memory Organization

The data memory (see Figure 2-2) is partitioned into

two banks, which contain the General Purpose regis-

ters and the Special Function registers. The Special

Functio n registers are located in the first 32 lo cations of

each bank. Register locations 20h-5Fh are General

Purpose re giste rs, imp leme nted as st atic RAM and a re

mapped across both banks. All other RAM is

unimplemented and returns ‘0’ when read. RP0

(STATUS<5>) is the bank select bit.

• RP0 = 0 Bank 0 is selected

• RP0 = 1 Bank 1 is selected

2.2. 1 GENERAL PURPOSE REGISTER

FILE

The register file is organized as 64 x 8 in the

PIC16F630/676 devices. Each register is accessed,

either directly or indirectly, through the File Select

PC<12:0>

000h

0004

0005

03FFh

0400h

1FFFh

Stack Level 1

Stack Level 8

RESET Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Note: The IRP and RP1 bits STATUS<7:6> are

reser ved and shoul d always be mai ntained

as ‘0’s.

PIC16F630/676

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 2-1). These

registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function registers

assoc iated with th e “core” are described in this sec tion.

Those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

FIGURE 2-2: DATA MEMORY MAP OF

THE PIC16F 63 0/67 6

Indirect addr. (1)

TMR0

PCL

STATUS

FSR

PORTA

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

7Fh

Bank 0

Unimplemented data memory locations, read as '0'.

1: Not a physical register.

2: PIC16F676 only.

CMCON VRCON

General

Purpose

Registers accesses

20h-5Fh

64 Bytes

EEDAT

EEADR

EECON2(1)

5Fh

60h

File

Address File

Address

WPUA

IOCA

Indirect addr.(1)

OPTION_REG

PCL

STATUS

FSR

TRISA

PCLATH

INTCON

PIE1

PCON

OSCCAL

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

FFh

Bank 1

DFh

E0h

ADRESH(2)

ADCON0(2)

EECON1

ADRESL(2)

ADCON1(2)

ANSEL(2)

TRISC

PORTC

© 2007 Microchip Technology Inc. DS40039E-page 9
PIC16F630/676
TABLE 2-1: PIC16F630/676 SPECIAL REGISTERS SUMMARY BANK 0 
AddrNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2  Bit 1Bit 0
Value on 
POR, 
BOD Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 18,61
01h TMR0 Timer0 Module’s R egist er xxxx xxxx 29
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 17
03h STATUS IRP(2) RP1(2) RP0 TO PD ZDCC
0001 1xxx 11
04h FSR Indirect data memory address pointer xxxx xxxx 18
05h PORTA — — I/O Control Registers --xx xxxx 19
06h —Unimplemented — —
07h PORTC — — I/O Control Registers --xx xxxx 26
08h —Unimplemented — —
09h —Unimplemented — —
0Ah PCLATH — — — Write buffer for  upper  5 bits of program coun ter ---0 0000 17
0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 13
0Ch PIR1 EEIF ADIF ——CMIF——TMR1IF00-- 0--0 15
0Dh —Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 32
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 32
10h T1CON — T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 34
11h —Unimplemented — —
12h —Unimplemented — —
13h —Unimplemented — —
14h —Unimplemented — —
15h —Unimplemented — —
16h —Unimplemented — —
17h —Unimplemented — —
18h —Unimplemented — —
19h CMCON —COUT—CINV CIS CM2 CM1 CM0 -0-0 0000 37
1Ah —Unimplemented — —
1Bh —Unimplemented — —
1Ch —Unimplemented — —
1Dh —Unimplemented — —
1Eh ADRESH(3) Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result  xxxx xxxx 44
1Fh ADCON0(3) ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 45,61
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
2: IRP & RP1 bits are reserved, always maintain these bits clear.
3: PIC16F6 76 onl y.

PIC16F630/676
DS40039E-page 10  © 2007 Microchip Technology Inc.
TABLE 2-2: PIC16F630/676 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
AddrName Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2  Bit 1Bit 0
Value on 
POR, 
BOD Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 18,61
81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 12,30
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 17
83h STATUS IRP(2) RP1(2) RP0 TO PD ZDCC
0001 1xxx 11
84h FSR Indirect data memory address pointer xxxx xxxx 18
85h TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 19
86h —Unimplemented — —
87h TRISC —— TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 —
88h —Unimplemented — —
89h —Unimplemented — —
8Ah PCLATH — — — Write buffer for upper  5 bits of program coun ter ---0 0000 17
8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 13
8Ch PIE1 EEIE ADIE ——CMIE——TMR1IE00-- 0--0 14
8Dh —Unimplemented — —
8Eh PCON — — — — — —PORBOD ---- --qq 16
8Fh ——
90h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- 16
91h ANSEL(3) ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 46
92h —Unimplemented — —
93h —Unimplemented — —
94h —Unimplemented — —
95h WPUA — — WPUA5 WPUA4 —WPUA2 WPUA1 WPUA0 --11 -111 20
96h IOCA —— IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 21
97h —Unimplemented — —
98h —Unimplemented — —
99h VRCON VREN —VRR— VR3 VR2 VR1 VR0 0-0- 0000 42
9Ah EEDAT EEPROM dat a regi ster 0000 0000 49
9Bh EEADR — EEPROM address register 0000 0000 49
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 50
9Dh EECON2 EEPROM control register 2 (not a physical register) ---- ---- 49
9Eh ADRESL(3) Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 44
9Fh ADCON1(3) — ADCS2 ADCS1 ADCS0 ————-000 ---- 45,61
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,  shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
2: IRP & RP1 bits are reserved, always maintain these bits clear.
3: PIC16F676 only.

PIC16F630/676

2.2.2.1 STATUS Register

The S TATUS registe r, shown i n Register 2-1, cont a ins :

• the arithm etic status of the ALU

• the RESET status

• the bank select bits for data memory (SRAM)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bit s are set or clea red according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any STATUS bits. For other instructions not

affecting any STATUS bits, see the “Instruction Set

Summary”.

Note 1: Bits IRP a nd RP1 (ST ATUS<7:6>) are not

used by the PIC16F630/676 and should

be maintained as clear. Use of these bits

is not rec ommended, sinc e this may af fect

upward compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

bit 7 IRP: This bit is reserved and should be maintained as ‘0’

bit 6 RP1: This bit is reserved and should be maintained as ‘0’

bit 5 RP0: Register Bank Select bit (used for direct addressing)

1 = Bank 1 (80h - FFh)

0 = Bank 0 (00h - 7Fh)

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

For borrow, the polarity is reversed.

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high or low order bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

2.2.2.2 OPTION Register

The OPTION register is a readable and writable

configure:

• TMR0/WDT prescaler

• External R A2/INT int errupt

•TMR0

• Weak pull-ups on PORTA

Note: To achieve a 1:1 prescaler assignment for

TMR0, as sign the pre scale r to th e WDT b y

setting PSA bit to ‘1’ (OPTION<3>). See

Section 4.4.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RAPU: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled

0 = PORTA pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RA2/INT pin

0 = Interrupt on falling edge of RA2/INT pin

bit 5 T0CS: TMR0 Clock Sourc e Sele ct bit

1 = Transition on RA2/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA2/T0CKI pin

0 = Increment on low-to-high transition on RA2/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16F630/676

2.2.2.3 INTCON Register

The INTCON register is a readable and writable

for TMR0 register overflow, PORTA change and

external RA2/INT pin interrupts.

Note: Interru pt flag bit s are set whe n an in terrupt

conditi on occurs, regardless of the sta te of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to enabling

an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GIE PEIE T0IE INTE RAIE T0IF INTF RAIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4 INTE: RA2/INT External Interrupt Enable bit

1 = Enables the RA2/INT external interrupt

0 = Disables the RA2/INT external interrupt

bit 3 RAIE: Port Change Interrupt Enable bit(1)

1 = Enables the PORTA change interrupt

0 = Disables the PORTA change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit(2)

1 = TMR0 reg ister has over flow ed (must be cl eared in software)

0 = TMR0 register did not over flow

bit 1 INTF: RA2/INT External Interrupt Flag bit

1 = The RA2/INT external interrupt occurred (must be cleared in software)

0 = The RA2/INT external interrupt did not occur

bit 0 RAIF: Port Change Interrupt Flag bit

1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software)

0 = None of the PORTA <5:0> pins have changed state

Note 1: IOCA register must also be enabled.

2: T0IF bit is se t when Timer0 rolls over. Ti mer 0 is un ch ang ed o n RESET and sh oul d

be initialized before clearing T0IF bit.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

2.2.2.4 PIE1 Regist er

The PIE1 regis te r con t ai ns th e in terrupt enable bi t s, a s

shown in Register 2-4.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0

EEIE ADIE — — CMIE — — TMR1IE

bit 7 bit 0

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt

0 = Disables the EE write complete interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit (PIC16F676 only)

1 = Enables the A/D converter interrupt

0 = Disables the A/D converter interrupt

bit 5-4 Unimplemented: Read as ‘0’

bit 3 CMIE: Comparator Interrupt Enable bit

1 = Enables the comparator interrupt

0 = Disables the comparator i nter rupt

bit 2-1 Unimplemented: Read as ‘0’

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

2.2.2.5 PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-5.

Note: Interru pt fl ag bit s are se t w he n an in terru pt

conditi on occ urs , re gardless of the st a t e of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interr upt flag bit s are clear prio r to enab ling

an interrupt.

R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0

EEIF ADIF ——CMIF——TMR1IF

bit 7 bit 0

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation has not completed or has not been started

bit 6 ADIF: A/D Converter Interrupt Flag bit (PIC16F676 only)

1 = The A/D conversion is complete (must be cleared in software)

0 = The A/D conversion is not complete

bit 5-4 Unimplemented: Read as ‘0’

bit 3 CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator input has not changed

bit 2-1 Unimplemented: Read as ‘0’

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not over flow

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

2.2.2.6 PCON Regist er

The Power Control (PCON) register contains flag bits

to differentiate between a:

• Power-on Reset (POR)

• Brown-out Detect (BOD)

• Watchdog Timer Reset (WDT)

• External MCLR Reset

The PCON Register bits are shown in Register 2-6.

2.2.2.7 OSCCAL Register

The Oscill ator Calibration register (OSCCAL) is used to

calibra te the inte rnal 4 MHz oscillato r. It conta ins 6 bits

to adjust the frequency up or down to achieve 4 MHz.

The OSCCAL register bits are shown in Register 2-7.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x

——————PORBOD

bit 7 bit 0

bit 7-2 Unimplemented: Read as '0'

bit 1 POR: Power-on Reset STATUS bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOD: Brown-out Detect STATUS bit

1 = No Brown-out Detect occurred

0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — —

bit 7 bit 0

bit 7-2 CAL5:CAL0: 6-bit Signed Oscillator Calibration bits

111111 = Maximum frequency

100000 = Center frequency

000000 = Minimum frequency

bit 1-0 Unimplemented: Read as '0'

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

2.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte

comes from th e PCL register, which is a readable an d

writable register. The high byte (PC<12:8>) is not

directly rea dable or wr itable and comes from PCLATH.

On any RESET, the PC is cleared. Figure 2-3 shows the

two situations for the loading of the PC. The upper

example in Figur e 2-3 shows how the PC is lo aded on

a write to PCL (PCLATH<4:0> → PCH). The lower

example in Figure 2-3 shows how the PC is loaded

during a CALL or GOTO instruction (PCLATH<4:3> →

PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 COMPUTED GOTO

A comput ed GOTO is a ccom pli shed by addi ng a n offset

to the program counter (ADDWF PCL). When perform-

ing a table read using a computed GOTO method, care

should be ex ercise d if th e t able loca tion c rosse s a PCL

memory boundary (each 256-byte block). Refer to the

Application Note “Implementing a Table Read"

(AN556).

2.3.2 STACK

The PI C16F630/676 family has an 8-level x 13-bi t wide

hardware stack (see Figure 2-1). The stack space is

not part of either program or data space and the stack

pointer is not readable or writable. The PC is PUSHed

onto the stack when a CALL instruction is executed or

an interrupt causes a branch. The stack is POPed in

the event of a RETURN, RETLW or a RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The st ack operates as a circular buf fer . This means that

after the stack has been PUSHed eight times, the ninth

push ove rwrite s the va lue tha t was s tored fro m the firs t

push. The tenth pus h ov erw ri tes the second pus h (an d

so on).

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode < 10:0 >

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no STATUS bits to indicate

stack overflow or stack underflow

conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interr upt add ress.

PIC16F630/676

2.4 Indirect Addressing, INDF and

FSR Registers

The INDF register is no t a physica l register. Addressin g

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the File Select

produce 00h. Writing to the INDF register indirectly

result s in a n o operation (although STA TUS b its may b e

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR register and the IRP bit

(STATU S<7>), as shown in F igure 2-4.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESS ING

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F630/676

movlw 0x20 ;initialize pointer

movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;no clear next

CONTINUE ;yes continue

For memory map detail see Figure 2-2.

Note 1: The RP1 and IRP bits a re reserved; always maintain these bits clear.

Data

Memory

Indirect AddressingDirect Addressing

Bank S elect Loc ation Sel ect

RP1(1) RP0 6 0

From Opcode IRP(1) FSR Register

Bank Select Location Select

00 01 10 11 180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Not Used

PIC16F630/676

3.0 PORTS A AND C

There are as man y as twelve general purpose I/O pins

available. Depending on which peripherals are

enabled , some or all of the pins may not be a vailable as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

3.1 PORTA and the TRISA Registers

PORTA is an 6-bit wide, bi-directional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA b it (= 1) will make the correspondin g PORTA pin

an input (i.e., put the corresponding output driver in a

Hi-impedance mode). Clearing a TRISA bit (= 0) will

make the correspon ding POR TA pin an output (i.e., put

the contents of the output latch on the selected pin).

The exception is RA3, which is input only and its TRIS

bit will always read as ‘1’. Example 3-1 shows how to

initialize PORTA.

Reading the PORTA register reads the status of the

pins, where as wri tin g to i t will write to the po rt lat ch. All

write operations are read-modify-write operations.

Therefore , a write to a port implies that the port pins are

read, this value is modified and then written to the port

data latch. RA3 reads ‘0’ when MCLREN = 1.

The TRISA register controls the direction of the

PORTA pins, even when they are being used as analog

inputs. The user must ensure the bits in the TRISA

input s. I/O pin s co nfigure d as analo g inpu t alw ays rea d

‘0’.

EXAMPLE 3- 1: INITIA LI ZING PORTA

3.2 Additional Pin Functions

Every PORTA pin on the PIC16F630/676 has an

interrupt-on-change option and every PORTA pin,

except RA3, has a weak pull-up option. The next two

sections describe these functions.

3.2.1 WEAK PULL-UP

Each of the PORTA pins, excep t RA3, has an in div id u-

ally configurable weak internal pull-up. Control bits

WPUAx enable or disable each pull-up. Refer to

off when the port pin is configured as an output. The

pull-ups are disabled on a Power-on Reset by the

RAPU bit (OPTION<7>).

Note: Additional information on I/O ports may be

found in the PIC® Mid-Range Reference

Manual, (DS33023)

Note: The ANSEL (91h) and CMCON (19h)

registers must b e initia lized to configure a n

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

The ANSEL register is defined for the

PIC16F676.

bcf STATUS,RP0 ;Bank 0

clrf PORTA ;Init PORTA

movlw 05h ;Set RA<2:0> to

movwf CMCON ;digital I/O

bsf STATUS,RP0 ;Bank 1

clrf ANSEL ;digital I/O

movlw 0Ch ;Set RA<3:2> as inputs

movwf TRISA ;and set RA<5:4,1:0>

;as outputs

bcf STATUS,RP0 ;Bank 0

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — RA5 RA4 RA3 RA2 RA1 RA0

bit 7 bit 0

bit 7-6: Unimplemented: Read as ’0’

bit 5-0: PORTA<5:0>: PORTA I/O pin

1 = Port pin is >VIH

0 = Port pin is <VIL

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

3.2.2 INTERRUPT-ON-CHANGE

Each of the PORTA pins is individually configurable as

an interrupt-on-change pin. Control bits IOCAx enable

or disable the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are

comp ared w ith the old value la tched on the last rea d of

PORTA. The ‘mismatch’ outputs of the last read are

OR'd together t o set, the PORTA Change In terrupt flag

bit (RAIF) in the INTCON register.

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of PORTA. This will end the

mismatch condition.

b) Clear the flag bit RAIF.

A mism at c h c ond it i on wi ll co nti n ue to s et f lag bi t RA IF.

Reading PORTA will end the mismatch condition and

allow flag bit RAIF to be cleared.

U-0 U-0 R/W-x R/W-x R-1 R/W-x R/W-x R/W-x

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

bit 7 bit 0

bit 7-6: Unimplemented: Read as ’0’

bit 5-0: TRISA<5:0>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)

0 = PORTA pin configured as an output

Note: TRISA<3> always reads 1.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1

—— WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 WPUA<5:4>: Weak Pull-up Register bit

1 = Pull-up enabled

0 = Pull-up disabled

bit 3 Unimplemented: Read as ‘0’

bit 2-0 WPUA<2:0>: Weak Pull-up Register bit

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode

(TRISA = 0).

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

Note: If a change on the I/O pin should occur

when th e read o peratio n is b eing ex ecuted

(start of the Q2 cycle), then the RAIF

interrupt flag may not get set.

PIC16F630/676

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 IOCA<5:0>: Interrupt-on-Change PORTA Control bit

1 = Interrupt-on-change enabled

0 = Interrupt-on-change disabled

Note: Global interrupt enable (GIE) must be enabled for individual interrupts to be

recognized.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

3.2.3 PIN DESCRIPTIONS AND

DIAGRAMS

Each PORTA pin is multiplexed with other functions.

The pins and their combined functions are briefly

described here. For specific information about individ-

ual functions such as the comparator or the A/D, refer

to the appropriate section in this Data Sheet.

3.2.3.1 RA0/AN0/CIN+

Figure 3-1 shows th e diagr am for thi s pin. Th e RA0 pi n

is configurable to function as one of the following:

• a general pu rpose I/ O

• an analog input for the A/D (PIC16F676 only)

• an analog input to the comparator

3.2.3.2 RA1/AN1/CIN-/VREF

Figure 3-1 shows th e diagr am for thi s pin. Th e RA1 pi n

is configurable to function as one of the following:

• as a general purpose I/O

• an analog input for the A/D (PIC16F676 only)

• an analog input to the comparator

• a voltage reference input for the A/D (PIC16F676

only)

FIGURE 3-1: BLOCK DIAGRAM OF RA0

AND RA1 PINS

I/O pin

VDD

VSS

VDD

Weak

Data Bus

WPUA

RD PORTA

PORTA

TRISA

IOCA

Interrupt-on-Change

To Comparato r

To A/D Converter

Analog

Input Mode

RAPU

Analog

Input Mode

PIC16F630/676

3.2.3.3 RA2/AN2/T0CKI/INT/COUT

Figure 3-2 shows th e diagr am f or this pi n. The RA2 pi n

is configurable to function as one of the following:

• a general pu rpose I/ O

• an analog input for the A/D (PIC16F676 only)

• a digital output from the comparator

• the clock input for TM R0

• an external edge triggered interrupt

FIGURE 3-2: BLOCK DIAGRAM OF RA2

3.2.3.4 RA3/MCLR/VPP

Figur e 3-3 sh ows the di agram fo r this pi n. The RA3 pi n

is configurable to function as one of the following:

• a general purpo se inp ut

• as Master C lear Rese t

FIGURE 3-3: BLOCK DIAGRAM OF RA3

I/O pin

VDD

VSS

VDD

Weak

Analog

Input Mode

Data Bus

WPUA

PORTA

TRISA

IOCA

Interrupt-on-Change

To A/D Converter

COUT

Enable

To INT

To TMR0

Analog

Input Mode

RAPU

RD PORTA

Analog

Input

Mode

I/O pin

VSS

Data Bus

RD PORTA

PORTA

IOCA

Interrupt-on-Change

RESET MCLRE

TRISA VSS

MCLRE

PIC16F630/676

3.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT

Figure 3-4 shows th e diagr am for thi s pin. Th e RA4 pi n

is configurable to function as one of the following:

• a general pu rpose I/ O

• an analog input for the A/D (PIC16F676 only)

• a TMR1 gate input

• a crystal/resonator connection

• a clock output

FIGURE 3-4: BLOCK DIAGRAM OF RA4

3.2.3.6 RA5/T1CKI/OSC1/CLKIN

Figur e 3-5 sh ows the di agram fo r this pi n. The RA5 pi n

is configurable to function as one of the following:

• a general purpo se I/O

•a TMR1 clock input

• a cryst al/ reso nator connectio n

• a cloc k inpu t

FIGURE 3-5: BLOCK DIAGRAM OF RA5

I/O pin

VDD

VSS

VDD

Weak

Analog

Input Mode

Data Bus

WPUA

PORTA

TRISA

IOCA

Interrupt-on-Change

FOSC/4

To A/D Converter

Oscillator

Circuit

OSC1

CLKOUT

Enable

Analog

Input Mode

RAPU

RD PORTA

To TMR1 T1G

INTOSC/

RC/EC

(2)

CLK(1)

Modes

CLKOUT

Enable

Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT

Enable.

2: With CLKOUT option .

I/O pin

VDD

VSS

VDD

Weak

Data Bus

WPUA

PORTA

TRISA

IOCA

Interrupt-on-Change

To TMR1 or CLKGEN

INTOSC

Mode

RD PORTA

INTOSC

Mode

RAPU

Oscillator

Circuit

OSC2

(1)

Note 1: Timer1 LP Oscillator enabled.

2: When using T imer1 with LP oscillator, the Schmitt

Trigger is by-passed.

TMR1LPEN(1)

PIC16F630/676

TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR,

BOD

Value on

all

other

RESETS

05h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu

0Bh/8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 000u

19h CMCON —COUT —CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000

81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

91h ANSEL(1) ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

95h WPUA —— WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 --11 -111

96h IOCA —— IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000

Note 1: PIC16F676 only.

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

PIC16F630/676

3.3 PORTC

POR TC is a general purp ose I/O port consi sting of 6 bi-

directional pins. The pins can be configured for either

digit al I/O or anal og inpu t to A/D co nverter. For spec ific

information about individual functions such as the

compara t o r or th e A/D , ref e r to th e appr o p ria t e se ct i on

in this Data Sheet.

EXAMPLE 3- 2: INITIALIZI NG PORTC

3.3.1 RC0/AN4, RC1/AN5, RC2/AN6, RC3/

AN7

The RC0/RC1/RC2/RC3 pins are configurable to

function as one of the following:

• a general pu rpose I/ O

• an analog input for the A/D Converter

(PIC16F6 76 onl y)

FIGURE 3-6: BLOCK DIAGRAM OF

RC0/RC1/RC2/RC3 PINs

3.3.2 RC4 AND RC5

The RC4 and RC5 pins are configurable to function as

a general purpo se I/O s.

FIGURE 3-7: BLOCK DIAGRAM OF RC4

AND RC5 PINS

Note: The ANS EL register (91h) must be cle ar to

configure an analog channel as a digital

input. Pin s conf igur ed as an alog in put s will

read ‘0’. The ANSEL regis te r is def ine d for

the PIC16F676.

bcf STATUS,RP0 ;Bank 0

clrf PORTC ;Init PORTC

bsf STATUS,RP0 ;Bank 1

clrf ANSEL ;digital I/O

movlw 0Ch ;Set RC<3:2> as inputs

movwf TRISC ;and set RC<5:4,1:0>

;as outputs

bcf STATUS,RP0 ;Bank 0

I/O Pin

VDD

VSS

Data bus

PORTC

TRISC

To A/D Converter

PORTC

Analog Input

Mode

I/O Pin

VDD

VSS

Data bus

PORTC

TRISC

PORTC

PIC16F630/676

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — RC5 RC4 RC3 RC2 RC1 RC0

bit 7 bit 0

bit 7-6: Unimplemented: Read as ’0’

bit 5-0: PORTC<5:0>: General Purpose I/O pin

1 = Port pin is >VIH

0 = Port pin is <VIL

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7 bit 0

bit 7-6: Unimplemented: Read as ’0’

bit 5-0: TRISC<5:0>: PORTC Tri-State Control bit

1 = PORTC pin configured as an input (tri-stated)

0 = PORTC pin configured as an output

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

Addres s Name Bit 7 Bit 6 B it 5 B it 4 Bit 3 B it 2 B it 1 B it 0 Value on:

POR, BOD

V alue on all

other

RESETS

07h PORTC —— RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu

87h TRISC —— TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

91h ANSEL(1) ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

Note 1: PIC16F676 only.

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTC.

PIC16F630/676

NOTES:

PIC16F630/676

4.0 TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 4-1 is a block diagram of the T ime r0 module and

the prescaler shared with the WDT.

4.1 Timer0 Operation

Timer mode is selected by clearing the T0CS bit

(OPTION_REG<5>). In Timer mode, the Timer0

module will increment every instruction cycle (without

prescal er). If TMR0 is written , the incre ment is inhibite d

for the following two instruction cycles. The user can

work around this by writing an adjusted value to the

TMR0 registe r.

Counter mode is selected by setting the T0CS bit

(OPTION_REG<5>). In this mode, the Timer0 module

will increment either on every rising or falling edge of

pin RA2/T0CKI. The incrementing edge is determined

by the source edge (T0SE) control bit

(OPTION_REG<4>). Clearing the T0SE bit selects the

rising edge.

4.2 Timer0 Interrupt

A Timer0 interrupt is generated when the TMR0

overflow set s the T0IF bit. The interrupt can be maske d

by clearing the T0IE bit (INTCON<5>). The T0IF bit

(INTCON<2>) must be cleared in software by the

Timer0 module Interrupt Service Routine before re-

enabling this interrupt. The Timer0 interrupt cannot

wake the processor from SLEEP since the timer is

shut-off during SLEEP.

FIGURE 4-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

Note: Additional information on the Timer0

module is ava ilable in the PIC ® M id -R ang e

Reference Manual, (DS33023).

Note: Counter mode has specific external clock

requirements. Additional information on

these requ irement s is availab le in the PIC®

Mid-Range Reference Manual,

(DS33023).

T0CKI

T0SE

CLKOUT

TMR0

Watchdog

Timer

WDT

Time-out

PS0 - PS2

WDTE

Data Bus

Set Flag bit T0IF

on Overflow

T0CS

Note 1: T0SE , T0CS, PSA, PS0-PS2 are bits in the Option register.

SYNC 2

Cycles

8-bit

Prescaler

(= FOSC/4)

PSA

PIC16F630/676

4.3 Using Timer0 with an External

Clock

When no pr escal er is used, t he ex tern al clo ck inp ut is

the same as the pre sc al er outp ut. Th e sy nch ron iz atio n

of T0CKI, with the internal phase clocks, is accom-

plishe d by sampling the prescale r output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necessary for T0CKI to be high for at least 2TOSC (and

a small RC delay of 20 ns) and low for at least 2TOSC

(and a small RC delay of 20 ns). Refer to the electrical

specification of the desired device.

Note: The ANSEL (91h) and CMCON (19h)

registers must b e initia lized to configure a n

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

The ANSEL register is defined for the

PIC16F676.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RAPU: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled

0 = PORTA pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RA2/INT pin

0 = Interrupt on falling edge of RA2/INT pin

bit 5 T0CS: TMR0 Clock Sourc e Sele ct bit

1 = Transition on RA2/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA2/T0CKI pin

0 = Increment on low-to-high transition on RA2/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16F630/676

4.4 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer. For simplicity, this counter will be referred to as

“prescaler” throughout this Data Sheet. The prescaler

assignment is controlled in software by the control bit

PSA (OPTION_REG<3>). Clearing the PSA bit will

assign the prescaler to Timer0. Prescale values are

select abl e via the PS2:PS0 b its (OPT ION_R EG<2:0 >).

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing

to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1, x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer.

4.4.1 SWITCHING PRESCALE R

ASSIGNMENT

The prescaler assignment is fully under software

control (i.e., it can be changed “on the fly” during

program execution). To avoid an unintended device

RESET, the following instruction sequence

(Example 4-1) must be executed when changing the

prescaler assignment from Timer0 to WDT.

EXAMPLE 4-1: CHANGING PRESCA LER

(TIMER0→WDT)

To change prescaler from the WDT to the TMR0

module , use the se quence sh own in Exa mple 4-2. This

preca ution mus t be tak en even if the WDT is dis abled.

EXAMPLE 4-2: CHANGING PRESCA LER

(WDT→TIMER0)

TABLE 4-1: REGISTERS ASSOCIATED WITH TIMER0

bcf STATUS,RP0 ;Bank 0

clrwdt ;Clear WDT

clrf TMR0 ;Clear TMR0 and

; prescaler

bsf STATUS,RP0 ;Bank 1

movlw b’00101111’ ;Required if desired

movwf OPTION_REG ; PS2:PS0 is

clrwdt ; 000 or 001

;

movlw b’00101xxx’ ;Set postscaler to

movwf OPTION_REG ; desired WDT rate

bcf STATUS,RP0 ;Bank 0

clrwdt ;Clear WDT and

; postscaler

bsf STATUS,RP0 ;Bank 1

movlw b’xxxx0xxx’ ;Select TMR0,

; prescale, and

; clock source

movwf OPTION_REG ;

bcf STATUS,RP0 ;Bank 0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Val ue o n

POR, BOD

Value on

all othe r

RESETS

01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu

0Bh/8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 000u

81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown.

Shaded cells are not used by the Timer0 module.

PIC16F630/676

5.0 TIMER1 MODULE WITH GATE

CONTROL

The PIC16F630/676 devices have a 16-bit timer.

Figure 5-1 shows the basic block dia gram of the T imer1

module. Timer1 has the following features:

• 16-bit timer/counter (TMR1H:TMR1L)

• Readable and writable

• Internal or external clock selection

• Synchronous or asynchronous operation

• Interrupt on overflow from FFFFh to 0000h

• Wake-up upon overflow (Asynchronous mode)

• Optional external ena ble input (T1G)

• Op tional LP oscillator

The Timer1 Control register (T1CON), shown in

select the various features of the Timer1 module.

FIGURE 5-1: TIMER1 BLOCK DIAGRAM

Note: Additional information on timer modules is

available in the PIC® Mid-Range Refer-

ence Manual, (DS33023).

TMR1H TMR1L

LP Oscillator T1SYNC

TMR1CS

T1CKPS<1:0> SLEEP Input

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronize

Detect

Synchronized

Clock Input

OSC1

OSC2

Set Flag bit

TMR1IF on

Overflow

TMR1

TMR1ON

TMR1GE

TMR1ON

TMR1GE

INTOSC

T1OSCEN

w/o CLKOUT

T1G

PIC16F630/676

5.1 Timer1 Modes of Operation

Timer1 can operate in one of three modes:

• 16-bit timer with prescaler

• 16-bit synchronous counter

• 16-bit asynchronous counter

In Timer mode, Timer1 is incremented on every instruc-

tion cycle. In Counter mode, Timer1 is incremented on

the rising edge of the external clock input T1CKI. In

addition, the Counter mode clock can be synchroni zed

to the microcontroller system clock or run

asynchronously.

In Count er and Tim er mo dul es , the c oun ter/t im er cl oc k

can be gated by the T1G input.

If an external clock oscillator is needed (and the

microcontroller is using the INTOSC w/o CLKOUT),

Timer1 can use the LP oscillator as a clock source.

5.2 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit (PIR1<0>) is set. To

enable the inter rupt on rollo ver , you m ust set th ese bits :

• Timer1 interru pt Enab le bit (PIE1< 0>)

• PEIE bit (INTCON<6>)

• GIE bit (INTCON<7>).

The interrupt is cleared by clearing the TMR1IF in the

Interrupt Service Routine.

5.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4, or 8

divisions of the clock input. The T1CKPS bits

(T1CON<5:4>) control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write

to TMR1H or TMR1L.

FIGURE 5-2: TIMER1 INCREMENTING EDGE

Note: In Counter mode, a falling edge must be

registered by the counter prior to the first

incr em enti ng ris ing edge.

Note: The T MR1H:TTMR1L regi st er pair and th e

TMR1IF bit should be cleared before

enabling interrupts.

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter in crem ents.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the

clock.

PIC16F630/676

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’

bit 6 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1 = Timer1 is on if T1G pin is l ow

0 = Timer1 is on

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Presca le Se lect bits

11 = 1:8 Prescale Value

10 = 1:4 Prescale Value

01 = 1:2 Prescale Value

00 = 1:1 Prescale Value

bit 3 T1OSCEN: LP Oscillator Enable Control bit

If INTOSC without CLKOUT oscillator is active:

1 = LP oscillator is enabled for Timer1 clock

0 = LP oscillator is off

Else:

This bit is ignored

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock.

bit 1 TMR1CS: Timer1 Clock Sour ce Select bit

1 = External clock from T1OSO/T1CKI pin (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

5.4 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external

clock input is not synchronized. The timer continues to

increment asynchronous to the internal phase clocks.

The timer will continue to run during SLEEP and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer

(Section 5.4.1).

5.4.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L, while the timer is running

from an external asynchronous clock, will ensure a

valid read (taken care of in hardware). However, the

user shoul d keep i n mind that r eadi ng the 16-b it time r

in two 8-b it va lu es i t self, poses c ert ain problem s, s ince

the timer may overflow between the reads.

For write s, it is re commend ed that the us er simply stop

the timer and write the desired values. A write conten-

tion may occur by writing to the timer registers, while

the register is incrementing. This may produce an

unpredictable value in the timer re gister.

Reading the 16-bit value requires some care.

Examples 12-2 and 12-3 in the PIC® Mid-Range MCU

Family Reference Manual (DS33023) show how to

read and write Timer1 when it is running in

Asynchronous mode.

5.5 Timer1 Oscillator

A cryst al osci llator circ uit is built-in between pins OSC1

(input) and OSC2 (amplifier output). It is enabled by

setting co ntrol bit T1OSCEN (T1CON <3>). The oscilla-

tor is a low power oscillator rated up to 32 kHz. It will

continue to run during SLEEP. It is primarily intended

for a 32 kHz crystal. Table 9-2 shows the capacitor

select ion for the Tim er1 osc il lat or.

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the system clock is derived from the internal oscillator.

As with the syste m LP oscillat or, the user must provide

a software time delay to ensure proper oscillator

start-up.

TRISA5 and TRISA4 bits are set when the Timer1

oscillator is enabled. RA5 and RA4 read as ‘0’ and

TRISA5 and TRISA4 bits read as ‘1’.

5.6 Timer1 Operation During SLEEP

Timer1 can only operate during SLEEP when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To setup the timer to wake the device:

• Timer1 must be on (T1CON<0>)

• TMR1IE bit (PIE1<0>) must be set

• PEIE bit (INTCON<6> ) must be set

The device will wake-up on an overflow. If the GIE bit

(INTCON< 7 >) is se t, the de vi ce wil l wa ke -up an d jum p

to the Interrupt Service Routine on an overflow.

TABLE 5-1: RE GISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Note: The ANSEL (91h) and CMCON (19h)

registers must be initia lized to configu re an

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

The ANSEL register is defined for the

PIC16F676.

Note: The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

Value on

all other

RESETS

0Bh/8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF — — CMIF ——TMR1IF00-- 0--0 00-- 0--0

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu

8Ch PIE1 EEIE ADIE — — CMIE ——TMR1IE00-- 0--0 00-- 0--0

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

PIC16F630/676

NOTES:

PIC16F630/676

6.0 COMPARATOR MODULE

The PI C16F630/676 devi ces hav e one anal og comp ar-

ator. The input s to th e comparat or are multiplex ed with

the RA0 and RA1 pins. There is an on-chip Comp arator

Voltage Reference that can also be applied to an input

of the comparator. In addition, RA2 can be configured

as the comparator output. The Comparator Control

the bits to control the comparator.

U-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—COUT— CINV CIS CM2 CM1 CM0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0 ’

bit 6 COUT: Comparator Output bit

When CINV = 0:

1 = VIN+ > VIN-

0 = VIN+ < VIN-

When CINV = 1:

1 = VIN+ < VIN-

0 = VIN+ > VIN-

bit 5 Unimplemented: Read as ‘0 ’

bit 4 CINV: Comparator Output Inversion bit

1 = Output inverted

0 = Output not inverted

bit 3 CIS: Comparator Input Switch bit

When CM2:CM0 = 110 or 101:

1 = VIN- connects to CIN+

0 = VIN- connects to CIN-

bit 2-0 CM2:CM0: Comparator Mode bit s

Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

6.1 Comparator Operation

A single comparator is shown in Figure 6-1, along with

the relationship between the analog input levels and

the digit al ou tput. When the an alog input a t VIN+ is less

than the analog input VIN-, the outp ut of the comp arator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 6-1 represent

the uncertainty due to input offsets and response time.

The polarity of the comparator output can be inverted

by setting the CINV bit (CMCON<4>). Clearing CINV

results in a non-inverted output. A complete table

showing the output state versus input conditions and

the polarity bit is shown in Table 6-1.

TABLE 6-1: OUTPUT STATE VS. INPUT

CONDITIONS

FIGURE 6-1: SINGLE COMPARATOR

Note: To use CIN+ and CIN- pins as analog

inputs, the appropriate bits must be

programmed in the CMCON (19h) register .

Input Conditions CINV COUT

VIN- > VIN+00

VIN- < VIN+01

VIN- > VIN+11

VIN- < VIN+10

Output

VIN-

VIN+

Output

–

VIN+

VIN-

Note: CINV bit (CMCON<4>) is clear.

PIC16F630/676

6.2 Comparator Configuration

There are eigh t mod es of operat ion fo r the c omp arato r.

The CMCON register , shown in Register 6-1, is used to

select the mode. Figure 6-2 shows the eight possible

modes. The TRISA register controls the data direction

of the comparator pins for each mode. If the

Comparator mode is changed, the comparator output

level may not be valid for a specified period of time.

Refer to the specifications i n Section 12.0.

FIGURE 6-2: COMPARATOR I/O OPERATING MODES

Note: Comparator interrupts should be disabled

during a C omp arator mode change. O ther-

wise, a false interrupt may occur.

Comparator Reset (POR Default Value - low power) Comparator Off (Lowest power)

CM2:CM0 = 000 CM2:CM0 = 111

Compara tor w itho ut Ou tput Compara tor w/ o Outp ut and with Interna l Referen ce

CM2:CM0 = 010 CM2:CM0 = 100

Compara t or with Ou tpu t and Intern al R efere nce Multiplexed Input with Internal Reference and Output

CM2:CM0 = 011 CM2:CM0 = 101

Comparator with Output Multiplexed Input with Internal Reference

CM2:CM0 = 001 CM2:CM0 = 110

A = Analog Input, ports always reads ‘0’

D = Digital Input

CIS = Comparator Input Switch (CMCON<3>)

RA1/CIN-

RA0/CIN+ Off (Read as '0')

RA2/COUT D

RA1/CIN-

RA0/CIN+ Off (Read as '0')

RA2/COUT D

RA1/CIN-

RA0/CIN+ COUT

RA2/COUT D

RA1/CIN-

RA0/CIN+ COUT

RA2/COUT D From CVREF Module

RA1/CIN-

RA0/CIN+ COUT

RA2/COUT D

From CV REF Module

RA1/CIN-

RA0/CIN+ COUT

RA2/COUT D

From CVREF Module

CIS = 0

CIS = 1

RA1/CIN-

RA0/CIN+ COUT

RA2/COUT D

RA1/CIN-

RA0/CIN+ COUT

RA2/COUT D

From CVREF Module

CIS = 0

CIS = 1

PIC16F630/676

6.3 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 6-3. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. Th e analog input, th erefore, must be betwee n

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latchup may occur. A

maximum source impedance of 10 kΩ is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

FIGURE 6-3: ANALOG INPUT MODE

6.4 Comparator Output

The comparator output, COUT, is read through the

CMCON reg is ter. This bit is rea d-on ly. The comp ara tor

output may also be directly output to the RA2 pin in

three of the eight possible modes, as shown in

Figure 6-2. When i n one of th ese modes , the ou tput on

RA2 is asynchronous to the internal clock. Figure 6-4

shows the comparator output block diagram.

The TRISA<2> bit functions as an output enable/

disable for the RA2 pin while the comparator is in an

Output mode.

FIGURE 6-4: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM

Rs < 10K

AIN CPIN

5 pF

VDD

VT = 0.6V

RIC

Leakage

±500 nA

Vss

Legend: CPIN = Input Capacitance

VT= Threshold Voltage

ILEAKAGE = Leakage Current at the pin due to Various Junctions

RIC = Interconnect Resistance

RS= Source Impedance

VA = Analog Voltage

Note 1: When reading the PORTA register, all

pins configured as analog inputs will read

as a ‘0’. Pins configured as digital inputs

will convert an analog input according to

the TTL input specification.

2: Analog le vels on any pin that is defined as

a digital input, may cause the in put buff er

to consume more current than is

specified.

To RA2/T0CKI pin

RD CMCON

Set CMIF bit

RESET

To Data Bus

CINV

CVREF

RD CMCON

RA1/CIN-

RA0/CIN+

CM2:CM0

PIC16F630/676

6.5 Comparator Reference

The com parato r m od ule also allo ws t he selection of an

internally generated voltage reference for one of the

comparator inputs. The internal reference signal is

used for four of the eight Comparator modes. The

VRCON register, Register 6-2, controls the voltage

reference module shown in Figure 6-5.

6.5.1 CONFIGURING THE VOLTAGE

REFERENCE

The voltage reference can output 32 distinct voltage

levels, 16 in a high range and 16 in a low range.

The follow ing equati ons determi ne the output vo ltages :

VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD

VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x

VDD / 32)

6.5.2 VOLTAGE REFERENCE

ACCURACY/ERROR

The full range of VSS to VDD cannot be rea liz ed due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figure 6-5) keep CVREF from approaching VSS or

VDD. T he V olt age Re ference is VDD derived and there-

fore, the CVREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Comparator

Voltage Reference can be found in S ection 12.0.

FIGURE 6-5: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

6.6 Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is ensured to have a valid level. If

the internal reference is changed, the maximum delay

of the internal voltage reference must be considered

when using the comparator outputs. Otherwise, the

maximum delay of the comparators should be used

(Table 12-7).

6.7 Operation During SLEEP

Both the comparator and voltage reference, if enabled

before entering SLEEP mode, remain active during

SLEEP. This results in higher SLEEP currents than

shown in the power-down specifications. The

additio nal current consumed by the comp arator and the

voltage reference is shown separately in the specifica-

tions. To minimize power consumption while in SLEEP

mode, turn off the comparator, CM2:CM0 = 111, and

voltage reference, VRCON<7> = 0.

While the comparator is enabled during SLEEP, an

interrupt will wake-up the device. If the device wakes

up from SLEEP, the contents of the CMCON and

VRCON registers are not affected.

6.8 Effects of a RESET

A device RESET forces the CMCON and VRCON

registers to their RESET states. This forces the

comparator module to be in the Comparator Reset

mode, CM2:CM0 = 000 and the volt age reference to it s

off state. Thus, all potential inputs are analog inputs

with the comparator and voltage reference disabled to

consume the smallest current possible.

VRR

VR3:VR0

16-1 Analog

8RRR RR

CVREF to

16 Stages

Comparator

Input

VREN

VDD

MUX

PIC16F630/676

6.9 Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of the comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<6>, to

determine the actual change that has occurred. The

CMIF bit, PIR1<3>, is the comparator interrupt flag.

This bit must be reset in software by clearing it to ‘0’.

Since it is also possible to write a '1' to this register, a

simulated interrupt may be initiated.

The CMIE bit (PIE1<3>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit must also be set. If any of these

bits are cleared, th e interrupt is not enabled, th ough the

CMIF bit wil l stil l be se t if an inter r upt co nd itio n occ urs .

The user , in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of CMCON. This will end the

mismatch condition.

b) Clear flag bit CMIF.

A mismatc h co ndi tio n will co nti nue to set fla g bit CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit CMIF to be cleared.

TABLE 6-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

VREN —VRR— VR3 VR2 VR1 VR0

bit 7 bit 0

bit 7 VREN: CVREF Enable bit

1 = CVREF circuit powered on

0 = CVREF circuit powered down, no IDD drain

bit 6 Unimplemented: Read as '0'

bit 5 VRR: CVREF Range Selection bit

1 = Low range

0 = High range

bit 4 Unimplemented: Read as '0'

bit 3-0 VR3:VR0: CVREF value selection 0 ≤ VR [3:0] ≤ 15

When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

Note: If a change in the CMCON register (COUT)

should occur when a read operation is

being exe cuted (start of the Q2 cycle), then

the CMIF (PIR1<3>) interrupt flag may not

get set.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

Value on

all other

RESETS

0Bh/8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF ——CMIF— — TMR1IF 00-- 0--0 00-- 0--0

19h CMCON —COUT— CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000

8Ch PIE1 EEIE ADIE ——CMIE— — TMR1IE 00-- 0--0 00-- 0--0

85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

99h VRCON VREN —VRR— VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.

PIC16F630/676

7.0 ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

(PIC16F676 ONLY)

The analo g-to-digital converter (A/D) allows conversion

of an analog input signal to a 10-bit binary representa-

tion of that signal. The PIC16F676 has eight analog

inputs, multiplexed into one sample and hold circuit.

The output of the sample and hold is connected to the

input of the converter. The converter generates a

binary result via successive approximation and stores

the result in a 10-bit register. The voltage reference

used in the conversion is software selectable to either

VDD or a voltage applied by the VREF pin. Figure 7-1

shows th e block diagram o f the A/D on the PIC16 F676.

FIGURE 7-1: A/D BLOCK DIAGRAM

7.1 A/D Configuration and Operation

There are three registers available to control the

functionality of the A/D module:

1. ADCON0 (Register 7-1)

2. ADCON1 (Register 7-2)

3. ANSEL (Register 7-3)

7.1.1 ANALOG PORT PINS

The ANS7:ANS0 bits (ANSEL<7:0>) and the TRISA

bits control the operation of the A/D port pins. Set the

corresp onding TRI SA bits to set the pi n output driver to

it s high i mpedance s tate. Li kewis e, set the correspon d-

ing ANS bit to disable the digital input buffer.

7.1.2 CHANNEL SELECTION

There are eight analog channels on the PIC16F676,

AN0 through AN7. The CHS2:CHS0 bits

(ADCON0<4 :2>) control w hich channel is co nnected to

the sample and hold circuit.

7.1.3 VOLTAGE REFERENCE

There are two options for the voltage reference to the

A/D converte r: either VDD is used, or an analo g voltag e

applied to VREF is used. The VCFG bit (ADCON0<6>)

controls the volta ge reference s election. If VCFG is set,

then the voltage on the VREF pin is the reference;

otherwise, VDD is the reference.

7.1.4 CONVERSION CLOCK

The A/D conversion cycle requires 11 TAD. The source

of the conversion clock is software selectable via the

ADCS bits (ADCON1<6:4>). There are seven possible

clock options:

•F

OSC/2

•F

OSC/4

•FOSC/8

•FOSC/16

•F

OSC/32

•FOSC/64

•FRC (dedicated internal oscillator)

For correct conversion, the A/D conversion clock

(1/TAD) must be selecte d to ensure a mi nimum TAD of

1.6 μs. Table 7-1 shows a few TAD calculations for

selected frequencies.

RA0/AN0

ADC

RA1/AN1/VREF

RA2/AN2

RC0/AN4

VDD

VREF

ADON

GO/DONE

VCFG = 1

VCFG = 0

CHS2:CHS0

ADRESH ADRESL

ADFM

VSS

RC1/AN5

RC2/AN6

RC3/AN7

RA4/AN3

Note: Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

PIC16F630/676

TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES

7.1.5 STARTING A CONVERSION

The A/D conversion is initiated by setting the

GO/DONE bi t ( ADCO N0< 1>). Wh en t he c onv ers ion is

complete, the A/D module:

• Clears the GO/DONE bit

• Sets the ADIF flag (PIR1<6 >)

• Generates an interrupt (if enabled)

If the conversion must be aborted, the GO/DONE bit

can be cleared in software. The ADRESH:ADRESL

A/D conversion sample. Instead, the

ADRESH:ADRESL registers wi ll re t ain th e va lue of the

previous conversion. After an aborted conversion, a

AD delay is required before another acquisition can

be initiated. Following the delay, an input acquisition is

automatically started on the selected channel.

7.1.6 CONVERSION OUTPUT

The A/D con version can be su pplied in two format s: left

or right shifted. The ADFM bit (ADCON0<7>) controls

the outpu t format. Figure 7-2 shows the output format s.

FIGURE 7-2: 10-BIT A/D RESULT FORMAT

A/D Clock Source (TAD) Device Frequ ency

Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz

2 TOSC 000 100 ns(2) 400 ns(2) 500 ns(2) 1.6 μs

4 TOSC 100 200 ns(2) 800 ns(2) 1.0 μs(2) 3.2 μs

8 TOSC 001 400 ns(2) 1.6 μs2.0 μs6.4 μs

16 TOSC 101 800 ns(2) 3.2 μs4.0 μs12.8 μs(3)

32 TOSC 010 1.6 μs6.4 μs8.0 μs(3) 25.6 μs(3)

64 TOSC 110 3.2 μs12.8 μs(3) 16.0 μs(3) 51.2 μs(3)

A/D RC x11 2 - 6 μs(1,4) 2 - 6 μs(1,4) 2 - 6 μs(1,4) 2 - 6 μs(1,4)

Legend:Shaded cells are outside of recommended range.

Note 1: The A/D RC source has a typical TAD time of 4 μs for VDD > 3.0V.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the

conversion will be perform ed during SLEEP.

Note: The GO/DONE bit should not be set in the

same instruction that turns on the A/D.

ADRESH ADRESL

(ADFM = 0) MSB LSB

bit 7bit 0bit 7bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1) MSB LSB

bit 7bit 0bit 7bit 0

Unimplemented: Read as ‘0 10-bit A/D Result

PIC16F630/676

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

bit 7 ADFM: A/D Result Formed Select bit

1 = Right justified

0 = Left justified

bit 6 VCFG: Voltage Reference bit

1 = VREF pin

0 = VDD

bit 5 Unimplemented: Read as zero

bit 4-2 CHS2:CHS0: Analog Channel Select bits

000 =Channel 00 (AN0)

001 =Channel 01 (AN1)

010 =Channel 02 (AN2)

011 =Channel 03 (AN3)

100 =Channel 04 (AN4)

101 =Channel 05 (AN5)

110 =Channel 06 (AN6)

111 =Channel 07 (AN7)

bit 1 GO/DONE: A/D Conversion STATUS bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0 = A/D conversion completed/not in progress

bit 0 ADON: A/D Conversion STATUS bit

1 = A/D converter module is operating

0 = A/D converter is shut-off and consumes no operating current

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— ADCS2 ADCS1 ADCS0 — — — —

bit 7 bit 0

bit 7: Unimplemented: Read as ‘0’.

bit 6-4: ADCS<2:0>: A/D Conversion Clock Select bits

000 =FOSC/2

001 =F

OSC/8

010 =F

OSC/32

x11 =F

RC (clock derived from a dedicated internal oscillator = 500 kHz max)

100 =F

OSC/4

101 =F

OSC/16

110 =F

OSC/64

bit 3-0: Unimplemented: Read as ‘0’.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0

bit 7 bit 0

bit 7-0: ANS<7:0>: Analog Select between analog or digital function on pins AN<7:0>, respectively.

1 = Analog input. Pin is assigned as analog input.(1)

0 = Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,

weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit

must be set to In put mode in ord er to allow ex tern al co ntro l o f t he vo ltage on the pin.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

7.2 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input m ode l is sh ow n in Figur e 7-3. The sourc e

impeda nce (RS) and the inte rnal sam pling swi tch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), see

Figure 7-3. The maximum recommended imped-

ance for analog sources is 10 kΩ. As the impedance

is decreased, the acquisition time may be decreased.

After the analog input channel is selected (changed),

this acquisition must be done before the conversion

can be sta r ted .

To calculate the minimum acquisition tim e, Equation 7-1

may be used. This equation ass umes that 1 /2 LSb error

is used (1024 step s for the A/D). The 1/2 LSb error is the

maximum error allowed for the A/D to meet its specified

resolution.

To calculate the minimum acquisition time, TACQ, see

the PIC® Mid-Range Reference Manual (DS33023).

EQUATION 7-1: ACQUISITION TIME

FIGURE 7-3: ANALOG INPUT MODEL

TACQ

Amplifier Settling Time +

Hold Capacitor Charging Time +

Temperature Coefficient

TAMP + TC + TCOFF

2μs + TC + [(Temperature -25°C)(0.05μs/°C)]

CHOLD (RIC + RSS + RS) In(1/2047)

- 120p F (1k Ω + 7kΩ + 10kΩ) In(0.00048 85)

16.47μs

2μs + 16.47μs + [(50°C -25°C)(0.05μs/°C)

19.72μs

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancel s itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

CPIN

RSANx

5 pF

VDD

VT = 0.6V

VT = 0.6V I LEAKAGE

RIC ≤ 1K

Sampling

Switch

SS RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

567891011

(kΩ)

VDD

= 120 pF

± 500 nA

Legend: CPIN

I LEAKAGE

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

PIC16F630/676

7.3 A/D Operation During SLEEP

The A/D converter module can operate during SLEEP.

This requires the A/D clock source to be set to the

internal oscillator. When the RC clock source is

selected, the A/D waits one instruction before starting

the co nve rsion . This allo ws the SLEEP instruction to b e

execut ed, thus eliminati ng m uc h o f th e s wi tc hin g n ois e

from the conversion. When the conversion is complete,

the GO/DONE bit is cleared, and the result is loaded

into the ADRESH:ADRESL registers. If the A/D

interrupt is enabled, the device awakens from SLEEP.

If the A/D interrupt is not enabled, the A/D module is

turned off, although the ADON bit remains set.

When the A/D clock source is something other than

RC, a SLEEP instruction causes the present conversion

to be aborted, and the A/D module is turned off. The

ADON bit remains set.

7.4 Effects of RESET

A device RESET forces all registers to their RESET

state. Thus, the A/D module is turned off and any

pending conversion is aborted. The ADRESH:ADRESL

registers are unchanged.

TABLE 7-2: SUMMARY OF A/D REGISTERS

Addr e s s N a m e Bit 7 Bit 6 B it 5 B i t 4 Bit 3 B it 2 Bit 1 Bit 0 Value on:

POR, BOD

Value on

all other

RESETS

05h PORTA — — PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 --xx xxxx --uu uuuu

07h PORTC — — PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 --xx xxxx --uu uuuu

0Bh, 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0

1Eh ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result xxxx xxxx uuuu uuuu

1Fh ADCON0 ADFM VCFG — CHS2 CHS1 CHS0 GO ADON 00-0 0000 00-0 0000

85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

87h TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0

91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111

9Eh ADRESL Least Significant 2 bit s of t he Le ft Shif ted A/D Result or 8 bit s of t he Righ t Shif ted Resu lt xxxx xxxx uuuu uuuu

9Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ----

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D converter module.

PIC16F630/676

8.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during norma l operati on (full VDD range). This memory

is not directly mapped in the register file space.

Instead, it is indirectly addressed through the Special

Function Registers. There are four SFRs used to read

and write this memory:

• EECON1

• EECON2 (not a physically implemented register)

• EEDATA

• EEADR

EEDATA holds the 8-bit data for read/write, and

EEADR holds the address of the EEPROM location

being accessed. PIC16F630/676 devices have 128

bytes of dat a EEPROM w ith an add res s ra nge from 0h

to 7Fh.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the n ew data (erase be fore write). The EEPROM

data memory is rated for high erase/write cycles. The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature as well as

from chip to chip. Please refer to AC Specifications for

exact limits.

When the data memory is code protected, the CPU

may continue to read and write the data EEPROM

memory. The device programmer ca n no longer access

this memory.

Additional information on the Data EEPROM is

available in the PIC® Mid-Range Reference Manual,

(DS33023).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0

bit 7 bit 0

bit 7-0 EEDATn: Byte value to write to or read from Data EEPROM

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0

bit 7 bit 0

bit 7 Unimplemented: Should be set to '0'

bit 6-0 EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

8.1 EEADR

The EEADR register can address up to a maximum of

128 bytes of data EEPROM. Only seven of the eight

bits in the register (EEADR<6:0>) are required. The

MSb (bit 7) is ignored.

The upper bit should always be ‘0’ to remain upward

compa tible with devices that have more d ata EEPROM

memory.

8.2 EECON1 AND EECON2

REGISTERS

EECON1 is the control register with four low order bits

physically implemented. The upper four bits are non-

implemented and read as '0's.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation.

On power- up, the WR EN bit is clear. The WRERR bit

is s et when a wr ite operat ion i s inte rrupte d by a MCLR

Reset, or a WDT Time-out Reset during normal

operation. In these situations, following RESET, the

user can check the WRERR bit, clear it, and rewrite

the location. The data and address will be cleared,

therefore, the EEDATA and EEADR registers will

need to be r e- ini tial ize d.

Interrupt flag bit EEIF in the PIR1 register is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all '0's. The EECON2 register is used

exclusively in the Data EEPROM write sequence.

U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

———— WRERR WREN WR RD

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’

bit 3 WRERR: EEPROM Error Flag bit

1 =A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or BOD detect)

0 =The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the data EEPROM

bit 1 WR: Write Control bit

1 =Initiates a write cycle (The bit is cleared by har dware once writ e is complete. The WR bit

can only be set, not cleared, in software.)

0 =Write cycle to the data EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit

can only be set, not cleared, in software.)

0 = Does not initiate an EEPROM read

Legend:

S = Bit can only be set

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’ 0’ = Bit is cleared x = Bit is unknown

PIC16F630/676

8.3 READING THE EEPROM DATA

MEMORY

To read a dat a memory location, the user must write the

address to the EEADR register and then set control bit

RD (EECON1<0>), as shown in Example 8-1. The data

is available, in the very next cycle, in the EEDATA

instruction. EEDA T A holds this value until another read,

or until it is written to by the user (during a write

operation).

EXAMPLE 8-1: DATA EEPROM READ

8.4 WRITING TO THE EEPROM DATA

MEMORY

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDATA register. Then the user must follow a

specific sequence to initiate the write for each byte, as

shown in Example 8-2.

EXAMPLE 8-2: DATA EEPROM WRI TE

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment. A cycle count is executed during the

required s equence . Any number th at is not equa l to the

required cycles to execute the required sequence will

prevent the data from being written into the EEPROM.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

After a write sequence has been initiated, clearing the

WREN bit wil l not af fect this writ e cycle. T he WR bit will

be inhibi ted from bei ng s et u nless the WREN b it is se t.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. The EEIF bit

(PIR<7>) register must be cleared by software.

8.5 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the Data

EEPROM should be verified (see Example 8-3) to the

desired value to be written.

EXAMPL E 8- 3: W RIT E V E RIF Y

8.5.1 USING THE DATA EEPROM

The Data EEPROM is a high-endurance, byte addres-

sable array that has been optimized for the storage of

frequently changing information (e.g., program

variables or other data that are updated often).

Frequently changing values will typically be updated

more ofte n than sp ecifica tions D120 or D120A. If this i s

not t he ca se, an arra y re fres h mus t be perf orm ed. For

this reason, variables that change infreq uently (such as

constants, IDs, calibration, etc.) should be stored in

FLASH program memory.

8.6 PROTECTION AGAINST

SPURIOUS WRITE

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been buil t in. On power-u p, WREN is cleare d. Also, the

Power-up Timer (72 ms duration) prevents

EEPROM write.

The writ e in iti ate sequence an d the WR EN bi t tog eth er

help prevent an accidental write during:

•brown-out

• power glitch

• software malfunction

bsf STATUS,RP0 ;Bank 1

movlw CONFIG_ADDR ;

movwf EEADR ;Address to read

bsf EECON1,RD ;EE Read

movf EEDATA,W ;Move data to W

bsf STATUS,RP0 ;Bank 1

bsf EECON1,WREN ;Enable write

bcf INTCON,GIE ;Disable INTs

movlw 55h ;Unlock write

movwf EECON2 ;

movlw AAh ;

movwf EECON2 ;

bsf EECON1,WR ;Start the write

bsf INTCON,GIE ;Enable INTS

Required

Sequence

bcf STATUS,RP0 ;Bank 0

: ;Any code

bsf STATUS,RP0 ;Bank 1 READ

movf EEDATA,W ;EEDATA not changed

;from previous write

bsf EECON1,RD ;YES, Read the

;value written

xorwf EEDATA,W

btfss STATUS,Z ;Is data the same

goto WRITE_ERR ;No, handle error

: ;Yes, continue

PIC16F630/676

8.7 DATA EEPROM OPERATIO N

DURING CODE PROTECT

Data me mory can be code prot ected by program ming

the CPD bit to ‘0’.

When the data memory is code protected, the CPU is

able to read and write data to the Data EEPROM. It is

recommended to code protect the program memory

when code protecting data memory. This prevents

anyone from programming zeroes over the existing

code (which will execute as NOPs) to reach an added

routine, programmed in unused program memory,

which outputs the contents of data memory.

Programming unused locations to ‘0’ will also help

prevent data memory code protection from becoming

breached.

TABLE 8-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n

POR, BOD

Value on all

other

RESETS

0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0

9Ah EEDATA EEPROM Data Register 0000 0000 0000 0000

9Bh EEADR — EEPROM Address Register -000 0000 -000 0000

9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000

9Dh EECON2(1) EEPROM Control Register 2 ---- ---- ---- ----

Legend: x = unknown, u = unchanged, – = unimplemented read as '0', q = value depends upon condition.

Shaded cells are not used by Data EEPRO M module .

Note 1: EEC ON 2 is not a physical register.

PIC16F630/676

9.0 SPECIAL FEATURES OF THE

CPU

Certain special circuits that deal with the needs of real

time applications are what sets a microcontroller apart

from other pro ce ssors . The PIC16 F630/676 famil y has

a host of such features intended to:

• maximize system reliability

• minimize cost through elimination of external

components

• provide power saving operating modes and offer

code protection

These features are:

• Oscillator selection

• RESET

- Power -on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Detect (BOD)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID Locations

• In-Circuit Serial Programming

The PIC16F630/676 has a Watchdog Timer that is

controlled by configuration bits. It runs off its own RC

oscill ator for ad ded reli abili ty. There ar e two time rs that

offer necessary delays on power-up. One is the

Oscillator Start-up Timer (OST), intended to keep the

chip in RESET until the crystal oscillator is stable. The

other is the Pow er-up Timer (PWR T ), which pr ovides a

fixed delay of 72 ms (nominal) on power-up only,

designed to keep the part in RESET while the power

supply stabilizes. There is also circuitry to reset the

device if a brown-ou t occurs, which can provide at least

a 72 ms RESET. With these three functions on-chip,

most applications need no external RESET circuitry.

The SLEEP mode is designed to offer a very low

current Power-down mode . The use r can wake-u p from

SLEEP through:

• External RESET

• Watchdog Timer wake-up

• An interrupt

Several oscillator options are also made available to

allow the p art to f it th e a ppl ic ati on. The INTOSC op tio n

saves system cost while the LP crystal option saves

power. A set of configuration bits are used to select

various o ptions (see Register 9-1).

PIC16F630/676

9.1 Configuration Bits

The conf iguration bits can be programmed (read as '0'),

or left unprogrammed (read as '1') to select various

device configurati ons, as shown in Regi ster 9-1. Thes e

bits are mapped in program memory location 2007h.

Note: Address 2007h is beyond the user program

memory space. It belongs to the special con-

figuration memory space (2000h - 3FFFh),

which can be accessed only during program-

ming. See PIC16F630/676 Programming

Specification for more information.

R/P-1 R/P-1 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

BG1 BG0 — — —CPDCP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0

bit 13 bit 0

bit 13-12 BG1:BG0: Bandgap Calibration bits for BOD and POR voltage(1)

00 = Lowest bandgap voltage

11 = Highest bandgap voltage

bit 11-9 Unimplemented: Read as ‘0’

bit 8 CPD: Data Code Protecti on bit(2)

1 = Data memory code protection is disabled

0 = Data memory code protection is enabled

bit 7 CP: Code Protection bit(3)

1 = Program Memory code protection is disabled

0 = Program Memory code protection is enabled

bit 6 BODEN: Brown-out Detect Enable bit(4)

1 = BOD enabled

0 = BOD disabled

bit 5 MCLRE: RA3/MCLR pin function select(5)

1 = RA3/MCLR pin function is MCLR

0 = RA3/MCLR pin function is digital I/O, MCLR internally tied to VDD

bit 4 PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

bit 3 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 2-0 FOSC2:FOSC0: Oscillator Selection bits

111 = RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN

110 = RC oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN

101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN

100 = INTOSC oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN

011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN

010 = HS oscillator: High speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN

001 = XT oscillator: Crys t al /res ona tor on RA4 /OS C2/CLKO UT and RA5/OSC1/CLKIN

000 = LP oscillator: Low power cry stal on RA4/OSC2/C LKOU T and RA5/OS C1/ CL KIN

Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing

the device as specified in the PIC16F630/676 Programming Specification. These bits are reflected

in an export of the configuration word. Microchip Development Tools maintain all calibration bits to

factory settings.

2: The entire data EEPROM will be erased when the code protection is turned off.

3: The entire program memory will be erased, including OSCCAL value, when the code protection is

turned off.

4: Enabling Brown-out Detect does not automatically enable Power-up Timer.

5: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

Legend:

P = Programmed using ICSP

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

PIC16F630/676

9.2 Oscillator Configurations

9.2.1 OSCILLA T OR TYPES

The PIC16F630/676 can be operated in eight different

Oscillator Option modes. The user can program three

configuration bits (FOSC2 through FOSC0) to select

one of these eight modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC External Resist or/C apacito r (2 modes )

• INT O SC Internal Oscillator (2 modes )

• EC External Cloc k In

9.2.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1 and OSC2 pins to establish

oscillation (see Figure 9-1). The PIC16F630/676 oscil-

lator design requires the use of a parallel cut crystal.

Use of a series cut crystal may yield a frequency

outside of the crystal manufacturers specifications.

When in XT, LP or HS modes, the device can have an

external clock source to drive the OSC1 pin (see

Figure 9-2).

FIGURE 9-1: CRYSTAL OPERATION (OR

CERAMIC RESONATOR)

(HS, XT OR LP OSC

CONFIGURATION)

FIGURE 9-2: EXTERNAL CLOCK INPUT

OPERAT ION (HS, XT, EC,

OR LP OSC

CONFIGURATION)

T ABLE 9-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

T ABLE 9-2: CAPACITOR SELECTION FOR

CRYST AL OSCILLATOR

Note: Additional information on oscillator config-

urations is available in the PIC® Mid-Rang e

Reference Manual, (DS33023).

Note 1: See Table 9-1 and Table 9-2 for recommended

values of C1 and C2.

2: A series resistor may be required for AT strip cut

crystals.

3: RF varies with the Oscillator mode selected

(Approx. value = 10 MΩ).

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3) SLEEP

To Internal

PIC16F630/676

Logic

RS(2)

Ranges Char ac teriz ed:

Mode Freq OSC1(C1) OSC2(C2)

XT 455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF

15 - 68 pF

68 - 100 pF

15 - 68 pF

HS 8.0 MHz

16.0 MHz 10 - 68 pF

10 - 22 pF 10 - 68 pF

10 - 22 pF

Note 1: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time. These values are for design

guidance only. Since each resonator has

its own characteristics, the user should

consult the resonator manufacturer for

appropriate values of external

components.

Mode Freq OSC1(C1) OSC2(C2)

LP 32 kHz 68 - 100 pF 68 - 100 pF

XT 100 kHz

2 MHz

4 MHz

68 - 150 pF

15 - 30 pF

150 - 200 pF

15 - 30 pF

HS 8 MHz

10 MHz

20 MHz

15 - 30 pF

Note 1: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time. These values are for design

guidance only. Rs may be required in HS

mode as well as XT mode to avoid

overdriving crystals with low drive level

specification. Since each crystal has its

own characteristics, the user should

consult the crystal manufacturer for

appropriate values of external

components.

Clock from

External Sy stem PIC16F630/676

OSC1

OSC2(1)

Open

Note 1: Functions as RA4 in EC Osc mode.

PIC16F630/676

9.2.3 EXTERN AL CLOC K IN

For applications where a clock is already available

elsewhere, users may directly drive the PIC16F630/

676 provided that this external clock source meets the

AC/DC timing requirements listed in Section 12.0.

Figure 9-2 shows how an external clock circuit should

be configur ed.

9.2.4 RC OSCILLATOR

For applications where precise timing is not a

requirement, the RC oscillator option is available. The

operation and functionality of the RC oscillator is

dependent upon a number of variables. The RC

oscillator frequency is a function of:

• Supply voltage

• Resistor (REXT) and capacit or (CEXT) values

• Operati ng tem pera ture

The oscillator frequency will vary from unit to unit due

to normal process parameter variation. The difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to account for the

tolerance of the external R and C components.

Figure 9-3 shows how the R/C combination is

connected.

Two options are available for this Oscillator mode

which allow RA4 to be used as a general purpose I/O

or to output FOSC/4.

FIGURE 9-3: RC OSCILLATOR MODE

9.2.5 INTERNAL 4 MHZ OSCILLATOR

When calib rated, the interna l oscillat or provides a fixe d

4 MHz (nominal) system clock. See Electrical

Specifications, Section 12.0, for information on

variation over voltage and temperature.

Two options are available for this Oscillator mode

which allow RA4 to be used as a general purpose I/O

or to output FOSC/4.

9.2.5.1 Calibrating the Internal Oscillator

A calibration instruction is programmed into the last

location of program memory. This instruction is a

RETLW XX, where the literal is the calibration value.

The literal is placed in the OSCCAL register to set the

calibration of the internal oscillator. Example 9-1

demonstrates how to calibrate the internal oscillator.

For best operation, decouple (with capacitance) VDD

and VSS as close to the device as possible.

EXAMPLE 9-1: CALIBRATING THE

INTERNAL OSCILLATOR

9.2.6 CLKOUT

The PIC16F630/676 devices can be configured to

provide a clock out signal in the INTOSC and RC

Oscillator modes. When configured, the oscillator

frequency divided by four (FOSC/4) is output on the

RA4/OSC2/CLKOUT pin. FOSC/4 can be used for test

purposes or to synchronize other logic.

RA4/OSC2/CLKOUT

CEXT

VDD

REXT

VSS

PIC16F630/676

RA5/OSC1/

FOSC/4

Internal

Clock

CLKIN

Note: Erasing the device will also erase the pre-

programmed internal calibration value for

the inte rnal osci llator. The calibra tion valu e

must be saved prior to erasing part as

specified in the PIC16F630/676 Program-

ming specification. Microchip Develop-

ment Tools maintain all calibration bits to

facto ry set t in gs.

bsf STATUS, RP0 ;Bank 1

call 3FFh ;Get the cal value

movwf OSCCAL ;Calibrate

bcf STATUS, RP0 ;Bank 0

PIC16F630/676

9.3 RESET

The PIC16F630/676 differentiates between various

kinds of RESET:

a) Power-on Reset (POR)

b) WDT Reset during normal operation

c) WDT Reset during SLEEP

d) MCLR Reset during normal operation

e) MCLR Reset during SLEEP

f) Brown-out Detect (BOD)

Some registers are not affected in any RESET

condition; their status is unknown on POR and

unchanged in any other RESET. Most other registers

are reset to a “RESET state” on:

• Power-on Reset

•MCLR

Reset

•WDT Reset

• WDT Reset during SLEEP

• Brown-out Detect (BOD)

They are not affected by a WDT wake-up, since this is

viewed as the resumption of no rm al op era t ion . T O an d

PD bits are set or cleared diffe rently in diffe rent RESET

situations as indicated in Table 9-4. These bits are

used in software to determine the na ture of the RESET.

See Table 9-7 for a full description of RESET states of

all registers.

A simplif ied block diagra m of the On-Chip Rese t Circu it

is sh own i n Figure 9-4.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Table 12-4 in Electrical

Specifications Section for pulse width specification.

FIGURE 9-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

VDD

OSC1/

WDT

Module

VDD Rise

Detect

OST/PWRT

On-chip(1)

RC OSC

WDT

Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST

Enable PWRT

SLEEP

See Table 9-3 for time-out situations.

Note 1: This is a separate oscillator from the INTOSC/EC oscillator.

Brown-out

Detect BODEN

CLKIN

VPP pin

10-bit Ripple Counter

PIC16F630/676

9.3.1 MCLR

PIC16F630/676 devices have a noise filter in the

MCLR Reset path. The filter will detect and ignore

small pul ses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

The behavior of the ESD protection on the MCLR pin

has been altered from previous devices of this family.

Vo lta ges app lied to the pin th at exce ed it s spe cif ication

can resu lt in both MCL R Rese t s a nd e xc es sive c urre nt

bey ond t h e de v ic e sp e ci fic at i on du ri ng th e ESD ev e nt .

For this rea son, Microc hip recomme nds that the MC LR

pin no long er be tied direc tly to VDD. The use of an RC

network, as shown in Figure 9 -5, is suggested.

An internal MCLR option is enabled by setting the

MCLRE bit in the configuration word. When enabled,

MCLR is internally tied to VDD. No internal pull-up

option is availab le for the MCLR pin.

FIGURE 9-5: RECOMMENDED MCLR

CIRCUIT

9.3.2 POWER-ON RESET (POR)

The on-chip POR circuit holds the chip in RESET until

VDD has reached a high enough level for proper

operat ion. To take a dvantage of the POR, simp ly tie the

MCLR pin through a res is tor to VDD. This will eliminate

external RC components usually needed to create

Power-on Reset. A maximum rise time for VDD is

required. See Electrical Specifications for details (see

Section 12.0). If the BOD is enabl ed, the maximu m rise

time specificatio n does not apply . The BOD circuitry will

keep the device in RESET until VDD reaches VBOD (see

Section 9.3.5).

When the device starts normal operation (exits the

RESET condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in RESET until the operating

conditions are met.

For additional information, refer to Application Note

AN607 “Power-up Trouble Shooting”.

9.3.3 POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 72 ms (nominal)

time-out on power-up only, from POR or Brown-out

Detect. The Power-up Timer operates on an internal

RC oscillator. The chip is kept in RESET as long as

PWRT is active. The PWRT delay allows the VDD to

rise to an accep table lev el. A configuration bit, PWRTE

can disable (if set) or enable (if cleared or

programmed) the Power-up Timer. The Power-up

Timer should always be enabled when Brown-out

Detect is enabled.

The Power-up Time delay will vary from chip to chip

and due to:

•V

DD variation

• Temperature variation

• Process variation.

See DC parameters for details (Section 12.0).

9.3.4 OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

Note: The POR c ircuit does not prod uce an inter-

nal RESET when VDD declines.

VDD PIC16F630/676

MCLR

1 kΩ (or greater)

0.1 μf

(optio nal, not critic al )

© 2007 Microchip Technology Inc. DS40039E-page 59
PIC16F630/676
9.3.5 BROWN-OUT DETECT (BOD)
The PIC1 6F630/676 me mbers have on -chip Brown-o ut
Detect circuitry. A configuration bit, BODEN, can
disable (if clear/programmed) or enable (if set) the
Brown-out Detect circuitry. If VDD falls below VBOD for
greater than parameter (TBOD) in Table 12-4 (see
Section 12.0), the Brown-out situation will reset the
devic e. This will occur regardless of VDD slew-rate. A
RESET is not guaranteed to occur if VDD falls below
VBOD for less than parameter (TBOD). 
On any RESET (Power-on, Brown-out Detect,
Watchdog, etc.), the chip will remain in RESET until
VDD rises above BVDD (see Figure 9-6). The  Power-up
T i mer w ill no w be in voked , if  enabl ed, and  wil l kee p the
chip in RESET an additional 72 ms. 
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Detect
and the Power-u p Timer will  be re-initialized. Onc e VDD
rises above BVDD, the Power-up Timer will execute a
72 ms RESET.
FIGURE 9-6: BROWN-OUT SITUATIONS 
9.3.6 TIME-OUT SEQUENCE
On power-u p, the tim e-out sequ ence is as fo llows: firs t,
PWRT time-out is invoked after POR has expired.
Then, OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE bit
status. For example, in EC mode with PWRTE bit
erased (PWRT disabled), there will be no time-out at
all. Figure 9-7, Figure 9-8 and Figure 9-9 depict time-
out sequences.
Since the  time-outs oc cur from the POR  pulse, if MCLR
is kep t low  long e nough , the ti me-out s w ill e xpire.  Then
bringing MCLR high will begin execution immediately
(see Figure 9-8). This is useful for testing purposes or
to synchronize more than one PIC16F630/676 device
operating in parallel.
Table 9-6 shows the RESET conditions for some
special registers, while Table 9-7 shows the RESET
conditions for all the registers. 
9.3.7 POWER CONTROL (PCON) STATUS 
REGISTER 
The power CONTROL/STATUS register, PCON
(address 8Eh) has two bits. 
Bit0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent RESETS to see if BOD = 0,  indicat ing
that a brown-o ut has occurred. The BOD STA T US bit is
a don’t care and is not necessarily predictable if the
brown-o ut ci rcu it is  dis abl ed  (by se tti ng BO DE N bit = 0
in the Configuration word).
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset  and unaf fec ted oth erwise. T he user m ust write  a
‘1’ to this bit following a Power-on Reset. On a
subsequent RESET, if POR is ‘0 ’, it wi ll indi cate tha t a
Power-on Reset must have occurred (i.e., VDD may
have gone too low ).
Note: A Brown-out Detect does not enable the
Power-up Timer if the PWRTE bit in the
configuration word is set.
72 ms(1)
VBOD 
VDD
Internal
RESET
VBOD 
VDD
Internal
RESET 72 ms(1)
<72 ms
72 ms(1)
VBOD 
VDD
Internal
RESET
Note 1: 72 ms delay only if PWRTE bit is programmed to ‘0’.

PIC16F630/676

TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS

TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE

TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

TABLE 9-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Oscillator Configuration Power-up Brown-out Detect Wake-up

from SLEEP

PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1

XT, HS, LP TPWRT +

1024•TOSC 1024•TOSC TPWRT +

1024•TOSC 1024•TOSC 1024•TOSC

RC, EC, INTOSC TPWRT —TPWRT ——

POR BOD TO PD

0u11Power-on Reset

1011Brown-out Detect

uu0uWDT Reset

uu00WDT Wake-up

uuuuMCLR Reset during normal operation

uu10MCLR Reset during SLEEP

Legend: u = unchanged, x = unknown

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

V alue on all

other

RESETS(1)

03h STATUS IRP RP1 RPO TO PD ZDC C0001 1xxx 000q quuu

8Eh PCON — — — — ——PORBOD ---- --0x ---- --uq

Legend:u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during

normal operation.

Condition Program

Counter STATUS

Power-on Reset 000h 0001 1xxx ---- --0x

MCLR Reset during normal operation 000h 000u uuuu ---- --uu

MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu

WDT R eset 000h 0000 uuuu ---- --uu

WDT Wake-up PC + 1 uuu0 0uuu ---- --uu

Brown-out Detect 000h 0001 1uuu ---- --10

Interrupt Wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu

Legend:u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the

interrupt vector (0004h) after execution of PC+1.

PIC16F630/676

TABLE 9-7: INITIALIZATION CONDITION FOR REGISTERS

Reset

•MCLR

Reset

• WDT Reset

• Brown-out Detect(1)

• Wake-up from SLEEP

through interrupt

• Wake-up from SLEEP

through WDT time-out

W—xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h/80h — — —

TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h/82h 0000 0000 0000 0000 PC + 1(3)

STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4)

FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu

PORTA 05h --xx xxxx --uu uuuu --uu uuuu

PORTC 07h --xx xxxx --uu uuuu --uu uuuu

PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu

INTCON 0Bh/8Bh 0000 0000 0000 000u uuuu uuqq(2)

PIR1 0Ch 00-- 0--0 00-- 0--0 qq-- q--q(2,5)

T1CON 10h -000 0000 -uuu uuuu -uuu uuuu

CMCON 19h -0-0 0000 -0-0 0000 -u-u uuuu

ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 1Fh 00-0 0000 00-0 0000 uu-u uuuu

OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu

TRISA 85h --11 1111 --11 1111 --uu uuuu

TRISC 87h --11 1111 --11 1111 --uu uuuu

PIE1 8Ch 00-- 0--0 00-- 0--0 uu-- u--u

PCON 8Eh ---- --0x ---- --uu(1,6) ---- --uu

OSCCAL 90h 1000 00-- 1000 00-- uuuu uu--

ANSEL 91h 1111 1111 1111 1111 uuuu uuuu

WPUA 95h --11 -111 --11 -111 uuuu uuuu

IOCA 96h --00 0000 --00 0000 --uu uuuu

VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu

EEDATA 9Ah 0000 0000 0000 0000 uuuu uuuu

EEADR 9Bh -000 0000 -000 0000 -uuu uuuu

EECON1 9Ch ---- x000 ---- q000 ---- uuuu

EECON2 9Dh ---- ---- ---- ---- ---- ----

ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu

ADCON1 9Fh -000 ---- -000 ---- -uuu ----

Legend:u = unchanged, x = unkn own, - = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 9-6 for RESET value for specific condition.

5: If wake-up was due to data EEPROM write completing, bit 7 = 1; A/D conversion completing, bit 6 = 1;

Comparator input changing, bit 3 = 1; or Timer1 rolling over, bit 0 = 1. All other interrupts generating a

wake-up will cause these bits to = u.

6: If RESET was due to brown-out, then bit 0 = 0. All other RESETS will cause bit 0 = u.

PIC16F630/676

FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT T ime-out

OST Time-out

Internal RESET

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal RESET

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal RESET

PIC16F630/676

9.4 Interrupts

The PIC16F630/676 has 7 sources of interrupt:

• External Inte rrup t RA2/INT

• TMR0 Overfl ow Interru pt

• PORTA Change Interrupts

• Comparator Interrupt

• A/D Interrupt (PIC16F676 only)

• TMR1 Overfl ow Interru pt

• EEPROM Data Write Interrupt

The Interrup t Control register (INTCON) and Peripheral

Interrupt register (PIR) record individual interrupt

requests in flag bits. The INTCON register also has

individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>) enables

(if set) all unmaske d interrupts, or disable s (if cleared) all

interrupts. Individual interrupts can be disabled through

their corresponding enable bits in INTCON register and

PIE register. GIE is cleared on R ESET.

The return from interrupt instruction, RETFIE, exits

interrupt routine, as well as sets the GIE bit, which re-

enables unmasked interrupts.

The following interrupt flags are contained in the

INTCON register:

• INT pin interrupt

• PORTA change interrupt

• TMR0 over flo w interru pt

The peripheral interrupt flags are contained in the

special register PIR1. The corresponding interrupt

enable bit is contained in Special Register PIE1.

The following interrupt flags are contained in the PIR

• EEPROM data write interrupt

• A/D interrupt

• Comparator interrupt

• Timer1 overflow interrupt

When an interrupt is serviced:

• The GIE is cleared to disable any further interrupt

• The return address is pushed onto the stack

• The PC is loaded with 0004h

Once in the Interrupt Service Routine, the source(s) of

the interrupt can be determined by polling the interrupt

flag bits. The interrupt fla g bit(s) must be cleared in soft-

ware before re-enabling interrupts to avoid RA2/INT

recursive int errup t s.

For external interrupt events, such as the INT pin, or

PORTA change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 9-11). The latency is the same for one or two-

cycle instructions. Once in the Interrupt Service

Routine, the source(s) of the interrupt can be

determined by polling the interrupt flag bits. The

interrupt flag bit(s) must be cleared in software before

re-enabling interrupts to avoid multiple interrupt

requests.

Note 1: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts which were

ignored are still pending to be serviced

when the GIE bit is set again.

PIC16F630/676

FIGURE 9-10: INTERRUPT LOGIC

TMR1IF

TMR1IE

CMIF

CMIE

T0IF

T0IE

INTF

INTE

RAIF

RAIE

GIE

PEIE

Wake-up (If in SLEEP mode)

Inter rupt to CPU

EEIE

EEIF

ADIF

ADIE (1)

Note 1: PIC16F676 only.

IOCA-RA0

IOCA0

IOCA-RA1

IOCA1

IOCA-RA2

IOCA2

IOCA-RA3

IOCA3

IOCA-RA4

IOCA4

IOCA-RA5

IOCA5

PIC16F630/676

9.4.1 RA2/INT INTERRUPT

External interrupt on RA2/INT pin is edge-triggered;

either rising if INTEDG bit (OPTION<6>) is set, or

falling, if INTEDG bit is clear. When a valid edge

appears on the RA2/INT pin, the INTF bit

(INTCON<1>) is set. This interrupt can be disabled by

clear ing th e INTE control bit (IN TCON<4> ). The I NTF

bit must be cleared in software in the Interrupt Service

Routine before re-enabling this interrupt. The RA2/INT

interrupt can wak e-up the proces sor f r om SL EEP i f th e

INTE bit was set prior to going into SLEEP. The status

of the GIE bit decides whether or not the processor

branche s to the interru pt vector foll owing wake-up. Se e

Section 9.7 for details on SLEEP and Figure 9-13 for

timing of wake-up from SLEEP through RA2/INT

interrupt.

9.4.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

be enabled/disabled by setting/clearing T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 4.0.

9.4.3 PORTA INTERRUPT

An input change on PORTA change sets the RAIF

(INTCON<0>) bit. The interrupt can be enabled/

disabled by setting/clearing the RAIE (INTCON<3>)

bit. Plus individual pins can be configured through the

IOCA register.

9.4.4 COMPARATOR INTERRUPT

See Secti on 6.9 for d escription o f compara tor interrup t.

9.4.5 A/D CONVERTER INTERRUPT

After a con ver sio n i s com ple te, t he ADIF fla g (PIR<6 >)

is set. T he inte rrupt ca n be en abled/ disab led by settin g

or clearing ADIE (PIE<6>).

See Section 7.0 for operation of the A/D converter

interrupt.

FIGURE 9-11: INT PIN INTERRUPT TIMING

Note: The ANSEL (91h) and CMCON (19h)

registers must be initia lized to configu re an

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

The ANSEL register is defined for the

PIC16F676.

Note: If a change on the I/O pin should occur

when th e read o peratio n is be ing ex ecuted

(start of the Q2 cycle), the n the RAIF inter-

rupt flag may not get set.

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC PC+1 PC+1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycl e

Inst (PC) Inst (PC+1)

Inst (PC-1) Inst (0004h)

Dummy Cycl e

Inst ( PC)

—

512

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC Oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

PIC16F630/676

TABLE 9-8: SUMMARY OF INTERRUPT REGISTERS

9.5 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W register and

STATUS register). This must be implemented in

software.

Example 9-2 stores and restores the STATUS and W

in both banks and must be defined at the same offset

from the bank base address (i.e., W_TEMP is defined

at 0x20 in Bank 0 and it must also be defined at 0xA0

in Bank 1 ). The us er registe r, STATUS_TEMP, must b e

defined in Bank 0. The Example 9-2:

• Stores the W regis ter

• Stores the STATUS register in Bank 0

• Executes the ISR code

• Restores the STATUS (and bank select bit

• Restores the W register

EXAMPLE 9-2: SA VING THE ST A TUS AND

W REGISTERS IN RAM

9.6 W atchdog Timer (WDT)

The Watchdog Timer is a free running, on-chip RC

oscillator , which requires no external components. This

RC oscillator is separate fro m the exte rnal RC oscillator

of the CLKIN pin. That means that the WDT will run,

even if the clock on the OSC1 and OSC2 pins of the

device has be en stoppe d (for ex ample , by ex ecuti on of

a SLEEP instructio n). During norm al operation, a WDT

time-out generates a device RESET. If the device is in

SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation. The WDT

can be permanently disabled by programming the

configuration bit WDTE as clear (Section 9.1).

9.6.1 WDT PERIOD

The WDT ha s a nominal time-o ut period of 18 ms, (wi th

no prescaler). The time-out periods vary with tempera-

ture, VDD and process variations from part to part (see

DC specs). If longer time-out periods are desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT under software control by writing

to the OPTION register. Thus, time-out periods up to

2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the presc al er, if assigned to the WD T, and prevent

it from timing out and generating a device RESET.

The TO bit in the STATUS register will be cleare d upon

a Watchdog Timer time-out.

9.6.2 WDT PROGRAMMING

CONSIDERATIONS

It should also be taken in account that under worst case

conditions (i.e., VDD = Min., Temperatu re = Max ., Max.

WDT prescaler) it may take several seconds before a

WDT time-out occurs.

AddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0 Value o n

POR, BOD

V alue on all

other

RESETS

0Bh, 8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 0000 000u

0Ch PIR1 EEIF ADIF ——CMIF——TMR1IF00-- 0--0 00-- 0--0

8Ch PIE1 EEIE ADIE ——CMIE——TMR1IE00-- 0--0 00-- 0--0

Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.

Shaded cells are not used by the Interrupt module.

MOVWF W_TEMP ;copy W to temp register,

could be in either bank

SWAPF STATUS,W ;swap status to be saved into W

BCF STATUS,RP0 ;change to bank 0 regardless of

current bank

MOVWF STATUS_TEMP ;save status to bank 0 register

:(ISR)

SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into

W, sets bank to original state

MOVWF STATUS ;move W into STATUS register

SWAPF W_TEMP,F ;swap W_TEMP

SWAPF W_TEMP,W ;swap W_TEMP into W

PIC16F630/676

FIGURE 9-12: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 9-9: SUMMARY OF WATCHDOG TIMER REGISTERS

T0CKI

T0SE

CLKOUT

TMR0

Watchdog

Timer

WDT

Time-out

PS0 - PS2

WDTE

Data Bus

Set Flag bit T0IF

on Overflow

T0CS

Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.

SYNC 2

Cycles

8-bit

Prescaler

(= FOSC/4)

PSA

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOD

V alue on all

other

RESETS

81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

2007h Config. bits CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 uuuu uuuu uuuu uuuu

Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.

PIC16F630/676

9.7 Power-Down Mode (SLEEP)

The Power-down mode is entered by executing a

SLEEP instruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running

•PD

bit in the STATUS register is cleared

•TO

bit is set

• Oscillator driver is turned off

• I/O ports maintain the status they had before

SLEEP was executed (driving high, lo w, or

hi-impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD, or VSS, with no external

circuitry drawing current from the I/O pin and the

comparators and CVREF should be disabled. I/O pins

that are hi-impedance inputs should be pulled high or

low externally to avoid switching currents caused by

floating inputs. The T0CKI input should also be at VDD

or VSS for lowest current consumption. The

contribu tion from on-chi p pull-ups on PORTA should be

considered.

The MCLR pin must be at a logic high level (VIHMC).

9.7.1 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1. External RESET input on MCLR pin

2. W atchdog Timer W ake-up (if WDT was enabled)

3. Interrupt from RA2/INT pin, PORTA change, or

a peripheral interrupt.

The first event will cause a device RESET. The two

latter events are considered a continuation of program

execution. The TO and PD bits in the STATUS register

can be used to determine the cause of device RESET.

The PD bi t, w hic h is se t on po wer- up, i s cl eare d when

SLEEP is invoked. TO bit is cleared if WDT Wake-up

occurred.

When the SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake -up throug h an interrupt event, th e corres pond-

ing inte rrupt enabl e bit mu st be set (enabled) . W ake-u p

is regardl ess of the st at e of the GIE bi t. If the G IE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction, then branches to the interrupt

address (0004h). In cases where the execution of the

instr u cti o n f o llo w ing SLEEP is not desirable, the user

should hav e an NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from

SLEEP, regardless of the source of wake-up.

FIGURE 9-13: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Note: It s hould be no ted that a RESET generate d

by a WDT time-out does not drive MCLR

pin low.

Note: If the global interrupts are disabled (GIE is

cleared ), but any in terru pt so urce has both

its interrupt en abl e bit and the co rres pon d-

ing interrupt flag bits set, the device will

immediately wake-up from SLEEP. The

SLEEP instructi on is com pl ete ly exec ute d.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 3)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC+2

Note 1: XT, HS or LP Osc illa tor mode assume d.

2: TOST = 1024TOSC (drawing not to scale). Approximately 1 μs delay for RC Oscillator mode. See Section 12 for wake-up from SLEEP

delay in INTOSC mode.

3: GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

4: CLKOUT is not available in XT, HS, LP or EC Osc modes, but shown here for timing reference.

PIC16F630/676

9.8 Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out for verificati on purp os es .

9.9 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution but are

readable and writable during Program/Verify. Only the

Least Significant 7 bits of the ID locations are used.

9.10 In-Ci rcuit Serial Programming

The PIC16F630/676 microcontrollers can be serially

progra mmed w hile in t he en d app licati on c ircuit. This i s

simply don e with two lines fo r clock and da ta, and three

other lines for:

• power

• ground

• programming voltage

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

The device is placed into a Program/Verify mode by

holding the RA0 and RA1 pins low, while raising the

MCLR (VPP) pin from VIL to VIHH (see Programming

Specification). RA0 becomes the programming data

and RA1 becomes the programming clock. Both RA0

and RA1 are Schmitt Trigger inputs in this mode.

After RESET, to place the device into Programming/

Verify mode, the program counter (PC) is at location

00h. A 6-bit command is then supplied to the device.

Depending on the command, 14 bits of program data

are then supplied to or from the device, depending on

whether the command was a load or a read. For

comple te d et a ils of s eri al p r ogr am mi ng, p lea se refe r to

the PIC16F630/676 Programming Specification.

A typical In-Circuit Serial Programming connection is

shown in Figure 9-14.

FIGURE 9-14: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

9.11 In-Circuit Debugger

Since in-circuit debugging requires the loss of clock,

data and MCLR pins, MPLAB® ICD 2 d evelopment with

an 14-pin device is not practical. A special 20-pin

PIC16F676-ICD device is used with MPLAB ICD 2 to

provi de separate cl ock , da t a and MCLR pins and free s

all normally available pins to the user.

This special ICD device is mounted on the top of the

header and its signals are routed to the MPLAB ICD 2

connector. On the bottom of the header is an 14-pin

socket that plugs into the user’s target via the 14-pin

stand-off connector.

When the ICD pin on the PIC16F676-ICD device is

held low, the In-Circuit Debugger functionality is

enabled. This function allows simple debugging

functions when used with MPLAB ICD 2. When the

microcontroller has this feature enabled, some of the

resour ces are not availa ble f or genera l use. Table 9-10

shows which features are consumed by the

background debugger:

TABLE 9-10: DEBUGGER RESOURCES

For more information, see 14-Pin MPLAB ICD 2

Header Information Sheet (DS51299) available on

Microchip’s website (www.microchip.com).

Note: The entire data EEPROM and FLASH

program memory will be erased when the

code protection is turned off. The INTOSC

calibration data is also erased. See

PIC16F630/676 Programming Specifica-

tion for more information.

I/O pins ICDCLK, ICDDATA

Stack 1 level

Program Memory A ddre s s 0h must be NOP

300h - 3FEh

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC16F630/676

VDD

VSS

RA3/MCLR/VPP

RA1

RA0

+5V

VPP

CLK

Data I/O

VDD

PIC16F630/676

NOTES:

PIC16F630/676

10.0 INSTRUCTION SET SUMMARY

The PIC1 6F630/676 ins truction set is highly orthog onal

and is comprised of three basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction type, and one

or more operands, which further specify the operation

of the instruction. The formats for each of the

categories is presented in Figure 10-1, while the

various opcode fields are summarized in Table 10-1.

Table 10-2 lists the instructions recognized by the

MPASMTM assembler. A complete description of each

instruction is also available in the PIC® Mid-Range Ref-

erence Manual (DS33023).

For byte-oriented instructions, ‘f’ represents a file

designator. The file register designator specifies which

file register is to be used by the instruction.

The desti nation designator specifies where the result of

the operation is to be placed. If ‘d’ is zer o , th e r e sult is

placed in the W re gister . If ‘ d’ is one, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operatio n, whi le ‘f’ re pre sen t s t he ad dres s o f the file i n

which the bit is located.

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value

One instr uction cycle co nsists of four os cillator periods ;

for an oscillator frequency o f 4 MHz, t his gives a normal

instruction execution time of 1 μs. All instructions are

executed within a single instruction cycle, unless a

conditional test is true, or the program counter is

change d as a result of an instruction. When this occurs,

the execution takes two instruction cycles, with the

second cycle executed as a NOP.

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies

a hexadecimal digit.

10.1 READ-MODIFY-WRITE

OPERATIONS

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

For example, a CLRF PORTA instruction will read

PORT A, clear all the data bits, then write the result back

to PORTA. This example would have the unintended

result of clearing the condition that set the RAIF flag.

TABLE 10-1: OPCODE FIELD

DESCRIPTIONS

FIGURE 10-1: GENERAL FORMAT FOR

INSTRUCTIONS

Note: To maintain upward compatibility with

future products, do not use the OPTION

and TRIS instructions.

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral field, constant data or label

xDon't care loc ati on (= 0 or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

dDestination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

PC Program Counter

TO Time-out bit

PD Power-down bit

Byte-orie nted file regi s ter operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriented file register operati ons

13 10 9 7 6 0

OPCODE b (B IT # ) f (F IL E #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (li te r a l )

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

PIC16F630/676

TABLE 10-2: PIC16F630/676 INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0xxx

dfff

lfff

0xx0

dfff

ffff

xxxx

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move litera l to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external

device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

Note: Addit ional inform ation on the mi d-range instru ction set is available in the PIC ® Mid-Range MCU Family Ref-

erence Manual (DS33023).

PIC16F630/676

10.2 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [label] ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → (W)

Status Affected: C, DC, Z

Description: The contents of the W register

are ad ded to the eight-bi t literal 'k'

and the result is placed in the W

ADDWF Add W and f

Syntax: [label] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) + (f) → (destination)

Status Affected: C, DC, Z

Desc ription: Add the con tents of the W re gister

with register 'f'. If 'd' is 0, the result

is stored in the W register. If 'd' is

1, the result is stored back in

ANDLW AND Literal with W

Syntax: [label] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. (k) → (W)

Status Affected: Z

Description: The contents of W register are

AND’ed with the eight-bit literal

'k'. The result is placed in the W

ANDWF AND W with f

Syntax: [label] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .AND. (f) → (destination)

Status Affected: Z

Description: AND the W register with register

'f'. If 'd' is 0, the result is stored in

the W regist er. If 'd' is 1, the re su lt

is stored back in register 'f'.

BCF Bit Clear f

Syntax: [label] BCF f,b

Operands: 0 ≤ f ≤ 12 7

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

St at us Af fe cte d: No ne

Description: Bit 'b' in register 'f' is cleared.

BSF Bit Set f

Syntax: [label] BSF f,b

Operands: 0 ≤ f ≤ 12 7

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

St at us Af fe cte d: No ne

Description: Bit 'b' in register 'f' is set.

BTFSS Bit Test f, Skip if Set

Syntax: [label] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7

Operation: skip if (f<b>) = 1

St at us Af fe cte d: None

Descr ipti on : If bit 'b' in regi st er ' f' is '0 ', the next

instructi on is ex ecuted.

If bit 'b' is '1', then the next instruc-

tion is discarded and a NOP is

executed instead, making this a

2-cycle instruction.

BTFSC Bit Test, Skip if Clear

Syntax: [label] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

St at us Af fe cte d: Non e

Description: If bit 'b' in register 'f' is '1', the next

instruction is executed.

If bit 'b', in register 'f', is '0', the

next instru ction is discarde d, and

a NOP is executed instead, making

this a 2-cycle instruction.

PIC16F630/676

CALL Call Subroutine

Syntax: [ label ] CALL k

Operands: 0 ≤ k ≤ 2047

Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected: None

Description: Call Subroutine. First, return

address (PC+1) is pushed onto

the stack. The eleven-bit immedi-

ate a ddress is loade d into P C bit s

<10:0>. The upper bits of the PC

are load ed from PCLA TH. CALL is

a two-cycle instruction.

CLRF Clear f

Syntax: [label] CLRF f

Operands: 0 ≤ f ≤ 127

Operation: 00h → (f)

1 → Z

Status Affected: Z

Desc ript ion : The content s of regi ste r 'f' are

cleared and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h → (W)

1 → Z

Status Affected: Z

Description: W register is cleared. Zero bit (Z)

is set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

St at us Af fe cte d: TO, PD

Description: CLRWDT instruction resets the

Watchdog Timer. It also resets

the prescaler of the WDT.

STATUS bits TO and PD are set.

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (destination)

St at us Af fe cte d: Z

Description: The contents of register 'f' are

complemented. If 'd' is 0, the

result is s tored in W. If 'd' is 1, the

result is stored back in register 'f'.

DECF Decrement f

Syntax: [label] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (destination)

St at us Af fe cte d: Z

Description: Decrement register 'f'. If 'd' is 0,

the result is stored in the W

stored back in register 'f'.

PIC16F630/676

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (destination);

skip if result = 0

Status Affected: None

Description: The contents of register 'f' are

decremented. If 'd' is 0, the result

is placed in the W register. If 'd' is

1, the result is placed back in

If the result is 1, the next instruc-

tion is executed. If the result is 0,

then a NOP is executed instead,

making it a 2-cycle instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 2047

Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Status Affected: None

Description: GOTO is an unconditional branch.

The e le ven -bi t im me dia t e v al ue i s

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTO is a two-

cycle instruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (destination)

Status Affected: Z

Description: The contents of register 'f' are

incremented. If 'd' is 0, the result

is placed in the W regis ter. If 'd' is

1, the result is placed back in

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (destination),

skip if result = 0

St at us Af fe cte d: None

Description: The contents of register 'f' are

incremen ted. If 'd' is 0, the result is

placed in the W register. If 'd' is 1,

the result is placed back in

regis te r 'f'.

If the result is 1, the next instruc-

tion is executed. If the result is 0,

a NOP is exe cuted ins tead, maki ng

it a 2-cycle instruction.

IORLW Inclusive OR Literal with W

Syntax: [ label ] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → (W)

St at us Af fe cte d: Z

Descr iption: The conten ts of the W register are

OR’ed with the eight-bit literal 'k'.

The result is placed in the W

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .OR. (f) → (destination)

St at us Af fe cte d: Z

Description: Inclusive OR the W register with

placed in the W re gis ter. If 'd' is 1,

the result is placed back in

PIC16F630/676

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (destination)

Status Affected: Z

Description: The contents of register f are

moved to a destination dependant

upon the status of d. If d = 0,

destination is W register. If d = 1,

the destination is file register f itself.

d = 1 is useful to test a file register ,

since status flag Z is affected.

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Description: The eight-bit literal 'k' is loaded

into W register. The don’t cares

will assemble as 0’s.

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0 ≤ f ≤ 12 7

Operation: (W) → (f)

Status Affected: None

Description: Move data from W register to

NOP No Op eration

Syntax: [ label ] NOP

Operands: None

Operation: No operation

St at us Af fe cte d: None

Description: No operation.

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE

Operands: None

Operation: TOS → PC,

1 → GIE

St at us Af fe cte d: None

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

St at us Af fe cte d: None

Description: The W register is loaded with the

eight-bit literal 'k'. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

PIC16F630/676

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0, the result is placed in

the W register . If 'd' is 1, the result is

stored back in register 'f'.

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS → PC

Status Affected: None

Description: Return from subroutine. The stack

is POPed an d t he top o f th e s t a ck

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Desc ript ion : The conten t s of regis te r 'f' are

rotat ed one bit to the r ight throug h

the C arry Flag. If 'd' is 0 , the result

is placed in the W register. If 'd' is

1, the result is placed back in

SLEEP

Syntax: [ label ] SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT prescaler,

1 → TO,

0 → PD

St at us Af fe cte d: TO , PD

Descripti on: The power-down STATUS bit,

PD is c lea red. Time-out STATUS

bit, TO is set. Watchdog Timer

and its pres caler are cleared.

The proce ssor is put into SLEEP

mode with th e oscillator sto pped.

SUBLW Subtract W from Literal

Syntax: [ label ] SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k - (W) → (W)

Status Affected: C, DC, Z

Description: The W register is subtracted (2’s

complement method) from the

eight-bit literal 'k'. The result is

placed in the W register.

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - (W) → (destination)

Status

Affected: C, DC, Z

Description: Subtract (2’s complement method)

W register from regi ster 'f'. If 'd' is 0,

the result is stored in the W

stored back in register 'f'.

PIC16F630/676

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (destination<7:4>),

(f<7:4>) → (destination<3:0>)

Status Affected: None

Description: The upper and lower nibbles of

0, the result is placed in the W

placed in register 'f'.

XORLW Exclusive OR Literal with W

Syntax: [label] XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Description: The contents of the W register

are XOR’ed with the eight-bit

literal 'k'. The result is placed in

the W register.

XORWF Exclusive OR W with f

Syntax: [label] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .XOR. (f) → (destination)

St at us Af fe cte d: Z

Description: Exclusive OR the contents of the

W register with register 'f'. If 'd' is

0, the result is stored in the W

stored back in register 'f'.

PIC16F630/676

11.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C18 and MPLAB C30 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Progra mmers

- PICSTART® Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

11.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- Emulator (sold separatel y)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Visual device initializer for easy register

initialization

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Exten si ve on-l in e help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

The MPLAB IDE allows you to:

• Edit your source files (eithe r asse mbly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug us ing :

- Sourc e files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC16F630/676

11.2 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assemb ler for all PIC MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

sour ce fil es

• Directives that allow complete control over the

assembly process

11.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC18 and PIC24 families of microcontrol-

lers an d th e d sPIC 3 0 a nd ds PIC33 family of d igi t al si g-

nal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

11.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB O bject Li brarian manag es the cre ation an d

modification of library files of precompiled code. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, de letion and extraction

11.5 MPLAB ASM30 Assembler, Linker

and Librarian

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linke d with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

11.6 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most periph erals and inte rnal regi sters.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

PIC16F630/676

11.7 MPLAB ICE 2000

High-Performance

In-Circui t Emu lator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing feat ures. Interc hangeabl e proces sor modul es allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows® 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

11.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash D SC® and MCU devic es. It debugs and

programs PIC® and dsPIC® Flash microcontrollers with

the easy-to-use, powerful graphical user interface of the

MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE pro be is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high speed, noise tolerant, low-

voltage differential signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB ID E, new devic es w ill be supported,

and new features will be add ed, such as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages over competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables .

11.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial ProgrammingTM (ICSPTM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug sou rce code by s etting bre akpoi nts , singl e step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

11.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64 ) for men us an d error m essages and a m odu-

lar, detachable socket assembly to support various

pack age types. The ICSP™ cable assembly is incl uded

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Devic e Programmer ca n read, verif y and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 h as high-spe ed co mmunicat ions and

optimized algorithms for quick programming of large

memory devices and in corporates an SD/MMC card for

file storage and secure data applications.

PIC16F630/676

11.11 PICSTART Plus Development

Programmer

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Inte grated Dev elopmen t En vironme nt so ftware makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76 X, may be sup ported with an a dapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

11.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families of

Flash m emory microcontrol lers. The PICkit 2 S tarter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler , and is desig ned to hel p get up to s peed

quickly using PIC® microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

11.13 Demonstration, Development and

Evaluation Boards

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards includ e prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The board s suppo rt a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory .

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart® battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

PIC16F630/676

12.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings†

Ambient temperature under bias...........................................................................................................-40 to +125°C

Storage temperature........................................................................................................................ -65°C to +150°C

Vo lt a ge on VDD with respect to VSS ..................................................................................................... -0.3 to +6.5V

Vo lt a ge on MCLR with respect to Vss ..................................................................................................-0.3 to +13.5V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total pow er dissipa tion(1) ...............................................................................................................................800 mW

Maximum curr ent o ut of VSS pin .....................................................................................................................300 mA

Maximum curr ent i nto VDD pin........................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................................................................± 20 mA

Output clamp current, IOK (Vo < 0 or Vo >VDD).........................................................................................................± 20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin..............................................................................................25 mA

Maximum current sunk by PORTA and PORTC (combined)..........................................................................200 mA

Maximum current sourced PORTA and PORTC (combined)..........................................................................200 mA

Note 1: Power dissip ati on is ca lcu la t ed as follows : PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL).

† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100 Ω should b e used w hen ap plying a "low" le vel to th e MCLR pin, rather than

pulling this pin directly to VSS.

PIC16F630/676

FIGURE 12-1: P IC16F6 30/6 76 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH,

-40°C ≤ TA ≤ +125°C

FIGURE 12-2: PIC16F676 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,

-40°C ≤ TA ≤ +125°C

5.5

2.0

3.5

2.5

3.0

4.0

4.5

5.0

Frequency (MHz)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

81612 2010

5.5

2.0

3.5

2.5

3.0

4.0

4.5

5.0

Frequency (MHz)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

81612 2010

PIC16F630/676

FIGURE 12-3: PIC16F676 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,

0°C ≤ TA ≤ +125°C

5.5

2.0

3.5

2.5

3.0

4.0

4.5

5.0

Frequency (MHz)

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

81612 2010

2.2

PIC16F630/676

12.1 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended)

DC CHARACTERISTICS Standa rd Operating Co nditi ons (unle ss otherw is e stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

D001

D001A

D001B

D001C

D001D

VDD Supply Voltage 2.0

2.2

2.5

3.0

4.5

—

5.5

FOSC < = 4 MHz:

PIC16F630/676 with A/D off

PIC16F676 with A/D on, 0°C to +125°C

PIC16F676 with A/D on, -40°C to +125°C

4 MHZ < FOSC < = 10 MHz

D002 VDR RAM Data Retention

Voltage(1) 1.5* — — V Device in SLEEP mode

D003 VPOR VDD Start Voltage to

ensure internal Power-on

Reset signal

—VSS — V See section on Power-on Reset for details

D004 SVDD VDD Rise Rate to ensure

internal Power-on Reset

signal

0.05* — — V/ms See section on Power-on Reset for details

D005 VBOD —2.1— V

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5.0V, 25°C unless othe rwis e stated . Thes e p a ram eters are for design guida nc e

only and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

PIC16F630/676

12.2 DC Characteristics: PIC16F630/676-I (Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Device Char ac teri s tics Min Typ† Max Units Conditions

VDD Note

D010 Supply Current (IDD)—916μA2.0FOSC = 32 kHz

LP Oscillator Mode

—1828μA3.0

—3554μA5.0

D011 — 110 150 μA2.0F

OSC = 1 MHz

XT Oscillator Mode

— 190 280 μA3.0

— 330 450 μA5.0

D012 — 220 280 μA2.0F

OSC = 4 MHz

XT Oscillator Mode

— 370 650 μA3.0

— 0.6 1.4 mA 5.0

D013 — 70 110 μA2.0F

OSC = 1 MHz

EC Osci ll ator Mo de

— 140 250 μA3.0

— 260 390 μA5.0

D014 — 180 250 μA2.0F

OSC = 4 MHz

EC Osci ll ator Mo de

— 320 470 μA3.0

— 580 850 μA5.0

D015 — 340 450 μA2.0F

OSC = 4 MHz

INTOSC Mode

— 500 780 μA3.0

— 0.8 1.1 mA 5.0

D016 — 180 250 μA2.0F

OSC = 4 MHz

EXTRC Mode

— 320 450 μA3.0

— 580 800 μA5.0

D017 — 2.1 2.95 mA 4.5 FOSC = 20 MHz

HS Osci llator Mode

— 2.4 3.0 mA 5.0

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The t est conditio ns for all I DD measurem ents in Active Operat ion mode ar e: OSC1 = exter nal square w ave,

from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loa di ng and switc hi ng rate, oscill ato r ty pe , i nte rnal c ode e xec ut ion p attern, and te mperature als o hav e

an impact on the current consumption.

PIC16F630/676

12.3 DC Characteristics: PIC16F630/676-I (Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Device Char ac teri s tics Min Typ† Max Units Conditions

VDD Note

D020 Power-down Base Current

(IPD) — 0.99 700 nA 2.0 WDT, BOD, Comparators, VREF,

and T1OSC disabled

— 1.2 770 nA 3.0

— 2.9 995 nA 5.0

D021 — 0.3 1.5 μA 2.0 WDT Current(1)

—1.83.5μA3.0

—8.417μA5.0

D022 — 58 70 μA 3.0 BOD Current(1)

—109130μA5.0

D023 — 3.3 6.5 μA 2.0 Comparator Current(1)

—6.18.5μA3.0

—11.516 μA5.0

D024 — 58 70 μA2.0CVREF Current(1)

—85100μA3.0

—138160μA5.0

D025 — 4.0 6.5 μA 2.0 T1 OSC Current(1)

—4.67.0μA3.0

— 6.0 10.5 μA5.0

D026 — 1.2 755 nA 3.0 A/D Current(1)

— 0.0022 1.0 μA5.0

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

2: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.

PIC16F630/676

12.4 DC Characteristics: PIC16F630/676-E (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C for extended

Param

No. Device Char ac teri s tics Min Typ† Max Units Conditions

VDD Note

D010E Supply Current (IDD)—916μA2.0FOSC = 32 kHz

LP Oscillator Mode

—1828μA3.0

—3554μA5.0

D011E — 110 150 μA2.0F

OSC = 1 MHz

XT Oscillator Mode

— 190 280 μA3.0

— 330 450 μA5.0

D012E — 220 280 μA2.0F

OSC = 4 MHz

XT Oscillator Mode

— 370 650 μA3.0

— 0.6 1.4 mA 5.0

D013E — 70 110 μA2.0F

OSC = 1 MHz

EC Osci ll ator Mo de

— 140 250 μA3.0

— 260 390 μA5.0

D014E — 180 250 μA2.0F

OSC = 4 MHz

EC Osci ll ator Mo de

— 320 470 μA3.0

— 580 850 μA5.0

D015E — 340 450 μA2.0F

OSC = 4 MHz

INTOSC Mode

— 500 780 μA3.0

— 0.8 1.1 mA 5.0

D016E — 180 250 μA2.0F

OSC = 4 MHz

EXTRC Mode

— 320 450 μA3.0

— 580 800 μA5.0

D017E — 2.1 2.95 mA 4.5 FOSC = 20 MHz

HS Osci llator Mode

— 2.4 3.0 mA 5.0

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The t est conditio ns for all I DD measurem ents in Active Operat ion mode ar e: OSC1 = exter nal square w ave,

from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loa di ng and switc hi ng rate, oscill ato r ty pe , i nte rnal c ode e xec ut ion p attern, and te mperature als o hav e

an impact on the current consumption.

PIC16F630/676

12.5 DC Characteristics: PIC16F630/676-E (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C for extended

Param

No. Device Characteristics Min Typ† Max Units Conditions

VDD Note

D020E Power- down Base Curren t

(IPD)— 0.00099 3.5 μA 2.0 WDT, BOD, Comparat ors, VREF,

and T1OSC disabled

— 0.0012 4.0 μA3.0

— 0.0029 8.0 μA5.0

D021E — 0.3 6.0 μA 2.0 WDT Current(1)

—1.89.0μA3.0

—8.420μA5.0

D022E — 58 70 μA 3.0 BOD Current(1)

—109130μA5.0

D023E — 3.3 10 μA 2.0 Comparator Current(1)

—6.113μA3.0

—11.524μA5.0

D024E — 58 70 μA2.0CVREF Current(1)

—85100μA3.0

—138165μA5.0

D025E — 4.0 10 μA2.0T1 OSC Current(1)

—4.612μA3.0

—6.020μA5.0

D026E — 0.0012 6.0 μA 3.0 A/D Current(1)

— 0.0022 8.5 μA5.0

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

2: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.

PIC16F630/676

12.6 DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40° C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Input Low Voltage

VIL I/O ports

D030 with TTL buffer VSS —0.8 V 4.5V ≤ VDD ≤ 5.5V

D030A VSS —0.15 VDD VOtherwise

D031 with Schmitt Trigger buffer VSS —0.2 VDD V Entir e range

D032 MCLR, OSC1 (RC mode) VSS —0.2 VDD V

D033 OSC1 (XT and LP modes) VSS —0.3 V (Note 1)

D033A OSC1 (HS mode) VSS —0.3 VDD V(Note 1)

Input High Voltage

VIH I/O ports —

D040

D040A with TTL buf fer 2.0

(0.25 VDD+0.8) —

—VDD

VDD V

V4.5V ≤ VDD ≤ 5.5V

otherwise

D041 with Schmitt Trigger buffer 0.8 VDD —VDD entire range

D042 MCLR 0.8 VDD —VDD V

D043 OSC1 (XT and LP modes) 1.6 —VDD V(Note 1)

D043A OSC1 (HS mode) 0.7 VDD —VDD V(Note 1)

D043B OSC1 (RC mode) 0.9 VDD —VDD V

D070 IPUR PORTA Weak Pull-up

Current 50* 250 400* μAVDD = 5.0V, VPIN = VSS

Input Leakage Current(3)

D060 IIL I/O ports —± 0.1± 1μAVSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

D060A Analog inp ut s —± 0.1± 1μAVSS ≤ VPIN ≤ VDD

D060B VREF —± 0.1± 1μAVSS ≤ VPIN ≤ VDD

D061 MCLR(2) —± 0.1± 5μAVSS ≤ VPIN ≤ VDD

D063 OSC1 —± 0.1± 5μAVSS ≤ VPIN ≤ VDD, XT, HS and

LP osc configuration

Output Low Voltage

D080 VOL I/O ports ——

0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.)

D083 OSC2/CLKOUT (RC mode) ——

0.6 V IOL = 1.6 mA, VDD = 4.5V (Ind.)

IOL = 1.2 mA, VDD = 4.5V (Ext.)

Output High Voltage

D090 VOH I/O ports VDD - 0.7 ——VIOH = -3.0 mA, VDD = 4.5V (Ind.)

D092 OSC2/CLKOUT (RC mode) VDD - 0.7 ——VIOH = -1.3 mA, VDD = 4.5V (Ind.)

IOH = -1.0 mA, VDD = 4.5V (Ext.)

* These parameters are characte rized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C un less o therwi se st ated . These para meters are for des ign gu idanc e only

and are not tested .

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use

an external clock in RC mode.

2: The leakage current on the MC LR pin is s trongly depend ent on the applied voltage level. The specified lev els

represent normal operating condi tions. Higher leaka ge cu rrent may be measu red at dif f erent input voltages.

3: Negative current is defined as current sourced by the pin.

PIC16F630/676

12.7 DC Charac ter istics: PIC16F630/ 676-I (Industrial), PIC16F630/676-E (E x t e nd e d)

(Cont.)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Capacitive Loading Specs

on Output Pins

D100 COSC2 OSC2 pin — — 15* pF In XT, HS and LP modes when

external clock is used to drive

OSC1

D101 CIO All I/O pins — — 50* pF

Data EEPROM Memory

D120 EDByte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C

D120A EDByte Endurance 10K 100K — E/W +85°C ≤ TA ≤ +125°C

D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write

VMIN = Minimum operating

voltage

D122 TDEW Erase/Write cycle time — 5 6 ms

D123 TRETD Characteristic Retention 40 — — Y ear Provided no other specifications

are violated

D124 TREF Number of Total Erase/Write

Cycle s befor e Refres h(1) 1M 10M — E/W -40°C ≤ TA ≤ +85°C

Program FLASH Memory

D130 EPCell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C

D130A EDCell Endurance 1K 10K — E/W +85°C ≤ TA ≤ +125°C

D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating

voltage

D132 VPEW VDD for Erase/Write 4.5 — 5.5 V

D133 TPEW Erase/Write cycle time — 2 2.5 ms

D134 TRETD Characteristic Retention 40 — — Y ear Provided no other specifications

are violated

* These parameter s are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: See Section 8.5.1 for additional information.

PIC16F630/676

12.8 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created with

one of the following formats:

FIGURE 12-4: LOAD CONDITIONS

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppercas e letters and their meanings :

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

Pin Pin

RL=464Ω

CL= 50 pF fo r all pins

15 pF for OSC2 output

Load Cond ition 1 Load Condition 2

PIC16F630/676

12.9 AC CHARACTERISTICS: PIC16F630/676 (INDUSTRIAL, EXTENDED)

FIGURE 12-5: EXTERNAL CLOCK TIMING

TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

FOSC External CLKIN Frequency(1) DC — 37 kHz LP Os c mo de

DC — 4 MHz XT mode

DC — 20 M Hz HS mode

DC — 20 M Hz EC mode

Oscilla tor Frequency(1) 5 — 37 kHz LP Osc mo de

—4 —MHzINTOSC mode

DC — 4 MHz RC Osc mode

0.1 — 4 MHz XT Osc mode

1— 20MHzHS Osc mode

OSC External CLKIN Period(1) 27 — ∞μsLP Osc mode

50 — ∞ns HS Osc mode

50 — ∞ns EC Osc mode

250 — ∞ns XT Osc mode

Oscillator Perio d (1) 27 200 μsLP Osc mode

—250 — nsINTOSC mode

250 — — ns RC Osc mode

250 — 10,000 ns XT Osc mode

50 — 1,000 ns HS Osc mode

CY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC

3 TosL,

TosH External CLKIN (OSC1) High

External CLKIN Low 2* — — μs LP oscilla tor, TOSC L/H duty cycle

20* — — ns HS oscilla tor, TOSC L/H duty cy cle

100 * — — ns XT oscillat or, TOSC L/H duty cycle

4TosR,

TosF External CLKIN Rise

External CLKIN Fall — — 50* ns LP oscillator

— — 25* ns XT oscillator

— — 15* ns HS oscillator

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested .

Note1: Instruction cycle period (TCY) equals four times the input oscillat or tim e-b as e pe riod . All specified va lu es a r e

based on charac teriza tion da ta f or that particu lar osc illat or type un der st anda rd opera tin g conditi ons w ith the

device e xecut ing co de. Exc eedin g t hese spe cif ied li mit s ma y resu lt in a n uns t able o scillat or o peratio n and/o r

higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external

clock app lie d to OSC 1 pin. Whe n an ex tern al cloc k in put is use d, the ‘max ’ cy c le time li mit is ‘DC’ (no clock)

for all devices.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

23344

PIC16F630/676

TABLE 12-2: PRECISION INTERNAL OSCILLATOR PARAMETERS

Param

No. Sym Characteristic Freq

Tolerance Min Typ† Max Units Conditions

F10 FOSC Internal Calibrated

INTOSC Frequency

±1 3.96 4.00 4.04 MHz VDD = 3.5V, 25°C

±2 3.92 4.00 4.08 MHz 2.5V ≤ VDD ≤ 5.5V

0°C ≤ TA ≤ +85°C

±5 3.80 4.00 4.20 MHz 2.0V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ +85°C (IND)

-40°C ≤ TA ≤ +125°C (EXT)

F14 TIOSC

ST Osci lla tor Wake -up from

SLEEP start-up time* ——6 8μsV

DD = 2.0V, -40°C to +85°C

——4 6μsVDD = 3.0V, -40°C to +85°C

——3 5μsVDD = 5.0V, -40°C to +85°C

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

PIC16F630/676

FIGURE 12-6: CLKOUT AND I/O TIMING

TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS

OSC1

CLKOUT

I/O pi n

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

20, 21

19 18

Old Value New Value

Param

No. Sym Characteristic Min Typ† Max Units Conditions

10 TosH2ckL OSC1↑ to CLOUT↓ — 75 200 ns (Note 1)

11 TosH2ckH OSC1↑ to CLOUT↑ — 75 200 ns (Note 1)

12 TckR CLKOUT rise time — 35 100 ns (Note 1)

13 TckF CLKOUT fall time — 35 100 ns (Note 1)

14 TckL2ioV CLKOUT↓ to Port out valid — — 20 ns (Note 1)

15 TioV2ckH Port in valid before CLKOUT↑ T

OSC + 200 ns — — ns (Note 1)

16 TckH2ioI Port in hold after CLKOUT↑ 0 — — ns (Note 1)

17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 50 150 * ns

— — 300 ns

18 TosH2ioI OSC1↑ (Q2 cycle) to Port input

invalid (I/O in hold time) 100 — — ns

19 TioV2osH Port input valid to OSC1↑

(I/O in setup time) 0——ns

20 T ioR Port output rise time — 10 40 ns

21 TioF Port output fall time — 10 40 ns

22 Tinp INT pin high or low time 25 — — ns

23 Trbp PORTA change INT high or low

time TCY ——ns

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4xTOSC.

PIC16F630/676

FIGURE 12-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

Watchdog

Timer

Reset

I/O Pins

BVDD

RESET (due to BOD)

VDD

(Device in Brown-out Detect)

(Device not in Brown-out Detect)

72 ms time-out(1)

Note 1: 72 ms delay only if PWRTE bit in configuration word is programmed to ‘0’.

PIC16F630/676

TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT DETECT REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

30 TMCLMCLR Pulse Width (low) 2

11 —

18 —

24 μs

ms VDD = 5V, -40°C to +85°C

Extended temperature

31 TWDT Wa tchdog Timer Time-out

Period

(No Prescaler)

10 17

17 25

30 ms

ms VDD = 5V, -40°C to +85°C

Extended temperature

32 TOST Oscillation Start-up Timer

Period — 1024TOSC ——TOSC = OSC1 period

33* TPWRT Power-up Timer Period 28*

TBD 72

TBD 132*

TBD ms

ms VDD = 5V, -40°C to +85°C

Extended Temperature

34 TIOZ I/O Hi-impedance from MCLR

Low or Watchdog Timer Reset ——2.0μs

BVDD Brown-out Detect Voltage 2.025 — 2.175 V

Brown-o ut Hy stere s is TBD — — —

35 TBOD Brown-out Detect Pulse Width 100* — — μsVDD ≤ BVDD (D005)

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

PIC16F630/676

FIGURE 12-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

T0CKI

T1CKI

45 46

47 48

TMR0 or

TMR1

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40* Tt0H T 0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 10 — — ns

42* Tt0P T0CKI Period Greater of:

20 or TCY + 40

— — ns N = prescale value

(2, 4, ..., 256)

45* Tt1H T1CKI High Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous,

with Prescaler 15 — — ns

Asynchronous 30 — — ns

46* Tt1L T 1CKI Low Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous,

with Prescaler 15 — — ns

Asynchronous 30 — — ns

47* Tt1P T 1CK I Input

Period Synchronous Greater of:

30 or TCY + 40

— — ns N = prescale value

(1, 2, 4, 8)

Asynchronous 60 — — ns

Ft1 Timer1 oscillator input frequency range

(oscillator enabled by setting bit T1OSCEN) DC — 200* kHz

48 TCKE Ztmr 1 Delay from external clock edge to timer increment 2 TOSC*—7 TOSC*—

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

PIC16F630/676

TABLE 12-6: COMPARATOR SPECIFICATIONS

TABLE 12-7: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

Comparator Specifications Standard Operating Conditions

-40°C to +125°C (unless otherwise stated)

Sym Characteristics Min Typ Max Units Comments

VOS Input Offset Voltage — ± 5.0 ± 10 mV

VCM Input Common Mode Voltage 0 — VDD - 1.5 V

CMRR Common Mode Rejection Ratio +55* — — db

TRT Response Time(1) — 150 400* ns

TMC2COV Comparator Mode Change to

Output Valid —— 10* μs

* These parameters are characterized but not tested.

Note1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from

VSS to VDD - 1.5V.

Volta ge Refer en ce Spec ifica tions Standard Operating Conditions

-40°C to +125°C (unless otherwise stated)

Sym Characteristics Min Typ Max Units Comments

Resolution —

—VDD/24*

VDD/32 —

—LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

Absolute Accuracy —

——

—± 1/2*

± 1/2* LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

Unit Resistor Value (R) — 2k* — Ω

Settling Time(1) ——10*μs

* These parameters are characterized but not tested.

Note1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.

PIC16F630/676

TABLE 12-8: PIC16F676 A/D CONVERTER CHARACTERISTICS:

Param

No. Sym Characteristic Min Typ† Max Units Conditions

A01 NRResol utio n — — 10 bits bit

A02 EABS Total Absolute

Error* —— ±1LSbVREF = 5.0V

A03 EIL Integral Error — — ±1LSbVREF = 5.0V

A04 EDL Dif fere nti al Error — — ±1 LSb No missing codes to 10 bits

VREF = 5.0V

A05 EFS Full Scale Range 2.2* — 5.5* V

A06 EOFF Offset Error — — ±1LSbVREF = 5. 0V

A07 EGN Gain Error — — ±1LSbVREF = 5.0V

A10 — Monotonicity — guaranteed(3) ——VSS ≤ VAIN ≤ VREF+

A20

A20A VREF Referen ce Voltage 2.0

2.5 ——

VDD + 0.3 VAbsolute minimum to ensure 10-bit

accuracy

A21 VREF Reference V High

(VDD or VREF)VSS —VDD V

A25 VAIN Analog Input

Voltage VSS —VREF V

A30 ZAIN Recommended

Impedan ce of

Analog Voltage

Source

—— 10kΩ

A50 IREF VREF Input

Current(2) 10

—

1000

μA

During VAIN acquisition .

Based on differential of VHOLD to VAIN.

During A/D conversion cycle.

* These parameters are characterized but n ot tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: When A/D is off, it wi ll n ot co ns ume any cu rrent other than leak ag e cu rrent. The power-dow n c urre nt sp ec

includes any such leakage from the A/D module.

2: VREF current is from External VREF or VDD pin, whichever is selected as reference input.

3: The A/D c onversion resul t never decre ases with an increase in the input voltage a nd has no m issing cod es.

PIC16F630/676

FIGURE 12-10: PIC16F676 A/D CONVERSION TIMING (NORMAL MODE)

TABLE 12-9: PIC16F676 A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DAT A

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

987 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 TCY

134 (TOSC/2)(1)

1 TCY

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D Clock Period 1.6 — — μsTOSC based, VREF ≥ 3.0V

3.0* — — μsT

OSC based, VREF full range

130 TAD A/D Internal RC

Oscillator Perio d 3.0* 6.0 9 .0* μsADCS<1:0> = 11 (RC mode)

At VDD = 2.5V

2.0* 4.0 6.0* μsAt V

DD = 5.0V

131 TCNV Conversion Time

(not includin g

Acquisiti on Time)(1)

—11—TAD Set GO bit to new data in A/D result

132 TACQ Acquisiti on Time (Note 2)

11.5

—

μs

μs The minimum time is the amplifier

settling time. This may be used if th e

“new” inpu t voltag e has not changed

by more than 1 LSb (i.e., 4.1 mV @

4.096V) from the last sampled volt-

age (as stored on CHOLD).

134 TGO Q4 to A/D Clock

Start —TOSC/2 — — If the A/D cl ock source is selecte d as

RC, a time of TCY is added before

the A/D clock starts. This allows the

SLEEP instruction to be executed.

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: ADRES register may be read on the following TCY cycl e.

2: See Table 7-1 for minimum conditions.

PIC16F630/676

FIGURE 12-11: PIC16F676 A/D CONVERSION TIMING (SLEEP MODE)

TABLE 12-10: PIC16F676 A/D CONVERSION REQUIREMENTS (SLEEP MODE)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D Clock Period 1.6 — — μsVREF ≥ 3.0V

3.0* — — μsVREF full range

130 TAD A/D Internal RC

Osci lla tor Perio d 3.0* 6. 0 9.0* μsADCS<1:0> = 11 (RC mode)

At VDD = 2. 5V

2.0* 4.0 6.0* μsAt VDD = 5.0V

131 TCNV Conversion Time

(not including

Acquisition T ime)(1)

—11—T

132 TACQ Acquis iti on Tim e (Note 2)

11.5

—

μs

μs The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

change d by more than 1 LSb (i.e .,

4.1 mV @ 4.096V) from the last

sampled voltage (as stored on

CHOLD).

134 TGO Q4 to A/D Clock

Start —TOSC/2 + TCY — — If the A /D clo ck s ou r ce i s selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEP instruction to b e

executed.

* These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Table 7-1 for minimum conditions.

131

130

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMP LING STOPPED

DONE

NEW_DATA

9 7 3210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

134

132

1 TCY

(TOSC/2 + TCY)(1)

1 TCY

PIC16F630/676

NOTES:

PIC16F630/676

13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period

of time and matrix samples. 'Typical' represents the mean of the distribution at 25°C. 'Max' or 'min' represents

(mean + 3σ) or (mean - 3σ) respectively, where σ is standard deviation, over the whole temperature range.

FIGURE 13-1: TYPICAL IPD vs. VDD OVER TEMP (-40°C TO +25°C)

FIGURE 13-2: TYPICAL IPD vs. VDD OVER TEMP (+85°C)

Typical Baselin e I

0.0E+00

1.0E-09

2.0E-09

3.0E-09

4.0E-09

5.0E-09

6.0E-09

2 2.5 3 3.5 4 4.5 5 5.5

(V)

(A)

-40

Typical Baselin e IPD

0.0E+00

5.0E-08

1.0E-07

1.5E-07

2.0E-07

2.5E-07

3.0E-07

3.5E-07

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

(A)

PIC16F630/676

FIGURE 13-3: TYPICAL IPD vs. VDD OVER TEMP (+125°C)

FIGURE 13-4: MAX IMU M IPD vs. VDD OVER TEMP (-40°C TO +25°C)

Typical Baseline IPD

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

2.5E-06

3.0E-06

3.5E-06

4.0E-06

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

(A)

125

Maximum Baseline I

0.0E+00

1.0E-08

2.0E-08

3.0E-08

4.0E-08

5.0E-08

6.0E-08

7.0E-08

8.0E-08

9.0E-08

1.0E-07

22.533.544.555.5

VDD (V)

(A)

-40

PIC16F630/676

FIGURE 13-5: MAX IMU M IPD vs. VDD OVER TEMP (+85°C)

FIGURE 13-6: MAX IMU M IPD vs. VDD OVER TEMP (+125° C)

Maximum Baseline I

0.0E+00

1.0E-07

2.0E-07

3.0E-07

4.0E-07

5.0E-07

6.0E-07

7.0E-07

8.0E-07

9.0E-07

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

(A)

Maximum Baseline I

0.0E+00

1.0E-06

2.0E-06

3.0E-06

4.0E-06

5.0E-06

6.0E-06

7.0E-06

8.0E-06

9.0E-06

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

(A)

125

PIC16F630/676

FIGURE 13-7: TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)

FIGURE 13-8: TYPICAL IPD WITH CMP ENABLED vs. VDD OVER TEMP (- 40°C TO +125°C)

Typical BOD I

100

110

120

130

3 3.5 4 4.5 5 5.5

(V)

(uA)

-40

125

Typical Comparator I

0.0E+00

2.0E-06

4.0E-06

6.0E-06

8.0E-06

1.0E-05

1.2E-05

1.4E-05

1.6E-05

1.8E-05

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

(A)

-40

125

PIC16F630/676

FIGURE 13-9: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (-40°C TO +25°C)

FIGURE 13-10: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+85°C)

Typical A/D I

0.0E+00

5.0E-10

1.0E-09

1.5E-09

2.0E-09

2.5E-09

3.0E-09

3.5E-09

4.0E-09

4.5E-09

5.0E-09

2 2.5 3 3.5 4 4.5 5 5.5

(V)

(A)

-40

Typical A/D I

0.0E+00

5.0E-08

1.0E-07

1.5E-07

2.0E-07

2.5E-07

3.0E-07

3.5E-07

2 2.5 3 3.5 4 4.5 5 5.5

(V)

(A)

PIC16F630/676

FIGURE 13-11: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125°C)

FIGURE 13-12: TYPICAL IPD WITH T1 OSC ENABLED vs. VDD OVER TEMP (-40°C TO +125°C),

32 KHZ, C1 AND C2=50 pF)

Typical A/D IPD

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

2.5E-06

3.0E-06

3.5E-06

22.533.544.555.5

(V)

(A)

125

Typical T1 I

0.00E+00

2.00E-06

4.00E-06

6.00E-06

8.00E-06

1.00E-05

1.20E-05

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

(V)

(A)

-40

125

PIC16F630/676

FIGURE 13-13: TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)

FIGURE 13-14: TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)

Typical CV

REF

100

120

140

160

2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

-40

125

Typical WDT I

2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

-40

125

PIC16F630/676

FIGURE 13-15: MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1μF AND

0.01μF DECOUPLING (VDD = 3.5V)

FIGURE 13-16: MAXIMUM AND MINIMUM INTOSC FREQ vs. VDD WITH 0.1μF AND 0.01μF

DECOUPLING (+25°C)

Internal Oscillator

Frequency vs Temperature

3.80E+06

3.85E+06

3.90E+06

3.95E+06

4.00E+06

4.05E+06

4.10E+06

4.15E+06

4.20E+06

-40°C 0°C 25°C 85°C 125°C

Temperature (°C)

Frequency (Hz)

-3sigma

average

+3sigma

Internal Oscillator

Frequency vs VDD

3.80E+06

3.85E+06

3.90E+06

3.95E+06

4.00E+06

4.05E+06

4.10E+06

4.15E+06

4.20E+06

2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

VDD (V)

Frequency

(Hz)

-3sigma

average

+3sigma

PIC16F630/676

FIGURE 13-17: TYPICAL WDT PERIOD vs. VDD (-40°C TO +125°C)

WDT Time - o u t

2 2.5 3 3.5 4 4.5 5 5.5

(V)

Time (

mS)

-40

125

PIC16F630/676

NOTES:

PIC16F630/676

14.0 PACKAGING INFORMATION

14.1 Package Mark ing Information

XXXXXXXXXXXXXX

14-Lead PDIP (Skinny DIP) Example

XXXXXXXXXXXXXX

YYWWNNN

16F630-I

0215/017

XXXXXXXXXXX

14-Lead SOIC

XXXXXXXXXXX

YYWWNNN

Example

16F630-E

0215/017

14-Lead TSSOP

NNN

XXXXXXXX

YYWW

Example

017

16F630

0215

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The P b-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

PIC16F630/676

14.2 Package Details

The following sections give the technical details of the

packages.

14-Lead Plastic Dual In-Line (P or PD) – 300 mil Body [PDIP]

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 14

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .735 .750 .775

Tip to Seating Plane L .115 .130 .150

Lead Thickness c .008 .010 .015

Upper Lead Width b1 .045 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

123

Microchip Technology Drawing C04-005

PIC16F630/676

14-Lead Plastic Small Outline (SL or OD) – Narrow, 3.90 mm Body [SOIC]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Ref erence Dimens ion, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 14

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff § A1 0.10 – 0.25

Overall Width E 6.00 BSC

Molded Package Width E1 3.90 BS C

Overall Length D 8.65 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

123

hα

Microchip Technology Drawing C04-065

PIC16F630/676

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Ref erence Dimens ion, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 14

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 4.90 5.00 5.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

NOTE 1

L1 L

Microchip Technology Drawing C04-087

PIC16F630/676

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A

This is a new data sheet.

Revision B

Added characterization graphs.

Updated specifications.

Added notes to indicate Microchip programmers

maintain all calibration bits to factory settings and the

PIC16F676 ANSEL register must be initialized to

configure pins as digital I/O.

Revision C

Revision D

Updated Package Drawings; Replaced PICmicro with

PIC.

Revision E (03/2007)

Replaced Package Drawings (Rev. AM); Replaced

Development Support Section

APPENDIX B: DEVICE

DIFFERENCES

The differences between the PIC16F630/676 devices

listed in this data sheet are shown in Table B-1.

TABLE B-1: DEVICE DIFFERENCES

Feature PIC16F630 PIC16F676

A/D No Yes

PIC16F630/676

APPENDIX C: DEVICE MIGRATIONS

This section is intended to describe the functional and

electrical specification differences when migrating

between functionally similar devices (such as from a

PIC16C74A to a PIC16C74B).

Not Applicable

APPENDIX D: MIGRATING FROM

OTHER PIC®

DEVICES

This discusses some of the issues in migrating from

other PIC dev ices to the PIC16 F6XX famil y of devices .

D.1 PIC12C67X to PIC12F6XX

TABLE 1: FEATURE COMPARISON

Feature PIC12C67X PIC16F6XX

Max Operating Speed 10 MHz 20 M Hz

Max Program Memory 2048 bytes 1024 bytes

A/D Resolution 8-bit 10-bit

Data EEPROM 16 bytes 64 bytes

Oscillator Modes 5 8

Brown-out Detect N Y

Internal Pull-ups RA0/1/3 RA0/1/2/4/5

Interrupt-on-change RA0/1/3 RA0/1/2/3/4/5

Comparator N Y

Note: This device has been designed to perform

to the parameters of its data sheet. It has

been tested to an electrical specification

designed to determine its conformance

with these parameters. Due to process

differences in the manufacture of this

device, this device may have different

performan ce c harac teristi cs than it s ea rlier

version. These differences may cause this

device to perform differently in your

application than the earlier version of this

device.

© 2007 Microchip Technology Inc. DS40039E-page 121
PIC16F630/676
INDEX 
A
A/D......................................................................................43
Acquisition Requirements ...........................................47
Block Diagr a m......................... ..................... ...............43
Calculating Acquisition Time.......................................47
Configuration and Operation..... .... .... .... .... .... . .. .... .... ...43
Effects of a RESET.....................................................48
Internal Sampling Switch (Rss) Impedance....... .. .. .... .47
Operation During SLEEP............................................48
PIC16F675 Converter Characteristics......................101
Source Impedance......................................................47
Summary of Reg isters........ .. ..................... .................48
Absolute Maximum Ratings................................................83
AC Characteristics
Industrial and Extended........... . .. .... .... .... .... ................94
Analog Input Connection Considerations............................40
Analog-to-Digital Converter. See A/D
Assembler
MPASM Assembler.....................................................80
B
Block Diagram
TMR0/WDT Prescaler.................................................29
Block Diagrams
Analog Input Mode................. ..................... ................40
Analog Input Model..................................... ................47
Com p ar a t o r Ou tput................. ..................... ...............40
Comparator Voltage Reference ..................................41
On-C h i p  R ese t Circui t. ........ ............... ..................... ....57
RA0 and RA1 Pins................... . .. .... .. .... .. .... .. . .. .... .. .... .22
RA2.............................................................................23
RA3.............................................................................23
RA4.............................................................................24
RA5.............................................................................24
RC Oscillator Mode.....................................................56
RC0/RC1/RC2/RC3 Pins............................................26
RC4 AND RC5 Pins....................................................26
Timer1.........................................................................32
Watchdog Timer..........................................................67
Brown-out
Asso c i a te d  R e g i st e r s........ ..................... .....................60
Brown-out Detect (BOD).....................................................59
Brown-out Detect Timing and Characteristics.....................97
C
C Compiler s
MPLAB C18... ......... ..................... .............. .................80
MPLAB C30... ......... ..................... .............. .................80
Calibrated Internal RC Frequencies.... .. .... .... .. .... .. . .. .... .. .... .95
CLKOUT .............................................................................56
Code Examples
Changing Prescaler ....................................................31
Dat a E EPROM Read...... .. ............... ..................... ......51
Dat a E EPROM Wr ite....................... ............... ............51
Initializing PORTA.......................................................19
Initializing PORTC .......................................................26
Saving STAT US and W Reg isters in  RAM ......... .. ......66
Write Verify .................................................................51
Code Protection ............... .. .... .... .. .... ................. .. ................69
Comparator.........................................................................37
Asso c i a te d  R e g isters....................... ............... ............42
Configuration...............................................................39
Effects of a RESET.....................................................41
I/O Operating Modes...................................................39
Interrupts.....................................................................42
Operation....................................................................38
Operation During SLEEP............................................ 41
Output......................................................................... 40
Reference................................................................... 41
Response Time .......................................................... 41
Compa r a tor Specification s ......... ........ ............... ........ ........ 100
Comparator Voltage Reference Specifications........ .. .... .. . 100
Configuration Bits ............................................................... 54
Configuring the Voltage Reference..................................... 41
Crystal Operation................................................................ 55
Customer Change Notification Service............................. 125
Cus tomer Notif i c a tio n  Se r v ice ....... ........ ............... ............ 125
Customer Support............................................................. 125
D
Data EEPROM Memory
Asso c i a te d  R e g i st e r s/Bits........ .. ..................... ............ 52
Code Protection. .. .... .. .... ................. .... .. . .. .. .... .... .. .... .. . 52
EEADR Register......................................................... 49
EECO N 1  R egister ................. .............. ..................... .. 49
EECO N 2  R egister ................. .............. ..................... .. 49
EEDATA Register....................................................... 49
Data Memory Organization................................................... 7
DC Characteristi cs
Extended and Industrial................ .... .... . .. .... .... .... .... ... 91
Industrial..................................................................... 86
Debugger............................................................................ 69
Development Support......................................................... 79
Device Differences............................................................ 119
Device Migrations............................................................. 120
Device Overview................................................................... 5
E
EEPROM Data Memory
Reading...................................................................... 51
Spu ri o u s W r ite................ ............... ..................... ........ 51
Write Verify................................................................. 51
Writing ........................................................................ 51
Electrical Specifications...................................................... 83
Errata.................................................................................... 3
F
Firmware Instructions......................................................... 71
G
General Purpose Register File ............................................. 7
I
ID Locations........................................................................ 69
In-Circuit Serial Programming............................................. 69
Indirect Addressing,  INDF and FSR Registers........ .... .. .. ... 18
Instruction Format............................................................... 71
Instruction Set..................................................................... 71
ADDLW....................................................................... 73
ADDWF ...................................................................... 73
ANDLW....................................................................... 73
ANDWF ...................................................................... 73
BCF ............................................................................ 73
BSF............................................................................. 73
BTFSC........................................................................ 73
BTFSS........................................................................ 73
CALL........................................................................... 74
CLRF.......................................................................... 74
CLRW......................................................................... 74
CLRWDT.................................................................... 74
COMF......................................................................... 74
DECF.......................................................................... 74
DECFSZ..................................................................... 75
GOTO......................................................................... 75
INCF........................................................................... 75

PIC16F630/676
DS40039E-page 122 © 2007 Microchip Technology Inc.
INCFSZ.......................................................................75
IORLW ........................................................................75
IORWF........................................................................75
MOVF..........................................................................76
MOVLW ......................................................................76
MOVWF ......................................................................76
NOP............................................................................76
RETFIE .......................................................................76
RETLW .......................................................................76
RETURN.....................................................................77
RLF.............................................................................77
RRF.............................................................................77
SLEEP ........................................................................77
SUBLW .......................................................................77
SUBWF.......................................................................77
SWAPF .......................................................................78
XORLW.......................................................................78
XORWF.......................................................................78
Summary Table...... ............... ............... ........ ...............72
Internal 4 MHz Oscillator.....................................................56
Internal Sampling Switch (Rss) Impedance.... .... .. .. .. .... ......47
Inte r n e t Ad d r e s s..... .. ............... .............. ..................... .......125
Interrupts.............................................................................63
A/D C onverter.... .. ............... ..................... ............... ....65
Comparator.................................................................65
Context Saving ............................................................66
PORTA........................................................................65
RA2/INT......................................................................65
Summary of Reg isters ...... ..................... .....................66
TMR0 ..........................................................................65
M
MCLR..................................................................................58
Memory Organization
Dat a E EPROM Memory........ ..................... ............... ..4 9
Mic rochip Internet  Web  Site......................... .............. .......125
Migr a tin g  fr o m  o th e r  PI Cmicro De v i c es ..... .............. .........120
MPLAB ASM30 Assembler, Linker, Librarian .....................80
MPLAB ICD 2 In-Circuit Debugger......................................81
MPLAB ICE 2000 High-Performance Universal
 In-Cir cuit Emu la to r........ ......... ..................... .............. .........81
MPLAB ICE 4000 High-Performance Universal
 In-Cir cuit Emu la to r........ ......... ..................... .............. .........81
MPLAB Integrated Development Environment Software ....79
MPLAB PM3 Device Programmer.......................................81
MPLI N K O b je c t Li n ke r / M P L IB Object Lib r a r ia n ... ........ .......80
O
OPC OD E Fie ld Descr ip tions... .. ........ ......... .............. ......... ..7 1
Oscillator Configurations.....................................................55
Oscilla t o r  Sta r t- u p  Time r  ( OST) ........ ......... .. ........ ........ .......58
P
Packaging .........................................................................115
Details.......................................................................116
Marking.....................................................................115
PCL and PCLATH...................... .... .... .... ..................... ........17
Computed GOTO........................................................17
Stack...........................................................................17
PICSTART Plus Deve lopme n t Progra mm e r ......... ......... .....82
Pinout Descriptions
PIC16F630....................................................................6
PIC16F676....................................................................6
PORTA
Additional Pin Functions .............................................19
Interrupt-on-Change............................................20
Weak Pull-up.......................................................19
Asso c i a te d  R e g i st e r s............ ..................... .................25
Pin Descriptions and Diagrams .. .... .. .. .... .. .. ............... . 22
PORTA and TRISIO Registers......... .. .... .... .... .... ................ 19
PORTC............................................................................... 26
Asso c i a te d  R e g isters........ ..................... ..................... 27
Power Control/Status Register (PCON).............................. 59
Power-Down Mode (SLEEP). .. .. .... .. . .. .. .... .. .... .. .. ................ 68
Power-on Reset (POR)....................................................... 58
Power-up Timer (PWRT).................................................... 58
Prescaler............................................................................. 31
Switching Pres ca ler Assignment ...... ...... ...... ..... ...... ... 3 1
Program Memory Organization...... .. . .. .. .... .. .... .. .. ................. . 7
Programming, Device Instructions...................................... 71
R
RC Oscillator....................................................................... 56
Reader Response... .... ............... .... .. . .. .. .... .. .... .. .... ............ 126
READ-MODIFY-WRITE OPERATIONS............................. 71
Registers
ADCON0 (A/D Control)....... ............... ............... .......... 45
ADCON1..................................................................... 45
CMCON (Co mp a r a to r  Co n trol)........ ........ ................... 37
CONFIG (Con figur a ti o n  Word) ....... ...... ...... ............... . 54
EEADR (EEPROM Address)......................................49
EECO N 1  (EEPROM Control)...... ........ ............... ........50
EEDAT (EEPROM Data)............................................49
INTCON (Interrupt Control)......................................... 13
IOCA (Interrupt-on-Change PORTA).......................... 21
MapsPIC16F630 ........................................................... 8
PIC16F676 ........................................................... 8
OPTI O N _ R EG  ( O p tion ).... ......... .............. ......... .... 12, 30
OSCCAL (Oscillator Calibration) ................................ 16
PCON (Power Control)............................................... 16
PIE1 (Peripheral Interrupt Enable 1)......... .... .............. 14
PIR1 (Peripheral Interrupt 1)................... .... ................ 15
PORTC....................................................................... 27
STATUS ..................................................................... 11
T1CON  ( Timer1 Con tr o l)...... ......... ........ ............... ...... 34
TRISC......................................................................... 27
VRCON (Voltage Reference Control)........... .............. 42
WPU A ( W e a k Pu ll-up PO RTA).................... ............... 20
RESET................................................................................ 57
Revision History................................................................ 119
S
Soft wa r e  Simulat or ( M P L AB SIM) ..................... ............... ..80
Spe cial Featur e s o f th e  CP U................. .............. ............... 53
Special Function Registers................................................... 8
T
Time-out Sequence ............................................................ 59
Timer0................................................................................. 29
Asso c i a te d  R e g i st e r s...... ............... ..................... ........ 31
External Clock............................................................. 30
Interrupt ...................................................................... 29
Operation.................................................................... 29
T0CKI ......................................................................... 30
Timer1
Asso c i a te d  R e g i st e r s...... ............... ..................... ........ 35
Asynchronous Counter Mode......... .. .. .... .. .... .............. 35
Reading and Writing......... .. .... .... .. .... .... . .. .... .... ... 35
Interrupt ...................................................................... 33
Mod es  o f Op e ra tions........ ......... .............. ................... 33
Operation During SLEEP............................................ 35
Oscillator..................................................................... 35
Prescaler .................................................................... 33
Timer1 Module with Gate Control..................... .... . .... .... ..... 32
Timing Diagrams

© 2007 Microchip Technology Inc. DS40039E-page 123
PIC16F630/676
CLKOUT and I/O.. .... ...... .... .... .....................................96
External Clock.............................................................94
INT Pin Interrupt..........................................................65
PIC16F675 A/D Conversion (Normal Mode).............102
PIC16F675 A/D Conversion Timing (SLEEP Mode).103
RESET, Watchdog Timer, Oscillator Start-up 
Timer and Power-up Timer............... .... .... ..................97
Time-out Sequence on Power-up (MCLR not Tie d  to  
VDD)/Case 1 ................................................................62
Case 2 ................................................................62
Time-out Sequence on Power-up 
(MCLR Tied to VDD)....................................................62
Timer0 and Timer1 External Clock .............................99
Timer1 Incrementing Edge..........................................33
Timin g  Paramete r  Symbolog y....... ......... .............. ...............93
TRISIO Registers..... ......... ..................... ..................... ........19
V
Voltage Reference Accuracy/Error .....................................41
W
Watchdog Timer
Summary of Reg isters........ .. ..................... .................67
Watchdog Timer (WDT)......................................................66
WWW Address..................................................................125
WWW, On-Line Support ..................... .... .... .... .... ..................3

PIC16F630/676

NOTES:

PIC16F630/676

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchip.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

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Technical suppo rt is avail able throug h the we b site

at: http://support.microchip.com

PIC16F630/676

READER RESPONSE

It is ou r intention to provide you w it h th e b es t do cumentation poss ib le to ensure suc c es sfu l u se of y ou r M ic roc hip prod-

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DS40039EPIC16F630/676

1. What are the be st features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

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7. How would you improve this document?

PIC16F630/676

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or deliv ery, refer to the factory or the listed sales office.

* JW Devices are UV er asable and can be pro grammed to any device conf iguration. JW Devices meet the electr ical requirement of

each oscillator type.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: : Standard VDD range

T: (Tape and Reel)

Temperature Range: I= -40°C to +85 °C

E= -40°C to +125 °C

Package: P=PDIP

SN = SOIC (Gull wing, 3.90 mm body)

ST = TSSOP(4.4 mm)

Pattern: 3-Digit Pattern Code for QTP (blank otherwise)

Examples:

a) PIC16F630 – E/P 301 = Extended T emp., PDIP

package, 20 MHz, QTP patter n #301

b) PIC16F676 – I/SO = Industrial Temp., SOIC

package, 20 MHz

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12/08/06