1
FEATURES
APPLICATIONS
GNDDIG
VCCDIG
CHIP_EN
VCCMIX
NC
NC
NC
NC
NC
MIXinp
MIXinn
VCCMIX
1
2
3
4
5
6
7
8
9
10
11
12 25
26
27
28
29
30
31
32
33
34
35
36 VCCBBI
AGND
BBIoutp
BBIoutn
LOip
LOin
NC
BBQoutp
BBQoutn
AGND
VCCBBQ
VCCLO
13 14 15 16 17 18 19 20 21 22 23 24
373839
40
4142
43
44
45
46
47
48
NC
NC
NC
MIXQoutn
NC
NC
REXT
VCCBIAS
GNDBIAS
VOFFQ
VCMQ
CLOCK
DATA
STROBE
MIXIoutp
MIXIoutn
NC
NC
Gain_B0
Gain_B1
Gain_B2
VOFFI
VCMI
ToMicrocontroller ToMicrocontroller
TRF3710
RFin
30kW
To ADCI
To ADCQ
LOin
MIXQoutp
DESCRIPTION
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008www.ti.com
IQ DEMODULATOR
2
•Frequency Range: 1.7 GHz to 2 GHz•Integrated Baseband Programmable-GainAmplifier
•On-Chip Programmable Baseband Filter•High Cascaded IP3: 21 dBm at 1.9 GHz•High IP2: 60 dBm at 1.9 GHz•Hardware and Software Power Down•3-Wire Serial Programmable Interface•Single Supply: 4.5-V to 5.5-V Operation
•Wireless Infrastructure:
– WCDMA
– CDMA•Wireless Local Loop•High-Linearity Direct DownconversionReceiver
The TRF3710 is a highly linear and integrated direct-conversion quadrature demodulator optimized forthird-generation (3G) wireless infrastructure. The TRF3710 integrates balanced I and Q mixers, LO buffers, andphase splitters to convert an RF signal directly to I and Q baseband. The on-chip programmable-gain amplifiersallow adjustment of the output signal level without the need for external variable-gain (attenuator) devices. TheTRF3710 integrates programmable baseband low-pass filters that attenuate nearby interference, eliminating theneed for an external baseband filter.
Housed in a 7-mm ×7-mm QFN package, the TRF3710 provides the smallest and most integrated receiversolution available for high-performance equipment.
AVAILABLE DEVICE OPTIONS
(1)
SPECIFIEDPACKAGE PACKAGE PACKAGE ORDERING TRANSPORT MEDIA,PRODUCT TEMPERATURELEAD DESIGNATOR MARKINGS NUMBER QUANTITYRANGE
TRF3710IRGZR Tape and reel, 2500TRF3710 QFN-48 RGZ – 40 °C to 85 °C TRF3710
TRF3710IRGZT Tape and reel, 500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
Decouplingrequired
VCCDIG2
VCCMIX4and9
VCCBIAS21
VCCBBQ25
VCCBBI36
VCCLO29
VCCs
Gnds
GNDDIG1
GNDBIAS22
AGND26
AGND35
Power
Down
CE 3
6
41
31
30
7
MIXinp
Gain_B0
LOip
LOin
MIXinn
40
39
Gain_B1
Gain_B2
90°
0°
DCOffsetCancel
DCOffsetCancel
PGA
PGA
OutBuffer
OutBuffer
PGA
Fast
Gain
Control
BBIoutn
DATA
STROBE
BBQoutn
BBIoutp
VOFFI
VCMQ
VCMI
VOFFQ
BBQoutp
33
47
46
27
34
38
24
37
23
28
SPI
CLOCK
48
GNDDIG
VCCDIG
CHIP_EN
VCCMIX
NC
NC
NC
NC
NC
MIXinp
MIXinn
VCCMIX
1
2
3
4
5
6
7
8
9
10
11
12 25
26
27
28
29
30
31
32
33
34
35
36 VCCBBI
AGND
BBIoutp
BBIoutn
LOip
LOin
NC
BBQoutp
BBQoutn
AGND
VCCBBQ
VCCLO
13 14 15 16 17 18 19 20 21 22 23 24
373839
40
4142
43
44
45
46
47
48
NC
NC
NC
MIXQoutp
MIXQoutn
NC
NC
REXT
VCCBIAS
GNDBIAS
VOFFQ
VCMQ
CLOCK
DATA
STROBE
MIXIoutp
MIXIoutn
NC
NC
Gain_B0
Gain_B1
Gain_B2
VOFFI
VCMI
RGZPackage
(TopView)
TRF3710
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
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THERMAL CHARACTERISTICS
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
AGND 26, 35 Analog ground; grounds can be tied together.BBIoutn 33 O Baseband I output: negative terminalBBIoutp 34 O Baseband I output: positive terminalBBQoutn 27 O Baseband Q output: negative terminalBBQoutp 28 O Baseband Q output: positive terminalCHIP_EN 3 I Chip enable; enabled = logic level 1, disabled = logic level 0CLOCK 48 I SPI clock inputSPI data input (programming data for baseband filter frequency setting, PGA gain settings, and dcDATA 47 I
offset calibration).Gain_B0 41 I PGA fast-gain control bit 0Gain_B1 40 I PGA fast-gain control bit 1Gain_B2 39 I PGA fast-gain control bit 2GNDBIAS 22 Bias-block ground. Grounds can be tied together.GNDDIG 1 Digital ground. Grounds can be tied together.LOin 30 I Local oscillator input: negative terminalLOip 31 I Local oscillator input: positive terminalMixer input: negative terminal, connected to external balanced-to-unbalanced (balun) transformer;MIXinn 7 I
balun type is frequency-specific.MIXIoutn 44 O Mixer I output: negative terminal (test pin). NC for normal operationMIXIoutp 45 O Mixer I output: positive terminal (test pin). NC for normal operationMIXinp 6 I Mixer input: positive terminal, connected to external balun; balun type is frequency-specific.MIXQoutn 17 O Mixer Q output: negative terminal (test pin). NC for normal operationMIXQoutp 16 O Mixer Q output: positive terminal (test pin). NC for normal operationREXT 20 O Reference-bias external resistor: 30 k Ω; used to set the bias of internal circuits of chipSTROBE 46 I SPI enable (latches data into SPI after final clock pulse. Logic level = 1.VCCBBQ 25 Baseband Q-chain power supply, 4.5 V to 5.5 V. Decoupled from other sourcesVCCBIAS 21 Bias-block power supply, 4.5 V to 5.5 V. Decoupled from other sourcesVCCDIG 2 Digital power supply, 4.5 V to 5.5 V. Decoupled from other sourcesVCCLO 29 Local oscillator power supply, 4.5 V to 5.5 V. Decoupled from other sourcesVCCMIX 4, 9 Mixer power supply, 4.5 V to 5.5 V. Decoupled from other sourcesVCMQ 24 I Baseband Q-chain input common mode, nominally 1.5 VVOFFQ 23 I Q-chain analog-offset correction input, 0 V to 3 V.VCCBBI 36 Baseband I power supply, 4.5 V to 5.5 V. Decoupled from other sourcesVCMI 37 I Baseband I chain input common mode, nominally 1.5 VVOFFI 38 I I-chain analog-offset correction input, 0 V to 3 V
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
(1)
TEST CONDITIONS MIN TYP MAX UNIT
Soldered slug, no airflow 26R
θJA
Soldered slug, 200-LFM (1,016 m/s) airflow 20.1Thermal derating, junction-to-ambient °C/WSoldered slug, 400-LFM (2,032 m/s) airflow 17.4R
θJA
(2)
7-mm ×7-mm, 48-pin PDFP 25R
θJB
Thermal derating, junction-to-board 7-mm ×7-mm, 48-pin PDFP 12 °C/W
(1) Determined using JEDEC standard JESD-51 with high-K board(2) 16 layers, high-K board
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
Over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
Supply voltage range
(2)
– 0.3 to 5.5 VDigital I/O voltage range – 0.3 to V
CC
+ 0.5 VT
J
Operating virtual junction temperature range – 40 to 150 °CT
A
Operating ambient temperature range – 40 to 85 °CT
stg
Storage temperature range – 65 to 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.
Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
CC
Power supply voltage 4.5 5 5.5 VPower supply voltage ripple 940 µV
pp
T
A
Operating ambient temperature range – 40 85 °CT
J
Operating virtual junction temperature range – 40 150 °C
Power supply = 5 V, LO = 0 dBm at 25 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
DC PARAMETERS
I
CC
Total supply current 360 mAPower-down current 5 mA
IQ DEMODULATOR AND BASEBAND SECTION
f
RF
Frequency range 1700 2000 MHzG
minBB
Minimum gain 20 dBG
maxBB
Maximum gain 43 45 dBGain range 22 24 dBGain step 1
(2)
dBNF
BB
Noise figure Gain setting = 15 13.5 14.5 dBIIP3
BB
Third-order input intercept Gain setting = 15
(3) (4)
21
dBmpointOIP3
BB
Output third intercept point Gain setting = 15; two tones, 1 V
PP
each
(5)
32 dBVrmsOIP1
BB
Output compression point One tone
(6)
3 dBVrmsIIP2
BB
Second-order input intercept Gain setting = 15
(7)
60
dBmpoint
Baseband low-pass filter cutofff
LPF
1-dB point
(8)
0.615 1.92 MHzfrequency
(1) Balun used for measurements: Band 1: 1700-MHz balun = Murata LDB211G8005C-001; Band 2: 1800- to 1900-MHz balun = MurataLDB211G9005C-001
(2) Between two consecutive gain settings(3) Two CW tones of – 30 dBm at ± 900-kHz and ± 1.7-MHz offset (baseband filter 1-dB cutoff frequency of minimum LPF).(4) Two CW tones of – 30 dBm at ± 2.7-MHz and ± 5.9-MHz offset (baseband filter 1-dB cutoff frequency of maximum LPF).(5) Two CW tones at an offset from LO frequency smaller than the baseband filter cutoff frequency.(6) Single CW tone at an offset from LO smaller than the baseband filter cutoff frequency.(7) Two tones at f
RF1
= f
LO
± 900 kHz and f
RF2
= f
LO
± 1 MHz; IM
2
product measured at 100-kHz output frequency (for minimum basebandfilter 1-dB cutoff frequency). The two tones are at f
RF1
= f
LO
± 2.7 MHz and f
RF2
= f
LO
± 2.8 MHz, and the IM
2
product measured at100-kHz output frequency (for maximum baseband filter 1-dB cutoff frequency).(8) Baseband low-pass filter 1-dB cutoff frequency is programmable through SPI between minimum and maximum values.
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TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS (continued)Power supply = 5 V, LO = 0 dBm at 25 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
615 kHz 1900 kHz 10Baseband relative attenuationat minimum LPF cutoff 1.7 MHz 50 dBfrequency
(9)
5 MHz 6020 MHz 1001.92 MHz 1Baseband relative attenuation
2.7 MHz 10at maximum LPF cutoff dB5 MHz 50frequency
(9)
20 MHz 100Baseband filter phase linearity RMS phase deviation from linear phase
(10)
1.8 DegreesBaseband filter amplitude
See
(10)
0.5 dBripple
Sideband suppression 35 dBOutput load impedance Parallel resistance 1 k Ω
Parallel capacitance 20 pFV
CM
Output common mode Measured at I and Q channel baseband outputs 0.7 1.5 4 V
LOCAL OSCILLATOR PARAMETERS
Local oscillator frequency 1700 2000 MHzLO input level 0 dBmLO leakage At MIXinn/p – 58 dBm
DIGITAL INTERFACE
V
IH
High-level input voltage 2 5 V
CC
VV
IL
Low-level input voltage 0 0.8 VV
OH
High-level output voltage 0.8 V
CC
VV
OL
Low-level output voltage 0.2 V
CC
V
(9) Attenuation relative to passband gain(10) Across-filter passband: 615 kHz (minimum baseband filter cutoff frequency) and 1.92 MHz (maximum baseband filter cutoff frequency).
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TIMING REQUIREMENTS
DB1
AddressBit2
DB2
CmdBit3
DB3
CmdBit4
DB29
CmdBit30
DB30
CmdBit31
DB31(MSB)
CmdBit32
DB0(LSB)
AddressBit1
CLOCK
DATA
STROBE
FirstClockPulse
tsu1
tsu2
th
tw
t(CLK)
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
Power supply = 5 V, LO = 0 dBm at 25 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
(CLK)
Clock period 50 nst
su1
Setup time, data 10 nst
h
Hold time, data 10 nst
w
Pulse width, STROBE 20 nst
su2
Setup time, STROBE 10 ns
Figure 1. Serial Programming Timing
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TYPICAL CHARACTERISTICS
41.5
42
42.5
43
43.5
44
1820 1840
1860 1880 1900
1940 1960 1980
2000
Gain – dB
85°C
–40°C
f – Frequency – MHz
25°C
CDMA
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
0 2 4
6
8 10 12 14 16 18 24
GainState
Gain – dB
25°C
85°C
–40°C
CDMA
20 22
10
12
14
16
18
20
22
24
26
28
30
1690
1700 1710
1720
1730
1740
1750 1760
1770
1780
1790
IIP – dBm
3
f – Frequency – MHz
CDMA
–40°C
85°C 25°C
10
12
14
16
18
20
22
24
26
28
30
1690 1700 1710 1720 1730 1740 1750 1760 1770 1780 1790
IIP – dBm
3
85°C
25°C
–40°C
f – Frequency – MHz
WCDMA
10
12
14
16
18
20
22
24
26
28
30
1820 1840 1860 1880 1900 1920 1940 1960 1980
2000
f – Frequency – MHz
IIP – dBm
3
–40°C
25°C
85°C
WCDMA
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
V
CC
= 5 V, T
A
= 25 °C, 1950 MHz, gain setting = 24 (unless otherwise stated).(CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7)
GAIN vs FREQUENCY GAIN vs GAIN STATE
Figure 2. Figure 3.
IIP
3
vs FREQUENCY IIP
3
vs FREQUENCY
Figure 4. Figure 5.
IIP
3
vs FREQUENCY IIP
3
vs FREQUENCY
Figure 6. Figure 7.
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50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
1820 1840
1860 1880
1900 1920
1940 1960
1980
2000
IIP – dBm
2
4.5V
5V
5.5V
f – Frequency – MHz
WCDMA
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
1690 1700 1710 1720 1730 1740 1750 1760 1770 1780
1790
IIP – dBm
2
25°C
–40°C
85°C
f – Frequency – MHz
WCDMA
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
1690
1700 1710 1720
1730
1740 1750 1760 1770
1780
1790
IIP – dBm
2
85°C
25°C
–40°C
f – Frequency – MHz
WCDMA
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
1820
1840
1860
1880
1900
1920
1940
1960
1980
2000
f – Frequency – MHz
IIP – dBm
2
–40°C
25°C
85°C
WCDMA
20
22
24
26
28
30
32
34
36
38
40
1820
1840 1860 1880 1900 1920 1940 1960 1980
2000
OIP – dBVrms
3
f – Frequency – MHz
–40°C
85°C
25°C
CDMA
20
22
24
26
28
30
32
34
36
38
40
1820
1840 1860 1880 1900
1920
1940 1960
1980
2000
f – Frequency – MHz
OIP – dBVrms
3
–40°C
85°C
25°C
WCDMA
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)V
CC
= 5 V, T
A
= 25 °C, 1950 MHz, gain setting = 24 (unless otherwise stated).(CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7)
IIP
2
vs FREQUENCY IIP
2
vs FREQUENCY
Figure 8. Figure 9.
IIP
2
vs FREQUENCY IIP
2
vs FREQUENCY
Figure 10. Figure 11.
OIP
3
vs FREQUENCY OIP
3
vs FREQUENCY
Figure 12. Figure 13.
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20
22
24
26
28
30
32
34
36
38
40
0 5 10 15 20 25 30
GainState
OIP – dBVrms
3
–40°C
85°C
25°C
WCDMA
20
22
24
26
28
30
32
34
36
38
40
0 5 10 15 20 25 30
GainState
OIP – dBVrms
3
–40°C
85°C
25°C
CDMA
15
20
25
30
35
40
45
–6 –4 –2 0 2 4 6
LOPower – dBm
OIP – dBVrms
3
WCDMA
5
10
15
20
25
30
35
–6 –4 –2 0 2 4 6
LOPower – dBm
IIP – dBm
3
WCDMA
15
20
25
30
35
40
45
50
55
60
65
70
75
–6 –4
–2
0 2 4 6
LOPower – dBm
IIP – dBm
2
WCDMA
0 5 10 15 20 25
GainState
GainError – dB
1850MHz
–0.002
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)V
CC
= 5 V, T
A
= 25 °C, 1950 MHz, gain setting = 24 (unless otherwise stated).(CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7)
OIP
3
vs GAIN STATE OIP
3
vs GAIN STATE
Figure 14. Figure 15.
OIP
3
vs LO POWER IIP
3
vs LO POWER
Figure 16. Figure 17.
IIP
2
vs LO POWER GAIN ERROR vs GAIN STATE
Figure 18. Figure 19.
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–80
–60
–40
–20
0
20
40
60
0.01 0.1
1 10 100
BasebandFrequency – MHz
Gain – dB
FilterGainShape
25°C,(1.92MHz)
BBFilterSetting=7
FilterGainShape
25°C,(615KHz)
BBFilterSetting=90
41.6
41.7
41.8
41.9
42
42.1
42.2
42.3
42.4
42.5
42.6
0.01 0.1 1 10
BasebandFrequency-MHz
Gain – dB
FilterGainShape
25°C,(1.92MHz)
BBFilterSetting=7
FilterGainShape
25°C,(615KHz)
BBFilterSetting=90
0 5 10 15 20 25
GainState
NoiseFigure – dB
CDMA Mode
1950MHz
25 C°
10
15
20
25
30
5V
4.5V
5.5V
0
0.5
1
1.5
2
2.5
3
0
16 32 48 64
80 96 112 128
BB – FrequencySetting
f– Frequency – MHz
1dB
5V
25°C
1950MHz
0 5 10 15 20 25
GainState
NoiseFigure – dB
CDMA Mode
1950MHz
5V
10
15
20
25
30
25 C°
–40 C°
85 C°
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS (continued)V
CC
= 5 V, T
A
= 25 °C, 1950 MHz, gain setting = 24 (unless otherwise stated).(CDMA = BBFREQ = 90, WCDMA = BBFREQ = 7)
GAIN vs BASEBAND FREQUENCY GAIN vs BASEBAND FREQUENCY
Figure 20. Figure 21.
CORNER FREQUENCY vs BB – FREQUENCY SETTING INTEGRATED NF vs GAIN STATE
Figure 22. Figure 23.
INTEGRATED NF vs GAIN STATE
Figure 24.
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TYPICAL CHARACTERISTICS
HISTOGRAM PLOTS
0
20
40
60
80
IIP3 – dBm
Distribution – %
CDMA
18.5
19
19.5
20
20.5
21
21.5
22
22.5
23
0
10
20
30
40
50
60
42.6 42.8 43 43.2 43.4 43.6 43.8
Gain – dB
Distribution – %
0
5
10
15
20
25
30
35
OIP – dBVrms
3
Distribution – %
CDMA
WCDMA
29 30 31 32 33 34 35 36
0
10
20
30
40
IIP – dBm
2
Distribution – %
CDMA
WCDMA
54 58 62 66 70 74 78 82
0
10
20
30
40
50
60
70
12.75 13 13.25 13.75 14 14.25
NF – dB
Distribution – %
13.5
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
CONVERSION GAIN DISTRIBUTION IIP
3
DISTRIBUTION
Figure 25. Figure 26.
IIP
2
DISTRIBUTION OIP
3
DISTRIBUTION
Figure 27. Figure 28.
NF DISTRIBUTION
Figure 29.
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SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION
DB1
AddressBit2
DB2
CmdBit3
DB3
CmdBit4
DB29
CmdBit30
DB30
CmdBit31
DB31(MSB)
CmdBit32
DB0(LSB)
AddressBit1
CLOCK
DATA
STROBE
FirstClockPulse
tsu1
tsu2
th
tw
t(CLK)
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
The TRF3710 features a 3-wire serial programming interface (SPI) that controls an internal 32-bit shift register.There are a total of three signals that must be applied: CLOCK (pin 48), serial DATA (pin 47), and STROBE (pin46). DATA (DB0 – DB31) is loaded LSB-first and is read on the rising edge of the CLOCK. STROBE isasynchronous to CLOCK, and at its rising edge, the data in the shift register are loaded onto the selected internalregister. The first two bits (DB0 – DB1) are the address to select the available internal registers. Figure 30 showsthe serial interface timing for the TRF3710.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
(CLK)
Clock period 50 nst
su1
Setup time, data 10 nst
h
Hold time, data 10 nst
w
Pulse width, STROBE 20 nst
su2
Setup time, STROBE 10 ns
Figure 30. Serial Interface Timing
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Register 0
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
PWD BBPWD PWD PWDPWD PWD PWD Ana FreqRegister Address Test Output RSVD Dig Cal Baseband Gain SettingMixer LO Buff Filter Cal CutoffBuff Buff Block
Block Set
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15
DC Detector CalBaseband Freq Cutoff Settings Cont. RSVD RSVD Spare SpareBandwidth Reset
Bit16 Bit17 Bit18 Bit19 Bit20 Bit21 Bit22 Bit23 Bit24 Bit25 Bit26 Bit27 Bit28 Bit29 Bit30 Bit31
Figure 31. Register 0 Map
Table 1. Register 0: Device Setup
RESETREGISTER 0 NAME WORKING DESCRIPTIONVALUE
Bit0 ADDR_0 0
Address bitsBit1 ADDR_1 0Bit2 PWD_MIX 0 Mixer power down (off = 1)Bit3 PWD_LO 0 LO buffer power down (off = 1)Bit4 PWD_BUF1 1 Test buffer power down (off = 1)Bit5 PWD_FILT 0 Baseband filter power down (off = 1)Bit6 PWD_BUF2 0 Output buffer power down (off = 1)Bit7 Reserved 0Bit8 PWD_DC_OFF_DIG 1 Digital calibration blocks power down (off = 1)Bit9 PWD_DC_OFF_ANA 1 Analog calibration blocks power down (off = 1)Bit10 BBGAIN_0 1
Sets baseband gain: the default power-on BBGAIN setting = 15 (corresponding to atypical gain of 34 dB). There are 25 gain settings (0 to 24) in 1-dB increments. For aBit11 BBGAIN_1 1
desired device gain, the BBGAIN setting is determined by the following equation:Bit12 BBGAIN_2 1
BBGAIN setting = 24 – [(typical device gain at BBGAIN = 24) – (desired deviceBit13 BBGAIN_3 1
gain)]. For example, for a desired device gain of 27 dB, the BBGAIN setting wouldbe 24 – (43 – 27) = 8, which is bits 14 – 10 <0 1000>.Bit14 BBGAIN_4 0Bit15 BBFREQ_0 1Bit16 BBFREQ_1 0
Sets BB frequency cutoff; default = 85. Example: For CDMA, the corner frequency isBit17 BBFREQ_2 1
615 kHz. See the 1-dB corner frequency vs. frequency setting plot Figure 22 toBit18 BBFREQ_3 0
determine the setting, which is 90. Then set bit 15 through bit 21 to <101 1010>,Bit19 BBFREQ_4 1
which corresponds to 90.Bit20 BBFREQ_5 0Bit21 BBFREQ_6 1Bit22 Reserved 1Bit23 Reserved 0Bit24 EN_FLT_B0 0
DC detector bandwidthBit25 EN_FLT_B1 0Bit26 Reserved 0Bit27 Internal use only 0Bit28 Internal use only 0Bit29 CAL_RESET 0 Reset the internal calibration logic when = 1.Bit30 Spare0 0Bit31 Spare1 0
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TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
•Baseband PGA gain: BBGAIN_[4:0] (B[14:10]) sets the gain of the baseband programmable gain amplifier.The acceptable values are from <0 0000> to <1 1000>. (See the Gain Control section for more information.)•Baseband filter cutoff frequency: BBFREQ_[6:0] (B[21:15]) controls the baseband 1-dB cutoff frequency.An all-0s word sets the filter to its maximum cutoff frequency, whereas an all-1s word corresponds tominimum filter bandwidth.•EN_FLT_B[0:1]: These bits control the bandwidth of the detector used to measure the dc offset during theautomatic calibration. There is an RC filter in front of the detector that can be fully bypassed. EN_FLT_B0controls the resistor (bypass = 1), while EN_FLT_B1 controls the capacitor (bypass = 1). The typical 3-dBcutoff frequencies of the detector bandwidth are summarized in Table 2 (see the Application Informationsection for more detail on the dc offset calibration and the detector bandwidth).
Table 2. Typical Cutoff Frequencies
Typical 3-dB CutoffEN_FLT_B1 EN_FLT_B0 NotesFrequency
X 0 10 MHz Maximum bandwidth; bypass R, C0 1 10 kHz Enable R1 1 1 kHz Minimum bandwidth; enable R, C
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Register 1
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
EnableRegister Address Autocal DAC Bits to Be Set During Manual Cal I/QAutocal
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15
DC Offset Digital DC Offset Digital
Bin Division Ratio for Clock Cal ClkDAC Bits CONT Cal. Resolution Cal. Resolution Internal Osc Freq TrimmingSearch Divider Selectfor I Channel for Q Channel
Bit16 Bit17 Bit18 Bit19 Bit20 Bit21 Bit22 Bit23 Bit24 Bit25 Bit26 Bit27 Bit28 Bit29 Bit30 Bit31
Figure 32. Register 1 Map
Table 3. Register 1: Device Setup
RESETREGISTER 1 NAME WORKING DESCRIPTIONVALUE
Bit0 ADDR_0 1
Address bitsBit1 ADDR_1 0Bit2 AUTO_CAL 1 Auto dc offset correction when = 1; otherwise manualBit3 EN_AUTOCAL 0 Autocalibration begins when bit = 1. This bit is reset after calibration completes.Bit4 IDAC_BIT0 0Bit5 IDAC_BIT1 0Bit6 IDAC_BIT2 0Bit7 IDAC_BIT3 0Bit8 IDAC_BIT4 0Bit9 IDAC_BIT5 0Bit10 IDAC_BIT6 0Bit11 IDAC_BIT7 1
DAC bits to be set during manual cal I/QBit12 QDAC_BIT0 0Bit13 QDAC_BIT1 0Bit14 QDAC_BIT2 0Bit15 QDAC_BIT3 0Bit16 QDAC_BIT4 0Bit17 QDAC_BIT5 0Bit18 QDAC_BIT6 0Bit19 QDAC_BIT7 1Bit20 IDET_B0 1
Set the dc offset digital calibration resolution for I channel.Bit21 IDET_B1 1Bit22 QDET_B0 1
Set the dc offset digital calibration resolution for Q channel.Bit23 QDET_B1 1Bit24 Bin Search 1 Set to 1 for autocalibration; set to 0 for manual control.Bit25 CLK_DIV_RATIO0 0
DC offset autocalibration clock divider:Bit26 CLK_DIV_RATIO1 0
division ratios = 1, 8, 16, 128, 256, 1024, 2048, 16,684Bit27 CLK_DIV_RATIO2 0Bit28 CAL_CLK_SEL 1 Select internal oscillator when 1; select SPI clock when 0.Bit29 OSC_TRIM0 1
Internal oscillator frequency trimmingBit30 OSC_TRIM1 1 000 →300 kHz111 →1.8 MHzBit31 OSC_TRIM2 0
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TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
•AUTO_CAL (Bit2): When 1, the dc offset autocalibration is selected.•EN_AUTOCAL (Bit3): Setting this bit to 1 starts the dc offset autocalibration. At the end of the calibration, thebit is reset to 0 (see the Application Information section for more details on dc offset correction).•IDET_B[1:0], QDET_B[1:0]: These bits control the maximum output dc voltage of the dc-offset correctionDAC (I and Q channels).•CLK_DIV_RATIO[2:0]: Frequency divider for the calibration clock. The incoming clock (either the serialinterface clock or the internal oscillator) divided by the divider ratio set by bits 25 – 27, generates the referenceclock used during the autocalibration.•CAL_CLK_SEL:Selects the internal oscillator or the external SPI clock as calibration clock•OSC_TRIM[2:0]: Bits 29 – 31 control the internal oscillator frequency.
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APPLICATION INFORMATION
GAIN CONTROL
Register0,Bits0–4 BBgain[0:4]
Fgain[0:2]
+
FromSPI ToPGA
FromExternalPins
AUTOMATED DC OFFSET CALIBRATION
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
The TRF3710 integrates a baseband programmable-gain amplifier (PGA) that provides 24 dB of gain range with1-dB steps. The PGA gain is controlled through SPI by a 5-bit word (register 0, bits 10 – 14). Alternatively, thePGA can be programmed by a combination of 5 bits programmed through the SPI and three parallel external bits(pins Gain_B2, Gain_B1, Gain_B0). The parallel bits allow a fast gain change (0 db to 7 dB by 1-dB steps)without the need to reprogram the SPI registers.
The PGA gain control word ( BBGAIN[0:4]) can be programmed to a setting between 0 and 24. This word is thesum of the SPI programmed gain (register 0, bits 10 – 14) and the parallel external 3 bits as shown in Figure 33 .Setting the PGA gain setting above 24 is not valid. Typical applications set the PGA gain to 15, which allowsroom to adjust the PGA gain up or down to maintain desired output signal to the analog-to-digital converter overall conditions.
Figure 33. PGA Gain Control Word
For example, if a PGA gain setting of 20 dB is desired, then the SPI can be programmed directly to 20.Alternatively, the SPI gain register can be programmed to 15 and the parallel external bits set to 101 (binary),corresponding to an additional 5 dB.
The TRF3710 provides an automatic calibration procedure for adjusting the dc offset in the baseband I/Q paths.The digital dc offset correction is engaged by setting the PWD_DC_OFF_DIG (register 0, bit 8) to 0 and thePWD_DC_OFF_ANA (register 0, bit 9) to 1. The internal calibration requires a clock in order to function.TRF3710 can use the internal relaxation oscillator or the external SPI clock. Using the internal oscillator is thepreferred method. Selecte the internal oscillator by setting the Cal_Sel_Clk (register 1, bit 28) to 1. The internaloscillator frequency is set through the OSC_TRIM bits (register 1, bits 29 – 31). The frequency of the oscillator isdetailed in Table 4 .
Table 4. Internal Oscillator Frequency Control
OSC_TRIM2 OSC_TRIM1 OSC_TRIM0 Frequency
0 0 0 300 kHz0 0 1 500 kHz0 1 0 700 kHz0 1 1 900 kHz1 0 0 1.1 MHz1 0 1 1.3 MHz1 1 0 1.5 MHz1 1 1 1.8 MHz
The default setting of these registers corresponds to 900-kHz oscillator frequency; this setting is sufficient forautocalibration and does not need to be modified.
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tc+(Auto_Cal_Clk_Cycles) (Clk_Divider)
Osc_Freq
(1)
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
The internal dc offset correction DACs output full scale range is programmable ( IDET_B[0:1] and QDET_B[0:1],register 1, bits 20 – 23). The range is shown in Table 5 .
Table 5. DC Offset Correction DAC Programmable
Range
I(Q)DET_B1 I(Q)DET_B0 Full Scale
0 0 10 mV0 1 20 mV1 0 30 mV1 1 40 mV
The maximum dc offset correction range can be calculating by multiplying the values in Table 5 by the basebandPGA gain. The LSB of the digital correction depends on the programmed maximum correction range. Foroptimum resolution and best correction, the dc offset DAC range should be set to 10 mV for both the I and Qchannels with the PGA gain set for the nominal condition. The output of the dc-offset-correction DAC is affectedby a change in the PGA gain, but if the initial calibration yields optimum results, then the adjustment of the PGAgain during normal operation does not significantly impair the dc offset balance. For example, if the optimizedcalibration yields a dc offset balance of 2 mV at a gain setting of 17, then the dc offset maintains less than 10-mVbalance as the gain is adjusted ± 7 dB.
The dc offset correction DACs are programmed from the internal registers when the AUTO_CAL bit (register 1,bit 2) is set to 1. At start-up, the internal registers are loaded at half-scale, corresponding to a decimal value of128. When an autocalibration is desired, verify that the Bin_Search bit (register 1, bit 24) is set to 1. Initiate theautocalibration process by toggling the EN_AUTOCAL bit (register 1, bit 3) to 1. When the calibration is over, thisbit is automatically reset to 0. During calibration, the RF local oscillator must be applied.
At each clock cycle during an autocalibration sequence, the internal circuitry senses the output dc offset andcalculates the new dc current for the DAC. After the ninth clock cycle, the calibration is complete and theAUTO_CAL bit is reset to 0. The dc offset DAC state is stored in the internal registers and maintained as long asthe power supply is kept on, or until the Cal Reset (register 1, bit 29) is toggled to 1 or a new calibration isstarted.
The required clock speed for the optimum calibration is determined by the internal detector behavior (integrationbandwidth, gain, sensitivity). The input bandwidth of the detector can be adjusted by changing the cutofffrequency of the RC low-pass filter in front of the detector (register 0, bits 24 – 25), corresponding to 3-dBcorner-frequency steps of 10 MHz, 10 kHz, and 1 kHz. The speed of the clock can be slowed down byselecting a clock divider ratio (register 1, bits 25 – 27).
The detector has more averaging time the slower the clock; therefore, it can be desirable to slow down the clockspeed for a given condition to achieve optimum results. For example, if there is no RF present on the RF inputport, the detection filter can be left wide (10 MHz) and the clock divider can be left at div-by-1. Theautocalibration yields a dc offset balance between the differential baseband output ports (I and Q) that is lessthan 15 mV. Some minor improvement may be obtained by increasing the averaging of the detector byincreasing the clock divider up to 256.
However, if there is a modulated RF signal present at the input port, it is desirable to reduce the detectorbandwidth to filter out most of the modulated signal. The detector bandwidth can be set to a 1-kHz cornerfrequency. With the modulated signal present, and with the detection bandwidth reduced, additional averaging isrequired to get optimum results. A clock divider setting of 1024 yields optimum results.
An increase in the averaging is possible by increasing the clock divider at the expense of longer converging time.The convergence time can be calculated by the following:
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tc+(9) (1024)
900 kHz +10.24 ms
(2)
ALTERNATE METHOD FOR ADJUSTING DC OFFSET
PCB LAYOUT GUIDELINES
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
With a clock divider of 1024 and with the nominal oscillator frequency of 900 kHz, the convergence time is:
The internal registers controlling the internal dc current DAC are accessible through the SPI, providing auser-programmable method for implementing the dc offset calibration. To employ this option, the Auto Cal bitmust be set to 0 and the Bin_Search set to 0. During this calibration, an external instrument monitors the outputdc offset between the I/Q differential outputs and programs the internal registers ( IDAC_BIT[0:7] andQDAC_BIT[0:7] bits, register 1, bits 4 – 19) to cancel the dc offset.
The TRF3710 also offers a third dc offset calibration option to control the output dc offset by an external voltage(0 – 3 V) injected at the VOFFI and VOFFQ pins. Set PWD_DC_OFF_DIG (register 0, bit 8) to 1 (Off) and setPWD_DC_OFF_ANA (register 0, bit 9) to 0 to engage the external analog voltage control of the output dc offset.The analog voltage at the VOFFI and VOFFQ pins can be adjusted to provide the proper dc offset balance.
The TRF3710 device is designed with a ground slug on the back of the package that must be soldered to theprinted-circuit board (PCB) ground with adequate ground vias to ensure a good thermal and electricalconnection. The recommended via pattern and ground pad dimensions are shown in Figure 34 . Therecommended via diameter is 8 mils (0.203 mm). The ground pins of the device can be directly tied to the groundslug pad for a low-inductance path to ground. Additional ground vias may be added if space allows. The NC (noconnect) pins can also be tied to the ground plane.
Decoupling capacitors at each of the supply pins is recommended. The high-frequency decoupling capacitors forthe RF mixers (VCCMIX) should be placed close to the respective pins. The value of the capacitor should bechosen to provide a low impedance RF path to ground at the frequency of operation. Typically, this value isaround 10 pF or lower. The other decoupling capacitors at the other supply pins should be kept as close to therespective pins as possible.
The device exhibits symmetry with respect to the quadrature output paths. It is recommended that the PCBlayout maintain that symmetry in order to ensure the quadrature balance of the device is not impaired. The I/Qoutput traces should be routed as differential pairs and the lengths all kept equal to each other. Decouplingcapacitors for the supply pins should be kept symmetrical where possible. The RF differential input lines relatedto the RF input and the LO input should also be routed as differential lines with the respective lengths kept equal.If an RF balun is used to convert a single-ended input to a differential input, then the RF balun should be placedclose to the device. Implement the RF balun layout according to the manufacturer ’ s guidelines to provide bestgain and phase balance to the differential outputs. On the RF traces, maintain proper trace widths to keep thecharacteristic impedance of the RF traces at a nominal 50 Ω.
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Ø 0.008(0,203)
0.025(0,635)
0.200(5,08)
0.200
(5,08)
0.0125
(0,318)
Dimensions: inches(mm)
0.025
(0,635)
APPLICATION SCHEMATICS
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
Figure 34. PCB Layout Guidelines
The typical application schematic is shown in Figure 35 . The RF bypass capacitors and coupling capacitors aredepicted with 10-pF capacitors. These values can be adjusted to provide the best high-frequency bypass basedon the frequency of operation.
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GNDDIG
VCCDIG
CHIP_EN
VCCMIX
NC
NC
NC
NC
NC
MIXinp
MIXinn
VCCMIX
1
2
3
4
5
6
7
8
9
10
11
12 25
26
27
28
29
30
31
32
33
34
35
36
VCCBBI
ADC_CM( 1.5V)~
ADC_CM( 1.5V)~
C1
0.1 Fm
C11
0.1 Fm
C12
0.1 Fm
C2
C8
C3
C6
1000pF
1000pF
10pF
10pF
10pF
10pF
10pF
0.1 FmAGND
BBIoutp
BBIoutn
LOip
LOin
NC
BBQoutp
BBQoutn
AGND
VCCBBQ
VCCLO
VCC
VCC
VCC
VCC
VCC
BBIN
BBQN
LON
13
14
15
16
17
18
19
20
21
22
23
24 37
38
39
40
41
42
43
44
45
46
47
48
NC
NC
NC
MIXQoutp
MIXQoutn
NC
NC
REXT
VCCBIAS
GNDBIAS
VOFFQ
VCMQ
SCLK
SDAT
STROBE
MIXIoutp
MIXIoutn
NC
NC
Gain_B0
Gain_B1
Gain_B2
VOFFI
VCMI
U1
TRF3710
RFin
R1
30kW
To ADCQ
ToSYNTHESIZER
CLOCK
DATA
STROBE
Gain_B0
Gain_B1
Gain_B2
To ADCI
BBIP
BBQP
LOP
C10
VCC
VCC
CHIP_EN
10pF
C9
C5
LDB21
C4
C7
B1
ADC INTERFACE
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
Figure 35. TRF3710 Application Schematic
The RF input port and the RF LO port require differential input paths. Single-ended RF inputs to these ports canbe converted with an RF balun that is centered on the band of interest. Linearity performance of the TRF3710depends on the amplitude and phase balance of the RF balun; therefore, care should be taken with the selectionof the balun device and with the RF layout of the device. The recommended RF balun devices are listed inTable 6 .
Table 6. Recommended RF Balun Devices
UNBALANCE BALANCEMANUFACTURER PART NUMBER FREQUENCY RANGE (MHz)
IMPEDANCE IMPEDANCE
Murata LDB211G8005C-001 1800 ± 100 MHz 50 Ω50 Ω
Murata LDB211G9005C-001 1900 ± 100 MHz 50 Ω50 Ω
The TRF3710 has an integrated ADC driver buffer that allows direct connection to an analog-to-digital converter(ADC) without additional active circuitry. The common-mode voltage generated by the ADC can be directlysupplied to the TRF3710 through the VCMI/Q pins (pins 24, 37). Otherwise, a nominal common-mode voltage of1.5 V should be applied to those pins. The TRF3710 device can operate with a common-mode voltage from 1.5V to 2.8 V without any impairment to the output performance. Figure 36 illustrates the degradation of the outputcompression point as the common mode voltage exceeds those values.
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0
0.5
1
1.5
2
2.5
3
3.5
0.5 1 1.5 2 2.5 3 3.5
V – Common-ModeVoltage – V
CM
P1dB – dBVrms
APPLICATION FOR A HIGH-PERFORMANCE RF RECEIVER SIGNAL CHAIN
0
90
TRF371x
LNA
TRF3761
ADS5232
12
12
TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
Figure 36. P1dB Performance vs Common-Mode Voltage
The TRF3710 is the centerpiece component in a high-performance direct downconverting receiver. The device isa highly integrated direct downconverting demodulator that requires minimal additional devices to complete thesignal chain. A signal chain block diagram example is shown in Figure 37 .
Figure 37. Block Diagram of Direct Downconverting Receiver
The lineup requires a low-noise amplifier (LNA) that operates at the frequency of interest with typical 1-db to2-dB noise-figure (NF) performance. An RF band-pass filter (BPF) is selected at the frequency band of interest toeliminate unwanted signals and images outside the band from reaching the demodulator. The TRF3710incorporates the direct downconverter demodulation, baseband filtering, and baseband gain control functions. Anexternal synthesizer, such as the TRF3761 , provides the local oscillator (LO) source to the TRF3710. Thedifferential outputs of the TRF3761 directly mate with the LO inputs of the TRF3710. The quadrature outputs(I/Q) of the TRF3710 directly drive the input to the ADC. A dual ADC such as the ADS5232 12-bit, 65-MSPSADC mates perfectly with the differential I/Q output of the TRF3710. In addition, the common-mode outputvoltage generated by the ADS5232 is fed directly into the common-mode ports (pins 24, 37) to ensure theoptimum dynamic range of the ADC is maintained.
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TRF3710
SLWS199A – AUGUST 2007 – REVISED FEBRUARY 2008
The cascaded performance of the TRF3710 with the ADS5232 and the TRF3761 was measured with WCDMAmodulated signals. A single channel WCDMA receive signal was injected into the TRF3710 at – 100 dBm. Thispower roughly corresponds to typical levels this device would see at sensitivity when an appropriate LNA andfilter are used. The error-vector magnitude (EVM) of the RX channel was measured as a gauge of the systemperformance. The EVM percentage at – 100 dBm is approximately 27.6% at 60 ksym/s. This result correlates withthe required signal-to-noise ratio (SNR) for the device with an appropriate LNA to meet or exceed the bit errorrate (BER) specification of 0.1% according to the standards at the input sensitivity level.
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TRF3710IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TRF3710IRGZRG4 ACTIVE VQFN RGZ 48 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TRF3710IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TRF3710IRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2009
Addendum-Page 1
IMPORTANT NOTICE
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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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