STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89950
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
A
SHEET 10
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
1/ For tests not listed in the referenced MIL-STD-883 (e.g. ΔICC), utilize the general test procedure under the conditions listed
herein. All inputs and outputs shall be tested, as applicable, to the tests in table I herein.
2/ Each input/output, as applicable shall be tested at the specified temperature for the specified limits. Output terminals not
designated shall be high level logic, low level logic, or open, except as follows:
a. VIC (pos) tests, the GND terminal can be open. TC = +25°C.
b. VIC (neg) tests, the VCC terminal shall be open. TC = +25°C.
c. All ICC and ΔICC tests, the output terminal shall be open. When performing these tests, the current meter shall be
placed in the circuit such that all current flows through the meter.
3/ The word "All" in the device type and device class column, means limits for all device types and classes.
4/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and
the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum
and maximum limits, as applicable, listed herein.
5/ For device classes B and S, this test is guaranteed, if not tested, to the limits specified in table I.
6/ Transmission driving tests are performed at VCC = 5.5 V dc with a 2 ms duration maximum. This test may be performed
using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for VIN = 2.0 V or 0.8 V.
7/ Power dissipation capacitance (CPD) determines the no load dynamic power consumption, PD = (CPD + CL) (VCC x VCC)f +(ICC
x VCC) + (n x d x ΔICC x VCC), and the dynamic current consumption, IS = (CPD + CL)VCCf + ICC + n x d x ΔICC. For both PD
and IS, n is the number of device inputs at TTL levels, f is the frequency of the input signal, and d is the duty cycle of the
input signal.
8/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at
V
IN = VCC - 2.1 V (alternate method). Classes B, S, Q, and V shall use the preferred method. When the test is performed
using the alternate method, the maximum limits are equal to the number of inputs at a high TTL input level times 1.6 mA;
and the preferred method and limits are guaranteed.
9/ This test is for qualification only. Ground bounce tests are performed on a non-switching (quiescent) output and are used to
measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is performed on a low
noise bench test fixture with all outputs fully dc loaded (IOL maximum and IOH maximum = i.e., ±24 mA) and 50 pF of load
capacitance (see figure 4). The loads must be located as close as possible to the device output. Inputs are then
conditioned with 1 MHz pulse (tr = tf = 3.5 ns ±1.5 ns) switching simultaneously and in phase such that one output is forced
low and all others (possible) are switched. The low level ground bounce noise is measured at the quiet output using a F.E.T
oscilloscope probe with at least 1 MΩ impedance. Measurement is taken from the peak of the largest positive pulse with
respect to the nominal low level output voltage (see figure 4). The device inputs are then conditioned such that the output
under test is at a high nominal VOH level. The high level ground bounce measurement is then measured from nominal VOH
level to the largest negative peak. This procedure is repeated such that all outputs are tested at a high and low level with a
maximum number of outputs switching.
10/ See EIA/JEDEC Standard No. 78 for electrically induced latch-up test methods and procedures. The values listed for
I
trigger and Vover are to be accurate within ± 5 percent.
11/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
patterns used for fault detection. Functional tests shall be performed in sequence as approved by the qualifying activity on
qualified devices. H ≥ 2.5 V, L < 2.5 V; high inputs = 2.4 V and low inputs = 0.4 V. The input voltage levels have the
allowable tolerances in accordance with MIL-STD-883 already incorporated.
12/ Device classes B and S are tested at VCC = 4.5 V and TC = +125°C for sample testing and at VCC = 4.5 V and TC = +25°C
for screening. Other voltages of VCC and temperatures are guaranteed, if not tested (see 4.4.1d).
13/ AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. Minimum ac limits
for VCC = 5.5 V are 1.0 ns and guaranteed by guardbanding the VCC = 4.5 V minimum limits to 1.5 ns. For propagation delay
tests, all paths must be tested.