REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Correct the drawing title to accurately describe the device function. Update the boilerplate to current requirements as specified in MIL-PRF-38535. Editorial changes throughout. - jak 06-07-19 Thomas M. Hess REV SHEET REV A A A A A A A SHEET 15 16 17 18 19 20 21 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Joseph A. Kerby STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Thomas J. Ricciuti APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 93-01-19 REVISION LEVEL AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil A MICROCIRCUIT, DIGITAL, ADVANCED CMOS, DUAL NEGATIVE EDGE TRIGGERED JK FLIPFLOP WITH ASYNCHRONOUS SET AND CLEAR, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 1 OF 5962-89950 21 5962-E377-06 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes M, Q, and B) and space application (device classes S and V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). 1.2 PIN. The PIN is as shown in the following examples. 5962 - Federal stock class designator \ RHA designator (see 1.2.1) 89950 01 M E A Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes B, S, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 01 54ACT112 Circuit function Dual negative edge triggered JK flip-flop with asynchronous set and clear, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A B, S, Q, or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter E F 2 Descriptive designator GDIP1-T16 or CDIP2-T16 GDFP2-F16 or CDFP3-F16 CQCC1-N20 or CQCC2-N20 Terminals 16 16 20 Package style Dual-in-line Flat pack Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes B, S, Q, and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) ........................................................................... DC input voltage range (VIN) ......................................................................... DC output voltage range (VOUT) .................................................................... DC input diode current (IIK) (0.0 V > VIN, VIN > VCC) ...................................... DC output diode current (IOK) (0.0 V > VOUT, VOUT < VCC) ............................. DC output current (IOUT) (per output pin) ....................................................... DC VCC or GND current (ICC, IGND) (per pin) .................................................. Storage temperature range (TSTG) ................................................................ Maximum power dissipation (PD) ................................................................. Lead temperature (soldering, 10 seconds).................................................... Thermal resistance, junction-to-case (JC) .................................................... Junction temperature (TJ) ............................................................................. Case operating temperature range (TC) ........................................................ STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 -0.5 V dc to +6.0 V dc -0.5 V dc to VCC + 0.5 V dc -0.5 V dc to VCC + 0.5 V dc 20 mA 20 mA 50 mA 200 mA 3/ -65C to +150C 500 mW +300C See MIL-STD-1835 +175C -55C to +125C SIZE 5962-89950 A REVISION LEVEL A SHEET 2 1.4 Recommended operating conditions - Continued. 1/ 2/ 4/ Supply voltage range (VCC) ........................................................................... Input voltage range (VIN) ............................................................................... Output voltage range (VOUT).......................................................................... Maximum low level input voltage (VIL): VCC = 4.5 V and VCC = 5.5V ........................................................................ Minimum high level input voltage (VIH): VCC = 4.5 V and VCC = 5.5V ........................................................................ Case operating temperature range (TC) ........................................................ Input rise or fall rate (tr, tf) maximum: (from VIN = 0.8 V to 2.0 V, 2.0 V to 0.8 V) .................................................. Maximum high level output current (IOH) ....................................................... Maximum low level output current (IOL) ......................................................... +4.5 V dc to +5.5 V dc 0.0 V to VCC 0.0 V to VCC 0.8 V 2.0 V -55C to +125C 125 mV/ns -24 mA 24 mA 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. ELECTRONIC INDUSTRIES ALLIANCE (EIA) EIA/JEDEC Standard No. 78 - IC Latch-Up Test JEDEC Standard No. 20 - Standard for Description of 54/74ACXXXX and 54/74ACTXXXX Advanced High-Speed CMOS Devices (Copies of these documents are available online at http://www.jedec.org or from the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 1/ Stresses above the absolute maximum rating may cause permanent damage to the device, Extended operation at the maximum levels may degrade performance and affect reliability. The maximum junction temperature may be exceeded for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ For packages with multiple VCC and GND pins, this value represents the maximum total current flowing into or out of all VCC or GND pins. 4/ Unless otherwise specified the values listed above shall apply over the full VCC and TC recommended operating range. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 3 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes B, S, Q, and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes B, S, Q, and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Ground bounce waveform and test circuit. The ground bounce waveform and test circuit shall be as specified on figure 4. 3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. Test conditions for these specified characteristics and limits are as specified in table I. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes B, S, Q, and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes B, S, Q, and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes B, S, Q, and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes B, S, Q, and V, the requirements of MIL-PRF-38535 and herein or for device class M the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes B, S, Q, and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 38 (see MIL-PRF-38535, appendix A). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 4 TABLE I. Electrical performance characteristics. Test and MIL-STD-883 test method 1/ Symbol Test conditions 2/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Device type 3/ and device class VCC Group A subgroups Limits 4/ Min High level output voltage 3006 VOH1 5/ For all inputs affecting output under test VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOH = -50 A All All 4.5 V 1, 2, 3 4.4 VOH2 For all inputs affecting output under test VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOH = -50 A All All 5.5 V 1, 2, 3 5.4 VOH3 For all inputs affecting output under test VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOH = -24 mA All All 4.5 V 1, 2, 3 3.7 VOH4 5/ For all inputs affecting output under test VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOH = -24 mA All All 5.5 V 1, 2, 3 4.7 VOH5 6/ For all inputs affecting output under test VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOH = -50 mA All All 5.5 V 1, 2, 3 3.85 Unit Max V See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 5 TABLE I. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Symbol Device type 3/ and device class Test conditions 2/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified VCC Group A subgroups Limits 4/ Min Low level output voltage 3007 Max VOL1 5/ For all inputs affecting output under test VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOL = 50 A All All 4.5 V 1, 2, 3 0.1 VOL2 For all inputs affecting output under test VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOL = 50 A All All 5.5 V 1, 2, 3 0.1 VOL3 For all inputs affecting output under test VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOL = 24 mA All B, S, Q, V 4.5 V 1, 3 0.4 2 0.5 1 0.4 2, 3 0.5 For all inputs affecting output under test VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOL = 24 mA All B, S, Q, V 1, 3 0.4 2 0.5 1 0.4 2, 3 0.5 For all inputs affecting output under test VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOL = 50 mA All All 1, 2, 3 1.65 VOL4 5/ VOL5 6/ All M 5.5 V All M 5.5 V Unit V See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Symbol Device type 3/ and device class Test conditions 2/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified VCC Group A subgroups Limits 4/ Min Max Unit VIC+ For input under test IIN = 1 mA All B, S, Q, V GND 1 0.4 1.5 V Negative input clamp VICvoltage 3022 For input under test IIN = -1 mA All B, S, Q, V Open 1 -0.4 -1.5 V Input current high 3010 For input under test VIN = VCC For all other inputs VIN = VCC or GND All B, S, Q, V 5.5 V 1 0.1 A 2 1.0 1 0.1 2, 3 1.0 1 -0.1 2 -1.0 1 -0.1 2, 3 -1.0 Positive input clamp voltage 3022 Input current low 3009 IIH IIL All M For input under test VIN = GND For all other inputs VIN = VCC or GND All B, S, Q, V 5.5 V All M A Input capacitance 3012 CIN See 4.4.1c TC = +25C All All GND 4 10.0 pF Power dissipation capacitance CPD 7/ See 4.4.1c TC = +25C All All 5.0 V 4 60.0 pF Quiescent supply current delta, TTL input levels 3005 ICC 8/ For input under test VIN = VCC - 2.1 V For all other inputs VIN = VCC or GND All B, S, Q, V 5.5 V 3 1.6 mA 1, 2 1.0 1, 2, 3 1.6 Quiescent supply current, output high 3005 ICCH OE = GND For all other inputs VIN = VCC or GND All B, S, Q, V 1 2.0 2 40.0 1 8.0 2, 3 160.0 All M 5.5 V All M A See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 7 TABLE I. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Symbol Device type 3/ and device class Test conditions 2/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified VCC Group A subgroups Limits 4/ Min Quiescent supply current, output low 3005 ICCL OE = GND For all other inputs VIN = VCC or GND All B, S, Q, V 5.5 V All M Low level ground bounce noise VGBL 9/ High level ground bounce noise VGBH 9/ Latch-up input/ output overvoltage ICC (O/V1) 10/ Latch-up input/ output positive over-current VLD = 2.5 V IOL = +24 mA See figure 4 VLD = 2.5 V IOL = -24 mA See figure 4 Unit Max 1 2.0 2 40.0 1 8.0 2, 3 160.0 A All B, S, Q, V 4.5 V 4 1000 mV All B, S, Q, V 4.5 V 4 1000 mV tw 100 s tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Vover = 10.5 V All B, S, Q, V 5.5 V 2 200 mA ICC (O/I1+) 10/ tw 100 s tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Itrigger = +120 mA All B, S, Q, V 5.5 V 2 200 mA Latch-up input/ output negative over-current ICC (O/I1-) 10/ tw 100 s tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Itrigger = -120 mA All B, S, Q, V 5.5 V 2 200 mA Latch-up supply over-voltage ICC (O/V2) 10/ tw 100 s tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Vover = 9.0 V All B, S, Q, V 5.5 V 2 100 mA See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 8 TABLE I. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Truth table test, output voltage 3014 Propagation delay time, CPn to Qn and Qn 3003 Propagation delay time, CDn and SDn to Qn and Qn 3003 Maximum operating frequency Input set-up time, data high and low, Jn and Kn to CPn Input hold time, data high and low, Jn and Kn from CPn High and low pulse Width, CDn, SDn and CPn Recovery time, CDn and SDn to CPn Symbol 11/ VIL = 0.40 V VIH = 2.40 V Verify output VOUT See 4.4.1e CL = 50 pF minimum tPHL1, RL = 500 tPLH1 See figure 5 12/ 13/ tPHL2, tPLH2 12/ 13/ fMAX ts th tw tREC VCC Device type 3/ and device class Test conditions 2/ -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups L H All M 5.5 V 7, 8 L H All B, S, Q, V 4.5 V 9, 11 10 1.0 1.0 13.0 14.0 9 1.0 13.0 10, 11 1.0 14.0 9, 11 10 1.0 1.0 12.5 13.5 9 1.0 12.5 10, 11 1.0 13.5 9, 11 95 10 80 9 95 10, 11 80 9, 11 7.0 10 8.0 9 7.0 10, 11 8.0 1.5 All B, S, Q, V 4.5 V 4.5 V All M All B, S, Q, V 4.5 V All M CL = 50 pF minimum RL = 500 See figure 5 See 4.4.1g All B, S, Q, V 5.5 V All B, S, Q, V All B, S, Q, V All M 1.5 9, 11 5.0 10 5.0 9, 10, 11 5.0 9, 11 3.0 10 3.0 9, 10, 11 3.0 5.5 V ns ns MHz ns ns 1.5 9, 10, 11 4.5 V All M CL = 50 pF minimum RL = 500 See figure 5 See 4.4.1g 9, 11 10 All M CL = 50 pF minimum RL = 500 See figure 5 See 4.4.1g Max 7, 8 All M CL = 50 pF minimum RL = 500 See figure 5 See 4.4.1g Min 4.5 V All B, S, Q, V CL = 50 pF minimum RL = 500 See figure 5 See 4.4.1f Unit All B, S, Q, V All M CL = 50 pF minimum RL = 500 See figure 5 Limits 4/ ns ns See footnotes on next sheet. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 9 TABLE I. Electrical performance characteristics - Continued. 1/ For tests not listed in the referenced MIL-STD-883 (e.g. ICC), utilize the general test procedure under the conditions listed herein. All inputs and outputs shall be tested, as applicable, to the tests in table I herein. 2/ Each input/output, as applicable shall be tested at the specified temperature for the specified limits. Output terminals not designated shall be high level logic, low level logic, or open, except as follows: a. VIC (pos) tests, the GND terminal can be open. TC = +25C. b. VIC (neg) tests, the VCC terminal shall be open. TC = +25C. c. All ICC and ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be placed in the circuit such that all current flows through the meter. 3/ The word "All" in the device type and device class column, means limits for all device types and classes. 4/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum and maximum limits, as applicable, listed herein. 5/ For device classes B and S, this test is guaranteed, if not tested, to the limits specified in table I. 6/ Transmission driving tests are performed at VCC = 5.5 V dc with a 2 ms duration maximum. This test may be performed using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for VIN = 2.0 V or 0.8 V. 7/ Power dissipation capacitance (CPD) determines the no load dynamic power consumption, PD = (CPD + CL) (VCC x VCC)f +(ICC x VCC) + (n x d x ICC x VCC), and the dynamic current consumption, IS = (CPD + CL)VCCf + ICC + n x d x ICC. For both PD and IS, n is the number of device inputs at TTL levels, f is the frequency of the input signal, and d is the duty cycle of the input signal. 8/ 9/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at VIN = VCC - 2.1 V (alternate method). Classes B, S, Q, and V shall use the preferred method. When the test is performed using the alternate method, the maximum limits are equal to the number of inputs at a high TTL input level times 1.6 mA; and the preferred method and limits are guaranteed. This test is for qualification only. Ground bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture with all outputs fully dc loaded (IOL maximum and IOH maximum = i.e., 24 mA) and 50 pF of load capacitance (see figure 4). The loads must be located as close as possible to the device output. Inputs are then conditioned with 1 MHz pulse (tr = tf = 3.5 ns 1.5 ns) switching simultaneously and in phase such that one output is forced low and all others (possible) are switched. The low level ground bounce noise is measured at the quiet output using a F.E.T oscilloscope probe with at least 1 M impedance. Measurement is taken from the peak of the largest positive pulse with respect to the nominal low level output voltage (see figure 4). The device inputs are then conditioned such that the output under test is at a high nominal VOH level. The high level ground bounce measurement is then measured from nominal VOH level to the largest negative peak. This procedure is repeated such that all outputs are tested at a high and low level with a maximum number of outputs switching. 10/ See EIA/JEDEC Standard No. 78 for electrically induced latch-up test methods and procedures. The values listed for Itrigger and Vover are to be accurate within 5 percent. 11/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic patterns used for fault detection. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified devices. H 2.5 V, L < 2.5 V; high inputs = 2.4 V and low inputs = 0.4 V. The input voltage levels have the allowable tolerances in accordance with MIL-STD-883 already incorporated. 12/ Device classes B and S are tested at VCC = 4.5 V and TC = +125C for sample testing and at VCC = 4.5 V and TC = +25C for screening. Other voltages of VCC and temperatures are guaranteed, if not tested (see 4.4.1d). 13/ AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. Minimum ac limits for VCC = 5.5 V are 1.0 ns and guaranteed by guardbanding the VCC = 4.5 V minimum limits to 1.5 ns. For propagation delay tests, all paths must be tested. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 10 Device type All Case outlines E and F Terminal number 2 Terminal symbol 1 CP1 NC 2 K1 CP1 3 J1 K1 4 SD1 J1 5 Q1 SD1 6 Q1 NC 7 Q2 Q1 8 GND Q1 9 Q2 Q2 10 SD2 GND 11 J2 NC 12 K2 Q2 13 CP2 SD2 14 CD2 J2 15 CD1 K2 16 VCC NC 17 --- CP2 18 --- CD2 19 --- CD1 20 --- VCC Terminal description Description Terminal symbol CP1, CP2 Clock pulse timing inputs (active falling edge) CD2, CD2 Asynchronous reset control inputs (active low) SD1, SD2 Asynchronous set control inputs (active low) J1, J2, K1, K2 Data inputs Q1, Q1, Q2, Q2 Outputs (noninverting, inverting) NC No connection FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 11 Inputs Outputs SDn CDn CPn Jn Kn Qn Qn L H X X X H L H L X X X L H L L X X H H H H X h h Qn Qn H H l h L H H H h l H L H H l l Qn Qn L = Low voltage level H = High voltage level X = Irrelevant = Falling edge of the clock h or l = Lower case letters indicate the state of the referenced input or output one setup time prior to the high-to-low clock transition. FIGURE 2. Truth table. FIGURE 3. Logic diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 12 NOTE: Resistor and capacitor tolerances are 10%. FIGURE 4. Ground bounce waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 13 FIGURE 5. Switching waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 14 NOTES: 1. CL = 50 pF or equivalent (includes test jig and probe capacitance). 2. RL = 500 or equivalent. RT = 50 or equivalent. 3. 4. Input signal from pulse generator: VIN = 0.0 V to 3.0 V; PRR 10 MHz; tr 3.0 ns, tf 3.0 ns, duty cycle = 50 percent. Timing parameters shall be tested at a minimum input frequency of 1 MHz. FIGURE 5. Switching waveforms and test circuit - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 15 4. VERIFICATION 4.1 Sampling and inspection. For device classes B, S, Q, and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes B, S, Q, and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device classes M, B, and S. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. (3) Delete the sequence specified in 3.1.10 through 3.1.14 of method 5004 and substitute the first seven test requirements of table II herein. (4) For device class M, unless otherwise specified, the requirements for device class B in method 1015 of MIL-STD-883 shall be followed. (5) Static burn-in device classes B and S, test condition A, test method 1015 of MIL-STD-883. Test duration for each static test shall be 24 hours minimum for class S devices and in accordance with table I of method 1015 for device class B devices. (a) For static burn-in I, all inputs shall be connected to GND. Outputs may be open or connected to VCC/2 0.5 V. Resistors R1 are optional on both inputs and open outputs, and required on outputs connected to VCC/2 0.5 V. R1 = 220 to 47 k. (b) For static burn-in II, all inputs shall be connected through the R1 resistors to VCC. Outputs may be open or connected to VCC/2 0.5 V. Resistors R1 are optional on open outputs, and required on outputs connected to VCC/2 0.5 V. R1 = 220 to 47 k. (c) VCC = 5.5 V +0.5 V, -0.0 V. (6) Dynamic burn-in, device class B and S, test condition D, method 1015 of MIL-STD-883. (a) Input resistors = 220 to 2 k 20%. (b) Output resistors = 220 20%. (c) VCC = 5.5 V + 0.5 V, -0.0 V. (d) The Jn, Kn, SDn, and CDn pins shall be connected trough the resistors in parallel to VCC. The clock inputs (CPn) shall be connected through resistors to a clock pulse (CP1). The outputs shall be connected through the resistors to VCC/2 0.5 V. (e) CP1 = 25 kHz to 1 MHz square wave; duty cycle = 50 % 15%; VIH = 4.5 V to VCC, VIL = 0 V 0.5 V; tr, tf 100 ns. b. Interim and final electrical test parameters shall be as specified in table II herein. c. For class S devices, post dynamic burn-in, or class B devices, post static burn-in, electrical parameter measurements may, at the manufacturer's option, be performed separately or included in the final electrical parameter requirements. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 16 TABLE II. Electrical test requirements. Test requirements, MIL-STD-883 test method Subgroups 1/ (in accordance with MIL-PRF-38535, table III) Subgroups 1/ (in accordance with MIL-STD-883, method 5005, table I) Device class M Device class B 2/ Device class S 2/ Device class Q Device class V 1 1 1 1 Not required Required 4/ Not required Required 4/ Interim electrical parameters, method 5004 Static burn-in I, method 1015 (See 4.2.1a) 3/ Interim electrical parameters, method 5004 (See 4.2.1b) 1 5/ Static burn-in II, method 1015 (See 4.2.1a) 3/ Interim electrical parameters, method 5004 (See 4.2.1b) Dynamic burn-in I, method 1015 (See 4.2.1a) 3/ 1 5/ Required 6/ Required 4/ Required 6/ Required 4/ 1 2/ 5/ 1 2/ 5/ 1 2/ 5/ 1 2/ 5/ Not required Required 4/ Not required Required 4/ Interim electrical parameters, method 5004 (See 4.2.1b) 1 5/ 1 5/ Final electrical parameters, method 5004 1, 2, 3, 7, 8, 9 2/ 1, 2, 7, 9 2/ 6/ 1, 2, 7, 9 2/ 1, 2, 3, 7, 8, 9, 10, 11 2/ 6/ 1, 2, 3, 7, 8, 9, 10, 11 2/ Group A test requirements, method 5005 (See 4.4.1) 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3 5/ 1, 2, 3, 7, 8, 9, 10, 11 5/ Group B end-point electrical parameters, method 5005 (See 4.4.2) 1, 2, 3, 7, 8, 9, 10, 11 5/ Group C end-point electrical parameters, method 5005 (See 4.4.3) 1, 2, 3 1, 2 5/ Group D end-point electrical parameters, method 5005 (See 4.4.4) 1, 2, 3 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 Group E end-point electrical parameters, method 5005 (See 4.4.5) 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9 1/ Blank spaces indicate tests are not applicable. 2/ PDA applies to subgroup 1 (see 4.2.3). For device classes S and V, PDA applies to subgroups 1 and 7 (see 4.2.3). 3/ The burn-in shall meet the requirements of 4.2.1a herein. 4/ On all class S lots, the device manufacturer shall maintain read-and-record data (as a minimum on disk) for burn-in electrical parameters (group A, subgroup 1), in accordance with test method 5004 of MIL-STD-883. For pre-burn-in and interim electrical parameters, the read-and-record requirements are for delta measurements only. 5/ Delta limits shall be required only on table I, subgroup 1. The delta values shall be computed with reference to the previous interim electrical parameters. The delta limits are specified in table III. 6/ The device manufacturer may, at his option, either complete subgroup 1 electrical parameter measurements, including delta measurements, within 96 hours after burn-in completion (removal of bias) or may complete subgroup 1 electrical measurements without delta measurements within 24 hours after burn-in completion (removal of bias). When the manufacturer elects to perform the subgroup 1 electrical parameter measurements without delta measurements, there is no requirement to perform the pre-burn-in electrical tests (first interim electrical parameters test in table II). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 17 TABLE III. Burn-in and operating life test, delta parameters (+25C). Parameter 1/ Symbol Device types Delta limits Supply current ICCH, ICCL All 100 nA 1/ These parameters shall be recorded before and after the required burn-in and life tests to determine delta limits. 4.2.2 Additional criteria for device classes B, S, Q, and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V or S beyond the requirements of device class Q or B shall be as specified in MIL-PRF-38535, appendix B. 4.2.3 Percent defective allowable (PDA). a. The PDA for class S or V devices shall be 5 percent for static burn-in and 5 percent for dynamic burn-in, based on the exact number of devices submitted to each separate burn-in. b. Static burn-in I and II failures shall be cumulative for determining the PDA. c. The PDA for class B or Q devices shall be in accordance with MIL-PRF-38535 for static burn-in. Dynamic burn-in is not required. d. The PDA for class M devices shall be in accordance with MIL-PRF-38535, appendix A for static burn-in and dynamic burn-in. e. Those devices whose measured characteristics, after burn-in, exceed the specified delta limits or electrical parameter limits specified in table I, subgroup I, are defective and shall be removed from the lot. The verified number of failed devices times 100 divided by the total number of devices in the lot initially submitted to burn-in shall be used to determine the percent defective for the lot and the lot shall be accepted or rejected based on the specified PDA. 4.3 Qualification inspection for device classes B, S, Q, and V. Qualification inspection for device classes B, S, Q, and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.5). 4.4 Conformance inspection. Technology conformance inspection for classes B, S, Q, and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.5). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 18 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Latch-up tests are required for device classes B, S, Q, and V. These tests shall be performed only for initial qualification and after process or design changes which may affect the performance of the device. Latch-up tests shall be considered destructive. For latch-up tests, test all applicable pins on five devices with zero failures. c. CIN and CPD shall be measured only for initial qualification and after process or design changes which may affect capacitance. CIN shall be measured between the designated terminal and GND at a frequency of 1 MHz. CPD shall be tested in accordance with the latest revision of JEDEC Standard No. 20 and table I herein. For CIN and CPD, test all applicable pins on five devices with zero failures. d. For device classes B, S, Q, and V, subgroups 9 and 11 tests shall be measured only for initial qualification and after process or design changes which may affect dynamic performance. e. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table on figure 2 herein. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output patterns per function shall be guaranteed, if not tested, to the truth table as approved by the qualifying activity. For device classes B, S, Q, and V, subgroups 7 and 8 shall include verification of the functionality of the device. f. For device classes M, B, and S, fMAX shall be measured only for initial qualification and after process or design changes which may affect the device frequency. Test all applicable pins on 22 devices with zero failures. g. For device classes M, B, and S, ts, th, tREC, and tw shall be guaranteed, if not tested, to the limits specified in table I. 4.4.2 Group B inspection. When applicable, the group B inspection end-point electrical parameters shall be as specified in table II herein. For device class S steady steady-state life tests, the test circuit shall be maintained by the manufacturer and shall be made available to the acquiring or preparing activity upon request. 4.4.3 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. 4.4.3.1 Additional criteria for device class M and B . Steady-state life test conditions, method 1005 of MIL-STD-883: a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.3.2 Additional criteria for device classes B, S, Q, and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB, in accordance with MIL-PRF-38535, and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. 4.4.4 Group D inspection. Group D inspection end-point electrical parameters shall be as specified in table II herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 19 4.4.5 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table II herein. b. For device classes B, S, Q, and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C 5C, after exposure, to the subgroups specified in table II herein. c. RHA tests for device classes M, B, S, Q, and V for levels M, D, P, L, R, and F shall be performed through each level to determine at what levels the devices meet the RHA requirements. These RHA tests shall be performed for initial qualification and after design or process changes that may affect the RHA performance of the device. d. Prior to irradiation, each selected sample shall be assembled in its qualified package. It shall pass the specified group A electrical parameters in table I for subgroups specified in table II herein. 4.4.5.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883, method 1019, condition A and as specified herein. Prior to and during total dose irradiation characterization and testing, the devices for characterization shall be biased so that 50 percent are at inputs high and 50 percent are at inputs low, and the devices for testing shall be biased to the worst case condition established during characterization. 4.4.5.1.1 Accelerated aging test. Accelerated aging shall be performed on classes M, B, S, Q, and V devices requiring an RHA level greater than 5K rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table I herein and shall be the pre-irradiation end-point electrical parameter limit at 25C 5C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.5 Methods of inspection. Methods of inspection shall be specified as follows. 4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal. Currents given are conventional current and positive when flowing into the referenced terminal. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes B, S, Q, and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.1.2 Substitutability. Device classes B and Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and which SMDs are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0547. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 20 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes B, S, Q, and V. Sources of supply for device classes B, S, Q, and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89950 A REVISION LEVEL A SHEET 21 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 06-07-19 Approved sources of supply for SMD 5962-89950 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ 5962-8995001MEA Vendor similar PIN 2/ 54ACT112DMQB 5962-8995001SEA Vendor CAGE number 27014 0C7V7 27014 0C7V7 27014 0C7V7 27014 0C7V7 27014 0C7V7 27014 0C7V7 3/ 5962-8995001SFA 3/ 54ACT112 5962-8995001S2A 3/ 54ACT112 5962-8995001MFA 5962-8995001M2A 5962-8995001BEA 5962-8995001BFA 5962-8995001B2A 54ACT112FMQB 54ACT112LMQB JM54ACT112BEA JM54ACT112BFA JM54ACT112B2A 54ACT112 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source of supply. Vendor CAGE number 27014 0C7V7 Vendor name and address National Semiconductor 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.