TOSHIBA JTMP04030-XXXS TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC JTMPO04030-XXXS CMOS 4BIT LL MICROCONTROLLER (LL : LOW-POWER CONSUMPTION & LOW-VOLTAGE OPERATION) JTMP04030-XXXS is a high-performance 4 bit LL microcontroller designed to be used in applications where low voltage operation is required. JTMP04030-XXXS integrates a high-performance CPU, memory (static work RAM, Data RAM, program ROM), LCD driver, and multifunction timers on a single chip. The basic features are as follows: FEATURES Number of instructions Minimum instruction execution time : Oscillator circuit Built-in ROM size Built-in RAM size : Work RAM Data RAM Input pins Input/output pins Output pins Interrups Timers Melody Serial interface LCD display driver controller 56 61 us (at 32.768 kHz) Tus (at 2MHz/3.0V) High-speed crystal oscillator (external resistor) Low-speed crystal oscillator (32.768 kHz / 36.864 kHz) 32 K words (1 word = 16 bits) 256 nibbles x 4 banks (including 64 stacks) 256 bytes x 2 banks (including melody data area) 4 pins (with interrupts) 12 pins (4 with interrupts) 2 melody pins (BZ, BZ) 2 external interrupts (IN, 100) 5 internal interrupts (timer/counter 1, 2 timing, SIO, melody) Event/timer x 1 8 bits x 2 channels or 16 bits x 1 channel timer / counter Watchdog timer x 1 channel Builtin scale generator circuit with Autoplay function 8 bit serial transfer 16 COM x 64 SEG 1 2001-06-27TOSHIBA SYSTEM BLOCK DIAGRAM [ I Test Oscillator Circuit Circuit T4X CORE ROM (32 kwords) Data RAM (4 Kbits) Melody data BZ Melody Circuit Interrupt Circuit Event Timer Timer /Counter1 Timer /Counter2 102 Port Reset Circuit Work RAM (4 Kbits) Display RAM (1024 bits) LCD Control Circuit 5 x Doubler Regulator SIO Circuit JTMP04030-XXXS LCD Panel Vpp 2001-06-27TOSHIBA JTMP04030-XXXS PAD / PIN LAYOUT 1. Pad Layout toma AON wnt mne- Oo ana AY Sere Ke KH KH MK KM HK KH DONWON tTMN- OD DO rAwnwnnnnuwnwnuwnnnwnnmnnnnnnnunnnn- - - - - - OO QOOOOOOOOOOOOOOOODOOOOOOO0O0O00000 1004 1003 1002 1001 SCK SDAT cM IN4 IN3 IN2 IN1 BRESET TEST HXOUT HXIN Vss XOUT XIN VXT VDD C2 a v1 v2 V3 va V5 cOM1 com2 COM3 $31 JTMPO04030-XXXS 535 (TOP VIEW) & OOOOOQOOOOOOOOOOOOO00OO0OOO0OO0O0O0O0000 OQOOOQOOQOOQOOOO0OOO0OOOO0OO0OO0OO0OO0O0000O00000000 OQOOOOOOOOOOOOOO0OO0O0OO0OO0OO0O0000000000 wont nn - Oo eee ee He Ke HAOR OHS MOK NM+tMHORMMOR- NmMTtZSZeSSS22 222222 SBRBRBBRBBBBSESESSESSSESSSESSESSES CHIP SIZE 5.25 5.31 (mm) CHIP THICKNESS 450430 (sem) REFERENCE VOLTAGE Vs 3 2001-06-27TOSHIBA JTMP04030-XXXS 2. Pad Locations and Functions No. NAME X POINT Y POINT FUNCTION 1 $49 -2181 2489 2 S50 - 2025 - 2489 3 S51 - 1870 2489 4 | S59 -1714 - 2489 5 $53 - 1558 2489 6 S54 - 1402 2489 7 $55 - 1246 2489 8 $56 1091 ~ 2489 Segment output pins 9 $57 - 935 2489 10 | S5g -779 2489 11 | S59 - 623 - 2489 12 | Sep - 467 - 2489 13 | S64 -312 - 2489 14 | S62 - 156 2489 15 | S63 0 - 2489 16 | S64 156 - 2489 17 COM 16 312 2489 18 | COM15 467 2489 19 | COM14 623 2489 20 | COM13 779 2489 21 COM 12 935 2489 22 cOM11 1091 2489 23 COM10 1246 2489 24 | COM9 1402 2489 . 25 | come 1558 3489 Common output pins 26 | COM7 1714 2489 27 | COM6 1870 2489 28 | COM5 2025 - 2489 29 | COM4 2181 2489 30 | COM3 2517 - 2190 31 | COM2 2517 - 2039 32 cOM1 2517 - 1888 33 | Vs 2517 - 1737 34 | V4 2517 - 1586 . . . a 35 | V3 2517 -74435 Capacitor connecting pins for stabilizing LCD reference voltage 36 | V2 2517 - 1284 37 | V4 2517 - 1133 38 | Cy 2517 - 982 39 | > 3517 331 Capacitor connecting pins for LCD booster 40 | Vpp 2517 - 680 Supply voltage pin ar | vxt 2517 529 Capacitor connecting pin for stabilizing reference voltage applied to low-speed oscillator circuit 4 2001-06-27TOSHIBA JTMP04030-XXXS No. NAME X POINT Y POINT FUNCTION 42 XLIN 2517 - 378 . . ao. 43 | XLOUT 2517 356 Crystal connecting pins for low-speed oscillation 44 | Vsg 2517 -75 |Ground pin 45 XHIN 2517 76 . . . . a, 46 | XHOUT 3517 7 Resistor connecting pin for high-speed oscillation 47 | TEST 2517 378 Always grounded (test pin) 48 | BRESET 2517 529 Reset capacitor connecting pin 49 IN1 2517 680 50 IN2 2517 831 . oo. 51 INB 517 982 Input port pins (with interrupts) 52 IN4 2517 1133 53 | CM 2517 1284 Melody capacitor connecting pin 54 SDAT 2517 1435 Serial Data 55 | SCK 2517 1586 Serial clock 56 1001 2517 1737 57 1002 2517 1888 . 58 1003 2517 2039 Input/output port 0 pins 59 1004 2517 2190 60 | BZ 2181 2489 Melody output Inverted Melody output/carrier output 61 | BBZ 2025 2489 (switchable by software) 62 1011 1870 2489 63 1012 1714 2489 . 64 | 1013 1558 2489 Input/output port 1 pins 65 1014 1402 2489 66 1021 1246 2489 67 | 1022 1091 2489 Input/output port 2 pins 68 | 1023 935 2489 69 1024 779 2489 70 | Sq 623 2489 71 | So 467 2489 72 | S3 312 2489 73 | Sa 156 2489 74 | Ss 0 2489 75 | S6 - 156 2489 76 | S7 - 312 2489 77 | Sg - 467 2489 Segment output pins 78 | Sg - 623 2489 79 $10 -779 2489 80 | S414 -935 2489 81 | S42 - 1091 2489 82 | $43 - 1246 2489 83 | S14 - 1402 2489 84 | S15 - 1558 2489 5 2001-06-27TOSHIBA JTMP04030-XXXS No. NAME X POINT Y POINT FUNCTION 85 | S416 -1714 2489 86 | S17 - 1870 2489 87 | Sig - 2025 2489 88 | Sig -2181 2489 89 | S20 -2517 2186 90 | S24 -2517 2030 91 | S22 -2517 1874 92 $23 -2517 1719 93 | So4q -2517 1563 94 $25 - 2517 1407 95 | $96 - 2517 1251 96 | S27 -2517 1095 97 | S28 -2517 940 98 | S29 -2517 784 99 | S39 - 2517 628 100 | $34 - 2517 472 101 | S39 -2517 316 Segment output pins 102 | $33 -2517 161 103 | S34 - 2517 5 104 | S35 - 2517 - 151 105 | $36 - 2517 - 307 106 | $37 - 2517 - 463 107 | S38 - 2517 -618 108 | S39 -2517 -774 109 | Sao -2517 - 930 110 | S44 -2517 - 1086 111 | S42 = 2517 = 1242 112 | S43 -2517 - 1397 113 | S44 -2517 - 1553 114 | S45 - 2517 - 1709 115 | Sag -2517 - 1865 116 | S47 -2517 - 2021 117 | Sag -2517 2176 2001-06-27TOSHIBA JTMP04030-XXXS 3. Dimensions for engineer-sampling package Unit mm * This package is only available with an engineer-sampling device; hence, the package is not in mass production. Please take this into account. 108 73 72 22.6TYP, 0.50 TYP. 37 18.70 TYP. OO > e lo ww ax} Low wv 4 TYP. 0.50 TYP, 0.55 TYP. ( 1.70 TYP, 7 2001-06-27TOSHIBA JTMP04030-XXXS 4. Pin assignment for engineer-sampling package No NAME No. NAME No. NAME No. NAME 1 $49 37 COM3 73 BZ 109 $20 2 550 38 CcOM2 74 BBZ 110 $21 3 $54 39 COM1 75 1011 111 $22 4 $52 40 V5 76 1012 112 $23 5 $53 41 Va 77 1013 113 $24 6 554 42 V3 78 1014 114 525 7 43 V2 79 115 $26 8 $55 44 80 1021 116 9 $56 45 V1 81 1022 117 $27 10 $57 46 Cy 82 1023 118 $28 11 $58 47 C2 83 1024 119 $29 12 $59 48 Vpb 84 120 $390 13 49 VXT 85 $1 121 14 S60 50 XIN 86 $2 122 $31 15 $15 51 87 $3 123 $32 16 52 XOUT 88 124 17 $62 53 89 $4 125 $33 18 $63 54 Vss 90 S5 126 $34 19 55 HXIN 91 127 20 S64 56 92 S6 128 $35 21 57 XHOUT 93 $7 129 22 COM16 58 94 Sg 130 $36 23 COM15 59 TEST 95 131 $37 24 60 BRESET 96 Sg 132 25 COM 14 61 IN1 97 $10 133 $38 26 COM13 62 IN2 98 $11 134 $39 27 COM12 63 IN3 99 135 S40 28 64 100 $12 136 29 cOM11 65 IN4 101 $43 137 $44 30 cOM10 66 cM 102 138 $42 31 cOM9 67 SDAT 103 $14 139 $43 33 COM8& 68 SCK 104 $15 140 S44 33 COM7 69 1001 105 $16 141 S45 34 COM6 70 1002 106 $17 142 S46 35 COM5 71 1003 107 $18 143 S47 36 cOM4 72 1004 108 $19 144 S48 8 2001-06-27TOSHIBA JTMP04030-XXXS MEMORY MAP 1. Program ROM The instruction word of T4X is 16 bits long. Op-codes and operands are executed in one-word units. Program ROM consists of 4K words per page. The internal program ROM area is 8 pages (32 Kwords). This program ROM area can be used for constant data ROM. In this case, it can be used in byte units (1 byte = 8 bits). PAGE PAGE 1~7 (Note) When coding interrupt entry addresses, use a CALL instruction. 1 word Upper byte Lower byte 0000H RESET START 0001H 0002H 0003H 0004H 0005H 0006H 0007H OFFFH 1000H 7FFFH --b-4 4 Fig.2 Program Memory Map Code NOP for interrupts not used. Example CALLA NOP CALL B NOP NOP NOP NOP ' ; INTO ; INT1 ; INT2 INT3 INT4 INT5 INT6 2001-06-27JTMP04030-XXXS 2001-06-27 Stack Area BankO Address _. 7 BoA 9 8 DC Fig.3 Work RAM 10 r T r mo I I I I I ! ! I I I I \ I ! \ w Pelt bt dt c i rr | OTT 1 r ru t I G 1 ee | es en | I oyot re | mo f--L-4-- 14-bit d e e I toto oboe oy ot toy tot 1 ee | es en | 1 oy ol er ee Sorento cha 4b 4 poor -4--p--r-4-- 1 ee | es en | toy ot en ee 1 1 1 1 1 I I 1 1 l | I l tL T T T T T T T T T T 1 T T T a N ! 1 1 1 1 1 1 1ot ! | 1 1 I ! ~ P--L-4--L--L-4--L--L deb Lt LL - c toro root roropeot 1 oy ol ty 1 a ee | pooh -4--+--P-d-- t-te pot fF -- I- 4 ! 1 1 1 1 1 1 I I 1 1 I 1 1 I ! roa Lott Lott oat og 1 ET Tp in oro | 1 oto oy ot I oy 1 l 1 L L L L L L L L L L -4--L__ Lod - ' CT roto a ee | a 1 ! I I ! I I I I I I l l I I I I I I ~ morc tr cba desde cbr senda nba nb nnn bebe tana aches 1 ee | es en | 1 1 o ! ! l ! 1 1 1 1 1 l I I 1 3 I \ ! TR TTT ' ' | ' l l l l l 1 1 l l I I I ' -5--7--L-=--4--L-HL de LL dL Lg Ee ge TT a 7 I 7 i ! ! ! ! 1 1 1 1 1 1ot 1 14 1 I ! an feed A --p-4--4--b-a-- tool 1 ororpeiot 1 I 14 1 boii 1 Bl S| SF] a] al 2] @ Pos prereset saa t--F-4-- 1 ool ee | 1 I -tu-te bed Logie L--b-4-- 1 en er T 1 m| oO alot n ' Loe \ ! wl t| at] al apo] & poppe t-- 1 1 ed | 1 I Sars tr crc tcc rc yo TooRra-7 1 ee ee | 1 I eal olal st] ec] ola pe--L_dt_o_ dt bt Ligeti po wm) ml tl eal apo] = cod TOTP TTT I 1 1 ool 1 oto 1 1 --L-4d--4--bL-4--4--L-4 i--4 tool 1 oro 1 I - | es en | 1 I Bln} @] BL RP S| cs] oe p--P-4--4--F-4--+--1+-4 1 ool 1 oto 1 I Lid toot i L SOD TT ae a] ol w | es en | 1 N 8) 8] $] 8] RR] S| potent pepo ool es en | 1 atc toch Han tora tool es ee | 1 = lo = 1 ol ee ee | 1 o| B] Se] a] a] al 2 POAT TTT Te Tarte | es en | 1 WJd--L--L-Jo-u-L--Le de 11 rrr od 1 al st] ol ol ofa] + iI--4 be----4--4 I wlio] t[ om] al ante pO tae 1 ee ee 1 TAT TTT TTT TTT | es en | 1 aml[ ul an} alo] m| wo Low tebe Ld wl mw] tt] mol of af] = 1 T T 1 1 T I ool es en | 1 2. Word RAM TOSHIBA 1024 x 4 bitsTOSHIBA JTMP04030-XXXS Work RAM consists of 1024 x 4 bits. R/W is performed at the address specified as fllows. (1) (2) (3) (4) Indirect addressing mode (Fig.4 (a) ) Specify a bank using DMB, a page using the H-Register, and an address in the page using the L-register. (Example) LD A, M : AjRAM (HL) Directly addressing mode (Fig.4 (b) ) Directly specify an address in the bank using the 8 bits (operand) in the instruction field. (Example) LDI 2CH, OAH : RAM (2CH) < AH Index addressing mode (Fig.4 (c)) Specify an address in the page using the sum of the LRegister contents and the 4 bits (operand) in the instruction field. (Example) LDRI 4H, 3H : RAM (HL + 4) < RAM (3H, L) LeL+1,AA- 1 Bank selector F-REGISTER BIT 3 BIT 2 BANK SWITCHING DMBO DMB1 0 0 Bank 0 1 0 Bank 1 0 1 Bank 2 1 1 Bank 3 Pages 8 to F in Bank 0 can be used as a stack. When using the CALL/CALLS instruction, or when the interrupt request occurred, the current contents of the program counter and the program memory bank are stored on the stack. The program returns using the RET instruction to the return address stored on the stack. The PUSH instruction is used to store register data, two 8 bit registers at a time, in the stack. The POP instruction is used to return the data to the registers. DMBO, 1 HR LR (a) Indirectly Addressing Instruction Field T | XXXX \ XXXX | or T | | XXXX \ XXXX | DMBO, 1 T RAM Address | XXXX | XXXK (b) Directly Addressing Instruction Field | | yyyy | 1 + LR RAM Address [| 1 Z22Z (c) Index Addressing Fig.4 Addressing mode The size of the stack is up to 64 bits (0 to 64), with each stack consisting of 8 bits. 11 2001-06-27TOSHIBA JTMP04030-XXXS 3. Data RAM JTMP04030-XXXS has a 4 Kbit data RAM (256 addresses x 2 banks x 8 bits). Addressing and data read/write is done using the register file as follows. Address (PB5) c A 0 1 Qo wet rrr rt tests cesses D E F ( 1 1 i 1 1 1 ) I I I I I I ss 4----H-----}--------------------4-----b----4----4 1 1 1 1 1 1 1 1 1 1 1 1 1 p----4t____ Hee booed I Po 2 1 1 1 b---- pecee eee pone noe eae ee +a - ee 4----- pan---t----4 ! 1 I 1 1 1 1 Page i 1 I 1 1 1 1 Bank 0 ea) ) | Hoo Ho eo} ! 1 1 1 1 1 1 1! p---- 4----a----- f-------------------- 4----- P----+----4 1 1 1 1 1 1 D 1 I 1 1 1 1 doe de bee eee 1 1 1 1 I 1 E cat De em mgs eee p eem pe mn F 1 1 1 1 1 1 1 1 1 1 1 1 r 1 1 1 1 1 1 0 1 1 1 1 1 1 Le te----Jo- Le dL 1 1 i 1 I 1 1 too potct fs hotels eine Pott ssa qccctt procs ! 1 1 1 1 1 1 Pot Poot | | i 1 1 1 Bank 1 1 1 1 ! i I i I 1 1 (PB30) Page ' ! ' ! | ! ! 9 < ! I l I I I I (PB4) ! I I I I c D E F \ Fig.5 Data RAM Before writing /reading data to/from data RAM, CE (PBOQ) must be set to 1. Before executing the HALT instruction, CE (PBO0) must be set to 0. 3 2 1 0 PBO CE Initial Value 0 CE : 0-Disables data RAM. 1-Enables data RAM. 12 2001-06-27TOSHIBA JTMP04030-XXXS The addresses of data RAM are set using RAB (PB31), RAR 1 to RAR4 (PB4), and RAC1 to RAC4 (PB5). Bank: 3 3 1 0 PB3 RAB Initial Value 0 RAB_: Q Selects bank 0. 1 Selects bank 1. Page: 3 ) 1 0 PB4 RAR4 RAR3 RAR2 RAR1 Initial Value 0 0 0 0 RAR1 to RAR4 : Set page in a Bank. Address : 3 3 1 0 PB5 RAC4 RAC3 RAC2 RAC1 Initial Value 0 0 0 0 RAC1 to RAC4 : Set addresses in a page. Data at the addresses specified by the bank, page, and address registers are read/ written through RAD1 to RAD8 (PB6, PB7). Since data are read/written in units of 8 bits, use 8 bit transfer instructions, not 4 bit transfer instructions. Setting AINC (PA23) to 1 increments by 1 the address in a bank every after data writing / reading. This is useful for continuous data write or read. Note that at auto increment on, write must be performed after one cycle or more. Continuous write does not automatically increment the address. 3 2 1 0 PB6 RAD4 RAD3 RAD2 RAD1 Initial Value * * * * PB7 RAD8 RAD? RAD6 RAD5S Initial Value * * * * * : Undefined RAD1 to RAD8 : 8bit data at the address specified by the data RAM bank, page, and address registers. 3 2 1 0 PA2 AINC WDT2 WDT1 Initial Value 0 0 0 AINC : 0-Auto increment OFF 1-Auto increment ON 13 2001-06-27TOSHIBA JTMP04030-XXXS 4. Display RAM JTMP04030-XXXS incorporates display RAM. Data are set and addressing is performed using the register file. Before writing or reading display RAM, DRCE (PC32) must be set to 1. Before executing a HALT instruction, DRCE (PC32) must be set to 0. 3 2 1 0 PC3 LOWCP DRCE DON DSTA Initial Value 0 0 0 0 DRCE: 0-Disables display RAM. 1-Enables display RAM. Addresses in display RAM are set using DRR1 to DRR4 (PC4) and DRC1 to DRC3 (PC5). (DRR1 is the least significant bit, DRC3 the most significant bit) 3 2 1 0 PC4 DRR4 DRR3 DRR2 DRR1 Initial Value 0 0 0 0 PC5 DRC3 DRC2 DRC1 Initial Value 0 0 0 DRR1 to DRR4 . . . DRC1 to DRC3 } : Used to set addresses in display RAM. Data DRD1 to DRD8 (PC6, PC7) are read from/written to the specified address. Since data are read / written in units of 8 bits, use 8 bit transfer instructions, not 4 bit transfer instructions. 3 2 1 0 PC6 DRD4 DRD3 DRD2 DRD1 Initial Value * * * * PC7 DRD8 DRD7 DRD6 DRD5 Initial Value * * * * * : Undefined DRD1 to DRD8 : 8 bit data in display RAM 14 2001-06-27JTMP04030-XXXS TOSHIBA DRD DRD DRD DRD DRD DRD DRD DRD Nn mM FF nN mM TF - N o Oo OO - N Oo MW Wo YW SVT VSS SSeS SSeS A WW Fa FR WO TST STS SS SS SS KK =~ BW Wa Ww - a S > 3 A 7 proooo nn cmco nn cn cc nnnnncenccnc be Wee eee eed = = S 8 g = S 8 8 ppm penned = S 8 ponooo nn mmcocnn cnc nnnnn ce nccn che ee eee eed 2 = 8 8 papoco nn mnconnn nce nnnnn ce ncnn che ee eee eed 2 = S 8 prooocnncnconnncn ce nnnnnnncn nc he ee eee eee _d 2 = 8 8 panooo nn cococnn cnc cnnncn ce nenn be ee eee eed 2 S 8 8 xc xt Lt xc mt tt Lt xc xt. Oo - AN -----H- HK oO w & @o@ = ~~~ oOo ww a) am 1 SF + a Fig.6 Display RAM 2001-06-27 15TOSHIBA JTMP04030-XXXS REGISTER FILE The register file contains general registers and peripheral circuit control registers. 1. Flag (F) register (ROO) F Register MSB 3 2 1 0 LSB ROO DMBQ DMB1 ZF CF CF : Carry flag ZF : Zero flag DMB1 : Select work RAM bank. DMBO : DMBO DMB1 WORK RAM BANK 0 0 Bank 0 1 0 Bank 1 0 1 Bank 2 1 1 Bank 3 2. Accumulator (A) register (RO1) 3. H-, L-register (RO3, RO2) The H- and L-registers are used to set work RAM addresses in the bank specified by DMB. H-Register MSB 3 2 1 0 LSB RO3 HR3 HR2 HR1 HRO Nn _/ yo Work RAM page L-Register MSB 3 2 1 0 LSB RO2 LR3 LR2 LR1 LRO NN _/ ~y Work RAM address 16 2001-06-27TOSHIBA JTMP04030-XXXS 4. Bank (B) register (RO7) The B register is used as a ROM page. MSB 3 2 1 Oo LSB RO7 3 2 1 0 0000 = page 0 0001 =page 1 0010 =page 2 0011 =page 3 0100 =page 4 0101 =page 5 0110 =page 6 0111 =page 7 5. D-register, E-register, P-register D-, E- and P- are general-purpose registers (R05, RO4, RQ6). When using ROM as a data table, the B-, P-, D-, and E-registers are used to set ROM addresses. (Data table function : The user can store constants in ROM in advance and access the constants using the LDBL and LDBH instructions.) 17 2001-06-27JTMP04030-XXXS TOSHIBA SL ~ SXXX OOPOdWLE pauyapun sueaw yue|q (3}0N) | ___SWLVOS fd lwivds |. OP4 ts VSWHD b2sw_ of tSD J rezk yd be Oildi a1 | ..9VLVOS | evivds |__| ZNAdWD | ENadAD of 22S] USD Wed L Lia! (4d) |___4Wivds | evivds | weout | MEL |__| suo tsa Pd Z Lig: Z evivas pVLVvds N3ZDL LId as | __SCHOVIN, | LeHQVIN, 1 S@HDL] bZM] SPMD PMOL] PIOL ENOL! LT 1 LLNIT O.Lla} ast |e eeeeee ee | SCHON 1 Q9@MDL] Ee e@MDLY I GLMOL] ZEW] SION) CNOI] TI) CLNIIY | L wa (xad) Lone -ee oe o f ECYOW 1 cdo. po SCHL EPMO] SEM LT ETON ENOU) ET) ESN Z 18) 3 y7udvl t Lig! gsi |} SLXQVIN, | LLMGWIN LGW STN IS Oa Ola: as] p-SEYQVIN, | cheOvin yt @WdN | SAWS SS 25ON all bla (*dd) [aoe enennnn nf ELMOWN TO Aiday [onus gore ia s INIW 1g: as }_...SGug_ | taud ft toed S| GOINGS aa eee ee Oia: 857 [gaya | aug zug | aa | Nog" "|" "zagowas |" aaa [wa | {Lig} (x04) }..--40uG | eau ft EON Eee | I EGU L_-_- Ves 1a! v LI: GSI _---fOVe ee Olid; as1 [gave ave va ave Lia! (Xda) ----f2VN EV @ Lid: E POV" LIG' SSW O18 [RIL sik [tM | L000) | Lodol| | LONI | EES wanneefunneee- i 2it | asta [eal | SL | LM | 200011 zOGOI| | ZOQNI] F Lie (Wd) Ell of ER ESI OOO! TEGOOTT EQON) Zig: g Lig as L Ola! 9s7 L (dS) Y3LNIOd |b Lig (xLu) | een nee n ee ee ZOO! | ETO! ELOO! AIVLS Le 11a t yzOOl | yzd0l 0 LIG|aSW LOLI8: a1 WaISIDSU- | YISIDAXd | YALSIOING | YALSIDINS | YaLSIDIN-H | UYALSIDANT | wALSIDIW-W | YaLSIDIY-4 |b 1a) 0 [z 118 1d: asW aL] avae | alm] avay | sina] avay | alan] avay | SLAn] way | aA] away | aim] away | ala] away | AA/Y (ada) Lia-pieddy Lid-743amo7 Lia-paeddn LIG-749M07 Lid-vieddn LIg-7iaMo] Lia-viaddn Lig-yJamo7 | ssayddav ee v 0 LId-8 9 v z L 0 ssaudav 31d 431S193y 2001-06-27 18TOSHIBA JTMP04030-XXXS EXPANDED REGISTER FILE ADDRESS | "\anae 3 2 1 0 00H ERO HCPON P2 P1 01H ER1 IISL4 IISL3 IISL2 IISL1 02H ER2 1OSL13 lOSL12 1OSL11 03H ER3 1OSL23 lOSL22 IOSL21 04H ER4 1O$L33 IOSL32 1OSL31 05H ER5 IOSL43 IOSL42 IOSL41 06H ER6 SET14 SET13 SET12 SET11 07H ER? SET18 SET17 SET16 SET15 08H ER8 SET24 SET23 SET22 SET21 09H ERY SET28 SET27 SET26 SET25 OAH ERA 10184 10183 10182 101$1 OBH ERB 10254 10283 10282 10251 OCH ERC SIGC SIGB SIGA 19 2001-06-27TOSHIBA JTMP04030-XXXS PERIPHERAL CIRCUITS Peripheral circuits can be read /written/set via the register file. 1. Oscillator Block The CPU clock is generated by the oscillator circuits as an asynchronous low-speed or a high-speed High-speed clock. Oscillator , E Clock Gear fy AAA W CKG1, 2 CPMODE1, 2 12 TP Low-speed . System CP = Oscillator FL | Level Shifter Generator Circuit f= CPU Clock et + Fig.7 Oscillator Block 3 2 1 0 PC2 CKG2 CKG1 CPMODE2 CPMODE1 Initial Value 0 0 1 1 CPMODE1, 2. : Set oscillator mode. CKG1, 2 : Set high-speed oscillation divider. Oscillator modes are controlled by CPMODE1 (PC20) AND CPMODE2 (PC21) of the register file. CPMODE | CPMODE | LOW-SPEED HIGH SPEED | SYSTEM MODE 2 1 OSCILLATOR | OSCILLATOR cP NAME 0 0 OFF OFF OFF (CPM0) 0 1 ON OFF Low-speed (CPM 1) 1 0 OFF ON High-speed | (CPM2) 1 1 ON ON High-speed (CPM3) (Initial value) The high-speed oscillation divider are controlled by CKG1 (PC22) and CKG2 (PC23) of the register file. Signals divided by the divider are supplied to the system CP generator circuit and peripheral circuits such as the timer/ counter. CKG2 | CKG1 | DIVISOR 0 0 Source clock (Initial value) 0 1 1/2 1 0 1/4 1 1 1/8 20 2001-06-27TOSHIBA JTMP04030-XXXS Reset START oT Mode | High-speed Mode INT. HALT at CPM1 Stop Low-speed HALT Mode HALT at CPMO Mode INT. Mode (Low speed ON) CPU STOP Fig.8 Mode Status CAUTIONS 1. Do not set the system CP to low-speed when the low-speed oscillator is not in operation or before the oscillator is stable. Do not set the system CP to high-speed when the high-speed oscillator is not in operation or before the oscillator is stable. The low-speed oscillator circuit has a warm-up function. However some crystal oscillators do not start oscillating within the warm-up time decided by hardware-timer. Thus, in order to start the low-speed oscillator, take appropriate warm-up time using soft ware- timer. Executing an instruction to change from CPM1/2/3 to CPMO does not actually change to CPMQ. The mode changes to Stop after a HALT instruction is executed. 21 2001-06-27TOSHIBA JTMP04030-XXXS 2. Interrupt function Interrupts are triggered by IN1 to IN4, 1001 to 1004, timing, timer/counter, melody, or SIO. (Interrupt priority) The interrupt priority is specified by P1 (EROO) and P2 (ERO1) of the expanded register file. 3 2 1 0 ERO HCPON P2 P1 Initial Value 0 0 0 P2 P1 INTO INT1 INT2 INT3 INT4 INT5 INT6 0 0 IINT IOINT ~ TIN TCIN1 TCIN2 MIN SIN 0 1 TIN IINT IOINT TCIN1 TCIN2 MIN SIN 1 0 TCIN1 TCIN2 IINT IOINT ~-TIN MIN SIN 1 1 SIN TCIN1 TCIN2 IINT IOINT TIN MIN (high) priority (low) IINT: IN1 to IN4, IOINT: 1001 to 1004, TIN : timing TCIN1: timer/counter 1, TCIN2: timer/counter 2 MIN : melody, SIN : SIO 22 2001-06-27TOSHIBA JTMP04030-XXXS (Interrupt enable / disable) Interrupts (IINT, IOINT, TIN, TCIN1, TCIN2, MIN, SIN) are enabled /disabled as follows: INT > WEI~4 JOINT : IOE1~4 TIN > TINE TCIN1 : TC1E TCIN2 : TC2E MIN > MINE SIN : SINE Interrupts with priority by P1 and P2 are enabled/disabled by INTO to INT6. At initial settings, disable interrupts which are not required, using IIE1 to IIE4, IOE1 to IOE4, TINE, TC1E, TC2E, MINE, or SINE. 2 R12 INT1 Initial Value 0 R13 INT5 Initial Value 0 INTO to INT6 : O-Disables an interrupt 1-Enables an interrupt (Interrupt reset) After an interrupt generation is detected, reset the interrupt as follows: First, reset the interrupt latch by disabling the interrupt using the interrupt enable/disable register, then reset the core interrupt latch circuit by setting interrupt enable/disable using R12 or R13 of the register file. 23 2001-06-27JTMP04030-XXXS TOSHIBA uoneinGiuo> yinsI> ydnwua}U| Jo Wesbeig ojq | 614 Be SXXX OEOPOdALLE td @d 3NIS | | W%L 13231 ols Ynoa!> yey YN) yr7e7 q 2 Ja}uNoD/J9WI, b ydnusaquy NIS ZNIDL qdnwajul ANIA MISL 1LDL spoon MINIW|D YpIeT INDI YReF J 1 saqunep sau, t ydnwaqu] NIA INIDL qWhauaquy Po LS a]lp 4938181 50 | ELu 10 ZLY OF} SOWA yesay | NID + yn yaze7 oT j. pe ne BU ydnuisyn sion-e naa YaeT pares uO arf ydnuequ) A wand . Jn 9~O1NI Ayu0ud et 3dnaia3u) v~La0l tT P ANIO! ?~INOI 3803 ~<F Po ball t P <t # nae +49) b~LNI Anil P~LLNII v 2001-06-27 24TOSHIBA JTMP04030-XXXS 2-1. IN Interrupt (Interrupt enable/disable) 3 2 1 0 PDO 1E4. NE3 IE2 11E1 Initial Value 0 0 0 0 IIE1 to IN4 : 0-Disables an interrupt 1-Enables an interrupt Disabling interrupts resets also the interrupt data. (Interrupt data read) 3 2 1 0 PEO (R) IINT4 IINT3 IINT2 IINT1 Initial Value 0 0 0 0 PEO (W) IIL4 IIL3 IIL2 11L1 Initial Value 0 0 0 0 IINT1 to IN4 : Interrupt data 0-No interrupt 1-Interrupt generated IIL1 to IN4 : Interrupt level /edge select 0-High-level interrupt 1-Rising-edge interrupt * Detecting a high-level interrupt requires the input pin to remain at high level for two or more cycles of the low-speed clock. Even when level interrupt is selected, an edge interrupt latch holds interrupt data. Thus, when the interrupt type is changed from level to edge, interrupts must be cleared (disabled). 25 2001-06-27TOSHIBA JTMP04030-XXXS 2-2. 100 Interrupt (Interrupt enable/disable) 3 2 1 0 PD1 IOE4 IOE3 IOE2 IOE1 Initial Value 0 0 0 0 IOE1 to IOE4 : 0Q-Disables an interrupt 1-Enables an interrupt Disabling interrupts resets the interrupt data. (Interrupt data read) 3 2 1 0 PE1 (R) ION4 ION3 ION2 ION1 Initial Value 0 0 0 0 PE1 (W) IOL4 IOL3 IOL2 IOL1 Initial Value 0 0 0 0 ION1 to ION4 : Interrupt data Q-No interrupt 1-Interrupt generated IOL1 to ION4 : Interrupt level /edge select 0-High-level interrupt 1-Rising-edge interrupt * Detecting a high-level interrupt requires the 1O pin to remain at high level for two or more cycles of the low-speed clock. Even when level interrupt is selected, an edge interrupt latch holds interrupt data. Thus, when the interrupt type is changed from level to edge, interrupts must be cleared (disabled). 26 2001-06-27TOSHIBA JTMP04030-XXXS 2-3. Timing Interrupt (Interrupt select) 3 2 1 0 PA3 TIS4 TIS3 TIS2 TIS1 Initial Value 0 0 0 0 TIS1 : Q-Selects a 128 Hz interrupt 1-Selects a 256 Hz interrupt TIS2 : Q-Selects a 16 Hz interrupt 1-Selects a 32 Hz interrupt TIS3 : Q-Selects a 4Hz interrupt 1-Selects a 8 Hz interrupt TIS4 : Q-Selects a 1 Hz interrupt 1-Selects a 2 Hz interrupt Before changing the frequency of timing interrupts, disable the interrupts. (Interrupt enable/disable) 3 2 1 0 PA4 TIE4 TIE3 TIE2 TIE1 Initial Value 0 0 0 0 TIE1 : O-Disables a 128/256 Hz interrupt 1-Enables a 128/256 Hz interrupt TIE2 : O0-Disables a 16/32 Hz interrupt 1-Enables a 16/32 Hz interrupt TIE3 : O-Disables a 4/8 Hz interrupt 1-Enables a 4/8 Hz interrupt TIE4 : O0-Disables a 1/2 Hz interrupt 1-Enables a 1/2 Hz interrupt Disabling interrupts resets also the interrupt data. 27 2001-06-27TOSHIBA JTMP04030-XXXS 2-4. Timer/Counter 1, 2 Interrupt When either timer/counter 1 or 2 overflows or a match with the TIME/COUNT set value occurs, the corresponding interrupt is generated. 3 2 1 0 PFO TC1El TCIRI Initial Value 0 0 TC1El : 0-Disables a timer/counter 1 interrupt 1-Enables a timer/counter 1 interrupt TC1R : _f Resets timer/counter 1 interrupt data 3 2 1 0 PF1 TC2El TC2RI Initial Value 0 0 TC2El : 0-Disables a timer/counter 2 interrupt 1-Enables a timer/counter 2 interrupt TC2RI: _f Resets timer/counter 2 interrupt data When timer/counters 1 and 2 are linked to make a 16 bit timer/counter, a timer/counter 1 interrupt only can occur, but a timer/counter 2 interrupt cannot. In such a case, the settings in TC2El and TC2RI are invalid. The 16 bit timer/counter is controlled by settings in TC1El and TCIRI. 28 2001-06-27TOSHIBA JTMP04030-XXXS 2-5. Melody Interrupt An interrupt occurs at the end of playing melodies. 3 2 1 0 PD5 MINE REPLY MPM2 MPM 1 Initial Value 0 0 0 0 MINE : 0-Disables a melody interrupt 1-Enables a melody interrupt 2-6. 8bit Serial Transfer Interrupt An interrupt occurs at the end of serial transfer. 3 2 1 0 PD2 SINE SSTA SRSEL SIO Initial Value 0 0 0 0 SINE : 0-Disables an 8 bit serial transfer interrupt 1-Enables an 8 bit serial transfer interrupt 29 2001-06-27TOSHIBA JTMP04030-XXXS 3. Timing Circuit Timings are generated using the low-speed clock as the source clock. timings selected by PA3 of the register file. TSTOP Stop / Reset Divider Divider FL 256 Hz Timing Selector Switches between 32 kHz and 36 kHz. FLSEL Timing Data Register (PA6 of register file) > TIN Fig.10 Block Diagram of Timing Signal Supply 4 is PA3 of register file 3 2 1 0 PA5 FLSEL TSTOP Initial Value 0 0 TSTOP : 0-Resets and stops the entire timing circuit. Also stops supplying clocks to the melody circuit. 1-Timing circuit operates FLSEL : Q0-When low-speed crystal is 32.768 kHz 1-When low-speed crystal is 36.864 kHz Specify timing interrupt frequency in PA3 of the register file. 3 2 1 0 PA3 TIS4 TIS3 TIS2 TIS1 Initial Value 0 0 0 0 TIS1 : O-Selects a 128 Hz interrupt 1-Selects a 256 Hz interrupt TIS2 =: O-Selects a 16 Hz interrupt 1-Selects a 32 Hz interrupt TIS3 =: O-Selects a 4Hz interrupt 1-Selects a 8Hz interrupt TIS4 =: Q-Selects a 1Hz interrupt 1-Selects a 2 Hz interrupt Interrupts are generated at 30 2001-06-27TOSHIBA JTMP04030-XXXS The selected timing interrupts can be enabled, disabled, or reset using PA4 and PA7 of the register file. The occurrence of each Interrupts can be read using PA6 of the register file. 3 2 1 0 PA4 TIE4 TIE3 TIE2 TIE1 Initial Value 0 0 0 0 TIE1 : Q-Disables a 128/256 Hz interrupt 1-Enables a 128/256 Hz interrupt TIE2 : O-Disables a 16/32 Hz interrupt 1-Enables a 16/32 Hz interrupt TIE3 : OQ-Disables a 4/8 Hz interrupt 1-Enables a 4/8Hz interrupt TIE4 : Q-Disables a 1/2 Hz interrupt 1-Enables a 1/2 Hz interrupt 3 2 1 0 PA7 (W) TIR4 TIR3 TIR2 TIR1 Initial Value 0 0 0 0 TIR1 : Clears 128/256 Hz interrupt data TIR2 : Clears 16/32 Hz interrupt data TIR3 : Clears 4/8 Hz interrupt data TIR4 : Clears 1/2 Hz interrupt data. Clears interrupt data at write (IL). Clear status is not held. 3 2 1 0 PAG (R) TI4 TI3 Tl2 TI Initial Value 0 0 0 0 Ti1 =: 128/256 Hz interrupt data TI2 : 16/32 Hz interrupt data TI3. : 4/8Hz interrupt data TI4. : 1/2Hz interrupt data. 0O-No interrupt 1-Interrupt generated 31 2001-06-27TOSHIBA JTMP04030-XXXS 4. Timer/ Counter Circuit The timer/ counter circuit can be used as an 8 bit x 2-channel or 16 bit x 1-channel timer/ counter. The timer/counter can also be used as general-purpose timer/counter or multi interrupts. The circuit can be switched between 8 and 16 bits using TCPS (PF34) of the register file. The source clock can be selected from low-speed, high-speed, or external clock. Divider Stop/Reset TCO fy a . o Divider Circuit (15 bit) f| o Switching 1 TCFSL | Selector 1 ! Selector 2 I 1004 I l t 7a CKS11 CcKS21 12 22 13 23 TCRI1~TCR1 TCR21~TCR28 TCIN1 CRIB TCIN2 Interrupt CK1 Interrupt 8 8 8 bit Selector : 8 bit wee eee eee eee eee] lL Ce nee nn ee eee ee eee CK2 Compare Register Compare Register Switching 8 TCPS 8 SET11~18 SET21~28 Control Circuit Fig.11 Block Diagram of Timer / Counter 32 2001-06-27TOSHIBA JTMP04030-XXXS Timer / counter source clock frequencies are selected as below: 3 2 1 0 PF2 TCFSL CKS13 CKS12 CKS11 Initial Value 0 0 0 0 PF3 TCPS CKS23 CKS22 CKS21 Initial Value 0 0 0 0 TCPS : O-8bit timer/counter x 2-channel 1-16 bit timer/counter x 1-channel TCFSL : Timer source clock frequency select 0-Low-speed (f,) 1-High-speed (fy) CKS11 to CKS13 } Timer/counter 1, 2 source clock select CKS$21 to CKS 23 SOURCE CLOCK SELECT BIT SELECTED SOURCE CLOCK FREQUENCY cxsi3_ | cks12_ | cksit | DIVISOR | 4, 1S>GgkHz| fy = 2 MHz 0 0 0 215 1Hz 61.0 Hz 0 0 1 213 4Hz 244 Hz 0 1 0 2" 16 Hz 977 Hz 0 1 1 29 64 Hz 3.91 kHz 1 0 0 27 256 Hz 15.6 kHz 1 0 1 2 1024 Hz 62.5 kHz 1 1 0 2? 4096 Hz 250 kHz 1 1 1 2! 16.384 kHz 1.00 MHz cxsaa | cxs2z | cxsar | SELECTED |, TRUSS | (TCS aT 0 0 0 2's 1 Hz 61.0 Hz 0 0 1 213 4Hz 244 Hz 0 1 0 2" 16 Hz 977 Hz 0 1 1 2? 64 Hz 3.91 kHz 1 0 0 27 256 Hz 15.6 kHz 1 0 1 25 1024 Hz 62.5 kHz 1 1 0 23 4096 Hz 250 kHz 1 1 1 1004 input signal is selected * When the source clock is changed, the timer/counter may count incorrectly. After changing the source clock, reset the timer/ counter. 33 2001-06-27TOSHIBA JTMP04030-XXXS Timer / counter is controlled by PF4 and PF5 of the register file. 3 2 1 0 PF4. TCIEN TCIR CMPEN1 CHASEL Initial Value 0 0 0 0 PF5 TC2EN TC2R CMPEN2 TCO Initial Value 0 0 0 0 CHASEL : 0- Eliminates chattering of 1004 signal 1- Does not eliminate chattering of 1004 signal CMPEN1 : 0- Generates an interrupt when timer/counter 1 overflows 1- Generates an interrupt when timer/counter 1 value matches the target value TC1IR : 1-Resets (Clears) timer/counter 1. After reset, counting restarts TC1EN _ : Q-Stops source clock input to timer/counter 1 1- Starts source clock input to timer/counter 1 TCO : O- Stops the divider circuit for supplying source clock 1- Starts the divider circuit for supplying source clock CMPEN2 : 0- Generates an interrupt when timer/counter 2 overflows 1- Generates an interrupt when timer/counter 2 value matches the target value TC2R : 1-Resets (Clears) timer/counter 2. After reset, counting restarts TC2EN : Q-Stops source clock input to timer/counter 2 1- Stops source clock input to timer/counter 2 * When a 16-bit single-channel timer/counter is selected (i.e. when PF3 <TCPS> =1), it can be controlled using PF4 (TC1EN, CMPEN1) of Timer Control Register 1 and PF5 (TC2R) of Timer Control Register 2. PF4 (TC1R) of timer Control Register 1 and PF5 (TC2EN, CMPEN2) are not used in this case. The 8-bit and 16-bit counters both have a margin for error of one source clock cycle (CK1 or CK2). 34 2001-06-27TOSHIBA JTMP04030-XXXS Timer / counter 1/2 data can be read from PE2, PE3, and PE4 of the register file. 3 2 1 0 PE2 TCR14 TCR13 TCR12 TCR11 Initial Value 0 0 0 0 PE3 TCR18 TCR17 TCR16 TCR15 Initial Value 0 0 0 0 PE4 TCR24 TCR23 TCR22 TCR21 Initial Value 0 0 0 0 PE5 TCR28 TCR27 TCR26 TCR25 Initial Value 0 0 0 0 Timer /counter 1/2 compare data are set using ER6, ER7, ER8, and ER9 of the expanded register file. 3 2 1 0 ER6 SET14 SET13 SET12 SET11 Initial Value 0 0 0 0 ER7 SET18 SET17 SET 16 SET15 Initial Value 0 0 0 0 ER8 SET24 SET23 SET22 SET21 Initial Value 0 0 0 0 ER9 SET28 SET27 SET26 SET25 Initial Value 0 0 0 0 (Notes) 1. To detect a match between the timer/counter value and the target value (SET11 to SET18, SET21 to SET28), first set the values in the expanded register file (ER6, ER7, ER8, and ER9), then set CMPEN1/2 to 1 (Match Detect mode). 2. When a 16 bit timer/counter is configured by linking timer/counters 1 and 2, and interrupts condition is set to match detection, set CMPEN1, CMPEN2, TC1EN, and TC2EN to 1. 3. When system clock is switched from low to high or vice versa using TCFSL, or the source clock is switched using CKS11 to CKS13 and CKS21 to CKS23 while a timer/counter is in operation, countup may malfunction. Before switching, set TC1EN and TC2EN to 0 (stop the source clock). 4. Do not use TCPS to switch between 8 bit and 16bit timer/counters while a timer/ counter is in operation, or data may be destroyed. 5. Timer/counter source clock and control instructions are asynchronous; thus, time is measured to a tolerance of up to 1 count of the source clock. 35 2001-06-27TOSHIBA JTMP04030-XXXS JTMP04030-XXXS incorporates a one-channel independent dedicated watchdog timer. Watchdog time can be selected from 32.768 kHz, 0.5, 1.0, or 2.0 seconds. Writing to PA2 of the register file clears the watchdog timer. 3 2 1 0 PA2 AINC WDT2 WDT1 Initial Value 0 0 0 WDT2 WDT1 OPERATION 0 0 Stop 0 1 Resets system at 0.55 1 0 Resets system at 1.05 1 1 Resets system at 2.05 (At 32.768 kHz of low-speed clock) * To run the watchdog timer, the timing circuit must be run. 36 2001-06-27TOSHIBA JTMP04030-XXXS 5. LCD Circuit The display status and duty of the LCD driver are set using PC3 of the register file and ERC of the expanded register file. Display duty can be selected from 1/8, 1/10, or 1/16. JTMP04030-XXXS incorporates a 5 x doubler circuit for supplying power to the LCD drivers. DUTY | FRAME FREQUENCY COMMON SEGMENT 1/8 97.5 Hz COM1~COM8 31~S64 1/10 117.0 Hz COM1~COM10 $1~S64 1/16 97.5 Hz COM1~COM16 S1~S64 The LCD driver circuits are controlled by DSTA (PC30) and DON (PC31) of PC3 of register file. Access to display RAM is enabled /disabed using DRCE (PC32). 3 2 1 0 PC3 LOWCP DRCE DON DSTA Initial Value 0 0 0 0 DSTA _: 0-Fixes all commons and segments to Vss level 1-Normal display possible DON : Q-Sets the 5 x doubler circuit to off 1-Sets the 5 x doubler circuit to on DRCE_ : 0-Disable display RAM 1-Enable display RAM LOWCP : 0-Stop supplying the low speed clock to the LCD driver 1-Supply the low speed clock to the LCD driver The display duty is selected using SIGA (ERCQ), SIGB (ERC1), and SIGC (ERC2) of ERC of the expanded register. 3 2 1 0 ERC SIGC SIGB SIGA Initial Value 0 0 0 SIGC SIGB SIGA Duty 1 0 0 1/8 0 1 1 1/10 0 0 0 1/16 (Note) Do not set other than the above. 37 2001-06-27TOSHIBA JTMP04030-XXXS 5 V4 COM! Vss cOM2 Vss coMi16 | 4 Vss $1 Vss FL FR Fig.12 1/16 Duty Display Output Waveform (Note 1) When the low-speed oscillator is not operating, display is not output even if the high-speed oscillator is operating. (Note 2) DON and DSTA of PC3 of the register file are read into the LCD circuit according to the clock generated by display clock LOWCP. Therefore, after DON and DSTA are updated, LOWCP (PC33) must be set to off after up to 103 ms (32.768 kHz of low-speed clock). 38 2001-06-27TOSHIBA JTMP04030-XXXS 6. Melody Circuit The melody is automatically played according to the melody data stored in data RAM. (Data RAM) Bank 1 0 Po pet mnt nnn nnn nnn nnn enn nnn nnnnnn= E F (Address) Melody Address Control bz & Buzzer . a, Melody Melody Timing _ Driver Melody Oscillator Circuit Control 32 Hz BZ kK 16 Hz 8Hz AHz HH Fig.13 Melody Play Block Set Melody Play mode using PD5 of the register file; set the play start address using PD6, PD7, PE6, and PE7 of the register file. 3 2 1 0 PD4 CRYO CRYS MLSEL Initial Value 0 0 0 PD5 MINE REPLY MPM2 MPM1 Initial Value 0 0 0 0 PD6 MADR14 MADR13 MADR12 MADR11 Initial Value 0 0 0 0 PD? MADR16 MADR15 Initial Value 0 0 PE6 MADR24 MADR23 MADR22 MADR21 Initial Value 0 0 0 0 PE7 MADR25 Initial Value 0 CRYS 0 ; Melody mode 1 ; Remote Control mode CRYO 0 ; Sets the BZ output pin to Low 1 ; Outputs remote carrier (low-speed Lin Remote Control mode oscillation) from the BZ output pin MLSEL: O ; Generates the scale from the melody oscillator 1; Generates the scale from the highspeed oscillator 39 2001-06-27TOSHIBA JTMP04030-XXXS MPM1, 2 : SET PLAY MODE MPM2 MPM 1 MODE DESCRIPTION 0 0 STOP Stops play 0 1 LONG Continuous play up to 16 seconds. Start address: [11]o00000~ [11]111111 COH FFH MADR11~6 1 0 SHORT1 |Halves melody data area. While playing the SHORT1 area, music note data in the SHORT2 area can be modified. Start address: [110]oo000~ [110]11111 COH DFH | MADR11~5 1 1 SHORT2 |Halves melody data area. While playing the SHORT2 area, music note data in the SHORT1 area can be modified. Start address: [111 ]ooo00~ [111] 11111 EOH FFH f MADR21~5 REPLY : 0-Automatically shifts to Stop mode 1-Repeats play from start to end addresses in the same mode MINE : 0-Disables melody interrupts (also resets interrupt data MIN) 1-Enables melody interrupts Note: Play stop (MPM 1,2 = Q) interval must be longer than five periods of low-speed clock. 40 2001-06-27