DATA SH EET
Product specification
Supersedes data of 1998 Aug 31
File under Integrated Circuits, IC24
1999 Sep 20
INTEGRATED CIRCUITS
74ALVCH16623
16-bit transceiver with dual enable;
3-state
1999 Sep 20 2
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
FEATURES
•Complies with JEDEC standard
no. 8-1A
•CMOS low power consumption
•Direct interface with TTL levels
•MULTIBYTE flow-through
standard pin-out architecture
•All data inputs have bus hold
circuitry
•Output drive capability 50 Ω
transmission lines at 85 °C
•Current drive ±24 mA at 3.0 V.
DESCRIPTION
The 74ALVCH16623 is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS compatible TTL families.
The 74ALVCH16623 is a 16-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions.
This 16-bit bus transceiver is designed for asynchronous two-way
communication between data buses. The control function implementation
allows maximum flexibility in timing. This device allows data transmission from
the A bus to the B bus or from the B bus to the A bus, depending upon the logic
levels at the enable inputs (nOEAB,nOEBA). The enable inputs can be used to
disable the device so that the buses are effectively isolated. The dual enable
function configuration gives this transceiver the capability to store data by
simultaneous enabling of nOEAB and nOEBA. Each output reinforces its input in
this transceiver configuration. Thus, when all control inputs are enabled and all
other data sources to the four sets of the bus lines are at high-impedance
OFF-state, all sets of bus lines will remain at their last states. The 8-bit codes
appearing on the two double sets of buses will be complementary. This device
can be used as two 8-bit transceivers or one 16-bit transceiver.
To ensure the high-impedance state during power-on or power-down, OEBA
shouldbetiedtoVCC throughapull-upresistorandOEAB shouldbetiedtoGND
through a pull-down resistor; the minimum value of the resistor is determined
by the current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a
valid logic level.
QUICK REFERENCE DATA
Ground = 0; Tamb =25°C; tr=t
f= 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
CL= output load capacitance in pF;
fo= output frequency in MHz;
VCC = supply voltage in Volts;
Σ(CL×VCC2×fo) = sum of outputs.
2. The condition is VI= GND to VCC.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay nAn,nB
nto nBn,nA
nC
L= 30 pF; VCC = 2.5 V 2.0 ns
CL= 50 pF; VCC = 3.3 V 1.9 ns
CI/O input/output capacitance 10.0 pF
CIinput capacitance 3.0 pF
CPD power dissipation capacitance per buffer notes 1 and 2
outputs enabled 35 pF
outputs disabled 5 pF
1999 Sep 20 3
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
ORDERING INFORMATION
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
PINNING
TYPE NUMBER PACKAGE
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74ALVCH16623DGG −40 to +85 °C 48 TSSOP plastic SOT362-1
INPUTS INPUTS/OUTPUTS
nOEAB nOEBA nAnnBn
L L A = B inputs
H H inputs B = A
LHZZ
H L A=B B=A
PIN SYMBOL DESCRIPTION
1, 24 1OEAB, 2OEAB output enable input (active HIGH)
2, 3, 5, 6, 8, 9, 11, 12 1B0to 1B7data inputs/outputs
4, 10, 15, 21, 28, 34, 39, 45 GND ground (0 V)
7, 18, 31, 42 VCC DC supply voltage
13, 14, 16, 17, 19, 20, 22, 23 2B0to 2B7data inputs/outputs
25, 48 2OEBA, 1OEBA output enable input (active LOW)
26, 27, 29, 30, 32, 33, 35, 36 2A7to 2A0data inputs/outputs
37, 38, 40, 41, 43, 44, 46, 47 1A7to 1A0data inputs/outputs
1999 Sep 20 4
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
Fig.1 Pin configuration.
f
page
16623
MNA307
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
1OEAB
1B0
1B1
GND
1B2
1B3
VCC
1B4
1B5
GND
1B6
1B7
2B0
2B1
GND
2B2
2B3
VCC
2B4
2B5
GND
2B6
2B7
2OEAB
1OEBA
1A0
1A1
GND
1A2
1A3
VCC
1A4
1A5
GND
1A6
1A7
2A0
2A1
GND
2A2
2A3
VCC
2A4
2A5
GND
2A6
2A7
2OEBA
Fig.2 Logic symbol.
47
2
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
46
3
44
5
43
6
41
8
40
9
38
11
37
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
12
36
13
35
14
33
16
32
17
30
19
29
20
27
22
26
23
MNA308
124
48
1OEAB
1OEBA
2OEAB
2OEBA
25
1999 Sep 20 5
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
Fig.3 IEC logic symbol.
handbook, halfpage
346
1
48
2
1
5
44
6
43
8
41
9
40
11
38
1237
2
1EN1
1EN2
47
1435
24
25
2
1
16
33
17
32
19
30
20
29
22
27
2326
13
2EN1
2EN2
36
MNA309
Fig.4 Bus hold circuit.
handbook, halfpage
to internal circuit
MNA310
VCC
data
input
1999 Sep 20 6
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55 °C the value of Ptot derates linearly with 8 mW/K.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VCC DC supply voltage
for max. speed performance CL= 30 pF 2.3 2.5 2.7 V
for max. speed performance CL= 50 pF 3.0 3.3 3.6 V
for low-voltage applications 1.2 2.4 3.6 V
VIDC input voltage 0 −VCC V
VODC output voltage 0 −VCC V
Tamb operating ambient temperature in free air −40 −+85 °C
tr, ftinput rise and fall times VCC = 2.3 to 3.0 V 0 −20 ns/V
VCC = 3.0 to 3.6 V 0 −10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC DC supply voltage −0.5 +4.6 V
IIK DC input diode current VI<0 −−50 mA
VIDC input voltage note 1 −0.5 +4.6 V
IOK DC output diode current VO>V
CC or VO<0 −±50 mA
VODC output voltage note 1 −0.5 VCC + 0.5 V
IODC output source or sink current VO=0toV
CC −±50 mA
ICC, IGND DC VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation for temperature range: −40 to +125 °C;
note 2 −600 mW
1999 Sep 20 7
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
DC CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
Notes
1. All typical values are measured at Tamb =25°C.
2. Valid for data inputs of bus hold parts.
SYMBOL PARAMETER TEST CONDITIONS Tamb =−40 TO +85 °CUNIT
VI(V) OTHER VCC (V) MIN. TYP.(1) MAX.
VIH HIGH-level input voltage 2.3 to 2.7 1.7 1.2 −V
2.7 to 3.6 2.0 1.5 −
VIL LOW-level input voltage 2.3 to 2.7 −1.2 0.7 V
2.7 to 3.6 −1.5 0.8
VOH HIGH-level output voltage VIH or VIL IO=−100 µA 2.3 to 3.6 VCC −0.2 VCC −V
IO=−6 mA 2.3 VCC −0.3 VCC −0.08 −
IO=−12 mA 2.3 VCC −0.6 VCC −0.26 −
IO=−12 mA 2.7 VCC −0.5 VCC −0.14 −
IO=−12 mA 3.0 VCC −0.6 VCC −0.09 −
IO=−24 mA 3.0 VCC −1.0 VCC −0.28 −
VOL LOW-level output voltage VIH or VIL IO= 100 µA 2.3 to 3.6 −GND 0.20 V
IO=6mA 2.3 −0.07 0.40
IO=12mA 2.3 −0.15 0.70
IO=12mA 2.7 −0.14 0.40
IO=24mA 3.0 −0.27 0.55
Ilinput leakage current VCC or
GND 2.3 to 3.6 −0.1 5 µA
IOZ 3-state output OFF-state
current VIHor VIL VO=V
CC or
GND 2.3 to 3.6 −0.1 10 µA
ICC quiescent supply voltage VCC or
GND IO= 0 2.3 to 3.6 −0.2 40 µA
∆ICC additionalquiescentsupply
current given per data I/O
pin with bus hold
VCC −0.6 IO= 0 2.3 to 3.6 −150 750 µA
IBHL bus hold LOW sustaining
current 0.7(2) 2.3(2) 45 −−µA
0.8(2) 3.0(2) 75 150 −
IBHH bus hold HIGH sustaining
current 1.7(2) 2.3(2) −45 −µA
2.0(2) 3.0(2) −75 −175 −
IBHLO bus hold LOW overdrive
current 3.6(2) 500 −−µA
I
BHHO bus hold LOW overdrive
current 3.6(2) −500 −−µA
1999 Sep 20 8
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
AC CHARACTERISTICS FOR VCC = 2.3 TO 2.7 V
Ground = 0 V; tr=t
f≤2.0 ns; CL=30pF.
Note
1. All typical values are measured at Tamb =25°C and VCC = 2.5 V.
AC CHARACTERISTICS FOR VCC = 2.7 V AND VCC = 3.0 TO 3.6 V
Ground = 0 V; tr=t
f≤2.5 ns; CL=50pF.
Notes
1. All typical values are measured at Tamb =25°C.
2. Typical values at VCC = 3.3 V.
SYMBOL PARAMETER TEST CONDITIONS Tamb =−40 TO +85 °CUNIT
WAVEFORMS VCC (V) MIN. TYP.(1) MAX.
tPHL/tPLH propagation delay
nAn,nB
nto nBn,nA
n
see Figs 5 and 8 2.3 to 2.7 1.0 2.4 3.5 ns
tPZH/tPZL 3-state output enable time
nOEAB to nBn
see Figs 7 and 8 2.3 to 2.7 1.0 3.0 5.0 ns
tPHZ/tPLZ 3-state output disable time
nOEBA to nAn
see Figs 6 and 8 2.3 to 2.7 1.0 3.0 5.1 ns
tPZH/tPZL 3-state output enable time
nOEAB to nBn
see Figs 7 and 8 2.3 to 2.7 1.0 2.8 4.5 ns
tPHZ/tPLZ 3-state output disable time
nOEBA to nAn
see Figs 6 and 8 2.3 to 2.7 1.0 2.4 4.0 ns
SYMBOL PARAMETER TEST CONDITIONS Tamb =−40 TO +85 °CUNIT
WAVEFORMS VCC (V) MIN. TYP.(1) MAX.
tPHL/tPLH propagation delay
nAn,nB
nto nBn,nA
n
see Figs 5 and 8 2.7 −2.5 3.4 ns
3.0 to 3.6 1.0 2.6(2) 3.1
tPZH/tPZL 3-state output enable time
nOEAB to nBn
see Figs 7 and 8 2.7 −2.8 4.5 ns
3.0 to 3.6 1.0 2.6(2) 4.0
tPHZ/tPLZ 3-state output disable time
nOEBA to nAn
see Figs 6 and 8 2.7 −3.3 5.0 ns
3.0 to 3.6 1.0 2.8(2) 4.2
tPZH/tPZL 3-state output enable time
nOEAB to nBn
see Figs 7 and 8 2.7 −3.8 5.4 ns
3.0 to 3.6 1.0 3.3(2) 4.6
tPHZ/tPLZ 3-state output disable time
nOEBA to nAn
see Figs 6 and 8 2.7 −3.2 4.5 ns
3.0 to 3.6 1.0 3.0(2) 4.3
1999 Sep 20 9
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
AC WAVEFORMS Notes: VCC = 2.3 to 2.7 V
VM= 0.5VCC;
VX=V
OL + 150 mV;
VY=V
OH −150 mV;
VI=V
CC;
VOL and VOH are typical output voltage drop that occur
with the output load.
Notes: VCC = 3.0 to 3.6 V and VCC = 2.7 V
VM= 1.5 V;
VX=V
OL + 300 mV;
VY=V
OH −300 mV;
VI= 2.7 V;
VOL and VOH are typical output voltage drop that occur
with the output load.
Fig.5 The input nAn, nBn to output nBn, nAn
propagation delay times.
handbook, halfpage
MNA311
nAn, nBn
input
nBn, nAn
output
tPHL tPLH
GND
VI
VM
VM
VOH
VOL
Fig.6 3-state enable and disable times for nOEBA input.
handbook, full pagewidth
MNA312
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOEBA input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
1999 Sep 20 10
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
Fig.7 3-state enable and disable times for nOEAB times.
handbook, full pagewidth
MNA313
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOEAB input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Fig.8 Load circuitry for switching times.
handbook, full pagewidth
open
GND
50 pF
2 × VCC
VCC
VIVO
MNA296
D.U.T.
CL
RT
RL
500 Ω
RL
500 Ω
PULSE
GENERATOR
S1
VCC VI
<2.7 V VCC
2.7 to 3.6 V 2.7 V
TEST S1
tPLH/tPHL open
tPLZ/tPZL 2×VCC
tPHZ/tPZH GND
Definitions for test circuit.
CL= load capacitance including jig and probe capacitance
(See Chapter “AC characteristics”).
RL= load resistance.
RT= terminationresistanceshouldbe equalto theoutput impedance
Zo of the pulse generator.
1999 Sep 20 11
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
PACKAGE OUTLINE
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywvθ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 93-02-03
95-02-10
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153ED
1999 Sep 20 12
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
SOLDERING
Introduction to soldering surface mount packages
Thistextgives a very brief insighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuitboard by screen printing, stencillingor
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
forsurface mount devices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswith leadsonfoursides,the footprint must
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Sep 20 13
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PACKAGE SOLDERING METHOD
WAVE REFLOW(1)
BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2) suitable
PLCC(3), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SSOP, TSSOP, VSO not recommended(5) suitable
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1999 Sep 20 14
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
NOTES
1999 Sep 20 15
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
NOTES
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74ALVCH16623
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74ALVCH16623
Product INFOrmation page
Information as of 2001-04-18
74ALVCH16623; 16-bit transceiver with dual enable; 3-state
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Description
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to
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of
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page
The 74ALVCH16623 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families.
The 74ALVCH16623 is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and
receive directions.
This 16-bit bus transceiver is designed for asynchronous two-way communication between data buses. The control
function implementation allows maximum flexibility in timing. This device allows data transmission from the A bus to the
B bus or from the B bus to the A bus, depending upon the logic levels at the enable inputs (nOEAB,nOEBA). The enable
inputs can be used to disable the device so that the buses are effectively isolated. The dual enable function configuration
gives this transceiver the capability to store data by simultaneous enabling of nOEAB and nOEBA. Each output reinforces
its input in this transceiver configuration. Thus, when all control inputs are enabled and all other data sources to the four
sets of the bus lines are at high-impedance OFF-state, all sets of bus lines will remain at their last states. The 8-bit codes
appearing on the two double sets of buses will be complementary. This device can be used as two 8-bit transceivers or
one 16-bit transceiver.
To ensure the high-impedance state during power-on or power-down, OEBA should be tied to VCC through a pull-up
resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined
by the current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
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Complies with JEDEC standard no. 8-1A● CMOS low power consumption● Direct interface with TTL levels● MULTIBYTETM flow-through standard pin-out architecture● All data inputs have bus hold circuitry● Output drive capability 50 Ω transmission lines at 85 °C● Current drive ±24 mA at 3.0 V.●
Datasheet
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page
Type nr. Title Publication
release date Datasheet status Page
count
File
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(kB) Datasheet
74ALVCH16623 16-bit transceiver with dual
enable; 3-state 20-Sep-99 Product Specification 16 91
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Philips Semiconductors: Product information on 74ALVCH16623, 16-bit transceiver with dual enable; 3-state
file:///K|/export/projects/bitting2/imaging/BITTING...il_pdf/20010521/08may2001/html/74alvch16623dgg.html (1 of 2) [5/21/2001 11:18:26 AM]
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74ALVCH16623DGG 74ALVCH16623DG 9352 543 50112 Standard
Marking * Tube SOT362-1
(TSSOP48) Full production
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product online
-
74ALVCH16623DG-T 9352 543 50118 Standard
Marking * Reel
Pack, SMD, 13"
SOT362-1
(TSSOP48) Full production
order this
product online
-
74ALVCH16623DL 9352 543 40112 Standard
Marking * Tube - Development -
9352 543 40118 Standard
Marking * Reel
Pack, SMD, 13" - Development -
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Philips Semiconductors: Product information on 74ALVCH16623, 16-bit transceiver with dual enable; 3-state
file:///K|/export/projects/bitting2/imaging/BITTING...il_pdf/20010521/08may2001/html/74alvch16623dgg.html (2 of 2) [5/21/2001 11:18:26 AM]
