TL/F/5946
CD4013BM/CD4013BC Dual D Flip-Flop
February 1988
CD4013BM/CD4013BC Dual D Flip-Flop
General Description
The CD4013B dual D flip-flop is a monolithic complementa-
ry MOS (CMOS) integrated circuit constructed with N- and
P-channel enhancement mode transistors. Each flip-flop
has independent data, set, reset, and clock inputs and ‘‘Q’’
and ‘‘Q’’ outputs. These devices can be used for shift regis-
ter applications, and by connecting ‘‘Q’’ output to the data
input, for counter and toggle applications. The logic level
present at the ‘‘D’’ input is transferred to the Q output during
the positive-going transition of the clock pulse. Setting or
resetting is independent of the clock and is accomplished
by a high level on the set or reset line respectively.
Features
YWide supply voltage range 3.0V to 15V
YHigh noise immunity 0.45 VDD (typ.)
YLow power TTL fan out of 2 driving 74L
compatibility or 1 driving 74LS
Applications
YAutomotive YAlarm system
YData terminals YIndustrial electronics
YInstrumentation YRemote metering
YMedical electronics YComputers
Connection Diagram
Dual-In-Line Package
TL/F/5946–1
Top View
Order Number CD4013B
Truth Table
CL²DRSQQ
L00001
L10010
Kx00QQ
xx1001
xx0110
xx1111
No change
²eLevel change
xeDon’t care case
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Supply Voltage (VDD)b0.5 VDC to a18 VDC
Input Voltage (VIN)b0.5 VDC to VDD a0.5 VDC
Storage Temp. Range (TS)b65§Ctoa
150§C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260§C
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (VDD)a3V
DC to a15 VDC
Input Voltage (VIN)0V
DC to VDD VDC
Operating Temperature Range (TA)
CD4013BM b55§Ctoa
125§C
CD4013BC b40§Ctoa
85§C
DC Electrical Characteristics CD4013BM (Note 2)
Symbol Parameter Conditions b55§Ca25§Ca125§CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD e5V, VIN eVDD or VSS 1.0 1.0 30 mA
Current VDD e10V, VIN eVDD or VSS 2.0 2.0 60 mA
VDD e15V, VIN eVDD or VSS 4.0 4.0 120 mA
VOL Low Level
l
IO
l
k1.0 mA
Output Voltage VDD e5V 0.05 0.05 0.05 V
VDD e10V 0.05 0.05 0.05 V
VDD e15V 0.05 0.05 0.05 V
VOH High Level
l
IO
l
k1.0 mA
Output Voltage VDD e5V 4.95 4.95 4.95 V
VDD e10V 9.95 9.95 9.95 V
VDD e15V 14.95 14.95 14.95 V
VIL Low Level
l
IO
l
k1.0 mA
Input Voltage VDD e5V, VOe0.5V or 4.5V 1.5 1.5 1.5 V
VDD e10V, VOe1.0V or 9.0V 3.0 3.0 3.0 V
VDD e15V, VOe1.5V or 13.5V 4.0 4.0 4.0 V
VIH High Level
l
IO
l
k1.0 mA
Input Voltage VDD e5V, VOe0.5V or 4.5V 3.5 3.5 3.5 V
VDD e10V, VOe1.0V or 9.0V 7.0 7.0 7.0 V
VDD e15V, VOe1.5V or 13.5V 11.0 11.0 11.0 V
IOL Low Level Output VDD e5V, VOe0.4V 0.64 0.51 0.88 0.36 mA
Current (Note 3) VDD e10V, VOe0.5V 1.6 1.3 2.25 0.9 mA
VDD e15V, VOe1.5V 4.2 3.4 8.8 2.4 mA
IOH High Level Output VDD e5V, VOe4.6V b0.64 b0.51 b0.88 b0.36 mA
Current (Note 3) VDD e10V, VOe9.5V b1.6 b1.3 b2.25 b0.9 mA
VDD e15V, VOe13.5V b4.2 b3.4 b8.8 b2.4 mA
IIN Input Current VDD e15V, VIN e0V b0.1 b10b5b0.1 b1.0 mA
VDD e15V, VIN e15V 0.1 10b50.1 1.0 mA
DC Electrical Characteristics CD4013BC (Note 2)
Symbol Parameter Conditions b40§Ca25§Ca85§CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD e5V, VIN eVDD or VSS 4.0 4.0 30 mA
Current VDD e10V, VIN eVDD or VSS 8.0 8.0 60 mA
VDD e15V, VIN eVDD or VSS 16.0 16.0 120 mA
VOL Low Level
l
IO
l
k1.0 mA
Output Voltage VDD e5V 0.05 0.05 0.05 V
VDD e10V 0.05 0.05 0.05 V
VDD e15V 0.05 0.05 0.05 V
VOH High Level
l
IO
l
k1.0 mA
Output Voltage VDD e5V 4.95 4.95 4.95 V
VDD e10V 9.95 9.95 9.95 V
VDD e15V 14.95 14.95 14.95 V
VIL Low Level
l
IO
l
k1.0 mA
Input Voltage VDD e5V, VOe0.5V or 4.5V 1.5 1.5 1.5 V
VDD e10V, VOe1.0V or 9.0V 3.0 3.0 3.0 V
VDD e15V, VOe1.5V or 13.5V 4.0 4.0 4.0 V
2
DC Electrical Characteristics CD4013BC (Note 2) (Continued)
Symbol Parameter Conditions b40§Ca25§Ca85§CUnits
Min Max Min Typ Max Min Max
VIH High Level
l
IO
l
k1.0 mA
Input Voltage VDD e5V, VOe0.5V or 4.5V 3.5 3.5 3.5 V
VDD e10V, VOe1.0V or 9.0V 7.0 7.0 7.0 V
VDD e15V, VOe1.5V or 13.5V 11.0 11.0 11.0 V
IOL Low Level Output VDD e5V, VOe0.4V 0.52 0.44 0.88 0.36 mA
Current (Note 3) VDD e10V, VOe0.5V 1.3 1.1 2.25 0.9 mA
VDD e15V, VOe1.5V 3.6 3.0 8.8 2.4 mA
IOH High Level Output VDD e5V, VOe4.6V b0.52 b0.44 b0.88 b0.36 mA
Current (Note 3) VDD e10V, VOe9.5V b1.3 b1.1 b2.25 b0.9 mA
VDD e15V, VOe13.5V b3.6 b3.0 b8.8 b2.4 mA
IIN Input Current VDD e15V, VIN e0V b0.3 b10b5b0.3 b1.0 mA
VDD e15V, VIN e15V 0.3 10b50.3 1.0 mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2: VSS e0V unless otherwise specified.
Note 3: IOH and IOL are measured one output at a time.
AC Electrical Characteristics*TAe25§C, CLe50 pF, RLe200k, unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CLOCK OPERATION
tPHL,t
PLH Propagation Delay Time VDD e5V 200 350 ns
VDD e10V 80 160 ns
VDD e15V 65 120 ns
tTHL,t
TLH Transition Time VDD e5V 100 200 ns
VDD e10V 50 100 ns
VDD e15V 40 80 ns
tWL,t
WH Minimum Clock VDD e5V 100 200 ns
Pulse Width VDD e10V 40 80 ns
VDD e15V 32 65 ns
tRCL,t
FCL Maximum Clock Rise and VDD e5V 15 ms
Fall Time VDD e10V 10 ms
VDD e15V 5 ms
tSU Minimum Set-Up Time VDD e5V 20 40 ns
VDD e10V 15 30 ns
VDD e15V 12 25 ns
fCL Maximum Clock VDD e5V 2.5 5 MHz
Frequency VDD e10V 6.2 12.5 MHz
VDD e15V 7.6 15.5 MHz
SET AND RESET OPERATION
tPHL(R), Propagation Delay Time VDD e5V 150 300 ns
tPLH(S) VDD e10V 65 130 ns
VDD e15V 45 90 ns
tWH(R), Minimum Set and VDD e5V 90 180 ns
tWH(S) Reset Pulse Width VDD e10V 40 80 ns
VDD e15V 25 50 ns
CIN Average Input Capacitance Any Input 5 7.5 pF
*AC Parameters are guaranteed by DC correlated testing.
3
Schematic Diagram
TL/F/5946–3
TL/F/5946–2
TL/F/5946–4
4
Logic Diagram
TL/F/5946–5
Switching Time Waveforms
TL/F/5946–6
5
CD4013BM/CD4013BC Dual D Flip-Flop
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4013BMJ or CD4013BCJ
NS Package Number J14A
Molded Dual-In-Line Package (N)
Order Number CD4013BMN or CD4013BCN
NS Package Number N14A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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