1
FEATURES
DB, DBQ, DGV, DW,
OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
A2
P0
P1
P2
P3
GND
VCC
SDA
SCL
INT
P7
P6
P5
P4
RGV PACKAGE
(TOP VIEW)
16
6 8
2
10 P7
P5
VCC
4
3
1
75
12
11
9
131415
SDA
A0
A1
P6
INT
SCL
P3
GND
P4
A2
P0
P1
P2
RGT PACKAGE
(TOP VIEW)
16
6 8
210 P7
P5 VCC
4
3
1
75
12
11
9
131415
SDA
A0
A1
P6
INT
SCL
P3
GND
P4
A2
P0
P1
P2
DESCRIPTION/ORDERING INFORMATION
PCA9554A
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........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
REMOTE 8-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
•I
2
C to Parallel Port Expander •Power-Up With All Channels Configured asInputs•Open-Drain Active-Low Interrupt Output
•No Glitch on Power Up•Operating Power-Supply Voltage Range of2.3 V to 5.5 V •Latched Outputs With High-Current DriveMaximum Capability for Directly Driving LEDs•5-V Tolerant I/Os
•Latch-Up Performance Exceeds 100 mA Per•400-kHz Fast I
2
C Bus
JESD 78, Class II•Three Hardware Address Pins Allow up to
•ESD Protection Exceeds JESD 22Eight Devices on the I
2
C/SMBus
– 2000-V Human-Body Model (A114-A)•Input/Output Configuration Register
– 200-V Machine Model (A115-A)•Polarity Inversion Register
– 1000-V Charged-Device Model (C101)•Internal Power-On Reset
This 8-bit I/O expander for the two-line bidirectional bus (I
2
C) is designed for 2.3-V to 5.5-V V
CC
operation. Itprovides general-purpose remote I/O expansion for most microcontroller families via the I
2
C interface [serial clock(SCL), serial data (SDA)].
The PCA9554A consists of one 8-bit Configuration (input or output selection), Input, Output, and PolarityInversion (active high or active low) registers. At power on, the I/Os are configured as inputs with a weak pullupto V
CC
. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/Oconfiguration bits. The data for each input or output is kept in the corresponding Input or Output register. Thepolarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read bythe system master.
The system master can reset the PCA9554A in the event of a timeout or other improper operation by utilizing thepower-on reset feature, which puts the registers in their default state and initializes the I
2
C/SMBus state machine.
The PCA9554A open-drain interrupt ( INT) output is activated when any input state differs from its correspondingInput Port register state and is used to indicate to the system master that an input state has changed.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
PCA9554A
SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008 ...........................................................................................................................................
www.ti.com
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, theremote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate viathe I
2
C bus. Thus, the PCA9554A can remain a simple slave device.
The device ' s outputs (latched) have high-current drive capability for directly driving LEDs and low currentconsumption.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I
2
C address and allow up to eightdevices to share the same I
2
C bus or SMBus.
The PCA9554A is pin-to-pin and I
2
C address compatible with the PCF8574A. However, software changes arerequired, due to the enhancements in the PCA9554A over the PCF8574A.
The PCA9554A and PCA9554 are identical except for their fixed I
2
C address. This allows for up to 16 of thesedevices (8 of each) on the same I
2
C/SMBus.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGT Reel of 3000 PCA9554ARGTR ZVHQFN – RGV Reel of 2500 PCA9554ARGVR PD554ATube of 75 PCA9554ADBQQSOP – DBQ PD554AReel of 2500 PCA9554ADBQRTube of 40 PCA9554ADWSOIC – DW PCA9554AReel of 2000 PCA9554ADWR– 40 ° C to 85 ° C PCA9554ADBTube of 80SSOP – DB PCA9554ADBG4 PD554AReel of 2000 PCA9554ADBRTube of 90 PCA9554APWTSSOP – PW PD554AReel of 2000 PCA9554APWRReel of 2000 PCA9554ADGVRTVSOP – DGV PD554AReel of 125 PCA9554ADGV
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
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14
I/O
Port
Shift
Register 8 Bits
LP Filter
Interrupt
Logic
Input
Filter
15
Power-On
Reset Read Pulse
Write Pulse
2
1
13
16
8
GND
VCC
SDA
SCL
A1
A0
INT
I2C Bus
Control
P7−P0
3
A2
PCA9554A
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........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
TERMINAL FUNCTIONS
NO.
QSOP (DBQ)SOIC (DW),
NAME DESCRIPTIONQFN (RGT ANDSSOP (DB),
RGV)TSSOP (PW), ANDTVSOP (DGV)
1 15 A0 Address input. Connect directly to V
CC
or ground.2 16 A1 Address input. Connect directly to V
CC
or ground.3 1 A2 Address input. Connect directly to V
CC
or ground.4 2 P0 P-port input/output. Push-pull design structure.5 3 P1 P-port input/output. Push-pull design structure.6 4 P2 P-port input/output. Push-pull design structure.7 5 P3 P-port input/output. Push-pull design structure.8 6 GND Ground9 7 P4 P-port input/output. Push-pull design structure.10 8 P5 P-port input/output. Push-pull design structure.11 9 P6 P-port input/output. Push-pull design structure.12 10 P7 P-port input/output. Push-pull design structure.13 11 INT Interrupt output. Connect to V
CC
through a pullup resistor.14 12 SCL Serial clock bus. Connect to V
CC
through a pullup resistor.15 13 SDA Serial data bus. Connect to V
CC
through a pullup resistor.16 14 V
CC
Supply voltage
FUNCTIONAL BLOCK DIAGRAM
A. Pin numbers shown are for the DB, DBQ, DGV, DW, or PW package.B. All I/Os are set to inputs at reset.
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Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Write Polarity
Pulse
Data From
Shift Register
Output Port
Register
Configuration
Register
Input Port
Register
Polarity
Inversion
Register
Polarity
Register Data
Input Port
Register Data
GND
P0 to P7
VCC
Output Port
Register Data
Q1
Q2
D
CK
FF
Q
Q
D
CK
FF
Q
Q
D
CK
FF
Q
Q
D
CK
FF
Q
Q
INT
100 kW
I/O Port
I
2
C Interface
PCA9554A
SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008 ...........................................................................................................................................
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SIMPLIFIED SCHEMATIC OF P0 TO P7
A. At power-on reset, all registers return to default values.
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high impedance input with aweak pullup (100 k Ωtyp) to V
CC
. The input voltage may be raised above V
CC
to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. Inthis case, there are low impedance paths between the I/O pin and either V
CC
or GND. The external voltageapplied to this I/O pin should not exceed the recommended levels for proper operation.
The bidirectional I
2
C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must beconnected to a positive supply through a pullup resistor when connected to the output stages of a device. Datatransfer may be initiated only when the bus is not busy.
I
2
C communication with this device is initiated by a master sending a Start condition, a high-to-low transition onthe SDA input/output while the SCL input is high (see Figure 1 ). After the Start condition, the device address byteis sent, most significant bit (MSB) first, including the data direction bit (R/ W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDAinput/output during the high of the ACK-related clock pulse. The address inputs (A0 – A2) of the slave device mustnot be changed between the Start and Stop conditions.
On the I
2
C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remainstable during the high pulse of the clock period, as changes in the data line at this time are interpreted as controlcommands (Start or Stop) (see Figure 2 ).
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SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
PCA9554A
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........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by themaster (see Figure 1 ).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and Stopconditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line beforethe receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACKclock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (seeFigure 3 ). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and holdtimes must be met to ensure proper operation.
A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK)after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA linehigh. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 1. Definition of Start and Stop Conditions
Figure 2. Bit Transfer
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Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for
Acknowledgment
NACK
ACK
PCA9554A
SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008 ...........................................................................................................................................
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Figure 3. Acknowledgment on the I
2
C Bus
Interface Definition
BITBYTE
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I
2
C slave address L H H H A2 A1 A0 R/ WPx I/O data bus P7 P6 P5 P4 P3 P2 P1 P0
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Device Address
0 1 1 1A1A2 A0
Slave Address
R/W
Fixed Hardware
Selectable
Control Register and Command Byte
0 0 0 0 B1 B000
PCA9554A
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........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
Figure 4 shows the address byte for the PCA9554A.
Figure 4. PCA9554A Address
Address Reference
INPUTS
I
2
C BUS SLAVE ADDRESSA2 A1 A0
L L L 56 (decimal), 38 (hexadecimal)L L H 57 (decimal), 39 (hexadecimal)L H L 58 (decimal), 3A (hexadecimal)L H H 59 (decimal), 3B (hexadecimal)H L L 60 (decimal), 3C (hexadecimal)H L H 61 (decimal), 3D (hexadecimal)H H L 62 (decimal), 3E (hexadecimal)H H H 63 (decimal), 3F (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a readis selected. A low (0) selects a write operation.
Following the successful acknowledgment of the address byte, the bus master sends a command byte that isstored in the control register in the PCA9554A. Two bits of this command byte state the operation (read or write)and the internal register (input, output, polarity inversion or configuration) that will be affected. This register canbe written or read through the I
2
C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until anew command byte has been sent.
Figure 5. Control Register Bits
Command Byte
CONTROL REGISTER BITS
COMMAND BYTE POWER-UPREGISTER PROTOCOL(HEX) DEFAULTB1 B0
0 0 0x00 Input Port Read byte XXXX XXXX0 1 0x01 Output Port Read/write byte 1111 11111 0 0x02 Polarity Inversion Read/write byte 0000 00001 1 0x03 Configuration Read/write byte 1111 1111
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Register Descriptions
Power-On Reset
PCA9554A
SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008 ...........................................................................................................................................
www.ti.com
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin isdefined as an input or an output by the Configuration register. It only acts on read operation. Writes to theseregisters have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to let the I
2
C device know that theInput Port register will be accessed next.
Register 0 (Input Port Register)
BIT I7 I6 I5 I4 I3 I2 I1 I0
DEFAULT XXXXXXXX
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by theConfiguration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from thisregister reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Register 1 (Output Port Register)
BIT O7 O6 O5 O4 O3 O2 O1 O0
DEFAULT 11111111
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configurationregister. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in thisregister is cleared (written with a 0), the corresponding port pin original polarity is retained.
Register 2 (Polarity Inversion Register)
BIT N7 N6 N5 N4 N3 N2 N1 N0
DEFAULT 00000000
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register iscleared to 0, the corresponding port pin is enabled as an output.
Register 3 (Configuration Register)
BIT C7 C6 C5 C4 C3 C2 C1 C0
DEFAULT 11111111
When power (from 0 V) is applied to V
CC
, an internal power-on reset holds the PCA9554A in a reset conditionuntil V
CC
has reached V
POR
. At that point, the reset condition is released and the PCA9554A registers andI
2
C/SMBus state machine will initialize to their default states. After that, V
CC
must be lowered to below 0.2 V andthen back up to the operating voltage for a power-reset cycle.
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Product Folder Link(s): PCA9554A
Interrupt Output ( INT)
Bus Transactions
Writes
SCL
SDA
Data to
Register
Start Condition R/W ACK From Slave ACK From Slave ACK From Slave
1 98765432
Data1/0A20 1S 11 A1 A0 0 A 1000000 A A P
Data to RegisterCommand ByteSlave Address
PCA9554A
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........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t
iv
, thesignal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the originalsetting; data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the readmode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the rising edge of the SCL signal.Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting ofthe interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an outputcannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if thestate of the pin does not match the contents of the Input Port register.
INT has an open-drain structure and requires a pullup resistor to V
CC
.
Data is exchanged between the master and PCA9554A through write and read commands.
Data is transmitted to the PCA9554A by sending the device address and setting the least-significant bit to a logic0 (see Figure 4 for device address). The command byte is sent after the address and determines which registerreceives the data that follows the command byte (see Figure 6 and Figure 7 ). There is no limitation on thenumber of data bytes sent in one write transmission.
Figure 6. Write to Output Port Register
< br/ >
Figure 7. Write to Configuration or Polarity Inversion Registers
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Reads
A20 1S 11 A1 A0 0 A A
Data From Register
Slave Address
Slave Address
R/W
ACK From
Slave
Command Byte
ACK From
Slave
S A20 1 11 A1 A0
R/W
1 A Data A
ACK From
Master
Data
Data From Register NACK From
Master
NA P
Last Byte
ACK From
Slave
SCL
SDA
INT
Start
Condition
R/W
Read From
Port
Data Into
Port
Stop
Condition
ACK From
Master
NACK From
Master
ACK From
Slave
Data From Port
Slave Address Data From Port
1 98765432
A2
01S 11 A1 A0 1AData 1 Data 4
A NA P
Data 2 Data 3 Data 4
tiv
tph tps
tir
Data 5
PCA9554A
SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008 ...........................................................................................................................................
www.ti.com
The bus master first must send the PCA9554A address with the least significant bit (LSB) set to a logic 0 (seeFigure 4 for device address). The command byte is sent after the address and determines which register isaccessed. After a restart, the device address is sent again, but this time the LSB is set to a logic 1. Data from theregister defined by the command byte then is sent by the PCA9554A (see Figure 8 and Figure 9 ). After a restart,the value of the register defined by the command byte matches the register being accessed when the restartoccurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on thenumber of data bytes received in one read transmission, but when the final byte is received, the bus master mustnot acknowledge the data.
Figure 8. Read From Register
< br/ >
A. This figure assumes the command byte has previously been programmed with 00h.B. Transfer of data can be stopped at any moment by a Stop condition.C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave addresscall and actual data transfer from the P port. See Figure 8 for these details.
Figure 9. Read From Input Port Register
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
PCA9554A
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........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range – 0.5 6 VV
I
Input voltage range
(2)
– 0.5 6 VV
O
Output voltage range
(2)
– 0.5 6 VI
IK
Input clamp current V
I
< 0 – 20 mAI
OK
Output clamp current V
O
< 0 – 20 mAI
IOK
Input/output clamp current V
O
< 0 or V
O
> V
CC
± 20 mAI
OL
Continuous output low current V
O
= 0 to V
CC
50 mAI
OH
Continuous output high current V
O
= 0 to V
CC
– 50 mAContinuous current through GND – 250I
CC
mAContinuous current through V
CC
160DB package 82DBQ package 90DGV package 120θ
JA
Package thermal impedance
(3)
DW package 57 ° C/WPW package 108RGT package TBDRGV package 51T
stg
Storage temperature range – 65 150 ° C
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 2.3 5.5 V0.7 ×SCL, SDA 5.5V
CCV
IH
High-level input voltage VA2 – A0, P7 – P0 2 5.5SCL, SDA – 0.5 0.3 × V
CCV
IL
Low-level input voltage VA2 – A0, P7 – P0 – 0.5 0.8I
OH
High-level output current P7 – P0 – 10 mAI
OL
Low-level output current P7 – P0 25 mAT
A
Operating free-air temperature – 40 85 ° C
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Electrical Characteristics
PCA9554A
SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008 ...........................................................................................................................................
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over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
IK
Input diode clamp voltage I
I
= – 18 mA 2.3 V to 5.5 V – 1.2 VV
POR
Power-on reset voltage V
I
= V
CC
or GND, I
O
= 0 V
POR
1.5 1.65 V2.3 V 1.83 V 2.6I
OH
= – 8 mA
4.5 V 3.14.75 V 4.1V
OH
P-port high-level output voltage
(2)
V2.3 V 1.73 V 2.5I
OH
= – 10 mA
4.5 V 34.75 V 4SDA V
OL
= 0.4 V 2.3 V to 5.5 V 3 82.3 V 8 103 V 8 14V
OL
= 0.5 V
4.5 V 8 174.75 V 8 35I
OL
P port
(3)
mA2.3 V 10 133 V 10 19V
OL
= 0.7 V
4.5 V 10 244.75 V 10 45INT V
OL
= 0.4 V 2.3 V to 5.5 V 3 10SCL, SDA ± 1I
I
V
I
= V
CC
or GND 2.3 V to 5.5 V µAA2 – A0 ± 1I
IH
P port V
I
= V
CC
2.3 V to 5.5 V 1 µAI
IL
P port V
I
= GND 2.3 V to 5.5 V – 100 µA5.5 V 104 175V
I
= V
CC
, I
O
= 0, I/O = inputs,
3.6 V 50 90f
scl
= 400 kHz, No load
2.7 V 20 65Operating mode
5.5 V 60 150V
I
= V
CC
, I
O
= 0, I/O = inputs,
3.6 V 15 40f
scl
= 100 kHz, No load
2.7 V 8 20I
CC
µA5.5 V 450 700V
I
= GND, I
O
= 0, I/O = inputs,
3.6 V 300 600f
scl
= 0 kHz, No load
2.7 V 225 500Standby mode
5.5 V 0.25 1V
I
= V
CC
, I
O
= 0, I/O = inputs,
3.6 V 0.2 0.9f
scl
= 0 kHz, No load
2.7 V 0.1 0.8One input at V
CC
– 0.6 V,
2.3 V to 5.5 V 1.5Other inputs at V
CC
or GNDAdditional current in standbyΔI
CC
mAmode
Every LED I/O at V
I
= 4.3 V;
5.5 V 1f
scl
= 0 kHzC
I
SCL V
I
= V
CC
or GND 2.3 V to 5.5 V 4 5 pFSDA 5.5 6.5C
io
V
IO
= V
CC
or GND 2.3 V to 5.5 V pFP port 8 9.5
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V V
CC
) and T
A
= 25 ° C.(2) The total current sourced by all I/Os must be limited to 85 mA.(3) Each I/O must be externally limited to a maximum of 25 mA, and the P port (P0 to P7) must be limited to a maximum current of 200 mA.
12 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
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I
2
C Interface Timing Requirements
Switching Characteristics
PCA9554A
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........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
over operating free-air temperature range (unless otherwise noted) (see Figure 10 )
STANDARD MODE FAST MODEI
2
C BUS I
2
C BUS
UNITMIN MAX MIN MAX
f
scl
I
2
C clock frequency 0 100 0 400 kHzt
sch
I
2
C clock high time 4 0.6 µst
scl
I
2
C clock low time 4.7 1.3 µst
sp
I
2
C spike time 50 50 nst
sds
I
2
C serial-data setup time 250 100 nst
sdh
I
2
C serial-data hold time 0 0 nst
icr
I
2
C input rise time 1000 20 + 0.1C
b
(1)
300 nst
icf
I
2
C input fall time 300 20 + 0.1C
b
(1)
300 nst
ocf
I
2
C output fall time 10-pF to 400-pF bus 300 20 + 0.1C
b
(1)
300 nst
buf
I
2
C bus free time between Stop and Start 4.7 1.3 µst
sts
I
2
C Start or repeated Start condition setup 4.7 0.6 µst
sth
I
2
C Start or repeated Start condition hold 4 0.6 µst
sps
I
2
C Stop condition setup 4 0.6 µst
vd(data)
Valid data time SCL low to SDA output valid 300 50 nsACK signal from SCL low tot
vd(ack)
Valid data time of ACK condition 0.3 3.45 0.1 0.9 µsSDA (out) lowC
b
I
2
C bus capacitive load 400 400 ns
(1) C
b
= Total capacitive load of one bus in pF
over operating free-air temperature range (unless otherwise noted) (see Figure 11 and Figure 12 )
STANDARD MODE FAST MODEFROM TO
I
2
C BUS I
2
C BUSPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX
t
iv
Interrupt valid time P port INT 4 4 µst
ir
Interrupt reset delay time SCL INT 4 4 µst
pv
Output data valid SCL P7 – P0 200 200 nst
ps
Input data setup time P port SCL 100 100 nst
ph
Input data hold time P port SCL 1 1 µs
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): PCA9554A
TYPICAL CHARACTERISTICS
0
5
10
15
20
25
30
35
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
ICC – Supply Current – nA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
SCL = VCC
0
5
10
15
20
25
30
35
40
45
50
55
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
ICC – Supply Current – µA
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
fSCL = 400 kHz
I/Os unloaded
0
50
100
150
200
250
300
350
400
450
500
550
600
0 1 2 3 4 5 6 7 8
Number of I/Os Held Low
ICC – Supply Current – µA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 85°C
0
10
20
30
40
50
60
70
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC – Supply Voltage – V
ICC – Supply Current – µA
fSCL = 400 kHz
I/Os unloaded
PCA9554A
SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008 ...........................................................................................................................................
www.ti.com
SUPPLY CURRENT QUIESCENT SUPPLY CURRENTvs vsTEMPERATURE TEMPERATURE
SUPPLY CURRENT SUPPLY CURRENTvs vsSUPPLY VOLTAGE NUMBER OF I/Os HELD LOW
14 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9554A
0
5
10
15
20
25
30
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 85°C
0
25
50
75
100
125
150
175
200
225
250
275
300
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
VOL – Output Low Voltage – mV
VCC = 5 V, ISINK = 10 mA
VCC = 2.5 V, ISINK = 10 mA
VCC = 2.5 V, ISINK = 1 mA
VCC = 5 V, ISINK = 1 mA
0
5
10
15
20
25
30
35
40
45
50
55
60
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
35
40
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOL – Output Low Voltage – V
ISINK – I/O Sink Current – mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 85°C
PCA9554A
www.ti.com
........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
TYPICAL CHARACTERISTICS (continued)
I/O OUTPUT LOW VOLTAGE I/O SINK CURRENTvs vsTEMPERATURE OUTPUT LOW VOLTAGE
I/O SINK CURRENT I/O SINK CURRENTvs vsOUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): PCA9554A
0
5
10
15
20
25
30
35
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – Output High Voltage – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 2.5 V
TA= 25°C
TA= 85°C
0
25
50
75
100
125
150
175
200
225
250
275
-40 -15 10 35 60 85
TA– Free-Air Temperature – °C
(VCC – VOH) – Output High Voltage – mV
VCC = 5 V, IOL = 10 mA
VCC = 2.5 V, IOL = 10 mA
VCC = 5 V, IOL = 1 mA
VCC = 2.5 V, IOL = 1 mA
0
5
10
15
20
25
30
35
40
45
50
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – Output High Voltage – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 3.3 V
TA= 25°C
TA= 85°C
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
(VCC – VOH) – Output High Voltage – V
ISOURCE – I/O Source Current – mA
TA= –40°C
VCC = 5 V
TA= 25°C
TA= 85°C
PCA9554A
SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008 ...........................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
I/O OUTPUT HIGH VOLTAGE I/O SOURCE CURRENTvs vsTEMPERATURE OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT I/O SOURCE CURRENTvs vsOUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE
16 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9554A
0
1
2
3
4
5
6
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC – Supply Voltage – V
VOH – Output High Voltage – V
IOH = –10 mA
IOH = –8 mA
TA= 25°C
PCA9554A
www.ti.com
........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
TYPICAL CHARACTERISTICS (continued)
OUTPUT HIGH VOLTAGE
vsSUPPLY VOLTAGE
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): PCA9554A
PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
VCC
CL = 50 pF
(see Note A)
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tPHL
tPLH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
Three Bytes for Complete
Device Programming
SDA LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDA
0.7 × VCC
0.3 × VCC
0.7 × VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Address
Bit 1
Address
Bit 6
BYTE DESCRIPTION
1 I2C address
2, 3 P-port data
PCA9554A
SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008 ...........................................................................................................................................
www.ti.com
A. C
L
includes probe and jig capacitance.B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤30 ns.C. All parameters and waveforms are not applicable to all devices.
Figure 10. I
2
C Interface Load Circuit and Voltage Waveforms
18 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9554A
A
A
A
A
S 0 1 1 1 A1A2 A0 1 Data 1 1 PData 2
Start
Condition 8 Bits
(One Data Bytes)
From Port Data From PortSlave Address R/W
87654321
tir
tir
tsps
tiv
Address Data 1 Data 2
INT
Data
Into
Port
B
B
A
A
PnINT
R/W A
tir
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
INT SCL
View B−BView A−A
tiv
RL = 4.7 kΩ
VCC
CL = 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
DUT INT
ACK
From Slave ACK
From Slave
1.5 V
PCA9554A
www.ti.com
........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
PARAMETER MEASUREMENT INFORMATION (continued)
A. C
L
includes probe and jig capacitance.B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤30 ns.C. All parameters and waveforms are not applicable to all devices.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): PCA9554A
P0 A 0.7 × VCC
0.3 × VCC
SCL P7
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tpv
(see Note B)
Slave
ACK
Unstable
Data
Last Stable Bit
SDA
Pn
Pn
WRITE MODE (R/W = 0)
P0 A 0.7 × VCC
0.3 × VCC
SCL P7
0.7 × VCC
0.3 × VCC
tps tph
READ MODE (R/W = 1)
P-PORT LOAD CONFIGURATION
DUT
CL = 50 pF
(see Note A)
Pn 2 × VCC
500 W
500 W
1.5 V
PCA9554A
SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008 ...........................................................................................................................................
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
A. C
L
includes probe and jig capacitance.B. t
pv
is measured from 0.7 × V
CC
on SCL to 50% I/O pin output.C. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤30 ns.D. The outputs are measured one at a time, with one transition per measurement.E. All parameters and waveforms are not applicable to all devices.
Figure 12. P-Port Load Circuit and Voltage Waveforms
20 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9554A
SDA
SCL
Start
ACK or Read Cycle
tw
tREC
RESET
0.3 y VCC
VCC/2
tRESET
Pn
RL = 1 kΩ
VCC
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
DUT SDA
P-PORT LOAD CONFIGURATION
VCC/2
tRESET
DUT
CL = 50 pF
(see Note A)
Pn 2 × VCC
500 W
500 W
PCA9554A
www.ti.com
........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
PARAMETER MEASUREMENT INFORMATION (continued)
A. C
L
includes probe and jig capacitance.B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤30 ns.C. All parameters and waveforms are not applicable to all devices.
Figure 13. Reset Load Circuits and Voltage Waveforms
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): PCA9554A
APPLICATION INFORMATION
A2
A1
SDA
SCL
INT
GND
P6
P0
P1
P2
P3
P4
P5
P7
INT
GND
VCC
VCC
(5 V) VCC 10 kW10 kW10 kW2 kW
Master
Controller
PCA9554A
INT
RESET
Subsystem 2
(e.g., Counter)
Subsystem 3
(e.g., Alarm System)
ALARM
Controlled Device
(e.g., CBT Device)
ENABLE
A
B
VCC
Subsystem 1
(e.g., Temperature Sensor)
SDA
SCL
A0
PCA9554A
SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008 ...........................................................................................................................................
www.ti.com
Figure 14 shows an application in which the PCA9554A can be used.
A. Device address is configured as 0111000 for this example.B. P0, P2, and P3 are configured as outputs.C. P1, P4, and P5 are configured as inputs.D. P6 and P7 are not used and have internal 100-k Ωpullup resistors to protect them from floating.
Figure 14. Typical Application
22 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9554A
Minimizing I
CC
When I/Os Control LEDs
LED
LEDx
VCC
100 kW
VCC
LED
3.3 V 5 V
LEDx
VCC
PCA9554A
www.ti.com
........................................................................................................................................... SCPS127D – SEPTEMBER 2006 – REVISED AUGUST 2008
When the I/Os are used to control LEDs, they are normally connected to V
CC
through a resistor as shown inFigure 14 . Because the LED acts as a diode, when the LED is off, the I/O V
IN
is about 1.2 V less than V
CC
. Thesupply current, I
CC
, increases as V
IN
becomes lower than V
CC
and is specified as ΔI
CC
in ElectricalCharacteristics.
For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to V
CC
whenthe LED is off to minimize current consumption. Figure 15 shows a high-value resistor in parallel with the LED.Figure 16 shows V
CC
less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/OV
IN
at or above V
CC
and prevents additional supply-current consumption when the LED is off.
Figure 15. High-Value Resistor in Parallel With the LED
Figure 16. Device Supplied by a Lower Voltage
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): PCA9554A
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCA9554ADB ACTIVE SSOP DB 16 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554ADBG4 ACTIVE SSOP DB 16 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554ADBR ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554ADBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554ADW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554ADWR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554ADWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554APW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554APWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9554ARGTR ACTIVE QFN RGT 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PCA9554ARGTRG4 ACTIVE QFN RGT 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PCA9554ARGVR ACTIVE VQFN RGV 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PCA9554ARGVRG4 ACTIVE VQFN RGV 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2009
Addendum-Page 1
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCA9554ADBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
PCA9554ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
PCA9554ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PCA9554APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PCA9554ARGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PCA9554ARGVR VQFN RGV 16 2500 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCA9554ADBR SSOP DB 16 2000 367.0 367.0 38.0
PCA9554ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0
PCA9554ADWR SOIC DW 16 2000 367.0 367.0 38.0
PCA9554APWR TSSOP PW 16 2000 367.0 367.0 35.0
PCA9554ARGTR QFN RGT 16 3000 367.0 367.0 35.0
PCA9554ARGVR VQFN RGV 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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