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FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3
December 2010
FOD8001
High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Features
■
High Noise Immunity characterized by Common Mode
Rejection (CMR) and Power Supply Rejection (PSR)
specifications
– 20kV/µs Minimum Static CMR @ Vcm = 1000V
– 25kV/µs Typical Dynamic CMR @ Vcm = 1500V,
20MBaud Rate
– PSR in excess of 10% of the supply voltages
across full operating bandwidth
■
High Speed:
– 25Mbit/sec Date Rate (NRZ)
– 40ns max. Propagation Delay
– 6ns max. Pulse Width Distortion
– 20ns max. Propagation Delay Skew
■
3.3V and 5V CMOS Compatibility
■
Extended industrial temperate range, -40°C to 105°C
temperature range
■
Safety and regulatory pending approvals:
– UL1577, 3750 VACRMS for 1 min.
– IEC60747-5-2 (pending)
Applications
■
Industrial fieldbus communications
– Profibus, DeviceNet, CAN, RS485
■
Programmable Logic Control
■
Isolated Data Acquisition System
Description
The FOD8001 is a 3.3V/5V high-speed logic gate
Optocoupler, which supports isolated communications
allowing digital signals to communicate between sys-
tems without conducting ground loops or hazardous
®
common mode rejection and power supply rejection
specifications.
This high-speed logic gate optocoupler, packaged in a
compact 8-pin small outline package, consists of a high-
speed AlGaAs LED driven by a CMOS buffer IC coupled
to a CMOS detector IC. The detector IC comprises an
integrated photodiode, a high-speed transimpedance
amplifier and a voltage comparator with an output driver.
The CMOS technology coupled to the high efficiency of
the LED achieves low power consumption as well as
very high speed (40ns propagation delay, 6ns pulse
width distortion).
Related Resources
■
www.fairchildsemi.com/products/opto/
■
www.fairchildsemi.com/pf/FO/FOD0721.html
■
www.fairchildsemi.com/pf/FO/FOD0720.html
■
www.fairchildsemi.com/pf/FO/FOD0710.html
Functional Schematic
1
2
3
4 5
6
7
8VDD2
NC
VO
GND2
*: Pin 3 must be left unconnected
VDD1
VI
*
GND1
VI
H
L
VO
H
L
LED
OFF
ON
Tr uth Table
voltages. It utilizes Fairchild’s proprietary coplanar pack-
aging technology, Optoplanar , and optimized IC design
to achieve high noise immunity, characterized by high
©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3 2
FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Pin Definitions
Absolute Maximum Ratings (TA = 25°C Unless otherwise specified.)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Notes:
1. Derate linearly from 25°C at a rate of tbd W/°C
2. Derate linearly from 25°C at a rate of tbd mW/°C.
3. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected
to conditions outside these ratings.
4. 0.1µF bypass capacitor must be connected between Pin 1 and 4, and 5 and 8.
Pin Number Pin Name Pin Function Description
1V
DD1 Input Supply Voltage
2V
IInput Data
3 LED Anode – Must be left unconnected
4 GND1 Input Ground
5 GND2 Output Ground
6V
OOutput Data
7NCNot Connected
8V
DD2 Output Supply Voltage
Symbol Parameter Value Units
TSTG Storage Temperature -40 to +125 °C
TOPR Operating Temperature -40 to +105 °C
TSOL Lead Solder Temperature
(Refer to Reflow Temperature Profile)
260 for 10 sec °C
VDD1, VDD2 Supply Voltage 0 to 6.0 V
VIInput Voltage -0.5 to VDD1 + 0.5 V
IIInput DC Current -10 to +10 µA
VOOutput Voltage -0.5 to VDD2 + 0.5 V
IOAverage Output Current 10 mA
PDIInput Power Dissipation(1)(3) 90 mW
PDOTotal Power Dissipation(2)(3) 70 mW
Symbol Parameter Min. Max. Unit
TAAmbient Operating Temperature -40 +105 °C
VDD1, VDD2 Supply Voltages (3.3V Operation)(4) 3.0 3.6 V
Supply Voltages (5.0V Operation)(4) 4.5 5.5
VIH Logic High Input Voltage 2.0 VDD V
VIL Logic Low Input Voltage 0 0.8 V
tr, tfInput Signal Rise and Fall Time 1.0 ms
©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3 3
FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Isolation Characteristics
(Apply over all recommended conditions, typical value is measured at T
A
= 25°C)
Notes:
5. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
6. 3,750 VAC
RMS
for 1 minute duration is equivalent to 4,500 VAC
RMS
for 1 second duration.
Electrical Characteristics
(Apply over all recommended conditions, typical value is measured at
V
DD1
= V
DD2
= +3.3V, V
DD1
= +3.3V and V
DD2
= +5.0V, V
DD1
= +5.0V and V
DD2
= +3.3V, V
DD1
= V
DD2
= +5.0V, T
A
= 25°C)
Symbol Characteristics Test Conditions Min. Typ.* Max. Unit
V
ISO
Input-Output Isolation Voltage f = 60Hz, t = 1.0 min, I
I-O
≤
10µA
(5)(6)
3750 — — Vac
RMS
R
ISO
Isolation Resistance V
I-O
= 500V
(5)
10
11
— —
Ω
C
ISO
Isolation Capacitance V
I-O
= 0V, f = 1.0MHz
(5)
— 0.2 — pF
Symbol Parameter Conditions Min. Typ. Max. Units
INPUT CHARACTERISTICS
I
DD1L
Logic Low Input Supply
Current
V
I
= 0V 6.2 10.0 mA
I
DD1H
Logic High Input Supply
Current
V
I
= V
DD1
0.8 3.0 mA
I
IA
, I
IB
Input Current -10 +10 µA
OUTPUT CHARACTERISTICS
I
DD2L
Logic Low Output Supply
Current
V
I
= 0V 4.5 9.0 mA
I
DD2H
Logic High Output Supply
Current
V
I
= V
DD1
4.5 9.0 mA
V
OH
Logic High Output Voltage I
O
= -20µA, V
I
= V
IH
, V
DD2
= +3.3V 2.9 3.3 V
I
O
= -4mA, V
I
= V
IH
, V
DD2
= +3.3V 1.9 2.9
I
O
= -20µA, V
I
= V
IH
, V
DD2
= +5.0V 4.4 5.0
I
O
= -4mA, V
I
= V
IH
, V
DD2
= +5.0V 4.0 4.8
VOL Logic Low Output Voltage I
O
= 20µA, V
I
= V
IL
0 0.1 V
I
O
= 4mA, V
I
= V
IL
0.3 1.0
©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3 4
FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Switching Characteristics (Apply over all recommended conditions, typical value is measured at
VDD1 = VDD2 = +3.3V, VDD1 = +3.3V and VDD2 = +5.0V, VDD1 = +5.0V and VDD2 = +3.3V, VDD1 = VDD2 = +5.0V, TA = 25°C)
Notes:
7. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any
given temperature within the recommended operating conditions.
8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of
the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity
at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to
assure that the output will remain low.
9. Unloaded dynamic power dissipation is calculated as follows:
CPD x VDD x f + IDD + VPD where f is switched time in MHz.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
tPHL Propagation Delay Time to
Logic Low Output
CL = 15pF 25 40 ns
tPLH Propagation Delay Time to
Logic High Output
CL = 15pF 25 40 ns
PWD Pulse Width Distortion,
| tPHL – tPLH |
PWD = 40ns, CL = 15pF 2 6 ns
Data Rate 25 Mb/s
tPSK Propagation Delay Skew CL = 15pF(7) 20 ns
tROutput Rise Time (10%–90%) 6.5 ns
tFOutput Fall Time (90%–10%) 6.5 ns
|CMH| Common Mode Transient
Immunity at Output High
VI = VDD1, VO > 0.8 VDD1,
VCM = 1000V(8)
20 40 kV/µs
|CML| Common Mode Transient
Immunity at Output Low
VI = 0V, VO < 0.8V,
VCM = 1000V(8)
20 40 kV/µs
CPDI Input Dynamic Power
Dissipation Capacitance(9)
30 pF
CPDO Output Dynamic Power
Dissipation Capacitance(9)
3pF
©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3 5
FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Typical Performance Curves
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
012345
V
O
-OutputVoltage (V)
V
I
-Input Voltage (V)
V
DD1
=V
DD 2
=3.3V
1.0
1.2
1.4
1.6
1.8
2.0
3.0 3.5 4.0 4.5 5.0 5.5
V
ITH
-TypicalInput Voltage Swi cthing Threshold (V)
V
DD1
-Input Supply Voltage (V)
V
DD2
=3.3V
5.5
6.0
6.5
7.0
7.5
-40 -20 0 20 406080100
t
r
-RiseTime(ns)
T
A
-AmbientTemperatur e ( °C)
Frequency = 12.5MHz
Duty Cycle = 50%
V
DD1
=V
DD2
=3.3V
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
-40 -20 0 20 406080100
t
f
-FallTime(ns)
T
A
-AmbientTemperature (°C)
Frequency = 12.5MHz
Dut y Cycle = 50%
V
DD1
=V
DD2
=3.3V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-40 -20 0 20 4060 80100
PW D - Pu lse Width Distortion (ns)
T
A
A
-Ambient Temperature (°C)
Frequency = 12.5MHz
Dut y Cycl e = 50 %
V
DD1
=V
DD2
=3.3V
20
22
24
26
28
30
32
-40 -20 0 20 406080100
t
P
-Propagation Delay (ns)
T-AmbientTemperat ur e ( °C)
t
PHL
t
PLH
Frequency = 12.5MHz
Duty Cycle = 50%
V
DD1
=V
DD 2
=3.3V
Figure 1. Typical Output Voltage vs. Input Voltage Figure 2. Input Voltage Switching Threshold vs. Input Supply Voltage
Figure 3. Propogation Delay vs. Ambient Temperature Figure 4. Pulse Width Distortion vs. Ambient Temperature
Figure 5. Typical Rise Time vs. Ambient Temperature Figure 6. Typical Fall Time vs. Ambient Temperature
©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3 6
FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Typical Performance Curves (Continued)
22
24
26
28
30
32
34
15 20 25 30 35 40 45 50 55
t
P
-Propagation Delay (ns)
C
L
-Output Load Capacitance (pF)
t
PHL
t
PLH
Frequency = 12.5MHz
Duty Cycle = 50%
V
DD1
=V
DD2
=3.3V
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
15 20 25 30 35 40 45 50 55
PWD - Pulse Width Dist or tion (ns)
C
L
-Output Load Capacitance (pF)
Frequency = 12.5MHz
Dut y Cycle = 50%
V
DD1
=V
DD2
=3.3V
4
5
6
7
8
9
10
11
12
15 20 25 30 35 40 45 50 55
t
r
-RiseTime(ns)
C
L
-Output Load Capacitance (pF)
Frequency = 12.5MHz
Dut y Cycl e = 50%
V
DD1
=V
DD2
=3.3V
2
4
6
8
10
12
14
16
15 20 25 30 35 40 45 50 55
t
f
-FallTime(ns)
C
L
-Output Load Capacitance (pF)
Frequency = 12. 5MHz
Duty Cycle = 50%
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
02000 4000 6000 8000 10000 12000
I
DD1
-Input Supply Current (mA)
f-Frequency (kHz)
T
A
=105°C
T
A
=25°C
T
A
=-40°C
V
DD1
=5.5V
5.0
5.2
5.4
5.6
5.8
6.0
02000 4000 6000 8000 10000 12000
I
DD2
-Output Supply Current (mA)
f-Frequency (kHz)
V
DD 1
=V
DD2
=5.5V
*Pin6Floating
T
A
=105°C
T
A
=25°C
T
A
=-40°C
Figure 7. Typical Propogation Delay vs. Output Load Capacitance Figure 8. Typical Width Distortion vs. Output Load Capacitance
Figure 9. Typical Rise Time vs. Output Load Capacitance Figure 10. Typical Fall Time vs. Output Load Capacitance
Figure 11. Input Supply Current vs. Frequency Figure 12. Output Supply Current vs. Frequency
V
DD1
=V
DD2
=3.3V
©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3 7
FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Test Circuits
Figure 13. Test Circuit for Propogation Delay Time and Rise Time, Fall Time
Figure 14. Test Circuit for Instantaneous Common Mode Rejection Voltage
VIN
tPLH
tR
VOUT VOL
50%
90%
10%
Input
Output
3.3V
50%
VOH
tF
tPHL
1
2VDD2 = 3.3V
VO
0.1µF
0V–3.3V
CL
3
4
8
7
6
5
0.1µF
VDD1 = 3.3V
Pulse width = 40ns
Duty Cycle = 50%
1
2VDD2 = 3.3V
VO
VCM
+–
0.1µF
SW
B
A
CL
3
4
8
7
6
5
0.1µF
VDD1 = 3.3V
VOH
0.8 x VDD
Switching Pos. (A) VIN = 3.3V
Switching Pos. (B) VIN = 0V
GND
1kV
VOL
VCM
CMH
CML
0.8V
©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3 8
FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Application Information
Noise is defined as any unwanted signal that degrades
or interferes with the operation of a system or circuit.
Input-output noise rejection is a key characteristic of an
optocoupler, and the performance specification for this
noise rejection is called, “Common Mode Transient
Immunity or Common Mode Rejection, CMR”. The CMR
test configuration is presented in high speed optocoupler
datasheets, which tests the optocoupler to a specified
rate of interfering signal (dv/dt), at a specified peak volt-
age (Vcm).
This defined noise signal is applied to the test device
while the coupler is a stable logic high or logic low state.
This test procedure evaluates the interface device in a
constant or static logic state. This type of CMR can be
referred to as “Static CMR”. Fairchild’s high speed opto-
couplers, which use an optically transparent, electrically
conductive shield, and offer active totem pole logic out-
put have static CMR in excess of 50KV/us at peak ampli-
tudes of 1.5kV to 2.0kV.
Dynamic Common Mode Rejection
The noise susceptibility of an interface while it is actively
transferring data is a common requirement in serial data
communication. However, the static CMR specification is
not adequate in quantifying the electrical noise suscepti-
bility for optocouplers used in isolating high speed data
transfer.
A serial data communication network’s noise perfor-
mance is usually quantified as the number of bit errors
per second or as a ratio of the number of bits transmitted
in a specified time frame. This describes Bit Error Rate,
BER. Test equipment that evaluates BER is called a Bit
Error Rate Tester, BERT. When a BERT system is com-
bined with a CMR tester, the active or dynamic noise
rejection of an isolated interface can then be quantified.
This type of CMR is thus defined as “Dynamic CMR”.
Therefore, evaluating the common mode rejection while
the optocoupler is switching at high speed represents a
realistic approach to understand noise interference.
Test circuit functions were built to interface a commercial
pseudo-random bit sequence (PRBS) generator and
error detector with a pair of high speed optocouplers,
FOD8001, connected in a loop-back configuration. With
a 10MBaud PRBS serial data stream, no error was
detected until the common mode voltage rose above
2.5kV with a dv/dt of 45kV/us. And increasing the data
rate beyond 10Mbaud, the test was conducted at
20MBaud, and no error was detected at dv/dt of 25kV/us
at common mode voltage of 1.5kV.
The test data for the dynamic CMR is comparable or
better than the static CMR specifications found in the
datasheet. These excellent noise rejection performances
are results of the innovative circuit design and the
Power Supply Noise Rejection
High levels of electrical noise can cause the optocoupler
to register the incorrect logic state. The most commonly
discussed noise signal is the common mode noise found
between the input and output of the optocoupler. How-
ever, common mode noise is not the only path of noise
into the input or output of the optocoupler. Due to the
high gain and wide bandwidth of the transimpedance
amplifier used for the photo detector circuits, power sup-
ply noise can cause the optocoupler to change state
independent of the LED operation. Power supply noise is
typically characterized as either random or periodic
pulses with varying amplitudes and rates of rise and fall.
The necessary tests have been conducted to understand
the influence of the power supply noise and its effect of
the proper operation of the FOD8001. The optocoupler
under test offered power supply noise rejection in excess
of 10% of the supply voltage for a frequency ranging
from 100kHz to 35MHz, for logic high and logic low
states.
proprietary coplanar assembly process.
©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3 9
FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Carrier Tape Specification
Note:
All dimensions are in millimeters.
Ordering Information
All packages are lead free per JEDEC: J-STD-020B standard.
Marking Information
Option Order Entry Identifier Description
No Suffix FOD8001 Small outline 8-pin, shipped in tubes (50 units per tube)
R2 FOD8001R2 Small outline 8-pin, tape and reel (2,500 units per reel)
4.0 ± 0.10
Ø1.5 MIN
User Direction of Feed
2.0 ± 0.05
1.75 ± 0.10
5.5 ± 0.05
12.0 ± 0.3
8.0 ± 0.10
0.30 MAX
8.3 ± 0.10
3.50 ± 0.20
0.1 MAX 6.40 ± 0.20
5.20 ± 0.20
Ø1.5 ± 0.1/-0
1
2
5
34
Definitions
1Fairchild logo
2Device number
3One digit year code, e.g., ‘8’
4Two digit work week ranging from ‘01’ to ‘53’
5Assembly package code
8001
S1YYX
©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD8001 Rev. 1.0.3 10
FOD8001 — High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Reflow Profile
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
Temperature
(°C)
Time (s)
0 60 180120 270
260°C
>245°C = 42 Sec
Time above
183°C = 90 Sec
360
1.822°C/Sec Ramp up rate
33 Sec
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