General Description
The MAX1392/MAX1395 micropower, serial-output,
10-bit, analog-to-digital converters (ADCs) operate with
a single power supply from +1.5V to +3.6V. These
ADCs feature automatic shutdown, fast wake-up, and a
high-speed 3-wire interface. Power consumption is only
0.740mW (VDD = +1.5V) at the maximum conversion
rate of 357ksps. AutoShutdown™ between conversions
reduces power consumption at slower throughput rates.
The MAX1392/MAX1395 require an external reference
VREF that has a wide range from 0.6V to VDD. The
MAX1392 provides one true-differential analog input
that accepts signals ranging from 0 to VREF (unipolar
mode) or ±VREF/2 (bipolar mode). The MAX1395 pro-
vides two single-ended inputs that accept signals rang-
ing from 0 to VREF. Analog conversion results are
available through a 5MHz, 3-wire SPI™-/QSPI™-
/MICROWIRE™-/digital signal processor (DSP)-compat-
ible serial interface. Excellent dynamic performance,
low voltage, low power, ease of use, and small pack-
age sizes make these converters ideal for portable bat-
tery-powered data-acquisition applications, and for
other applications that demand low power consumption
and minimal space.
The MAX1392/MAX1395 are available in a space-sav-
ing (3mm x 3mm) 10-pin TDFN package. The parts
operate over the extended (-40°C to +85°C) and mili-
tary (-55°C to +125°C) temperature ranges.
Applications
Portable Datalogging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Process Control
Features
♦357ksps 10-Bit Successive-Approximation
Register (SAR) ADCs
♦Single True-Differential Analog Input Channel
with Unipolar-/Bipolar-Selected Input (MAX1392)
♦Dual Single-Ended Input Channel with Channel-
Selected Input (MAX1395)
♦±0.5 LSB INL, ±0.5 LSB DNL, No Missing Codes
♦±1 LSB Total Unadjusted Error
♦61dB SINAD at 85kHz Input Frequency
♦Single-Supply Voltage (+1.5V to +3.6V)
♦0.945mW at 350ksps, 1.8V
♦0.27mW at 100ksps, 1.8V
♦3.1µW at 1ksps, 1.8V
♦< 1µA Shutdown Current
♦External Reference (0.6V to VDD)
♦AutoShutdown Between Conversions
♦SPI-/QSPI-/MICROWIRE-/DSP-Compatible,
3- or 4-Wire Serial Interface
♦Small (3mm x 3mm), 10-Pin TDFN
MAX1392/MAX1395
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3709; Rev 2; 11/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
ANALOG INPUTS
TOP MARK PKG CODE
MAX1392ETB -40°C to +85°C 10 TDFN-EP* 1-CH DIFF AOY T1033-1
MAX1392MTB** -55°C to +125°C 10 TDFN-EP* 1-CH DIFF —T1033-1
MAX1395ETB -40°C to +85°C 10 TDFN-EP* 2-CH S/E APB T1033-1
MAX1395MTB** -55°C to +125°C 10 TDFN-EP* 2-CH S/E —T1033-1
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Typical Operating Circuit and Pin Configurations appear at
end of data sheet.
*EP = Exposed pad.
**Future product—contact factory for availability.
MAX1392/MAX1395
2 _______________________________________________________________________________________
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +4V
SCLK, CS, OE, CH1/CH2, UNI/BIP,
DOUT to GND.........................................-0.3V to (VDD + 0.3V)
AIN+, AIN-, AIN1, AIN2, REF to GND ........-0.3V to (VDD + 0.3V)
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (TA= +70°C)
10-Pin TDFN (derate 18.5mW/°C above +70°C) ....1481.5mW
Operating Temperature Ranges
MAX139_E_ _...................................................-40°C to +85°C
MAX139_M_ _................................................-55°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 2)
Resolution 10 Bits
Integral Nonlinearity INL
±0.5
LSB
Differential Nonlinearity DNL No missing code overtemperature
±0.5
LSB
Offset Error
0.25 ±0.5
LSB
Gain Error Offset nulled
0.25 ±0.5
LSB
Total Unadjusted Error TUE ±1 LSB
Offset-Error Temperature
Coefficient ±0.001
LSB/°C
Gain-Error Temperature
Coefficient ±0.00025
LSB/°C
Channel-to-Channel Offset
Matching MAX1395 only
±0.1
LSB
Channel-to-Channel Gain
Matching MAX1395 only
±0.1
LSB
Input Common-Mode Rejection CMR VCM = 0 to VDD, MAX1392 only
±0.1
mV/V
DYNAMIC SPECIFICATIONS (Note 3)
Signal-to-Noise Plus Distortion SINAD VREF = VDD = 1.6 to 3.6V 61 dB
Signal-to-Noise Ratio SNR VREF = VDD = 1.6 to 3.6V 61 dB
Total Harmonic Distortion THD -83 -73 dBc
Spurious-Free Dynamic Range SFDR -84 -74 dBc
Intermodulation Distortion IMD fIN1 = 83kHz at -6.5dBFS,
fIN2 = 87kHz at -6.5dBFS -75 dB
Channel-to-Channel Crosstalk MAX1395 only -70 dB
Full-Power Bandwidth -3dB point 4
MHz
MAX1392
200
Full-Linear Bandwidth SINAD > 59dB MAX1395
150
kHz
MAX1392/MAX1395
_______________________________________________________________________________________ 3
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
CONVERSION RATE
Conversion Time tCONV 11 clock cycles 2.2 µs
Throughput Rate 14 clocks per conversion; includes power-
up, acquisition, and conversion time 357
ksps
Power-Up and Acquisition Time tACQ Three SCLK cycles
600
ns
Aperture Delay tAD 8ns
Aperture Jitter tAJ 30 ps
Serial Clock Frequency fCLK 0.1 5.0
MHz
ANALOG INPUTS (AIN+, AIN-, AIN1, AIN2)
Unipolar 0
VREF
Input Voltage Range VIN Bipolar, MAX1392 only (AIN+ - AIN-)
-VREF/2 +VREF/2
V
Common-Mode Input Voltage
Range VCM
Bipolar, MAX1392 only [(AIN+) + (AIN-)] / 2
0
VDD
V
Input Leakage Current Channel not selected, or conversion
stopped, or in shutdown mode
±1.5
µA
Input Capacitance 16 pF
REFERENCE INPUT (REF)
REF Input Voltage Range VREF 0.6 VDD +
0.05
V
REF Input Capacitance 24 pF
REF DC Leakage Current
0.025 ±2.5
µA
REF Input Dynamic Current 357ksps 20 60 µA
DIGITAL INPUTS (SCLK, CS, OE, CH1/CH2, UNI/BIP)
Input-Voltage Low VIL 0.3 x
VDD
V
Input-Voltage High VIH 0.7 x
VDD
V
Input Hysteresis 0.06 x
VDD
V
Input Leakage Current IIL Inputs at GND or VDD ±1 µA
CS, OE 1
Input Capacitance CIN CH1/CH2, UNI/BIP
12.5
pF
DIGITAL OUTPUT (DOUT)
Output-Voltage Low VOL ISINK = 2mA 0.1 x
VDD
V
Output-Voltage High VOH ISOURCE = 2mA 0.9 x
VDD
V
MAX1392/MAX1395
4 _______________________________________________________________________________________
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Tri-State Leakage Current ILT OE = VDD ±1 µA
Tri-State Output Capacitance COUT OE = VDD 10 pF
POWER SUPPLY
Positive Supply Voltage VDD 1.5 3.6 V
VDD = 1.6V
150
170
fSAMPLE = 100ksps VDD = 3V
200
225
VDD = 1.6V
520
600
fSAMPLE = 357ksps VDD = 3V
710
800
Power-down mode (Note 5) 5 10
Positive Supply Current (Note 4) IDD
Power-down mode (Note 6) 0.2
±2.5
µA
Power-Supply Rejection
(Note 7) PSR VDD = 1.5V to 3.6V, full-scale input
±150 ±1000 µV/V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Clock Period tCP 200 10000 ns
SCLK Pulse-Width High tCH 90 ns
SCLK Pulse-Width Low tCL 90 ns
CS Fall to SCLK Rise Setup tCSS 80 ns
SCLK Rise to CS Fall Ignore tCSO 0ns
SCLK Fall to DOUT Valid tDOV CLOAD = 0 to 30pF 10 80 ns
OE Rise to DOUT Disable tDOD 620ns
OE Fall to DOUT Enable tDOE 920ns
CS Pulse-Width High or Low tCSW 80 ns
OE Pulse-Width High or Low tOEW 80 ns
CH1/CH2 Setup Time (to the First SCLK) tCHS MAX1395 only 10 ns
CH1/CH2 Hold Time (to the First SCLK) tCHH MAX1395 only 0 ns
UNI/BIP Setup Time (to the First SCLK) tUBS MAX1392 only 10 ns
UNI/BIP Hold Time (to the First SCLK) tUBH MAX1392 only 0 ns
Note 1: Devices are production tested at TA= +25°C and TA= +85°C. Specifications to -40°C are guaranteed by design.
Note 2: VDD = 1.5V, VREF = 1.5V, and VAIN = 1.5V.
Note 3: VDD = 1.5V, VREF = 1.5V, VAIN = 1.5VP-P, fSCLK = 5MHz, fSAMPLE = 357ksps, and fIN (sine-wave) = 85kHz.
Note 4: All digital inputs swing between VDD and GND. VREF = VDD, fIN = 85kHz sine-wave, VAIN = VREFP-P, CLOAD = 30pF on DOUT.
Note 5: CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is active.
Note 6: CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is inactive.
Note 7: Change in VAIN at code boundary 1022.5.
TIMING CHARACTERISTICS
(VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1µF, fSCLK = 5MHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at
TA= +25°C.) (Figure 1)
MAX1392/MAX1395
_______________________________________________________________________________________ 5
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
Figure 1. Detailed Serial-Interface Timing Diagram
GND
50pF 50pF
DOUT DOUT
GND
VDD
a) HIGH IMPEDANCE TO VOH, VOL TO VOH,
AND VOH TO HIGH IMPEDANCE
b) HIGH IMPEDANCE TO VOL, VOH TO VOL,
AND VOL TO HIGH IMPEDANCE
10mA
10mA
Figure 2. Load Circuits for Enable/Disable Times
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
MAX1392/MAX1395
6 _______________________________________________________________________________________
DNL ERROR vs. REFERENCE VOLTAGE
MAX1392/95 toc04
REFERENCE VOLTAGE (V)
DNL ERROR (LSB)
3.12.62.11.61.1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0.6 3.6
VDD = 3.6V
MAX DNL
MIN DNL
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1392/95 toc05
SUPPLY VOLTAGE (V)
OFFSET ERROR (µV)
VREF = 1.5V
TEMPERATURE = +25°C
-300
-200
-100
0
100
200
300
400
-400
3.33.01.8 2.1 2.4 2.71.5 3.6
AIN1
AIN2
OFFSET ERROR vs. TEMPERATURE
MAX1392/95 toc06
TEMPERATURE (°C)
OFFSET ERROR (µV)
95-25 5 35 65
-300
-200
-100
0
100
200
300
400
-400
-55 125
VDD = 3.6V
AIN1
AIN2
OFFSET ERROR
vs. REFERENCE VOLTAGE
MAX1392/95 toc07
REFERENCE VOLTAGE (V)
OFFSET ERROR (µV)
3.11.1 1.6 2.1 2.6
-300
-200
-100
0
100
200
300
400
-400
0.6 3.6
VDD = 3.6V
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1392/95 toc08
SUPPLY VOLTAGE (V)
GAIN ERROR (µV)
3.33.01.8 2.1 2.4 2.7
-300
-200
-100
0
100
200
300
400
-400
1.5 3.6
VREF = 1.5V
TEMPERATURE = +25°C
AIN1
AIN2
GAIN ERROR vs. TEMPERATURE
MAX1392/95 toc09
TEMPERATURE (°C)
GAIN ERROR (µV)
95-25 5 35 65
-300
-200
-100
0
100
200
300
400
-400
-55 125
VDD = 3.6V
AIN1
AIN2
Typical Operating Characteristics
(VDD = +1.5V, VREF = +1.5V, CREF = 0.1µF, CL= 30pF, fSCLK = 5MHz. TA= +25°C, unless otherwise noted.)
INL vs. CODE
MAX1392/95 toc01
CODE
INL (LSB)
896768512 640256 384128
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
01024
INL ERROR vs. REFERENCE VOLTAGE
MAX1392/95 toc02
REFERENCE VOLTAGE (V)
INL ERROR (LSB)
3.12.62.11.61.1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0.6 3.6
VDD = 3.6V
MAX INL
MIN INL
DNL vs. CODE
MAX1392/95 toc03
CODE
DNL (LSB)
896768512 640256 384128
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 1024
MAX1392/MAX1395
_______________________________________________________________________________________ 7
SUPPLY CURRENT
vs. CONVERSION RATE
MAX1392/95 toc13
fSAMPLE (ksps)
SUPPLY CURRENT (µA)
30025020015010050
200
400
600
800
0
0350
fSCLK = 5MHz, fSAMPLE = 357ksps
AIN = FULL SCALE, 85kHz SINE WAVE
CL = 30pF
VDD = VREF = 1.6V
VDD = VREF = 3.0V
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX1392/95 toc14
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (µA)
3.33.02.72.42.11.8
0.1
0.2
0.3
0.4
0.5
0
1.5 3.6
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1392/95 toc15
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (µA)
9565355-25
0.4
0.8
1.2
1.6
2.0
0
-55 125
VDD = 1.8V
VDD = 3.6V
SCLK-TO-DOUT TIMING
MAX1392/95 toc16
CLOAD (pF)
DOUT DELAY (ns)
500400300200100
10
20
30
40
50
60
70
80
90
100
0
0600
VDD = 3.6V
VDD = 1.5V
FFT
MAX1392/95 toc17
FREQUENCY (kHz)
MAGNITUDE (dB)
12010080604020
-100
-80
-60
-40
-20
0
-120
0140
160 180
VDD = 1.6V
VREF = 1.6V
fS = 357ksps
fIN = 85kHz
THD = -82.7dB
SINAD = 61.3dB
SFDR = -83.8dB
SAMPLING ERROR
vs. SOURCE IMPEDANCE
MAX1392/95 toc18
SOURCE IMPEDENCE (Ω)
SAMPLING ERROR (LSB)
200015001000500
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 2500
AIN HIGH-TO-LOW FS TRANSITION
AIN LOW-TO-HIGH FS TRANSITION
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
GAIN ERROR
vs. REFERENCE VOLTAGE
MAX1392/95 toc10
REFERENCE VOLTAGE (V)
GAIN ERROR (µV)
3.11.1 1.6 2.1 2.6
-300
-200
-100
0
100
200
300
400
-400
0.6 3.6
VDD = 3.6V
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1392/95 toc11
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
3.33.02.72.42.11.8
500
600
700
800
400
1.5 3.6
VREF = 1.5V, CL = 33pF
fSCLK = 5MHz, fSAMPLE = 357ksps
AIN = FULL SCALE, 10kHz SINE WAVE
SUPPLY CURRENT vs. TEMPERATURE
MAX1392/95 toc12
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
9565355-25
450
500
550
600
400
-55 125
VREF = 1.5V, CL = 33pF
fSCLK = 5MHz, fSAMPLE = 357ksps
AIN = FULL SCALE, 10kHz SINE WAVE
Typical Operating Characteristics (continued)
(VDD = +1.5V, VREF = +1.5V, CREF = 0.1µF, CL= 30pF, fSCLK = 5MHz. TA= +25°C, unless otherwise noted.)
MAX1392/MAX1395
Detailed Description
The MAX1392/MAX1395 use an input track and hold
(T/H) circuit along with a SAR to convert an analog input
signal to a serial 10-bit digital output data stream. The
serial interface provides easy interfacing to microproces-
sors and DSPs. Figure 3 shows the simplified functional
diagram for the MAX1392 (1 channel, true differential)
and the MAX1395 (2 channels, single ended).
True-Differential Analog Input T/H
The equivalent input circuit of Figure 4 shows the
MAX1392/MAX1395 input architecture, which is com-
posed of a T/H, a comparator, and a switched-capacitor
DAC. The T/H enters its tracking mode on the falling
edge of CS (while OE is held low). The positive input
capacitor is connected to AIN+ (MAX1392), or to AIN1 or
AIN2 (MAX1395). The negative input capacitor is con-
nected to AIN- (MAX1392) or GND (MAX1395). The T/H
enters its hold mode on the 3rd falling edge of SCLK
8 _______________________________________________________________________________________
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
PIN
MAX1392
MAX1395
NAME FUNCTION
11V
DD Positive Supply Voltage. Connect VDD to a 1.5V to 3.6V power supply. Bypass VDD to GND
with a 0.1µF capacitor as close to the device as possible.
2—AIN- Negative Analog Input
—2 AIN2 Analog Input Channel 2
3—AIN+ Positive Analog Input
—3 AIN1 Analog Input Channel 1
4 4 GND Ground
5 5 REF External Reference Voltage Input. VREF = 0.6V to (VDD + 0.05V). Bypass REF to GND with a
0.1µF capacitor as close to the device as possible.
6—
UNI/BIP
Input-Mode Select. Drive UNI/BIP high to select unipolar input mode. Pull UNI/BIP low to
select bipolar input mode. In unipolar mode, the output data is in straight binary format. In
bipolar mode, the output data is in two’s-complement format.
—6
CH1/CH2
Channel-Select Input. Pull CH1/CH2 low to select channel 1. Drive CH1/CH2 high to select
channel 2.
77OE
Active-Low Output Enable. Pull OE low to enable DOUT. Drive OE high to disable DOUT.
Connect to CS to interface with SPI, QSPI, and MICROWIRE devices or set low to interface
with DSP devices.
88CS Active-Low Chip-Select Input. A falling edge on CS initiates power-up and acquisition.
9 9 DOUT Serial-Data Output. DOUT changes state on the falling edge of SCLK. DOUT is high
impedance when OE is high.
10 10 SCLK
Serial-Clock Input. SCLK drives the conversion process and clocks data out. Acquisition ends
on the 3rd falling edge after the CS falling edge. The LSB is clocked out on the SCLK 13th
falling edge and the device enters AutoShutdown mode (see Figures 8, 9, and 10).
——EP Exposed Pad. Not internally connected. Connect the exposed pad to GND or leave
unconnected.
Pin Description
DOUT
VDD
REF
10-BIT SAR
ADC
CS
SCLK
OE
GND
OUTPUT
SHIFT
REGISTER
CONTROL
LOGIC AND
TIMING
*INDICATES THE MAX1395
AIN+ (AIN1)*
AIN- (AIN2)*
INPUT
MUX
AND T/H
UNI/BIP
(CH1/CH2)*
MAX1392
MAX1395
Figure 3. Simplified Functional Diagram
and the difference between the sampled positive and
negative input voltages is converted. The time required
for the T/H to acquire an input signal is determined by
how quickly its input capacitance is charged. The
required acquisition time lengthens as the input signal’s
source impedance increases. The acquisition time,
tACQ, is the minimum time needed for the signal to be
acquired. It is calculated by the following equation:
tACQ ≥7.4 x (RSOURCE + RIN) x CIN + tPU
where:
RSOURCE is the source impedance of the input signal.
RIN = 500Ω, which is the equivalent differential analog
input resistance.
CIN = 16pF, which is the equivalent differential analog
input capacitance.
tPU = 400ns.
Note: tACQ is never less than 600ns and any source
impedance below 400Ωdoes not significantly affect the
ADC’s AC performance.
Analog Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz full-
power bandwidth, making it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques.
Use anti-alias filtering to avoid high-frequency signals
being aliased into the frequency band of interest.
Analog Input Range and Protection
The MAX1392/MAX1395 produce a digital output that
corresponds to the analog input voltage as long as the
analog inputs are within their specified range. When
operating the MAX1392 in unipolar mode (UNI/BIP = 1),
the specified differential analog input range is from 0 to
VREF. When operating in bipolar mode (UNI/BIP = 0),
the differential analog input range is from -VREF/2 to
+VREF/2 with a common mode range of 0 to VDD. The
MAX1395 has an input range from 0 to VREF.
Internal protection diodes confine the analog input volt-
age within the region of the analog power input rails
(VDD, GND) and allow the analog input voltage to swing
from GND - 0.3V to VDD + 0.3V without damage. Input
voltages beyond GND - 0.3V and VDD + 0.3V forward
bias the internal protection diodes. In this situation, limit
the forward diode current to less than 50mA to avoid
damage to the MAX1392/MAX1395.
Output Data Format
Figures 8, 9, and 10 illustrate the conversion timing for
the MAX1392/MAX1395. Fourteen SCLK cycles are
required to read the conversion result and data on
DOUT transitions on the falling edge of SCLK. The con-
version result contains 4 zeros, followed by 10 data bits
with the data in MSB-first format. For the MAX1392, data
is straight binary for unipolar mode and two’s comple-
ment for bipolar mode. For the MAX1395, data is always
straight binary.
Transfer Function
Figure 5 shows the unipolar transfer function for the
MAX1392/MAX1395. Figure 6 shows the bipolar trans-
fer function for the MAX1392. Code transitions occur
halfway between successive-integer LSB values.
MAX1392/MAX1395
_______________________________________________________________________________________ 9
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
+
-
HOLD
TRACK
CIN+
REF
GND DAC
CIN-
RIN+RIN-
VDD/2
RSOURCE
COMPARATOR
HOLD
HOLD
AIN2
AIN1 (AIN+)*
GND- (AIN-)*
ANALOG
SIGNAL
SOURCE
MAX1392
MAX1395
*INDICATES THE MAX1392
Figure 4. Equivalent Input Circuit
MAX1392/MAX1395
Applications Information
Starting a Conversion
A falling edge on CS initiates the power-up sequence
and begins acquiring the analog input as long as OE is
also asserted low. On the 3rd SCLK falling edge, the
analog input is held for conversion. The most significant
bit (MSB) decision is made and clocked onto DOUT on
the 4th SCLK falling edge. Valid DOUT data is available
to be clocked into the master (microcontroller (µC)) on
the following SCLK rising edge. The rest of the bits are
decided and clocked out to DOUT on each successive
SCLK falling edge. See Figures 8 and 9 for conversion
timing diagrams.
Once a conversion has been initiated, CS can go high at
any time. Further falling edges of CS do not reinitiate an
acquisition cycle until the current conversion completes.
Once a conversion completes, the first falling edge of CS
begins another acquisition/conversion cycle.
Selecting Unipolar or Bipolar Mode
(MAX1392 Only)
Drive UNI/BIP high to select unipolar mode or pull
UNI/BIP low to select bipolar mode. UNI/BIP can be
connected to VDD for logic high, to GND for logic low,
or actively driven. UNI/BIP needs to be stable for tUBS
prior to the first rising edge of SCLK after the CS falling
edge (see Figure 1) for a valid conversion result when
being actively driven.
Selecting Analog Input AIN1 or AIN2
(MAX1395 Only)
Pull CH1/CH2 low to select AIN1 or drive CH1/CH2
high to select AIN2 for conversion. CH1/CH2 can be
connected to VDD for logic high, to GND for logic low,
or actively driven. CH1/CH2 needs to be stable for tCHS
prior to the first rising edge of SCLK after the CS falling
edge (see Figure 1) for a valid conversion result when
being actively driven.
10 ______________________________________________________________________________________
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
ZS = 0
FS = VREF
1 LSB = VREF
1024
FS
3FF
3FE
3FC
3FB
000
001
003
004
OUTPUT CODE (hex)
INPUT VOLTAGE (LSB)
3FD
01234 FS - 1.5 LSB
FULL-SCALE
TRANSITION
002
Figure 5. Unipolar Transfer Function
ZS = 0
+FS = VREF
2
-FS = -VREF
2
1 LSB = VREF
1024
-FS +FS
1FF
1FE
001
000
200
201
3FE
OUTPUT CODE (hex)
INPUT VOLTAGE (LSB)
3FF
0+FS - 1.5 LSB-FS + 0.5 LSB
FULL-SCALE
TRANSITION
Figure 6. Bipolar Transfer Function
AutoShutdown Mode
The ADC automatically powers down on the SCLK
falling edge that clocks out the LSB. This is the falling
edge after the 13th SCLK. DOUT goes low when the
LSB has been clocked into the master (µC) on the 16th
rising SCLK edge.
Alternatively, drive OE high to force the MAX1392/
MAX1395 into power-down. Whenever OE goes high,
the ADC powers down and disables DOUT regardless
of CS, SCLK, or the state of the ADC. DOUT enters a
high-impedance state after tDOD.
External Reference
The MAX1392/MAX1395 use an external reference
between 0.6V and (VDD + 50mV). Bypass REF with a
0.1µF capacitor to GND for best performance (see the
Typical Operating Circuit).
Serial Interface
The MAX1392/MAX1395 serial interface is fully compati-
ble with SPI, QSPI, and MICROWIRE (see Figure 7). If a
serial interface is available, set the µC’s serial interface
in master mode so the µC generates the serial clock.
Choose a clock frequency between 100kHz and 5MHz.
CS and OE can be connected together and driven
simultaneously. OE can also be connected to GND if the
DOUT bus is not shared and driven independently.
SPI and MICROWIRE
When using SPI or MICROWIRE, make the µC the bus
master and set CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1. (These are the bits in the SPI or
MICROWIRE control register.) Two consecutive 1-byte
reads are required to get the entire 10-bit result from
the ADC. The MAX1392/MAX1395 shut down after
clocking the LSB and DOUT becomes high impedance.
DOUT transitions on SCLK’s falling edge and is
clocked into the µC on the SCLK’s rising edge. See
Figure 7 for connections and Figures 8 and 9 for timing
diagrams. The conversion result contains 4 zeros, fol-
lowed by the 10 data bits with the data in MSB-first for-
mat. When using CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1, the MSB of the data is clocked into the
µC on the SCLK’s fifth rising edge. To be compatible
with SPI and MICROWIRE, connect CS and OE togeth-
er and drive simultaneously.
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 10 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1392/MAX1395 require a minimum of 14
clock cycles from the µC to clock out the 10 bits of
data. See Figure 7 for connections and Figures 8 and 9
for timing diagrams. The conversion result contains 4
zeros, followed by the 10 data bits with the data in
MSB-first format. The MAX1392/MAX1395 shut down
after clocking out the LSB. DOUT then becomes high
impedance. When using CPOL = 0 and CPHA = 0 or
CPOL = 1 and CPHA = 1, the MSB of the data is
clocked into the µC on the SCLK’s fifth rising edge. To
be compatible with QSPI, connect CS and OE together
and drive simultaneously.
DSP Interface
Figure 10 shows the timing for DSP operation. Figure 11
shows the connections between the MAX1392/
MAX1395 and several common DSPs.
MAX1392/MAX1395
______________________________________________________________________________________ 11
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
MAX1392
MAX1395
OE
a) SPI
I/O
SCK
CS
DOUTMISO
I/O UNI/BIP
(CH1/CH2)*
SCLK
MAX1392
MAX1395
OECS
SCK
CS
DOUTMISO
I/O UNI/BIP
(CH1/CH2)*
SCLK
MAX1392
MAX1395
OEI/O
SK
CS
DOUTSI
I/O UNI/BIP
(CH1/CH2)*
SCLK
b) QSPI
c) MICROWIRE
*INDICATES THE MAX1395
Figure 7. Common Serial-Interface Connections to the
MAX1392/MAX1395
MAX1392/MAX1395
12 ______________________________________________________________________________________
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
Figure 8. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 1) and MICROWIRE (G6 = 0, G5 = 1)
Figure 9. Serial-Interface Timing for SPI/QSPI (CPOL = CPHA = 0) and MICROWIRE (G6 = 0, G5 = 0)
As shown in Figure 11, drive the MAX1392/MAX1395
chip-select input (CS) with the DSP’s frame-sync signal.
OE may be connected to GND or driven independently.
For continuous conversion operation, keep OE low and
make the CS falling edge coincident with the 14th
falling edge of the SCLK. Fourteen-bit data transfers
can also be performed with compatible DSPs.
Unregulated Two-Cell or Single Lithium
LiMnO2Cell Operation
Low operating voltage (1.5V to 3.6V) and ultra-low-power
consumption make the MAX1392/MAX1395 ideal for low
cost, unregulated, battery-powered applications without
the need for a DC-DC converter. Power the MAX1392/
MAX1395 directly from two alkaline/NiMH/NiCd cells in
series or a single lithium coin cell as shown in the Typical
Operating Circuit.
Fresh alkaline cells have a voltage of approximately
1.5V per cell (3V with 2 cells in series) and approach
end of life at 0.8V (1.6V with 2 cells in series). A typical
2xAA alkaline discharge curve is shown in Figure 12a.
A typical CR2032 lithium (LiMnO2) coin cell discharge
curve is shown in Figure 12b.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Board layout
must ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 13 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at the MAX1392/MAX1395s’ GND
pin or use the ground plane.
High-frequency noise in the power supply (VDD)
degrades the ADC’s performance. Bypass VDD to GND
with a 0.1µF capacitor as close to the device as possi-
ble. Minimize capacitor lead lengths for best supply
noise rejection. To reduce the effects of supply noise, a
10Ωresistor can be connected as a lowpass filter to
attenuate supply noise.
Exposed Pad
The MAX1392/MAX1395 TDFN package has an
exposed pad on the bottom of the package. This pad is
not internally connected. Connect the exposed pad to
the GND pin on the MAX1392/MAX1395 or leave
unconnected for proper electrical performance.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For the MAX1392/
MAX1395, this straight line is between the end points of
the transfer function once offset and gain errors have
been nullified. INL deviations are measured at every
step and the worst-case deviation is reported in the
Electrical Characteristics section.
MAX1392/MAX1395
______________________________________________________________________________________ 13
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
Figure 10. DSP Serial-Timing Diagram
MAX1392/MAX1395
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
less than ±1 LSB guarantees no missing codes and a
monotonic transfer function. For the MAX1392/
MAX1395, DNL deviations are measured at every step
and the worst-case deviation is reported in the
Electrical Characteristics section.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus the RMS distortion. RMS
noise includes all spectral components to the Nyquist
frequency excluding the fundamental, the first five har-
monics (HD2–HD6), and the DC offset. RMS distortion
includes the first five harmonics (HD2–HD6).
SINAD SIGNAL
NOISE DISTORTION
RMS
RMS RMS
log
=×
+
20
22
14 ______________________________________________________________________________________
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
MAX1392
MAX1395
OE
a) TMS320C541 CONNECTION DIAGRAM
I/O
FSX
FSR
CS
DOUTDR
I/O UNI/BIP
(CH1/CH2)*
CLKX
CLKR
SCLK
MAX1392
MAX1395
OE
b) ADSP218x CONNECTION DIAGRAM
I/O
TFS
RFS
CS
DOUTDR
I/O UNI/BIP
(CH1/CH2)*
SCLK SCLK
MAX1392
MAX1395
OE
c) DSP563xx CONNECTION DIAGRAM
*INDICATES THE MAX1395
I/O
SC2 CS
DOUT
I/O UNI/BIP
(CH1/CH2)*
SLK
SDR
SCLK
Figure 11. Common DSP Connections to the MAX1392/MAX1395
DAYS
VOLTAGE (V)
1.8
2.0
2.2
2.4
2.6
2.8
3.0
1.6
0 700600500400300200100
TA = +25°C
Figure 12a. Typical 2xAA Discharge Curve at 100ksps
DAYS
VOLTAGE (V)
40302010
1.8
2.0
2.2
2.4
2.6
2.8
3.0
1.6
050
TA = +25°C
Figure 12b. Typical CR2032 Discharge Curve at 100ksps
Signal-to-Noise Ratio (SNR)
SNR is a dynamic figure of merit that indicates the con-
verter’s noise performance. For a waveform perfectly
reconstructed from digital samples, the theoretical
maximum SNR is the ratio of the full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization error only and results
directly from the ADC’s resolution (N bits):
SNRdB[max] = 6.02dB x N + 1.76dB
In reality, there are other noise sources such as thermal
noise, reference noise, and clock jitter that also
degrade SNR. SNR is computed by taking the ratio of
the RMS signal to the RMS noise. RMS noise includes
all spectral components to the Nyquist frequency
excluding the fundamental, the first five harmonics, and
the DC offset.
Total Harmonic Distortion (THD)
THD is a dynamic figure of merit that indicates how much
harmonic distortion the converter adds to the signal.
THD is the ratio of the RMS sum of the first five harmon-
ics of the fundamental signal to the fundamental itself.
This is expressed as:
where V1is the fundamental amplitude, and V2through
V6are the amplitudes of the 2nd- through 6th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is a dynamic figure of merit that indicates the
lowest usable input signal amplitude. SFDR is the ratio
of the RMS amplitude of the fundamental (maximum
signal component) to the RMS value of the next-largest
spurious component, excluding DC offset. SFDR is
specified in decibels relative to the carrier (dBc).
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
The fundamental input tone amplitudes (V1and V2) are
at -6.5dBFS. Fourteen intermodulation products (VIM_)
are used in the MAX1392/MAX1395 IMD calculation.
The intermodulation products are the amplitudes of the
output spectrum at the following frequencies, where fIN1
and fIN2 are the fundamental input tone frequencies:
•2nd-order intermodulation products:
fIN1 + fIN2, fIN2 - fIN1
•3rd-order intermodulation products:
2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1
•4th-order intermodulation products:
3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1
•5th-order intermodulation products:
3 x fIN1 - 2 x fIN2, 3 x fIN2 - 2 x fIN1, 3 x fIN1 + 2 x
fIN2, 3 x fIN2 + 2 x fIN1
Channel-to-Channel Crosstalk
Channel-to-channel crosstalk indicates how well each
analog input is isolated from the others. The channel-to-
channel crosstalk for the MAX1395 is measured by
applying DC to channel 2 while an AC sine wave is
applied to channel 1. An FFT is taken for channel 1 and
channel 2 and the difference (in dB) is reported as the
channel-to-channel crosstalk.
IMD VV V V
VV
IM IM IM IMN
log .....
=× ++++
+
20 1
222322
1
222
THD VVVVV
V
log
=× ++++
20 2
2
3
2
4
2
5
2
6
2
1
MAX1392/MAX1395
______________________________________________________________________________________ 15
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
10Ω
(OPTIONAL)
VDD
VDD
POWER SUPPLY
GND
DIGITAL
CIRCUITRY
GND DGND
DATA
STAR
GROUND
POINT
DVDD
VDD
MAX1392/MAX1395
Figure 13. Power-Supply Grounding Connections
MAX1392/MAX1395
Aperture Delay
The MAX1392/MAX1395 sample data on the falling
edge of its third SCLK cycle (Figure 14). In actuality,
there is a small delay between the falling edge of the
sampling clock and the actual sampling instant.
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the aperture delay (Figure 14).
DC Power-Supply Rejection Ratio (PSRR)
DC PSRR is defined as the change in the positive full-
scale transfer function point caused by a full range vari-
ation in the analog power-supply voltage (VDD).
16 ______________________________________________________________________________________
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
tAD
T/H
(INTERNAL
SIGNAL)
SCLK
tAJ
TRACK HOLD
ANALOG
INPUT
SAMPLED
DATA
THIRD FALLING EDGE
Figure 14. T/H Aperture Timing
AIN+ (AIN1)*
DOUT
SCLK
AIN- (AIN2)*
REF
INPUT
VOLTAGE
*INDICATES THE MAX1395 ONLY
2 x AA CELLS
CPU
+
-
VDD
GND
REF
INPUT
VOLTAGE
0.1µF
0.1µF
CS
OE
UNI/BIP
(CH1/CH2)*
MISO
SCL
SS
MAX1392
MAX1395
Typical Operating CircuitChip Information
TRANSISTOR COUNT: 9106
PROCESS: BiCMOS
MAX1392/MAX1395
______________________________________________________________________________________ 17
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
Pin Configurations
Revision History
Pages changed at Rev 2: 1, 3, 8, 13, 14, 18
MAX1392/MAX1395
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
6, 8, &10L, DFN THIN.EPS
H
1
2
21-0137
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
COMMON DIMENSIONS
SYMBOL MIN. MAX.
A 0.70 0.80
D 2.90 3.10
E 2.90 3.10
A1 0.00 0.05
L 0.20 0.40
PKG. CODE N D2 E2 eJEDEC SPEC b[(N/2)-1] x e
PACKAGE VARIATIONS
0.25 MIN.k
A2 0.20 REF.
2.30–0.101.50–0.106T633-1 0.95 BSC MO229 / WEEA 1.90 REF0.40–0.05
1.95 REF0.30–0.050.65 BSC2.30–0.108T833-1
2.00 REF0.25–0.050.50 BSC2.30–0.1010T1033-1
2.40 REF0.20–0.05- - - - 0.40 BSC1.70–0.10 2.30–0.1014T1433-1
1.50–0.10
1.50–0.10
MO229 / WEEC
MO229 / WEED-3
0.40 BSC - - - - 0.20–0.05 2.40 REFT1433-2 14 2.30–0.101.70–0.10
T633-2 6 1.50–0.10 2.30–0.10 0.95 BSC MO229 / WEEA 0.40–0.05 1.90 REF
T833-2 8 1.50–0.10 2.30–0.10 0.65 BSC MO229 / WEEC 0.30–0.05 1.95 REF
T833-3 8 1.50–0.10 2.30–0.10 0.65 BSC MO229 / WEEC 0.30–0.05 1.95 REF
-DRAWING NOT TO SCALE- H
2
2
21-0137
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
2.30–0.10 MO229 / WEED-3 2.00 REF0.25–0.05
0.50 BSC
1.50–0.1010T1033-2
ENGLISH • ???? • ??? • ???
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MAX1392, MAX1395
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/2-Channel Single-Ended, 10-Bit, SAR ADCs
Ultra-Low Power and Supply Voltage Make These ADCs Ideal for Battery-Powered Applications
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DRAWING CODE/VAR *
Temp
RoHS/Lead-Free?
Materials Analysis
MAX1392ETB-T
THIN QFN (Dual);10 pin;10 mm
Dwg: 21-0137I (PDF)
Use pkgcode/variation: T1033-1*
-40C to +85C
RoHS/Lead-Free: See data sheet
Materials Analysis
MAX1392ETB
THIN QFN (Dual);10 pin;10 mm
Dwg: 21-0137I (PDF)
Use pkgcode/variation: T1033-1*
-40C to +85C
RoHS/Lead-Free: See data sheet
Materials Analysis
MAX1392MTB-T
THIN QFN (Dual);10 pin;10 mm
Dwg: 21-0137I (PDF)
Use pkgcode/variation: T1033-1*
-55C to +125C
RoHS/Lead-Free: See data sheet
Materials Analysis
MAX1392MTB
THIN QFN (Dual);10 pin;10 mm
Dwg: 21-0137I (PDF)
Use pkgcode/variation: T1033-1*
-55C to +125C
RoHS/Lead-Free: See data sheet
Materials Analysis
MAX1395
Free
Sam ple
Buy
Package:
TYPE PINS FOOTPRINT
DRAWING CODE/VAR *
Temp
RoHS/Lead-Free?
Materials Analysis
MAX1395MTB+
-55C to +125C
RoHS/Lead-Free: See data sheet
MAX1395ETB
THIN QFN (Dual);10 pin;10 mm
Dwg: 21-0137I (PDF)
Use pkgcode/variation: T1033-1*
-40C to +85C
RoHS/Lead-Free: No
Materials Analysis
MAX1395ETB+
THIN QFN (Dual);10 pin;10 mm
Dwg: 21-0137I (PDF)
Use pkgcode/variation: T1033+1*
-40C to +85C
RoHS/Lead-Free: Lead Free
Materials Analysis
MAX1395MTB
THIN QFN (Dual);10 pin;10 mm
Dwg: 21-0137I (PDF)
Use pkgcode/variation: T1033-1*
-55C to +125C
RoHS/Lead-Free: See data sheet
Materials Analysis
MAX1395ETB+T
THIN QFN (Dual);10 pin;10 mm
Dwg: 21-0137I (PDF)
Use pkgcode/variation: T1033+1*
-40C to +85C
RoHS/Lead-Free: Lead Free
Materials Analysis
MAX1395ETB-T
THIN QFN (Dual);10 pin;10 mm
Dwg: 21-0137I (PDF)
Use pkgcode/variation: T1033-1*
-40C to +85C
RoHS/Lead-Free: No
Materials Analysis
MAX1395MTB-T
THIN QFN (Dual);10 pin;10 mm
Dwg: 21-0137I (PDF)
Use pkgcode/variation: T1033-1*
-55C to +125C
RoHS/Lead-Free: See data sheet
Materials Analysis
MAX1395MTB+T
-55C to +125C
RoHS/Lead-Free: See data sheet
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Document Ref.: 1 9-3709; Rev 2; 2006-11-07
This page last modified: 2 006 -11-10
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