TDA8358J_N1 - Philips Semiconductors / NXP Semiconductors

DATA SH EET

Product speciﬁcation

File under Integrated Circuits, IC02 1999 Dec 22

INTEGRATED CIRCUITS

TDA8358J

Fullbridgeverticaldeflectionoutput

circuit in LVDMOS with east-west

amplifier

1999 Dec 22 2

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

FEATURES

•Few external components required

•High efficiency fully DC coupled vertical bridge output

circuit

•Vertical flyback switch with short rise and fall times

•Built-in guard circuit

•Thermal protection circuit

•Improved EMC performance due to differential inputs

•East-west output stage.

GENERAL DESCRIPTION

The TDA8358J is a power circuit for use in 90°and 110°

colour deflection systems for 25 to 200 Hz field

frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC

contains a vertical deflection output circuit, operating as a

high efficiency class G system. The full bridge output

circuit allows DC coupling of the deflection coil in

combination with single positive supply voltages.

The east-west output stage is able to supply the sink

current for a diode modulator circuit.

The IC is constructed in a Low Voltage DMOS (LVDMOS)

process that combines bipolar, CMOS and DMOS

devices. DMOS transistors are used in the output stage

because of absence of second breakdown.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VPsupply voltage 7.5 12 18 V

VFB ﬂyback supply voltage 2VP45 66 V

Iq(P)(av) average quiescent supply current during scan −10 15 mA

Iq(FB)(av) average quiescent ﬂyback supply current during scan −−10 mA

PEW east-west power dissipation −−4W

tot total power dissipation −−15 W

Inputs and outputs

Vi(dif)(p-p) differential input voltage (peak-to-peak value) −1000 1500 mV

Io(p-p) output current (peak-to-peak value) −−3.2 A

Flyback switch

Io(peak) maximum (peak) output current t ≤1.5 ms −−±1.8 A

East-west ampliﬁer

Vooutput voltage −−68 V

VI(bias) input bias voltage 2 −3.2 V

Iooutput current −−750 mA

Thermal data; in accordance with IEC 747-1

Tstg storage temperature −55 −+150 °C

Tamb ambient temperature −25 −+75 °C

Tjjunction temperature −−150 °C

1999 Dec 22 3

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

ORDERING INFORMATION

BLOCK DIAGRAM

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

TDA8358J DBS13P plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6

handbook, full pagewidth

MGL866

INPUT

AND

FEEDBACK

CIRCUIT

GUARD

CIRCUIT

TDA8358J

11 93

INA

INB

INEW

VGND EWGND

GUARD VPVFB

VI(bias)

Vi(p-p)

VI(bias)

Vi(p-p)

0OUTB

OUTEW

OUTA

FEEDB

COMP.

CIRCUIT

COMP

II(av)

Ii(p-p)

Fig.1 Block diagram.

1999 Dec 22 4

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

PINNING FUNCTIONAL DESCRIPTION

Vertical output stage

The vertical driver circuit has a bridge configuration.

The deflection coil is connected between the

complimentary driven output amplifiers. The differential

input circuit is voltage driven. The input circuit is specially

designed for direct connection to driver circuits delivering

a differential signal but it is also suitable for single-ended

applications. The output currents of the driver device are

converted to voltages by the conversion resistors

RCV1 and RCV2 (see Fig.3) connected to pins INA

and INB. The differential input voltage is compared with

the voltage across the measuring resistor RM, providing

internal feedback information. The voltage across RM is

proportional with the output current. The relationship

between the differential input current and the output

current is defined by:

2×Ii(dif)(p-p) ×RCV =I

o(p-p) ×RM

The output current should measure 0.5 to 3.2 A (p-p) and

is determined by the value of RMand RCV. The allowable

input voltage range is 100 mV to 1.6 V for each input. The

formula given does not include internal bondwire

resistances.DependingonthevalueofRMandtheinternal

bondwireresistance(typical value50 mΩ)theactualvalue

of the current in the deflection coil will be about 5% lower

than calculated.

Flyback supply

The flyback voltage is determined by the flyback supply

voltage VFB.The principleof twosupply voltages(class G)

allows to use an optimum supply voltage VP for scan and

an optimum flyback supply voltage VFB for flyback, thus

very high efficiency is achieved. The available flyback

output voltage across the coil is almost equal to VFB, due

to the absence of a coupling capacitor which is not

required in a bridge configuration. The very short

rise and fall times of the flyback switch are determined

mainly by the slew-rate value of more than 300 V/µs.

Protection

The output circuit contains protection circuits for:

• Too high die temperature

• Overvoltage of output A.

SYMBOL PIN DESCRIPTION

INA 1 input A

INB 2 input B

VP3 supply voltage

OUTB 4 output B

INEW 5 east-west input

VGND 6 vertical ground

EWGND 7 east-west ground

OUTEW 8 east-west output

VFB 9 ﬂyback supply voltage

OUTA 10 output A

GUARD 11 guard output

FEEDB 12 feedback input

COMP 13 compensation input

handbook, halfpage

TDA8358J

MGL867

INA

INB

OUTB

INEW

VGND

EWGND

OUTEW

VFB

OUTA

GUARD

FEEDB

COMP

Fig.2 Pin configuration.

Thediehasbeen gluedto themetal blockof thepackage. Ifthe metal

block is not insulated from the heatsink, the heatsink shall only be

connected directly to pin VGND.

1999 Dec 22 5

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

Guard circuit

A guard circuit with output pin GUARD is provided.

The guard circuit generates a HIGH-level during the

flyback period. The guard circuit is also activated for one

of the following conditions:

•During thermal protection (Tj≈170 °C)

•During an open-loop condition.

The guard signal can be used for blanking the picture tube

and signalling fault conditions. The vertical

synchronization pulses of the guard signal can be used by

an On Screen Display (OSD) microcontroller.

Damping resistor compensation

HF loop stability is achieved by connecting a damping

resistor RD1 (see Fig.4) across the deflection coil.

The current values in RD1 during scan and flyback are

significantly different. Both the resistor current and the

deflection coil current flow into measuring resistor RM,

resulting in a too low deflection coil current at the start of

the scan.

The difference in the damping resistor current values

during scan and flyback have to be externally

compensated in order to achieve a short settling time.

For that purpose a compensation resistor RCMP is

connected between pins OUTA and COMP. The value of

RCMP is calculated by:

where:

•Rcoil is the coil resistance

•Vloss(FB) isthe voltageloss between pins VFB and OUTA

at flyback.

East-west ampliﬁer

The east-west amplifier is a current driver sinking the

current of a diode modulator circuit. A feedback

resistor REWF (see Fig.4) has to be connected between

the input and output of the inverting east-west amplifier in

order to convert the east-west correction input current into

an output voltage. The output voltage of the east-west

circuit at pin OUTEW is given by:

Vo≈Ii×REWF +V

The maximum output voltage is Vo(max) = 68 V, while the

maximum output current of the circuit is Io(max) = 750 mA.

RCMP VFB Vloss FB()

–V

–()R

×RS300+()×

FB Vloss FB()

–I

coil peak()

coil

×–()R

-------------------------------------------------------------------------------------------------------------

1999 Dec 22 6

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.

2. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.

3. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.

4. For repetitive time durations of t < 0.1 ms or a non repetitive time duration of t < 5 ms the maximum (peak) east-west

power dissipation PEW(peak) =15W.

5. Internally limited by thermal protection at Tj≈170 °C.

THERMAL CHARACTERISTICS

In accordance with IEC 747-1.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VPsupply voltage −18 V

VFB ﬂyback supply voltage −68 V

∆VVGND-EWGND voltage difference between

pins VGND and EWGND −0.3 V

VnDC voltage

pins OUTA and OUTEW note 1 −68 V

pin OUTB −VPV

pins INA, INB, INEW, GUARD,

FEEDB, and COMP −0.5 VPV

InDC current

pins OUTA and OUTB during scan (p-p) −3.2 A

pins OUTA and OUTB at ﬂyback (peak); t ≤1.5 ms −±1.8 A

pins INA, INB, INEW, GUARD,

FEEDB, and COMP −20 +20 mA

pin OUTEW −750 mA

Ilu latch-up current input current into any pin;

pin voltage is 1.5 ×VP; Tj= 150 °C−+200 mA

input current out of any pin;

pin voltage is −1.5 ×VP; Tj= 150 °C−200 −mA

Ves electrostatic handling voltage machine model; note 2 −300 +300 V

human body model; note 3 −2000 +2000 V

PEW east-west power dissipation note 4 −4W

tot total power dissipation −15 W

Tstg storage temperature −55 +150 °C

Tamb ambient temperature −25 +75 °C

Tjjunction temperature note 5 −150 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-c) thermal resistance from junction to case 4 K/W

Rth(j-a) thermal resistance from junction to ambient in free air 40 K/W

1999 Dec 22 7

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

CHARACTERISTICS

VP= 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb =25°C; measured in test circuit of Fig.3; unless otherwise

speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VPoperating supply voltage 7.5 12 18 V

VFB ﬂyback supply voltage note 1 2VP45 66 V

Iq(P)(av) average quiescent supply current during scan −10 15 mA

Iq(P) quiescent supply current no signal; no load −55 75 mA

Iq(FB)(av) average quiescent ﬂyback supply

current during scan −−10 mA

Inputs A and B

Vi(dif)(p-p) differential input voltage

(peak-to-peak value) note 2 −1000 1500 mV

VI(bias) input bias voltage note 2 100 880 1600 mV

II(bias) input bias current −25 35 µA

Outputs A and B

Vloss(1) voltage loss ﬁrst scan part note 3

Io= 1.1 A −−4.5 V

Io= 1.6 A −−6.6 V

Vloss(2) voltage loss second scan part note 4

Io=−1.1 A −−3.3 V

Io=−1.6 A −−4.8 V

Io(p-p) output current (peak-to-peak value) −−3.2 A

LE linearity error Io(p-p) = 3.2 A; notes 5 and 6

adjacent blocks −12%

non adjacent blocks −13%

offset offset voltage across RM; Vi(dif) =0V

I(bias) = 200 mV −−±15 mV

VI(bias) =1V −−±20 mV

∆Voffset(T) offset voltage variation with

temperature across RM; Vi(dif) =0V −−40 µV/K

VODC output voltage Vi(dif) =0V −0.5VP−V

Gv(ol) open-loop voltage gain notes 7 and 8 −60 −dB

f−3dB(h) high −3 dB cut-off frequency open-loop −1−kHz

Gvvoltage gain note 9 −1−

∆Gv(T) voltage gain variation with

temperature −−10−4K−1

PSRR power supply rejection ratio note 10 80 90 −dB

1999 Dec 22 8

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

Notes

1. To limit VOUTA to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA

and VFB at the first part of the flyback.

2. Allowable input range for both inputs: VI(bias) +V

i(dif)(peak) < 1600 mV and VI(bias) −Vi(dif)(peak) > 100 mV.

3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and

between pins OUTB and GND. Specified for Tj= 125 °C. The temperature coefficient for Vloss(1) is a positive value.

4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and

between pins OUTA and GND. Specified for Tj= 125 °C. The temperature coefficient for Vloss(2) is a positive value.

5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’

measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time

parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists

of two successive parts. The voltage amplitudes are measured across RM, starting at k = 1 and ending at k = 10,

where Vk and Vk+1 are the measured voltages of two successive blocks. Vmin, Vmax and Vavg are the minimum,

maximum and average voltages respectively. The linearity errors are defined as:

a) (adjacent blocks)

b) (non adjacent blocks)

Flyback switch

Io(peak) maximum (peak) output current t ≤1.5 ms −−±1.8 A

Vloss(FB) voltage loss at ﬂyback note 11

Io= 1.1 A −7.5 8.5 V

Io= 1.6 A −89V

Guard circuit

VO(grd) guard output voltage IO(grd) = 100 µA 567V

O(grd)(max) allowable guard voltage maximum leakage current

IL(max) =10µA−−18 V

IO(grd) output current VO(grd) = 0 V; not active −−10 µA

VO(grd) = 4.5 V; active 1 −2.5 mA

East-west ampliﬁer

Vooutput voltage at pin OUTEW −−68 V

Vloss voltage loss Io= 750 mA; note 12 −−5V

I(bias) input bias voltage 2 2.5 3.2 V

II(bias) input bias current into pin INEW; note 13

Io= 100 mA −2.5 −µA

= 500 mA −11.5 −µA

v(ol) open-loop voltage gain −−30 dB

THD harmonic distortion −0.5 1 %

f−3dB(h) high −3 dB cut-off frequency −−1 MHz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

LE VkVk1+

–

avg

-------------------------- 100%×=

LE Vmax Vmin

–

Vavg

------------------------------- 100%×=

1999 Dec 22 9

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

6. The linearity errors are specified for a minimum input voltage of 300 mV single-ended. Lower input voltages lead to

voltage dependent S-distortion in the input stage.

8. Pin FEEDB not connected.

10. VP(ripple) = 500 mV (RMS value); 50 Hz < fP(ripple) < 1 kHz; measured across RM.

11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA.

12. This value specifies the internal voltage loss of the current path between pins OUTEW and EWGND.

13. Measured for REWF =10kΩ; REWL =30Ω; Vo=6V.

a) For Io= 100 mA and a voltage of 9 V at REWL connected to the line output transformer, the east-west amplifier

input current (see Fig.4) is Ii= 300 µA.

b) For Io= 500 mA and a voltage of 21 V at REWL connected to the line output transformer, the east-west amplifier

input current (see Fig.4) is Ii= 350 µA.

Gvol() V

OUTA VOUTB

–

VFEEDB VOUTB

–

--------------------------------------------

GVVFEEDB VOUTB

–

VINA VINB

–

--------------------------------------------

1999 Dec 22 10

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

APPLICATION INFORMATION

handbook, full pagewidth

INA

INB

VFB

FEEDB

100 nF C2

100 nF

10 nF

GUARD

RGRD

4.7 kΩ

RCV1

2.2 kΩ

(1%)

RCV2

2.2 kΩ

(1%)

REWL

30 Ω

REWF

10 kΩ

0.5 Ω

3.2 Ω

2.7 kΩ

II(bias)

Ii(dif)

MGL873

INPUT

AND

FEEDBACK

CIRCUIT

GUARD

CIRCUIT

TDA8358J

11 93

VGND EWGND

VPVFB

OUTB

OUTA

VI(bias)

INEW OUTEW to line output

transformer

COMP.

CIRCUIT

COMP

II(av)

Ii(p-p)

Vi(p-p)

Fig.3 Test diagram.

1999 Dec 22 11

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

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ll pagewidth

VP = 14 V

Vfb = 30 V

deflection

coil

5 mH

6 Ω

(W66ESF)

0.5 Ω

RD1

270 Ω

RCMP

820 kΩ

CD(1)

47 nF

100

D1(2)

47 µF

(100 V)

2.7 µH(3)

100 nF C2

220 µF

(25 V)

RFB

10 Ω

RD2(1)

22 Ω

FEEDB

GUARD

RGRD

5.6 kΩ

2.7 kΩ

INPUT

AND

FEEDBACK

CIRCUIT

GUARD

CIRCUIT

TDA8358J

11 3

VPVFB

OUTB

OUTA

DEFLECTION

CONTROLLER

2.2 nF

INA

INB

RCV1

2.2 kΩ

(1%)

RCV2

2.2 kΩ

(1%)

VI(bias)

REWL

12 Ω

REWF

82 kΩ

MGL874

VGND EWGND

INEW OUTEW to line output

transformer

COMP.

CIRCUIT

COMP

II(av)

Ii(p-p)

Vi(p-p)

Fig.4 Application diagram.

Deflection circuit: fvert = 50 Hz; tFB = 640 µs; II(bias) = 400 µA; Ii(dif)(peak) = 290 µA; Io(p-p) = 2.4 A.

East-west amplifier: Ii(B) = 290 µA; Ii(T) = 510 µA.

(1) Optional, component values depend on the deflection coil impedance.

(2) Extended flash over protection; BYD33D or equivalent.

(3) Optional, extended flash over protection.

1999 Dec 22 12

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

Supply voltage calculation

For calculating the minimum required supply voltage,

several specific application parameter values have to be

known. These parameters are the required

maximum (peak) deflection coil current Icoil(peak), the coil

parameters Rcoil and Lcoil, and the measuring resistance

of RM. The required maximum (peak) deflection coil

current should also include the overscan.

The deflection coil resistance has to be multiplied with 1.2

in order to take account of hot conditions.

Chapter “Characteristics” supplies values for the voltage

losses of the vertical output stage. For the first part of the

scan the voltage loss is given by Vloss(1). For the second

part of the scan the voltage loss is given by Vloss(2).

The voltage drop across the deflection coil during scan is

determined by the coil impedance. For the first part of the

scan the inductive contribution and the ohmic contribution

to the total coil voltage drop are of opposite sign, while for

the second part of the scan the inductive part and the

ohmic part have the same sign.

For the vertical frequency the maximum frequency

occurring must be applied to the calculations.

The required power supply voltage VP for the first part of

the scan is given by:

The required power supply voltage VPfor the second part

of the scan is given by:

The minimum required supply voltage VP shall be the

highest of the two values VP(1) and VP(2). Spread in supply

voltage and component values also has to be taken into

account.

Flyback supply voltage calculation

If the flyback time is known, the required flyback supply

voltage can be calculated by the simplified formula:

where:

The flyback supply voltage calculated this way is about

5% to 10% higher than required.

Calculation of the power dissipation of the vertical

output stage

The power dissipation of the vertical output stage is given

by the formula:

PV=P

sup −PL

The power to be supplied is given by the formula:

In this formula 0.3 [W] represents the average value of the

losses in the flyback supply.

The average external load power dissipation in the

deflection coil and the measuring resistor is given by the

formula:

Example

Table 1 Application values

Table 2 Calculated values

VP1() I

coil peak()

coil RM

+()

coil 2Icoil peak()

vert max()

loss 1()

+××–×=

P2() I

coil peak()

coil RM

+()×=

coil 2Icoil peak()

vert max()

loss 2()

+××+

FB Icoil p p–()

coil RM

t–

FB x⁄

–

---------------------------

×=

xLcoil

Rcoil RM

---------------------------

SYMBOL VALUE UNIT

Icoil(peak) 1.2 A

Icoil(p-p) 2.4 A

Lcoil 5mH

coil 6Ω

RM0.6 Ω

fvert 50 Hz

tFB 640 µs

SYMBOL VALUE UNIT

VP14 V

RM+R

coil (hot) 7.8 Ω

tvert 0.02 s

x 0.000641

VFB 30 V

Psup 8.91 W

PL3.74 W

PV5.17 W

Psup VPIcoil peak()

------------------------ VP0.015 [A] 0.3 [W]+×+×=

PLIcoil peak()

()

-------------------------------- Rcoil RM

+()×=

1999 Dec 22 13

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

Power dissipation calculation for the east-west stage

In general the shape of the east-west output wave form is

a parabola. The output voltage will be higher at the

beginning and end of the vertical scan compared to the

voltage at the scan middle, while the output current will be

higheratthescanmiddle. This results inanalmostuniform

power dissipation distribution during scan. Therefore the

power dissipation can be calculated by multiplying the

average values of the output voltage and the output

current of pin OUTEW.

When verifying the dissipation also the start-up and stop

dissipation should be taken into account. Power

dissipation during start-up can be 3 to 5 times higher than

during normal operation.

Heatsink calculation

The value of the heatsink can be calculated in a standard

way with a method based on average temperatures.

The required thermal resistance of the heatsink is

determined by the maximum die temperature of 150 °C.

In general we recommend to design for an average die

temperature not exceeding 130 °C. It should be noted

that the heatsink thermal resistance Rth(h-a) found by

performing a standard calculation will be lower then

normally found for a vertical deflection stand alone device,

due to the contribution of the EW power dissipation to this

value.

EXAMPLE

Measured or known values:

PEW = 3 W; PV= 6 W; Tamb =40°C; Tj= 130 °C;

Rth(j-c) = 4 K/W; Rth(c-h) = 1 K/W.

The required heatsink thermal resistance is given by:

When we use the values known we find:

The heatsink temperature will be:

Th=T

amb +R

th(h-a) ×Ptot =40+5×9=85°C

Equivalent thermal resistance network

The TDA8358J has two independent power dissipating

systems, the vertical output circuit and the east-west

circuit.

Itisrecommended to verifythe individual maximum (peak)

junction temperatures of both circuits. Therefore the

maximum (peak) power dissipations of the circuits and

also the heatsink temperature should be measured.

The maximum (peak) junction temperatures can be

calculated by using an equivalent thermal network

(see Fig.5).

The network does only consist the contribution of the

maximum (peak) power dissipation PTRv(peak), being the

dissipation of the most critical transistor internally

connected to pins OUTB and VGND. The model assumes

equivalent maximum (peak) power dissipations during the

different vertical scan stages for all the functionally paired

transistors. The calculated maximum (peak) junction

temperatures should not exceed Tj= 150 °C.

Rth h a–()T

amb

–

PEW PV

------------------------- R(th j c–()

–R

th c h–()

)+=

th h a–()130 40–

36+

---------------------- 4(–1)+5 K/W==

1999 Dec 22 14

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

EXAMPLE

Measured or known values:

•The east-west power dissipation: PEW =3W

•The vertical power dissipation: PV=6W

•The maximum (peak) power dissipation of the most

critical transistor: PTRv(peak) =5W

•The case temperature: Tc=85°C.

The IC total power dissipation is:

Ptot =P

EW +P

=6+3=9W

It should be noted that the allowed IC total power

dissipation is Ptot = 15 W (maximum value).

The maximum (peak) temperature TP1(peak) is given by:

•TP1(peak) =T

c+(P

EW +P

TRv(peak))×Rth(P1-c)

=85+(3+5)×2.2 = 102.6 °C

The maximum (peak) junction temperatures for the output

circuits are given by:

•Tj(EW)(peak) =T

P1(peak) +R

th(EW-P1) ×PEW

= 102.6 + 10.5 ×3 = 134.1 °C

•Tj(TRv)(peak) =T

P1(peak) +R

th(TRv-P1) ×PTRv(peak)

= 102.6 + 5.2 ×5 = 128.6 °C

handbook, halfpage

MGL872

TEW(M)

PEW

TTRv(M)

TP1(M) PTRv(M)

Ptot

Rth(TRv-P1)

5.2 K/W

Rth(P1-c)

2.2 K/W

Rth(EW-P1)

10.5 K/W

Fig.5 Equivalent thermal resistance network.

1999 Dec 22 15

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

INTERNAL PIN CONFIGURATION

PIN SYMBOL EQUIVALENT CIRCUIT

1 INA

2 INB

4 OUTB

6 VGND

10 OUTA

5 INEW

7 EWGND

8 OUTEW

1300 Ω

MBL100

2300 Ω

MBL102

MGL869

MGL868

300 Ω

1999 Dec 22 16

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

11 GUARD

12 FEEDB

13 COMP

PIN SYMBOL EQUIVALENT CIRCUIT

MGL870

300 Ω

MGL871

300 Ω

MGL875

300 Ω

1999 Dec 22 17

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

PACKAGE OUTLINE

UNIT A e1

A2bpcD

(1) E(1) Z(1)

deD

hLL

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 17.0

15.5 4.6

4.4 0.75

0.60 0.48

0.38 24.0

23.6 20.0

19.6 10 3.4

0.8

12.2

11.8 1.7

5.08 2.4

1.6

62.00

1.45

2.1

1.8

3.4

3.1 4.3

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

12.4

11.0

SOT141-6

0 5 10 mm

scale

0.25

0.03

Ze2

113

non-concave

view B: mounting base side

97-12-16

99-12-17

DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6

1999 Dec 22 18

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

SOLDERING

Introduction to soldering through-hole mount

packages

This text gives a brief insight to wave, dip and manual

soldering.Amore in-depth accountofsoldering ICs canbe

found in our

“Data Handbook IC26; Integrated Circuit

Packages”

(document order number 9398 652 90011).

Wave soldering is the preferred method for mounting of

through-hole mount IC packages on a printed-circuit

board.

Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact

with the joints for more than 5 seconds.

Thetotalcontacttimeofsuccessivesolderwavesmustnot

exceed 5 seconds.

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the

specified maximum storage temperature (Tstg(max)). If the

printed-circuit board has been pre-heated, forced cooling

may be necessary immediately after soldering to keep the

temperature within the permissible limit.

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the

package, either below the seating plane or not more than

2 mm above it. If the temperature of the soldering iron bit

is less than 300 °C it may remain in contact for up to

10 seconds. If the bit temperature is between

300 and 400 °C, contact may be up to 5 seconds.

Suitability of through-hole mount IC packages for dipping and wave soldering methods

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

PACKAGE SOLDERING METHOD

DIPPING WAVE

DBS, DIP, HDIP, SDIP, SIL suitable suitable(1)

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development.

Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later.

Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of this speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

1999 Dec 22 19

Philips Semiconductors Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer TDA8358J

NOTES

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999 68

Philips Semiconductors – a world wide company

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Printed in The Netherlands 545004/100/01/pp20 Date of release: 1999 Dec 22 Document order number: 9397 750 06197