TPS54383PWP - Texas Instruments - Datasheet.Directory

FEATURES CONTENTS

DESCRIPTION

APPLICATIONS

PVDD2

BOOT2

SW2

PVDD1

BOOT1

SW1

GND

TPS54383

SEQ

ILIM2

FB2

EN1

EN2

FB1

OUTPUT1 OUTPUT2

VIN

UDG-07123

GND

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007www.ti.com

3-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE MOSFET

•4.5-V to 28-V Input Range

Device Ratings 2•Output Voltage Range 0.8 V to 90% of Input Electrical Characteristics 3Voltage

Device Information 9•Output Current Up to 3 A Application Information 12Design Examples 32•Two Fixed Switching Frequency Versions:

Additional References 44– TPS54383: 300 kHz– TPS54386: 600 kHz•Three Selectable Levels of OvercurrentProtection (Output 2)

The TPS54383 and TPS54386 are dual output,non-synchronous buck converters capable of•0.8-V 1.5% Voltage Reference

supporting 3-A output applications that operate from a•2.1-ms Internal Soft Start

4.5-V to 28-V input supply voltage, and require output•Dual PWM Outputs 180 °Out-of-Phase

voltages between 0.8 V and 90% of the input voltage.•Ratiometric or Sequential Startup Modes

With an internally-determined operating frequency,Selectable by a Single Pin

soft start time, and control loop compensation, these•85-m ΩInternal High-Side MOSFETs

converters provide many features with a minimum ofexternal components. Channel 1 overcurrent•Current Mode Control

protection is set at 4.5 A, while Channel 2 overcurrent•Internal Compensation (See Page 16)

protection level is selected by connecting a pin to•Pulse-by-Pulse Overcurrent Protection

ground, to BP, or left floating. The setting levels areused to allow for scaling of external components for•Thermal Shutdown Protection at +148 °C

applications that do not need the full load capability of•14-Pin PowerPAD™ HTSSOP package

both outputs.

The outputs may be enabled independently, or maybe configured to allow either ratiometric or sequential•Set Top Box

startup sequencing. Additionally, the two outputs may•Digital TV

be powered from different sources.•Power for DSP•Consumer Electronics

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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DEVICE RATINGS

ABSOLUTE MAXIMUM RATINGS

(1)

RECOMMENDED OPERATING CONDITIONS

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

PACKAGE DISSIPATION RATINGS

(1) (2) (3)

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

(1)

PART NUMBER OPERATING FREQUENCY (kHz) PACKAGE MEDIA UNITS (Pieces)

TPS54383PWP Tube 90300TPS54383PWPR Tape and Reel 2000Plastic 14-Pin HTSSOPTPS54386PWP Tube 90600TPS54386PWPR Tape and Reel 2000

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .

VALUE UNIT

PVDD1, PVDD2, EN1, EN2 30

BOOT1, BOOT2 V

+ 7

SW1, SW2 – 2 to 30

Input voltage range SW1, SW2 transient (< 50ns) – 3 to 31 V

BP 6.5

SEQ, ILIM2 – 0.3 to 6.5

FB1, FB2 – 0.3 to 3

SW1, SW2 output current 7 A

BP load current 35 mA

stg

Storage temperature – 55 to +165

Operating temperature – 40 to +150 °C

Soldering temperature +260

(1) Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to theRecommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extendedperiods of time may affect device reliability.

MIN MAX UNIT

PVDD2

Input voltage 4.5 28 V

Operating junctionT

– 40 +125 °Ctemperature

MIN UNIT

Human body model 2k

CDM 1.5k V

Machine Model 250

THERMAL IMPEDANCEJUNTION-TO-THERMAL PAD T

= +25 °C T

= +85 °CPACKAGE ( °C/W) POWER RATING (W) POWER RATING (W)

Plastic 14-Pin HTSSOP (PWP) 2.07

(4)

1.6 1.0

(1) For more information on the PWP package, refer to TI Technical Brief (SLMA002A ).(2) TI device packages are modeled and tested for thermal performance using printed circuit board designs outlined in JEDEC standardsJESD 51-3 and JESD 51-7.(3) For application information, see the Power Derating section.(4) T

J-A

= +40 °C/W.

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ELECTRICAL CHARACTERISTICS

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

– 40 °C≤T

≤+125 °C, V

PVDD1

= V

PVDD2

= 12 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT SUPPLY (PVDD)

PVDD1

Input voltage range 4.5 28 VV

PVDD2

IDD

SDN

Shutdown V

EN1

= V

EN2

= V

PVDD2

70 150 µA

IDD

Quiescent, non-switching V

= 0.9 V, Outputs off 1.8 3.0

mASW node unloaded; Measured as BP sinkIDD

Quiescent, while-switching 5current

UVLO

Minimum turn-on voltage PVDD2 only 3.8 4.1 4.4 V

UVLO(hys)

Hysteresis 400 mV

= 10 µF, EN1 and EN2 go lowt

START

(1) (2)

Time from startup to softstart begin 2 mssimultaneously

ENABLE ( EN)

EN1

Enable threshold 0.9 1.2 1.5 VV

EN2

Hysteresis 50 mV

EN1

Enable pull-up current V

EN1

= V

EN2

= 0 V 6 12 µAI

EN2

(1)

Time from enable to soft-start begin Other EN pin = GND 10 µs

BP REGULATOR (BP)

BP Regulator voltage 8 V < P

VDD2

< 28 V 5 5.25 5.6 V

VDD2

= 4.5 V; switching, no external load onBP

LDO

Dropout voltage 400 mVBP

(1)

Regulator external load 2

mAI

BPS

Regulator short circuit 4.5 V < P

VDD2

< 28 V 10 20 30

OSCILLATOR

TPS54383 255 310 375f

Switching frequency kHzTPS54386 510 630 750

DEAD

(1)

Clock dead time 140 ns

ERROR AMPLIFIER (EA) and VOLTAGE REFERENCE (REF)

FB1

0°C < T

< +85 °C 788 800 812Feedback input voltage mVV

FB2

– 40 °C < T

< +125 °C 786 812

FB1

Feedback input bias current 3 50 nAI

FB2

(1)

Transconductance 30 µSg

(1)

SOFT START (SS)

SS1

Soft start time 1.5 2.1 2.7 msT

SS2

OVERCURRENT PROTECTION

CL1

Current limit channel 1 3.6 4.5 5.6

ILIM2

= V

3.6 4.5 5.6

CL2

Current limit channel 2 V

ILIM2

= (floating) 2.4 3.0 3.6

ILIM2

= GND 1.15 1.50 1.75

UV1

Low-level output threshold to declare a fault Measured at feedback pin. 670 mVV

UV2

HICCUP

(1)

Hiccup timeout 10 ms

ON1(oc)

(1)

Minimum overcurrent pulse width 90 150 nst

ON2(oc)

(1)

(1) Ensured by design. Not production tested.(2) When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lowerBP capacitor value. More information can be found in the Input UVLO and Startup section.

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TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

ELECTRICAL CHARACTERISTICS (continued)– 40 °C≤T

≤+125 °C, V

PVDD1

= V

PVDD2

= 12 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BOOTSTRAP

BOOT1

From BP to BOOT1 or BP to BOOT2,Bootstrap switch resistance 18 ΩI

EXT

= 50 mAR

BOOT2

OUTPUT STAGE (Channel 1 and Channel 2)

= +25 °C, V

PVDD2

= 8 V 85R

DS(on)

(3)

MOSFET on resistance plus bond wire resistance m Ω– 40 °C < T

< +125 °C, V

PVDD2

= 8 V 85 165

ON(min)

(3)

Minimum controllable pulse width I

SWx

peak current > 1 A

(4)

100 200 ns

MIN

Minimum Duty Cycle V

= 0.9 V 0 %

TPS54383 f

= 300 kHz 90 95 %D

MAX

Maximum Duty Cycle

TPS54386 f

= 600 kHz 85 90 %

Switching node leakage current (sourcing) Outputs OFF 2 12 µA

THERMAL SHUTDOWN

(3)

Shutdown temperature 148

°CT

SD(hys)

(3)

Hysteresis 20

(3) Ensured by design. Not production tested.(4) See Figure 14 for I

SWx

peak current <1 A.

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TYPICAL CHARACTERISTICS

-50 -25 0 25 50 75 100 125

1.6

1.7

1.9

1.5

2.0

2.1

1.8

T JunctionTemperature C°

J- -

I QuiescentCurrent mA

DDQ - -

V 5.25V

BP =

100

120

-50 -25 0 25 50 75 100 125

140

T JunctionTemperature C°

J- -

I ShutdownCurrent Am

SD - -

VPVDDx 12V=

VPVDDx 4.5V=

V 28V

PVDDx =

3.6

3.7

3.8

3.9

4.1

4.2

4.0

UVLO(Off)

UVLO(On)

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

VUVLO- -UndervoltageLockout V

1.15

1.17

1.21

1.23

1.19

1.25

-50 -25 0 25 50 75 100 125

EN(Off)

EN(On)

T JunctionTemperature C°

J- -

V EnableThresholdVoltage V

EN - -

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

QUIESCENT CURRENT (NON-SWITCHING) SHUTDOWN CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 1. Figure 2.

UNDERVOLTAGE LOCKOUT THRESHOLD ENABLE THRESHOLDSvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 3. Figure 4.

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270

310

350

290

330

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

V 5.25V

BP =

f PWMFrequency kHz

PWM --

1.5

2.0

2.5

3.0

3.5

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

t SoftStartTime ms

SS - -

V 5.25V

BP =

580

640

680

600

660

-50 -25 0 25 50 75 100 125

620

T JunctionTemperature C°

J- -

f PWMFrequency kHz

PWM - -

V 5.25V

BP =

-50 -25 0 25 50 75 100 125

-3

-5

-1

T JunctionTemperature C°

J- -

IFeedbackBiasCurrent nA

FB - -

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

TYPICAL CHARACTERISTICS (continued)

SOFT START TIME SWITCHING FREQUENCY (300 kHz)vs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 5. Figure 6.

SWITCHING FREQUENCY (600 kHz) FEEDBACK BIAS CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 7. Figure 8.

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4.8

4.6

4.4

4.2

4.0-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

VPVDD =24V

VPVDD =5V

VPVDD =12V

I OvercurrentLimit A

CL - -

788

793

798

803

808

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

VFeedbackVoltage mV

FB - -

2.6

2.8

3.0

3.2

3.4

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

VPVDDx 24V=

VPVDDx 12V=

VPVDDx 5V=

I OvercurrentLimit A

CL --

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

VPVDDx =24V

VPVDDx =12V

VPVDDx =5V

I OvercurrentLimit A

CL --

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

TYPICAL CHARACTERISTICS (continued)

FEEDBACK VOLTAGE OVERCURRENT LIMIT (CH1, CH2 HIGH LEVEL)vs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 9. Figure 10.

OVERCURRENT LIMIT (CH2 MID LEVEL) OVERCURRENT LIMIT (CH2 LOW LEVEL)vs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 11. Figure 12.

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200

250

300

350

400

100

0 0.2 0.4 0.6 0.8 1.0 1.4

TA= 0°C

IL- Load Current - A

tON - Minimum Controllable Pulse Width - ns

–40

TA(°C)

TA= –40°C

TA= 25°C

TA= 85°C

1.2

150

-50 -25 0 25 50 75 100 125

TJ- Junction Temperature - °C

ISW(off) - Switching Node Leakage Current - mA

4 8 12 16 20 24 28

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

OCL = 4.5 A

OCL = 3.0 A

OCL = 1.5 A

VDD - Supply Voltage - V

IOC - Overcurrent Limit - A

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

TYPICAL CHARACTERISTICS (continued)

SWITCHING NODE LEAKAGE CURRENT MINUMUM CONTROLLABLE PULSE WIDTHvs vsJUNCTION TEMPERATURE LOAD CURRENT

Figure 13. Figure 14.

OVERCURRENT LIMITvsSUPPLY VOLTAGE

Figure 15.

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DEVICE INFORMATION

PIN CONNECTIONS

PVDD2

BOOT2

SW2

PVDD1

BOOT1

SW1

GND

SEQ

ILIM2

FB2

EN1

EN2

FB1

Thermal Pad

(bottom side)

HTSSOP (PWP)

(Top View)

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTIONNAME NO.

Input supply to the high side gate driver for Output 1. Connect a 22-nF to 82-nF capacitor from this pinto SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch isBOOT1 2 I

turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a smallresistor (1 Ωto 3 Ω) may be placed in series with the bootstrap capacitor.Input supply to the high side gate driver for Output 2. Connect a 22-nF to 82-nF capacitor from this pinto SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch isBOOT2 13 I

turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a smallresistor (1 Ωto 3 Ω) may be placed in series with the bootstrap capacitor.Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low ESR (4.7- µFBP 11 -

to 10- µF X7R or X5R) ceramic capacitor.Active low enable input for Output 1. If the voltage on this pin is greater than 1.55 V, Output 1 isdisabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 1 and allows soft start ofEN1 5 I

Output 1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin toGND for "always ON" operation.Active low enable input for Output 2. If the voltage on this pin is greater than 1.55 V, Output 2 isdisabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 2 and allows soft start ofEN2 6 I

Output 2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin toGND for "always ON" operation.Voltage feedback pin for Output 1. The internal transconductance error amplifier adjusts the PWM forOutput 1 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider fromFB1 7 I Output 1 to ground, with the center connection tied to this pin, determines the value of the regulatedoutput voltage. Compensation for the feedback loop is provided internally to the device. See FeedbackLoop and Inductor-Capacitor ( L-C) Filter Selection section for further information.Voltage feedback pin for Output 2. The internal transconductance error amplifier adjusts the PWM forOutput 2 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider fromFB2 8 I Output 2 to ground, with the center connection tied to this pin, determines the value of the regulatedOutput voltage. Compensation for the feedback loop is provided internally to the device. See FeedbackLoop and Inductor-Capacitor ( L-C) Filter Selection section for further information.GND 4 - Ground pin for the device. Connect directly to Thermal Pad.Current limit adjust pin for Output 2 only. This function is intended to allow a user with asymmetricalload currents (Output 1 load current much greater than Output 2 load current) to optimize componentILIM2 9 I scaling of the lower current output while maintaining proper component derating in a overcurrent faultcondition. The discrete levels are available as shown in Table 2 ,Current Limit Threshold Adjustment forOutput 2. Note: An internal 2-resistor divider (150-k Ωeach) connects BP to ILIM2 and to GND.Power input to the Output 1 high side MOSFET only. This pin should be locally bypassed to GND with aPVDD1 1 I

low ESR ceramic capacitor of 10- µF or greater.The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2pins and provides power to the Output 2 high-side MOSFET. This pin should be locally bypassed toPVDD2 14 I

GND with a low ESR ceramic capacitor of 10- µF or greater. The UVLO function monitors PVDD2 andenables the device when PVDD2 is greater than 4.1 V.

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TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

TERMINAL FUNCTIONS (continued)

TERMINAL

I/O DESCRIPTIONNAME NO.

This pin configures the output startup mode. If the SEQ pin is connected to BP, then when Output 2 isenabled, Output 1 is allowed to start after Output 2 has reached regulation; that is, sequential startupwhere Output 1 is slave to Output 2. If EN2 is allowed to go high after the outputs have been operating,then both outputs are disabled immediately, and the output voltages decay according to the load that ispresent. For this sequence configuration, tie EN1 to ground.If the SEQ pin is connected to GND, then when Output 1 is enabled, Output 2 is allowed to start afterOutput 1 has reached regulation; that is, sequential startup where Output 2 is slave to Output 1. If EN1is allowed to go high after the outputs have been operating, then both outputs are disabled immediately,SEQ 10 I

and the output voltages decay according to the load that is present. For this sequence configuration, tieEN2 to ground.If left floating, Output 1 and Output 2 start ratio-metrically when both outputs are enabled at the sametime. They will soft start at a rate determined by their final output voltage and enter regulation at thesame time. If the EN1 and EN2 pins are allowed to operate independently, then the two outputs alsooperate independently

NOTE: An internal two resistor (150-k Ωeach) divider connects BP to SEQ and to GND. See theSequence States table.Source (switching) output for Output 1 PWM. A snubber is recommended to reduce ringing on thisSW1 3 O

node. See SW Node Ringing for further information.Source (switching) output for Output 2 PWM. A snubber is recommended to reduce ringing on thisSW2 12 O

node. See SW Node Ringing for further information.Thermal Pad - - This pad must be tied externally to a ground plane and the GND pin.

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BLOCK DIAGRAM

7FB1

Soft Start

1CCOMP

S Q

Current

Comparator

f(IDRAIN1) + DC(ofst)

Anti-Cross

Conduction

1.2 MHz

Oscilator

Divide

by 2/4

Ramp

Gen 1

Ramp

Gen 2

CLK1

CLK2

CLK1

Weak

Pull-Down

MOSFET

5EN1

6EN2

6mA6 mA

VDD2

Internal

Control

10SEQ

150 kW

Output

Undervoltage

Detect

BP FB1

FB2

CLK1

4GND

8FB2

Soft Start

2CCOMP

S Q

Current

Comparator

Anti-Cross

Conduction

CLK2

Weak

Pull-Down

MOSFET

11BP

9ILIM2

150 kW

CLK2

4GND

Level

Select

5.25-V

Regulator

References

BOOT1

PVDD1

SW1

BOOT2

PVDD2

SW2

f(IDRAIN2) + DC(ofst)

0.8 VREF

IMAX2 (Set to one of three limits)

f(IDRAIN1)

f(IMAX1)

Overcurrent Comp

f(ISLOPE1)

Level

Shift

Level

Shift

f(IDRAIN2)

f(IMAX2)

f(ISLOPE2)

FET

Switch

TSD

PVDD2

f(ISLOPE1)

f(ISLOPE2)

SD1

SD2

UVLO

0.8 VREF

SD2

0.8 VREF

SD1

UDG-07124

Overcurrent Comp

RCOMP

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

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APPLICATION INFORMATION

FUNCTIONAL DESCRIPTION

Voltage Reference

Oscillator

Input Undervoltage Lockout (UVLO) and Startup

Enable and Timed Turn On of the Outputs

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

The TPS54383 and TPS54386 are dual output, non-synchronous converters. Each PWM channel contains aninternally-compensated error amplifier, current mode pulse width modulator (PWM), switch MOSFET, enable,and fault protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference,clock oscillator, and output voltage sequencing functions.

DESIGN HINT

The TPS5438x contains internal slope compensation and loop compensationcomponents; therefore, the external L-C filter must be selected appropriately so thatthe resulting control loop meets criteria for stability. This approach differs from anexternally-compensated controller, where the L-C filter is generally selected first, andthe compensation network is found afterwards. (See Feedback Loop and L-C FilterSelection section.)

NOTE:

Unless otherwise noted, the term TPS5438x applies to both the TPS54383 andTPS54386. Also, unless otherwise noted, a label with a lowercase xappended impliesthe term applies to both outputs of the two modulator channels. For example, the termENx implies both EN1 and EN2. Unless otherwise noted, all parametric values givenare typical. Refer to the Electrical Characteristics for minimum and maximum values.Calculations should be performed with tolerance values taken into consideration.

The bandgap cell common to both outputs, trimmed to 800 mV.

The oscillator frequency is internally fixed at two times the SWx node switching frequency. The two outputs areinternally configured to operate on alternating switch cycles (that is, 180 °out of phase).

When the voltage at the PVDD2 pin is less than 4.1 V, a portion of the internal bias circuitry is operational, andall other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage risesabove the UVLO turn-on threshold, the state of the enable pins determines the remainder of the internal startupsequence. If either output is enabled ( ENx pulled low), the BP regulator turns on, charging the BP capacitor witha 20-mA current. When the BP pin is greater than 4 V, PWM is enabled and soft start begins, depending on theSEQ mode of operation and the EN1 and EN2 settings.

Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may behigher or lower than PVDD2. (See the Dual Supply Operation section.)

Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin toPVDD2. By grounding, or by pulling the ENx pin to below approximately 1.2 V with an external circuit, theassociated output is enabled and soft start is initiated.

If both enable pins are left in the high state, the device operates in a shutdown mode, where the BP regulator isshut down and minimal functions are active. The total standby current from both PVDD pins is approximately 70µA at 12-V input supply.

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DELAY

IN ENx

TH ENx

C farads

V 2 I R

R n V I R

=æ ö

- ´ ´

´ç ÷

- ´

è ø

(1)

TPS5438x

ENx

PVDD2

PVDDx

6mA

1.2V

T Time-

tDELAY

0tDELAY +tSS

PVDDx

ENx

VOUTx

1.2-V

Threshold

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

An R-C connected to an ENx pin may be used to delay the turn-on of the associated output after power isapplied to PVDDx (see Figure 16 ). After power is applied to PVDD2, the voltage on the ENx pin slowly decaystowards ground. Once the voltage decays to approximately 1.2 V, then the output is enabled and the startupsequence begins. If it is desired to enable the outputs of the device immediately upon the application of power toPVDD2, then omit these two components and tie the ENx pin to GND directly.

If an R-C circuit is used to delay the turn-on of the output, the resistor value must be much less than 1.2 V / 6 µAor 200 k Ω. A suggested value is 51 k Ω. This resistor value allows the ENx voltage to decay below the 1.2-Vthreshold while the 6- µA bias current flows.

The capacitor value required to delay the startup time (after the application of PVDD2) is shown in Equation 1 .

where:

•R and C are the timing components•V

is the 1.2-V enable threshold voltage•I

ENx

is the 6 µA enable pin biasing current

Other enable pin functionality is dictated by the state of the SEQ pin. (See the Output Voltage Sequencingsection.)

Figure 16. Startup Delay Schematic Figure 17. Startup Delay with R-C on Enable

DESIGN HINT

If delayed output voltage startup is not necessary, simply connect EN1 and EN2 toGND. This configuration allows the outputs to start immediately on valid application ofPVDD2.

If ENx is allowed to go high after the Outputx has been in regulation, the upper MOSFET shuts off, and theoutput decays at a rate determined by the output capacitor and the load. The internal pulldown MOSFET remainsin the OFF state. (See the Bootstrap for N-Channel MOSFET section.)

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Output Voltage Sequencing

5-V VOUT1

(2 V/div)

3.3-V VOUT2

(2 V/div)

T - Time - 1 ms/div

SEQ = BP

Sequential

CH2 then CH1

T - Time - 1 ms/div

SEQ = GND

Sequential

CH1 then CH2

5-V VOUT1

(2 V/div)

3.3-V VOUT2

(2 V/div)

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

The TPS5438x allows single-pin programming of output voltage startup sequencing. During power-on, the stateof the SEQ pin is detected. Based on whether the pin is tied to BP, to GND, or left floating, the outputs behaveas described in Table 1 .

Table 1. Sequence States

SEQ PIN STATE MODE EN1 EN2

Ignored by the device.when V

EN2

<enable threshold voltageTie EN1 to < enable threshold voltagefor BP to be active when V

EN2

>BP Sequential, Output 2 then Output 1 Activeenable threshold voltageTie EN1 to > enable threshold voltagefor low quiescent current (BP inactive)when V

EN2

> enable threshold voltage

Ignored by the device.when V

EN1

<enable threshold voltageTie EN2 to < enable threshold voltagefor BP to be active when V

EN1

>GND Sequential, Output 1 then Output 2 Active

enable threshold voltageTie EN2 to > enable threshold voltagefor low quiescent current (BP inactive)when V

EN1

> enable threshold voltageIndependent or Ratiometric, Output 1 Active. EN1 and EN2 must be tied Active. EN1 and EN2 must be tied(floating)

and Output 2 together for Ratio-metric startup. together for Ratio-metric startup.

If the SEQ pin is connected to BP, then when Output 2 is enabled, Output 1 is allowed to start approximately 400µs after Output 2 has reached regulation; that is, sequential startup where Output 1 is slave to Output 2. If EN2 isallowed to go high after the outputs have been operating, then both outputs are disabled immediately, and theoutput voltages decay according to the load that is present.

If the SEQ pin is connected to GND, then when Output 1 is enabled, Output 2 is allowed to start approximately400 µs after Output 1 has reached regulation; that is, sequential startup where Output 2 is slave to Output 1. IfEN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately,and the output voltages decay according to the load that is present.

Figure 18. SEQ Pin TIed to BP Figure 19. SEQ Pin Tied to GND

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5-V VOUT1

(2 V/div)

3.3-V VOUT2

(2 V/div)

T - Time - 1 ms/div

Soft Start

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

NOTE:

An R-C network connected to the ENx pin may be used in addition to the SEQ pin insequential mode to delay the startup of the first output voltage. This approach may benecessary in systems with a large number of output voltages and elaborate voltagesequencing requirements. See Enable and Timed Turn On of the Outputs .

If the SEQ pin is left floating, Output 1 and Output 2 each start ratiometrically when both outputs are enabled atthe same time. Output 1 and Output 2 soft start at a rate that is determined by the respective final outputvoltages and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently,then the two outputs also operate independently.

Figure 20. SEQ Pin Floating

Each output has a dedicated soft start circuit. The soft start voltage is an internal digital reference ramp to one oftwo noninverting inputs of the error amplifier. The other input is the (internal) precision 0.8-V reference. The totalramp time for the FB voltage to charge from 0 V to 0.8 V is about 2.1 ms. During a soft start interval, theTPS5438x output slowly increases the voltage to the noninverting input of the error amplifier. In this way, theoutput voltage ramps up slowly until the voltage on the noninverting input to the error amplifier reaches theinternal 0.8 V reference voltage. At that time, the voltage at the noninverting input to the error amplifier remainsat the reference voltage.

NOTE:

To avoid a disturbance in the output voltage during the stepping of the digital softstart, a minimum output capacitance of 50 µF is recommended. See Feedback Loopand Inductor-Capacitor (L-C) Filter Selection Once the filter and compensationcomponents have been established, laboratory measurements of the physical designshould be performed to confirm converter stability.

During the soft start interval, pulse-by-pulse current limiting is in effect. If an overcurrent pulse is detected, sixPWM pulses are skipped to allow the inductor current to decay before another PWM pulse is applied. (See theOutput Overload Protection section.) There is no pulse skipping if a current limit pulse is not detected.

DESIGN HINT

If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low

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Output Voltage Regulation

VREF

VOUT -VREF

R2=R1´

(2)

PVDD2

BOOT2

SW2

PVDD1

BOOT1

SW1

GND

TPS5438x

SEQ

ILIM2

FB2

EN1

EN2

FB1

OUTPUT1

UDG-07011

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

to support the desired regulation voltage by the time Soft Start has completed, thenthe output UV circuit may trip and cause a hiccup in the output voltage. In this case,use a timed delay startup from the ENx pin to delay the startup of the output until thePVDDx voltage has the capability of supporting the desired regulation voltage. SeeOperating Near Maximum Duty Cycle and Maximum Output Capacitance for relatedinformation.

Each output has a dedicated feedback loop comprised of a voltage setting divider, an error amplifier, a pulsewidth modulator, and a switching MOSFET. The regulation output voltage is determined by a resistor dividerconnecting the output node, the FBx pin, and GND (see Figure 21 ). Assuming the value of the upper voltagesetting divider is known, the value of the lower divider resistor for a desired output voltage is calculated byEquation 2 .

where

•V

REF

is the internal 0.8-V reference voltage

Figure 21. Feedback Network for Channel 1

DESIGN HINT

There is a leakage current of up to 12 µA out of the SW pin when a single output ofthe TPS5438x is disabled. Keeping the series impedance of R1 + R2 less than 50 k Ωprevents the output from floating above the referece voltage while the controller outputis in the OFF state.

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Feedback Loop and Inductor-Capacitor (L-C) Filter Selection

TPS5438x

CCOMP

11.5kW

Error Amplifier

0.8VREF

BOOT

RCOMP

Offset f(IDRAIN)

PWMto

Switch

ISLOPE

ICOMP

TPS54383

TPS54386

RCOMP

(kW)

CCOMP

(pF)

700

UDG-07012

ICOMP -ISLOPE

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

In the feedback signal path, the output voltage setting divider is followed by an internal g

-type error amplifierwith a typical transconductance of 30 µS. An internal series connected R-C circuit from the g

amplifier output toground serves as the compensation network for the converter. The signal from the error amplifier output is thenbuffered and combined with a slope compensation signal before it is mirrored to be referenced to the SW node.Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM) signal-fed todrive the upper MOSFET switch. A simplified equivalent circuit of the signal control path is depicted in Figure 22 .

NOTE:

Noise coupling from the SWx node to internal circuitry of BOOTx may impact narrowpulse width operation, especially at load currents less than 1 A. See SW NodeRinging for further information on reducing noise on the SWx node.

Figure 22. Feedback Loop Equivalent Circuit

A more conventional small signal equivalent block diagram is shown in Figure 23 . Here, the full closed loopsignal path is shown. Because the TPS5438x contains internal slope compensation and loop compensationcomponents, the external L-C filter must be selected appropriately so that the resulting control loop meets criteriafor stability. This approach differs from an externally-compensated controller, where the L-C filter is generallyselected first, and the compensation network is found afterwards. To find the appropriate L and C filtercombination, the Output-to-Vc signal path plots (see the next section ) of gain and phase are used along withother design criterial to aid in finding the combinations that best results in a stable feedback loop.

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VREF

VIN

VOUT

Compensation

Network

Modulator

Filter

Current

Feedback

Network

Inductor-Capacitor (L-C) Selection

100 1 M1 k 100 k10 k

-90

135

180

-45

270

225

Duty Cycle %

Gain Phase

Phase - °

-20

100

Gain - dB

1 M1 k 100 k10 k

-90

135

180

-45

270

225

f - Frequency -Hz

Phase - °

100

-20

100

Gain - dB

Duty Cycle %

Gain Phase

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

Figure 23. Small Signal Equivalent Block Diagram

The following figures plot the TPS5438x Output-to-Vc gain and phase versus frequency for various duty cycles(10%, 30%, 50%, 70%, 90%) at three (200 mA, 400 mA, 600 mA) peak-to-peak ripple current levels. The loopresponse curve selected to compensate the loop is based on the duty cycle of the application and the ripplecurrent in the inductor. Once the curve has been selected and the inductor value has been calculated, the outputcapacitor is found by calculating the L-C resonant frequency required to compensate the feedback loop. A briefexample follows the curves.

Note that the internal error amplifier compensation is optimized for output capacitors with an ESR zero frequencybetween 20 kHz and 60 kHz. See the following sections for further details.

GAIN AND PHASE GAIN AND PHASEvs vsFREQUENCY FREQUENCY

Figure 24. TPS54383 at 200-mApp Ripple Current Figure 25. TPS54383 at 400-mApp Ripple Current

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100 1 M1 k 100 k10 k

-90

135

180

-45

270

225

Duty Cycle %

Gain Phase

f - Frequency -Hz

Phase - °

-20

100

Gain - dB

100 1M1k 100k10k

f Frequency Hz- -

-20

100

-5

-90

135

180

-45

270

225

GainPhase

Gain dB-

Phase -°

DutyCycle%

100 1 M1 k 100 k10 k

-90

135

180

-45

270

225

f - Frequency -Hz

Phase - °

-20

100

Gain - dB

Duty Cycle %

Gain Phase

100 1M1k 100k10k

-90

135

180

-45

270

225

f Frequency Hz- -

GainPhase

-20

100

-5

Gain dB-

Phase -°

DutyCycle%

Maximum Output Capacitance

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

GAIN AND PHASE GAIN AND PHASEvs vsFREQUENCY FREQUENCY

Figure 26. TPS54383 at 600-mApp Ripple Current Figure 27. TPS54386 at 200-mApp Ripple Current

GAIN AND PHASE GAIN AND PHASEvs vsFREQUENCY FREQUENCY

Figure 28. TPS54386 at 400-mApp Ripple Current Figure 29. TPS54386 at 600-mApp Ripple Current

With internal pulse-by-pulse current limiting and a fixed soft start time, there is a maximum output capacitancewhich may be used before startup problems begin to occur. If the output capacitance is large enough so that thedevice enters a current limit protection mode during startup, then there is a possibility that the output will neverreach regulation. Instead, the TPS5438x simply shuts down and attempts a restart as if the output wereshort-circuited to ground. The maximum output capacitance (including bypass capacitance distributed at theload) is given by Equation 3 :

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C =

OUTmax

tSS

VREF

ICLx V-REF(1 + )

VREF(1 + ) ´ TS

2 VIN

´ ´ LRLOAD

(1 -)

(3)

Minimum Output Capacitance

Modifying The Feedback Loop

PVDD2

BOOT2

SW2

PVDD1

BOOT1

SW1

GND

TPS5438x

SEQ

ILIM2

FB2

EN1

EN2

FB1

OUTPUT1

UDG-07013

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

Ensure the value of capacitance selected for closed loop stability is compatible with the requirements of SoftStart .

Within the limits of the internal compensation, there is flexibility in the selection of the inductor and outputcapacitor values. A smaller inductor increases ripple current, and raises the resonant frequency, therebyincerasing the required amount of output capacitance. A smaller capacitor could also be used, increasing theresonant frequency, and increasing the overall loop bandwidth — perhaps at the expense of adequate phasemargin.

The internal compensation of the TPS54x8x is designed for capacitors with an ESR zero frequency between20kHz and 60kHz. It is possible, with additional feedback compensation components, to use capacitors withhigher or lower ESR zero frequencies. For either case, the components C1 and R3 (ref.Figure 30 ) are added tore-compensate the feedback loop for stability. In this configuration a low frequency pole is followed by a higherfrequency zero. The placement of this pole-zero pair is dependent on the type of output capacitor used, and thedesired closed loop frequency response.

Figure 30. Optional Loop Compensation Components

NOTE:

Once the filter and compensation components have been established, laboratorymeasurements of the physical design should be performed to confirm converterstability.

Using High-ESR Output Capacitors

If a high ESR capacitor is used in the output filter, a zero appears in the loop response that could lead toinstability. To compensate, a small R-C series connected network is placed in parallel with the lower voltagesetting divider resistor (Ref Figure 30 ). The values of the components are determined such that a pole is placedat the same frequency as the ESR zero and a new zero is placed at a frequency location conducive to good loopstability.

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ZERO(desired)

ESR(zero)

=æ ö

æ ö

ç ÷

è ø

(4)

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

The value of the resistor is calculated using a ratio of impedances to match the ratio of ESR zero frequency tothe desired zero frequency.

where:

•f

ESR(zero)

is the ESR zero frequency of the output capacitor.•f

ZERO(desired)

is the desired frequency of the zero added to the feedback. This frequency should be placedbetween 20 kHz and 60 kHz to ensure good loop stability.

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EQ ESR(zero)

C1 2 R

=p´ ´

(5)

R R3 1 1

R1 R2

= + æ ö

æ ö æ ö

ç ÷

ç ÷ ç ÷

è ø è ø

è ø

(6)

EQ POLE(desired)

C1 2 R

=p´ ´

(7)

R R3 1 1

R1 R2

= + æ ö

æ ö æ ö

ç ÷

ç ÷ ç ÷

è ø è ø

è ø

(8)

( )

1 R1

C2 1

2 R1 R2 R3

R2 R3

= ´ +

p´ ´ æ ö

ç ÷

è ø

(9)

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

The value of the capacitor is calculated in Equation 5 .

where:

•R

is an equivalent impedance created by the parallel combination of the voltage setting divider resistors (R1and R2) in series with R3.

Using All Ceramic Output Capacitors

With low ESR ceramic capacitors, there may not be enough phase margin at the crossover frequency. In thiscase, (Ref Figure 30 ) resistor R3 is set equal to 1/2 R2. This lowers the gain by 6 dB, reduce the crossoverfrequency, and improve phase margin.

The value of C1 is found by determining the frequency to place the low frequency pole. The minimum frequencyto place the pole is 1 kHz. Any lower, and the time constant will be too slow and interfere with the internal softstart. (Ref. Soft Start ) The upper bound for the pole frequency is determined by the operating frequency of theconverter. It is 3 kHz for the TPS54x83, and 6 kHz for the TPS54x86. C1 is then found from Equation 7 . Keepcomponent tolerances in mind when selecting the desired pole frequency.

where:

•f

POLE(desired)

is the desired pole frequency between 1 kHz and 3 kHz (TPS54x83) or 1 kHz and 6 kHz(TPS54x86).

•R

is an equivalent impedance created by the parallel combination of the voltage setting divider resistors (R1and R2) in series with R3.

If it is necessary to increase phase margin, place a capacitor in parallel with the upper voltage setting dividerresistor (Ref. C2 in Equation 9 ).

where

•f

is the unity gain crossover frequency, (approximately 50 kHz for most designs following these guidelines)

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Example: TPS54386 Buck Converter Operating at 12-V Input, 3.3-V Output and 400-mA

(P-P)

Ripple Current

VOUT DIODE

VIN +VDIODE

3.3 0.5+

12 0.5+

d===30%

(10)

IN OUT S

V V 12 3.3 1

L T 0.3 10.9 H

I 0.4 600000

= ´ d ´ = ´ ´ = m

(11)

( ) ( )

2 2

RES

1 1

C 70 F

10 10 2 3.14 6000

L 2 f -

= = = m

´ ´ ´ ´

´ ´ p ´

(12)

( )

ESR 6

RES

1 1

R 40 m

2 10 C 2 3.14 10 6000 68 10 -

< = » W

´ p´ ´ ´ ´ ´ ´ ´ ´

(13)

100 1M1k 100k10k

-20

-180

-90

-45

-135

180

135

f Frequency Hz- -

Gain

Phase

-10

Gain dB-

Phase -°

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

First, the steady state duty cycle is calculated. Assuming the rectifier diode has a voltage drop of 0.5 V, the dutycycle is approximated using Equation 10 .

The filter inductor is then calculated; see Equation 11 .

A custom-designed inductor may be used for the application, or a standard value close to the calculated valuemay be used. For this example, a standard 10- µH inductor is used. Using Figure 28 , find the 30% duty cyclecurve. The 30% duty cycle curve has a down slope from low frequency and rises at approximately 6 kHz. Thiscurve is the resonant frequency that must be compensated. Any frequency wthin an octave of the peak may beused in calculating the capacitor value. In this example, 6 kHz is used.

A 68- µF capacitor should be used as a bulk capacitor, with up to 10 µF of ceramic bypass capacitance. Toensure the ESR zero does not significantly impact the loop response, the ESR of the bulk capacitor should beplaced a decade above the resonant frequency.

The resulting loop gain and phase are shown in Figure 31 . Based on measurement, loop crossover is 45 kHzwith a phase margin of 60 degrees.

GAIN AND PHASE

vsFREQUENCY

Figure 31. Example Loop Result

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Bootstrap for the N-Channel MOSFET

Light Load Operation

IDCM =´

2´ d ´ TS

V V

IN OUT

(14)

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fullyenhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to a maximum of 90%,allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP andBOOTx) during every cycle. When the PWM switch is commanded to turn ON, the energy used to drive theMOSFET gate is derived from the voltage on this capacitor.

To allow the bootstrap capacitor to charge each switching cycle, an internal pulldown MOSFET (from SW toGND) is turned ON for approximately 140 ns at the beginning of each switching cycle. In this way, if, during lightload operation, there is insufficient energy for the SW node to drive to ground naturally, this MOSFET forces theSW node toward ground and allow the bootstrap capacitor to charge.

Because this is a charge transfer circuit, care must be taken in selecting the value of the bootstrap capacitor. Itmust be sized such that the energy stored in the capacitor on a per cycle basis is greater than the gate chargerequirement of the MOSFET being used.

DESIGN HINT

For the bootstrap capacitor, use a ceramic capacitor with a value between 22 nF and82 nF.

NOTE:

For 5-V input applications, connect PVDDx to BP directly. This connection bypassesthe internal control circuit regulator and provides maximum voltage to the gate drivecircuitry. In this configuration, shutdown mode IDD

SDN

will be the same as quiescentIDD

There is no special circuitry for pulse skipping at light loads. The normal characteristic of a nonsynchronousconverter is to operate in the discontinuous conduction mode (DCM) at an average load current less thanone-half of the inductor peak-to-peak ripple current. Note that the amplitude of the ripple current is a function ofinput voltage, output voltage, inductor value, and operating frequency, as shown in Equation 14 .

Further, during discontinuous mode operation the commanded pulse width may become narrower than thecapability of the converter to resolve. To maintain the output voltage within regulation, skipping switching pulsesat light load conditions is a natural by-product of that mode. This condition may occur if the output capacitor ischarged to a value greater than the output regulation voltage, and there is insufficient load to discharge thecapacitor. A by-product of pulse skipping is an increase in the peak-to-peak output ripple voltage.

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Inductor

Current

VOUT

Ripple

SW Waveform

Steady State

VIN = 12 V

VOUT = 5 V

SW Waveform

VOUT

Ripple Inductor

Current

Skipping

VIN = 12 V

VOUT = 5 V

SW Node Ringing

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

Figure 32. Steady State Figure 33. Skipping

DESIGN HINT

If additional output capacitance is required to reduce the output voltage ripple duringDCM operation, be sure to recheck Feedback Loop and Inductor-Capacitor (L-C)Filter Selection and Maximum Output Capacitance sections.

A portion of the control circuitry is referenced to the SW node. To ensure jitter-free operation, it is necessary todecrease the voltage waveform ringing at the SW node to less than 5 volts peak and of a duration of less than30-ns. In addition to following good printed circuit board (PCB) layout practices, there are a couple of designtechniques for reducing ringing and noise.

SW Node Snubber

Voltage ringing observable at the SW node is caused by fast switching edges and parasitic inductance andcapacitance. If the ringing results in excessive voltage on the SW node, or erratic operation of the converter, anR-C snubber may be used to dampen the ringing and ensure proper operation over the full load range.

DESIGN HINT

A series-connected R-C snubber (C = between 330 pF and 1 nF, R = 10 Ω)connected from SW to GND reduces the ringing on the SW node.

Bootstrap Resistor

A small resistor in series with the bootstrap capacitor reduces the turn-on time of the internal MOSFET, therebyreducing the rising edge ringing of the SW node.

DESIGN HINT

A resistor with a value between 1 Ωand 3 Ωmay be placed in series with the bootstrapcapacitor to reduce ringing on the SW node.

DESIGN HINT

Placeholders for these components should be placed on the initial prototype PCBs incase they are needed.

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Output Overload Protection

Operating Near Maximum Duty Cycle

OUT DIODE

IN DIODE

V V

d = +

(15)

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

In the event of an overcurrent during soft start on either output (such as starting into an output short),pulse-by-pulse current limiting and PWM frequency division are in effect for that output until the internal soft starttimer ends. At the end of the soft start time, a UV condition is declared and a fault is declared. During this faultcondition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON.This process ensures that both outputs discharge to GND in the event that overcurrent is on one output while theother is not loaded. The converter then enters a hiccup mode timeout before attempting to restart. "FrequencyDivision" means if an overcurrent pulse is detected, six clock cycles are skipped before a next PWM pulse isinitiated, effectively dividing the operating frequency by six and preventing excessive current build up in theinductor.

In the event of an overcurrent on either output after the output reaches regulation, pulse-by-pulse current limit isin effect for that output. In addition, an output undervoltage (UV) comparator monitors the FBx voltage (thatfollows the output voltage) to declare a fault if the output drops below 85% of regulation. During this faultcondition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON.This design ensures that both outputs discharge to GND, in the event that overcurrent is on one output while theother is not loaded. The converter then enters a hiccup mode timeout before attempting to restart.

The overcurrent threshold for Output 1 is set nominally at 4.5 A. The overcurrent level of Output 2 is determinedby the state of the ILIM2 pin. The ILIM setting of Output 2 is not latched in place and may be changed duringoperation of the converter.

Table 2. Current Limit Threshold Adjustment forOutput 2

ILIM2 Connection OCP Threshold for Output 2

BP 4.5 A nominal setting(floating) 3.0 A nominal settingGND 1.5 A nominal setting

DESIGN HINT

The OCP threshold refers to the peak current in the internal switch. Be sure to addone-half of the peak inductor ripple current to the dc load current in determining howclose the actual operating point is to the OCP threshold

If the TPS5438x operates at maximum duty cycle, and if the input voltage is insufficient to support the outputvoltage (at full load or during a load current transient), then there is a possibility that the output voltage will fallfrom regulation and trip the output UV comparator. If this should occur, the TPS5438x protection circuitry willdeclare a fault and enter a shut down-and-restart cycle.

DESIGN HINT

Ensure that under ALL conditions of line and load regulation, there is sufficient dutycycle to maintain output voltage regulation.

To calculate the operating duty cycle, use Equation 15 .

where

•V

DIODE

is the voltage drop of the rectifier diode

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Dual Supply Operation

Cascading Supply Operation

PVDD2

BOOT2

SW2

PVDD1

BOOT1

SW1

GND

TPS54383

SEQ

ILIM2

FB2

EN1

EN2

FB1

OUTPUT1 OUTPUT2

VIN

UDG-07015

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

It is possible to operate a TPS5438x from two supply voltages. If this application is desired, then the sequencingof the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This levelrequirement ensures that the internal regulator and the control circuitry are in operation before PVDD1 suppliesenergy to the output. In addition, Output 1 must be held in the disabled state ( EN1 high) until there is sufficientvoltage on PVDD1 to support Output 1 in regulation. (See the Operating Near Maximum Duty Cycle section.)

The preferred sequence of events is:

1. PVDD2 rises above the input UVLO voltage2. PVDD1 rises with Output 1 disabled until PVDD1 rises above level to support Output 1 regulation.With these two conditions satisfied, there is no restriction on PVDD2 to be greater than, or less than PVDD1.

DESIGN HINT

An R-C delay on EN1 may be used to delay the startup of Output1 for a long enoughperiod of time to ensure that PVDD1 can support Output 1 load.

It is possible to source PVDD1 from Output 2 as depicted in Figure 34 and Figure 35 . This configuration may bepreferred if the input voltage is high, relative to the voltage on Output 1.

Figure 34. Schematic Showing Cascading PVDD1 from Output 2

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T Time-

Output1

Output2

PVDD1

PVDD2

Multiphase Operation

Bypass and FIltering

Over-Temperature Protection and Junction Temperature Rise

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

Figure 35. Waveforms Resulting from Cascading PVDD1 from Output 2

In this configuration, the following conditions must be maintained:1. Output 2 must be of a voltage high enough to maintain regulation of Output 1 under all load conditions.2. The sum of the current drawn by Output 2 load plus the current into PVDD1 must be less than the overloadprotection current level of Output 2.3. The method of output sequencing must be such that the voltage on Output 2 is sufficient to support Output 1before Output 1 is enabled. This requrement may be accomplished by:a. a delay of the enable functionb. selecting sequential sequencing of Output 1 starting after Output 2 is in regulation

The TPS5438x is not designed to operate as a two-channel multiphase converter. See http://www.power.ti.comfor appropriate device selection.

As with any integrated circuit, supply bypassing is important for jitter-free operation. To improve the noiseimmunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible.1. PVDD1 to GND: Use a 10- µF ceramic capacitor2. PVDD2 to GND: Use a 10- µF ceramic capacitor3. BP to GND: Use a 4.7- µF to 10- µF ceramic capacitor

The over-temperature thermal protection limits the maximum power to be dissipated at a given operating ambienttemperature. In other words, at a given device power dissipation, the maximum ambient operating temperature islimited by the maximum allowable junction operating temperature. The device junction temperature is a functionof power dissipation, and the thermal impedance from the junction to the ambient. If the internal die temperatureshould reach the thermal shutdown level, the TPS5438x shuts off both PWMs and remains in this state until thedie temperature drops below the hysteresis value, at which time the device restarts.

The first step to determine the device junction temperature is to calculate the power dissipation. The powerdissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated byeach MOSFET is composed of conduction losses and output (switching) losses incurred while driving theexternal rectifier diode. To find the conduction loss, first find the RMS current through the upper switch MOSFET.

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( ) ( )2

2OUTPUTx

RMS(outputx) OUTPUTx

I D I 12

æ ö

ç ÷

= ´ +

ç ÷

è ø

(16)

D(cond) RMS(outputx) DS(on)

P I R= ´

(17)

PD(SW) =

(V ) C f

IN J S

2´ ´

(18)

D D(cond)output1 D(SW )output1 D(cond)output2 D(SW )output2 IN

P P P P P V Iq= + + + + ´

(19)

( )

J A D TH(pkg) TH(pad amb)

T T P -

= + ´ q + q

(20)

Power Derating

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

where

•D is the duty cycle•I

OUTPUTx

is the dc output current•ΔI

OUTPUTx

is the peak ripple current in the inductor for Outputx

Notice the impact of the operating duty cycle on the result.

Multiplying the result by the R

DS(on)

of the MOSFET gives the conduction loss.

The switching loss is approximated by:

where

•where C

is the prallel capacitance of the rectifier diode and snubber (if any)•f

is the switching frequency

The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internalregulator.

The temperature rise of the device junction depends on the thermal impedance from junction to the mounting pad(See the Package Dissipation Ratings table), plus the thermal impedance from the thermal pad to ambient. Thethermal impedance from the thermal pad to ambient depends on the PCB layout (PowerPAD interface to thePCB, the exposed pad area) and airflow (if any). See the PCB Layout Guidelines, Additional References section.

The operating junction temperature is shown in Equation 20 .

The TPS5438x delivers full current at ambient temperatures up to +85 °C if the thermal impedance from thethermal pad maintains the junction temperature below the thermal shutdown level. At higher ambienttemperatures, the device power dissipation must be reduced to maintain the junction temperature at or below thethermal shutdown level. Figure 36 illustrates the power derating for elevated ambient temperature under variousairflow conditions. Note that these curves assume that the PowerPAD is properly soldered to the recommendedthermal pad. (See the References section for further information.)

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0.4

0.6

0.8

1.0

1.8

0.2

0 20 40 60 14080 100 120

TA- Ambient Temperature - °C

PD- Power Dissipation - W

150

250

500

LFM

1.2

1.6

1.4

LFM = 0

LFM = 150

LFM = 250

LFM = 500

PowerPAD Package

PCB Layout Guidelines

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

POWER DISSIPATION

vsAMBIENT TEMPERATURE

Figure 36. Power Derating Curves

The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPADderives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuitboard must have an area of solder-tinned-copper underneath the package. The dimensions of this area dependon the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes andshould have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the viais plated with copper. This plug is needed to prevent wicking the solder away from the interface between thepackage body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13mils) work well when 1-oz. copper is plated at the surface of the board while simultaneously plating the barrel ofthe via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask materialshould be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This cappingprevents the solder from being wicked through the thermal vias and potentially creating a solder void under thepackage. (See the Additional References section.)

The layout guidelines presented here are illustrated in the PCB layout examples given in Figure 37 andFigure 38 .•The PowerPAD must be connected to a low current (signal) ground plane having a large copper surface areato dissipate heat. Extend the copper surface well beyond the IC package area to maximize thermal transfer ofheat away from the IC.•Connect the GND pin to the PowerPAD through a 10-mil (.010 in, or 0.0254 mm) wide trace.•Place the ceramic input capacitors close to PVDD1 and PVDD2; connect using short, wide traces.•Maintain a tight loop of wide traces from SW1 or SW2 through the switch node, inductor, output capacitor andrectifier diode. Avoid using vias in this loop.•Use a wide ground connection from the input capacitor to the rectifier diode, placed as close to the powerpath as possible. Placement directly under the diode and the switch node is recommended.•Locate the bootstrap capacitor close to the BOOT pin to minimize the gate drive loop.•Locate voltage setting resistors and any feedback components over the ground plane and away from theswitch node and the rectifier diode to input capacitor ground connection.

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VIN

GND

C1 C10

C16

C17

C14

C11

C13

C18

C19

C12

C15

GND

VOUT1

VOUT2

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

•Locate snubber components (if used) close to the rectifier diode with minimal loop area.•Locate the BP bypass capacitor very close to the IC; a minimal loop area is recommended.•Locate the output ceramic capacitor close to the inductor output terminal between the inductor and anyelectrolytic capacitors, if used.

Figure 37. Top Layer Copper Layout and Component Placement

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Figure 38. Bottom Layer Copper Layout

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DESIGN EXAMPLES

Example 1: Detailed Design of a 12-V to 5-V and 3.3-V Converter

TPS54383 , , TPS54386

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The following example illustrates a design process and component selection for a 12-V to 5-V and 3.3-V dualnon-synchronous buck regulator using the TPS54383 converter. Design Example List of Materials and Table 4 ,Definition of Symbols is found at the end of this section.PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNIT

INPUT CHARACTERISTICS

Input voltage 6.9 12.0 13.2 V

Input current V

= nom, I

OUT

= max 1.6 2.0 A

No load input current V

= nom, I

OUT

= 0 A 12 20 mA

OUTPUT CHARACTERISTICS

OUT1

Output voltage 1 V

= nom, I

OUT

= nom 4.8 5.0 5.2

OUT2

Output voltage 2 V

= nom, I

OUT

= nom 3.2 3.3 3.4

Line regulation V

= min to max 1%

Load regulation I

OUT

= min to max 1%

OUT(ripple

Output voltage ripple V

= nom, I

OUT

= max 50 mV

PP)

OUT1

Output current 1 V

= min to max 0 2.0

OUT2

Output current 2 V

= min to max 0 2.0

Output overcurrent channel

OCP1

= nom, V

OUT

= V

OUT1

= 5% 2.4 3 3.51

Output overcurrent channelI

OCP2

= nom, V

OUT

= V

OUT2

= 5% 2.4 3 3.52

Transient response ΔV

OUT

ΔI

OUT

= 1 A @ 3 A/ µs 200 mVfrom load transient

Transient response settling

1 mstime

SYSTEM CHARACTERISTICS

Switching frequency 250 310 370 kHz

ηFull load efficiency 85%

Operating temperatureT

0 25 60 °Crange

Figure 39. Design Example Schematic

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Design Procedure

Duty Cycle Estimation

OUT FD

max

IN(min) FD

V V

DV V

»+

(21)

OUT FD

min

IN(max) FD

V V

DV V

»+

(22)

Inductor Selection

IN(max) OUT

min min

LRIP(m ax) SW

V V 1

L D

I f

» ´ ´

(23)

IN(max) OUT

RIPPLE min

V V 1

I D

L f

» ´ ´

(24)

( ) ( ) ( )

L(avg) RIPPLE

L rms

I I I

= +

(25)

( ) OUT(max) RIPPLE

L peak

I I I

» +

(26)

Rectifier Diode Selection

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

The first step is to estimate the duty cycle of each switching FET.

Using an assumed forward drop of 0.5 V for a schottky rectifier diode, the Channel 1 duty cycle is approximately40.1% (minimum) to 48.7% (maximum) while the Channel 2 duty cycle is approximately 27.7% (minimum) to32.2% (maximum).

The peak-to-peak ripple is limited to 30% of the maximum output current. This places the peak current farenough from the minimum overcurrent trip level to ensure reliable operation.

For both Channel 1 and Channel 2, the maximum inductor ripple current is 600 mA. The inductor size isestimated in Equation 23 .

The inductor values are•L1 = 18.3 µH•L2 = 15.3 µH

The next higher standard inductor value of 22 µH is used for both inductors.

The resulting ripple currents are :

Peak-to-peak ripple currents of 0.498 A and 0.416 A are estimated for Channel 1 and Channel 2 respectively.

The RMS current through an inductor is approximated by Equation 25 .

and is approximately 2.0 A for both channels.

The peak inductor current is found using:

An inductor with a minimum RMS current rating of 2.0 A and minimum saturation current rating of 2.25 A isrequired. A Coilcraft MSS1278-223ML 22- µH, 6.8-A inductor is selected.

A schottky diode is selected as a rectifier diode for its low forward voltage drop. Allowing 20% over VIN forringing on the switch node, the required minimum reverse break-down voltage of the rectifier diode is:

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( ) ( ) IN

BR R min

V 1.2 V³ ´

(27)

( ) ( ) ( )

D avg OUT max

I I 1 D» ´ -

(28)

( ) ( )

D m a x D av g

P V I» ´

(29)

Output Capacitor Selection

( )

OUT 2

2RES

4 f L

=´ p ´ ´

(30)

OUT

RIPPLE(tot) RIPPLE(cap) RIPPLE(tot)

(max)

RIPPLE RIPPLE S

V V V D

ESR I I f C

= = - ´

(31)

Voltage Setting

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

The diode must have reverse breakdown voltage greater than 15.8 V, therefore a 20-V device is used.

The average current in the rectifier diode is estimated by Equation 28 .

For this design, 1.2-A (average) and 2.25 A (peak) is estimated for Channel 1 and 1.5-A (average) and 2.21-A(peak) for Channel 2.

An MBRS320, 20-V, 3-A diode in an SMC package is selected for both channels. This diode has a forwardvoltage drop of 0.4 V at 2 A.

The power dissipation in the diode is estimated by Equation 29 .

For this design, the full load power dissipation is estimated to be 480 mW in D1, and 580 mW in D2.

The TPS54383's internal compensation limits the selection of the output capacitors. From Figure 25 , the internalcompensation has a double zero resonance at about 3 kHz. The output capacitor is selected by Equation 30 .

Solving for C

OUT

using•f

RES

= 3 kHz•L = 22 µH

The resulting is C

OUT

= 128 µF. The output ripple voltage of the converter is composed of the ripple voltageacross the output capacitance and the ripple voltage across the ESR of the output capacitor. To find themaximum ESR allowable to meet the output ripple requirements the total ripple is partitioned, and the equationmanipulated to find the ESR.

Based on 128 µF of capacitance, 300-kHz switching frequency and 50-mV ripple voltage plus rounding up theripple current to 0.5 A, and the duty cycle to 50%, the capacitive portion of the ripple voltage is 6.5 mV, leaving amaximum allowable ESR of 87 m Ω.

To meet the ripple voltage requirements, a low-cost 100- µF electrolytic capacitor with 400 m ΩESR (C5, C17)and two 10- µF ceramic capacitors (C3 and C4; and C18 and C19) with 2.5-m ΩESR are selected. From thedatasheets for the ceramic capacitors, the parallel combination provides an impedance of 28 m Ω@ 300 kHz for14 mV of ripple.

The primary feedback divider resistors (R2, R9) from VOUT to FB should be between 10 k Ωand 50 k Ωtomaintain a balance between power dissipation and noise sensitivity. For this design, 20 k Ωis selected.

The lower resistors, R4 and R7 are found using the following equations.

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OUT1 FB

V R2

R4 V V

(32)

OUT2 FB

V R9

R7 V V

(33)

Compensation Capacitors

fESR(zero)

2 C ESR

=´ p´ ´

(34)

ZERO(desired)

ESR(zero)

=æ ö

æ ö

ç ÷

è ø

(35)

R R5 1 1

R2 R4

= + æ ö

æ ö æ ö

ç ÷

ç ÷ ç ÷

è ø è ø

è ø

(36)

EQ ESR(zero)

C8 2 R

=´ p´ ´

(37)

Input Capacitor Selection

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

•R2 = R9 = 20 k Ω

•V

= 0.80 V•R4= 3.80 k Ω(3.83 k Ωstandard value is used)•R7= 6.40 k Ω(6.34 k Ωstandard value is used)

Checking the ESR zero of the output capacitors:

•C = 100 µF•ESR = 400 m Ω

•ESR(zero) = 3980 Hz

Since the ESR zero of the main output capacitor is less than 20 kHz, an R-C filter is added in parallel with R4and R7 to compensate for the electrolytic capacitors' ESR and add a zero approximately 40 kHz.

•f

ESR(zero)

= 4 kHz•f

ESR(desired)

= 40 kHz•R4 = 3.83 k Ω

•R5 = 424 Ω(422 Ωselected)•R7 = 6.34 k Ω

•R8 = 702 Ω(698 Ωselected)

•R2 = R9 = 20 k Ω

•R

EQ1

= 3.63 k Ω

•R

EQ2

= 5.51 k Ω

•C8 = 10.9 nF (10 nF selected)•C15 = 7.22 nF (6800 pF selected)

The TPS54383 datasheet recommends a minimum 10- µF ceramic input capacitor on each PVDD pin. Thesecapacitor must be capable of handling the RMS ripple current of the converter. The RMS current in the inputcapacitors is estimated by Equation 38 .

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( ) ( )2

2OUTPUTx

RMS(outputx) OUTPUTx

I D I 12

æ ö

ç ÷

= ´ +

ç ÷

è ø

(38)

Boot Strap Capacitor

ILIM

SEQ

Power Dissipation

( ) ( )2

2OUTPUTx

RMS(outputx) OUTPUTx

I D I 12

æ ö

ç ÷

= ´ +

ç ÷

è ø

(39)

( ) ( )

()

CON DS on QSW rms

P R I= ´

(40)

( )

()( )

DJ OSS SW

IN max

V C C f

´ + ´

(41)

( ) ( )

()

REG DD BP BP

IN max IN max

P I V I V V» ´ + ´ -

(42)

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

•I

RMS(CIN)

= 0.43 A

One 1210 10- µF, 25 V, X5R ceramic capacitor with 2-m ΩESR and a 2-A RMS current rating are selected foreach PVDD input. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage toensure the capacitors maintain sufficient capacitance at the working voltage.

To ensure proper charging of the high-side FET gate and limit the ripple voltage on the boost capacitor, a 33-nFboot strap capacitor is used.

Current limit must be set above the peak inductor current I

L(peak)

. Comparing I

L(peak)

to the available minimumcurrent limits, ILIM is connected to BP for the highest current limit level.

The SEQ pin is left floating, leaving the enable pins to function independently. If the enable pins are tiedtogether, the two supplies start-up ratiometrically. Alternatively, SEQ could be connected to BP or GND toprovide sequential start-up.

The power dissipation in the TPS54383 is composed of FET conduction losses, switching losses and internalregulator losses. The RMS FET current is found using Equation 39 .

This results in 1.05-A RMS for Channel 1 and 0.87-A RMS for Channel 2.

Conduction losses are estimated by:

Conduction losses of 198 mW and 136 mW are estimated for Channel 1 and Channel 2 respectively.

The switching losses are estimated in Equation 41 .

From the data sheet of the MBRS320, the junction capacitance is 658 pF. Since this is large compared to theoutput capacitance of the TPS54x8x the FET capacitance is neglected, leaving switching losses of 17 mW foreach channel.

The regulator losses are estimated in Equation 42 .

With no external load on BP (I

=0) the regulator power dissipation is 66 mW.

Total power dissipation in the device is the sum of conduction and switching for both channels plus regulatorlosses.

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Design Example Test Results

SW 3.3 V

SW 5 V

VIN = 12 V

t − Time − 40 ns/div

100

ILOAD - Load Current - A

h- Efficiency - %

VIN = 13.2 V

VIN = 9.6 V

VIN = 12.0 V

VOUT = 5.0 V

VIN (V)

9.6

12.0

13.2

0 0.5 1.0 1.5 2.0 2.5 3.0

100

ILOAD - Load Current - A

h- Efficiency - %

VIN = 9.6 V

VOUT = 3.3 V

VIN (V)

9.6

12.0

13.2

VIN = 12.0 V

VIN = 13.2 V

0 0.5 1.0 1.5 2.0 2.5 3.0

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

The total power dissipation is P

DISS

=0.198+0.136+0.017+0.017+.066 = 434 mW.

The following results are from the TPS54383-001 EVM.

Figure 40. Switching Node Waveforms

Figure 41. 5.0-V Output Efficiency vs. Load Current Figure 42. 3.3-V Output Efficiency vs. Load Current

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0.995

0.997

0.999

1.001

0.996

0.998

1.000

1.003

1.005

1.002

1.004

VOUT - Output Voltage (Normalized) - V

VOUT = 5.0 V

VIN (V)

9.6

12.0

13.2

VIN = 12.0 V

VIN = 9.6 V

VIN = 13.2 V

0 0.5 1.0 1.5 2.0 2.5 3.0

IOUT - Load Current - A

0.995

0.997

0.999

1.001

0.996

0.998

1.000

1.003

1.005

1.002

1.004

VOUT - Output Voltage (Normalized) - V

VOUT = 3.3 V

VIN (V)

9.6

12.0

13.2

VIN = 12.0 V

VIN = 9.6 V

VIN = 13.2 V

0 0.5 1.0 1.5 2.0 2.5 3.0

IOUT - Load Current - A

1 k 10 k 100 k

f - Frequency -Hz

-80

-20

-60

Gain - dB

-40

-180

-90

-45

-135

180

135

Phase - °

300 k

Gain Phase

5.0 V

3.3 V

TPS54383 , , TPS54386

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Figure 43. 5.0-V Output Voltage vs. Load Current Figure 44. 3.3-V Output Voltage vs. Load Current

Figure 45. Example 1 Loop Response

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Table 3. Design Example List of Materials

REFERENCE

QTY VALUE DESCRIPTION SIZE PART NUMBER MANUFACTURERDESIGNATOR

1 C1 100 µF Capacitor, Aluminum, 25V, 20% E-can EEEFC1E101P Panasonic2 C10, C11 10 µF Capacitor, Ceramic, 25V, X5R 20% 1210 C3216X5R1E106M TDK1 C12 4.7 µF Capacitor, Ceramic, 10V, X5R 20% 0805 Std Std2 C14, C16 470 pF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std1 C15 6.8 nF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std StdCapacitor, Aluminum, 10V, 20%, FC1 C17, C5 100 µF F-can EEEFC1A101P PanasonicSeries4 C3, C4, C18, C19 10 µF Capacitor, Ceramic, 6.3V, X5R 20% 0805 C2012X5R0J106M TDK1 C8 10 nF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std2 C9, C13 0.033 µF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std2 D1, D2 MBRS320 Diode, Schottky, 3-A, 30-V SMC MBRS330T3 On Semi0.484 x2 L1, L2 22 µH Inductor, Power, 6.8A, 0.038 ΩMSS1278-153ML Coilcraft0.4842 R2, R9 20 k ΩResistor, Chip, 1/16W, 1% 0603 Std Std1 R5 422 ΩResistor, Chip, 1/16W, 1% 0603 Std Std2 R6, R10 10 ΩResistor, Chip, 1/16W, 5% 0603 Std Std1 R8 698 ΩResistor, Chip, 1/16W, 1% 0603 Std Std1 R4 3.83 k ΩResistor, Chip, 1/16W, 1% 0603 Std Std1 R7 6.34 k ΩResistor, Chip, 1/16W, 1% 0603 Std StdTPS54383 DC-DC Switching Converter HTSSOP1 U1 TPS54383PWP TIw/ FET -14

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Table 4. Definition of Symbols

Average junction capacitance of the rectifier diode from 0V to VIN(max)C

OSS

Average output capacitance of the switching MOSFET from 0V to VIN(max)C

OUT

Output CapacitorD

(max)

Maximum steady state operating duty cycleD

(min)

Minimum steady state operating duty cycleESR

(max)

Maximum allowable output capacitor ESRf

Switching frequencyI

Output Current of BP regulator due to external loadsI

Switching quiescent current with no load on BPI

D(avg)

Average diode conduction currentI

D(peak)

Peak diode conduction currentI

IN(avg)

Average input currentI

IN(rms)

Root mean squared (RMS) input currentI

L(avg)

Average inductor currentI

L(rms)

Root mean squared (RMS) inductor currentI

L(peak)

Peak current in inductorI

LRIP(max)

Maximum allowable inductor ripple currentL

(min)

Minimum inductor value to maintain desired ripple currentI

OUT(max)

Maximum designed output currentI

RMS(cin)

Root mean squared (RMS) current through the input capacitorI

RIPPLE

Inductor peak to peak ripple currentI

QSW(rms)

Root mean squared current through the switching MOSFETP

CON

Power loss due to conduction through switching MOSFETP

D(max)

Maximum power dissipation in diodeR

DS(on)

Drain to source resistance of the switching MOSFET when “ ON ”P

Power loss due to switchingP

REG

Power loss due to the internal regulatorV

Output Voltage of BP regulatorV

(BR)R(min)

Minimum reverse breakdown voltage rating for rectifier diodeV

Regulated feedback voltageV

Forward voltage drop across rectifier diodeV

Power stage input voltageV

OUT

Regulated output voltageV

RIPPLE(cap)

Peak to Peak ripple voltage due to ideal capacitor (ESR = 0 )V

RIPPLE(tot)

Maximum allowable peak to peak output ripple voltage

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Example 2: 24-V to 12-V and 24-V to 5-V

VOUT

(5 V/div)

VIN = 24 V

IOUT = 2 A

T − Time − 10 ns / div

VOUT

(5 V/div)

VIN = 24 V

IOUT = 2 A

T − Time − 10 ns / div

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

For a higher input voltage, both a snubber and bootstrap resistors are added to reduce ringing on the switchnode and a 30 V schottky diode is selected. A higher resistance feedback network is chosen for the 12 V outputto reduce the feedback current.

Figure 46. 24-V to 12-V and 24-V to 5-V Using the TPS54383

Figure 47. Switch Node Ringing Without Snubber and Figure 48. Switch Node Ringeing With Snubber andBoost Resistor Boost Resistor

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h- Efficiency - %

VOUT = 12 V

VOUT = 5 V

0 0.5 1.0 1.5 2.0 2.5 3.0

IOUT - Load Current - A

VIN = 24 V

VOUT (V)

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SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

Figure 49. Efficiency vs. Load Current

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Example 3: 5-V to 3.3V and 5-V to 1.2 V

1 k 10 k 100 k 300 k

-180

-90

-45

-135

180

135

f - Frequency -Hz

Phase - °

-80

-20

-60

Gain - dB

-40

VOUT = 1.2 V

Gain Phase

WIth Lead

Without Lead

100

h- Efficiency - %

0 0.5 1.0 1.5 2.0 2.5 3.0

IOUT - Load Current - A

VOUT = 1.2 V

VOUT = 3.3 V

VIN = 5 V

VOUT (V)

1.2

3.3

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

For a low input voltage application, the TPS54386 is selected for reduced size and all ceramic output capacitorsare used. 22- µF input capacitors are selected to reduce input ripple and lead capacitors are placed in thefeedback to boost phase margin.

Figure 50. 5-V to 3.3V and 5-V to 1.2 V

Figure 51. Efficiency vs. Load Current Figure 52. Example 3 Loop Response

Product Folder Link(s): TPS54383 TPS54386

www.ti.com

ADDITIONAL REFERENCES

Related Devices

References

Package Outline and Recommended PCB Footprint

TPS54383 , , TPS54386

SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007

The following parts have characteristics similar to the TPS54383/6 and may be of interest.

Table 5. Devices Related to the TPS54383 and TPS54386

TI LITERATURE

DEVICE DESCRIPTIONNUMBER

SLUS642 TPS40222 5-V Input, 1.6-A Non-Synchronous Buck ConverterTPS54283 /SLUS749 2-A Dual Non-Synchronous Converter with Integrated High-Side MOSFETTPS54286

These references, design tools and links to additional references, including design software, may be found athttp:www.power.ti.com

Table 6. References

TI LITERATURE

DESCRIPTIONNUMBER

SLMA002 PowerPAD Thermally Enhanced Package Application ReportSLMA004 PowerPAD™ Made EasySLUP206 Under The Hood Of Low Voltage DC/DC Converters. SEM1500 Topic 5, 2002 Seminar SeriesSLVA057 Understanding Buck Power Stages in Switchmode Power SuppliesSLUP173 Designing Stable Control Loops. SEM 1400, 2001 Seminar Series

The following pages outline the mechanical dimensions of the 14-Pin PWP package and providerecommendations for PCB layout.

Product Folder Link(s): TPS54383 TPS54386

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TPS54383PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS54383PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS54383PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS54383PWPRG4 ACTIVE HTSSOP PWP 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS54386PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS54386PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS54386PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS54386PWPRG4 ACTIVE HTSSOP PWP 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 17-Jan-2008

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS54383PWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TPS54386PWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2009

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS54383PWPR HTSSOP PWP 14 2000 346.0 346.0 29.0

TPS54386PWPR HTSSOP PWP 14 2000 346.0 346.0 29.0

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2009

Pack Materials-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TPS54383PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart

TPS54383PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart

TPS54383PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart

TPS54383PWPRG4 ACTIVE HTSSOP PWP 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart

TPS54386PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart

TPS54386PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart

TPS54386PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart

TPS54386PWPRG4 ACTIVE HTSSOP PWP 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Add to cart

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2012

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS54383PWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TPS54386PWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS54383PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0

TPS54386PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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