HT0313A (5.0V SPECIFICATION) 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD August. 2000. VER 0.0 TOMATO LSI Inc. HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD HT0313A Specification revision history Content Version 0.0 1. Operating voltage range : VDD = 2.4V ~ 5.5V TOMATO LSI Inc. 2 Ver 0.0 Date August. 2000 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 CONTENTS 1. INTRODUCTION ----------------------------------------------------------------------------------------------------------- 5 2. FEATURES --------------------------------------------------------------------------------------------------------------- 5 3. BLOCK DIAGRAM ----------------------------------------------------------------------------------------------------- 7 4. PAD CONFIGURATION -----------------------------------------------------------------------------------------------4-1. Pad center coordinates ------------------------------------------------------------------------------------------- 8 9 5. PIN DESCRIPTION ---------------------------------------------------------------------------------------------------- 12 6. FUNCTIONAL DESCRIPTION ----------------------------------------------------------------------------------6-1. Microprocessor interface ---------------------------------------------------------------------------------------a. Chip select input b. Interface c. Parallel interface (PS = "H") d. Serial interface (PS = "L") e. Busy flag f. Data accessing 6-2. Display data RAM (DDRAM) -------------------------------------------------------------------------------------a. Display data RAM b. Page address circuit c. Column address circuit d. Line address circuit e. Segment control circuit 6-3. LCD display circuit ---------------------------------------------------------------------------------------------------a. Oscillator b. Display timing generator circuit c. Common output control circuit 6-4. LCD driver circuit --------------------------------------------------------------------------------------------------6-5. Power supply circuits ------------------------------------------------------------------------------------------a. Voltage converter circuits b. Voltage regulator circuits c. Voltage follower circuits d. High power mode 6-6. Reference circuit examples -------------------------------------------------------------------------------------6-7. Reset circuit -------------------------------------------------------------------------------------------------------- 16 16 7. PROGRAM INSTRUCTION ---------------------------------------------------------------------------------------7-1. Read display data ------------------------------------------------------------------------------------------------7-2. Write display data -----------------------------------------------------------------------------------------------7-3. Read status ----------------------------------------------------------------- --------------------------------------7-4. Display ON / OFF ----------------------------------------------------------------------------------------------------7-5. Initial display line ------------------------------------------------------------------------------------------------7-6. Reference voltage select -------------------------------------------------------------------------------------7-7. Set page address -----------------------------------------------------------------------------------------------7-8. Set column address ----------------------------------------------------------------------------------------------7-9. ADC select --------------------------------------------------------------------------------------------------------7-10. Reverse display ON / OFF----------------------------------------------------------------------------------------7-11. Entire display ON / OFF-------------------------------------------------------------------------------------------7-12. Select LCD bias -------------------------------------------------------------------------------------------------7-13. Set modify-read --------------------------------------------------------------------------------------------------7-14. Reset modify-read ----------------------------------------------------------------------------------------------7-15. Reset ---------------------------------------------------------------------------------------------------------------7-16. SHL select ---------------------------------------------------------------------------------------------------------- 34 35 35 36 36 36 37 38 38 39 39 39 39 40 40 41 41 TOMATO LSI Inc. 3 19 22 23 24 31 33 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-17. Power control --------------------------------------------------------------------------------------------------------7-18. Regulator resistor select -----------------------------------------------------------------------------------------7-19. Set static indicator state ------------------------------------------------------------------------------------------7-20. Power save (Compound instruction) --------------------------------------------------------------------------7-21. Referential instruction set flow----------------------------------------------------------------------------------- 41 42 42 43 44 8. SPECIFICATIONS -------------------------------------------------------------------------------------------------------8-1. Absolute maximum ratings --------------------------------------------------------------------------------------8-2. DC characteristics ---------------------------------------------------------------------------------------------------8-3. AC characteristics -------------------------------------------------------------------------------------------------a. Read / write characteristics (8080-series MPU) b. Read / write characteristics (6800-series MPU) c. Serial interface characteristics d. Reset input timing e. Display control output timing 48 48 48 51 9. REFERENCE APPLICATION --------------------------------------------------------------------------------------------- 55 9-1. MPU interface ------------------------------------------------------------------------------------------------------55 9-2. Connections between HT0313A and LCD panel -----------------------------------------------------------------56 9-3. TCP pin layout (sample) ----------------------------------------------------------------------------------------61 9-4. Application circuit for serial -------------------------------------------------------------------------------------62 TOMATO LSI Inc. 4 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 1. INTRODUCTION The HT0313A is a driver and controller LSI for graphic dot-matrix liquid crystal display systems. It contains 65 common and 132 segment driver circuits. This chip is connected directly to a microprocessor (MPU), accepts serial or 8-bit parallel display data and stores in an on-chip Display Data RAM (DDRAM) of 65 x 132 bits. It provides a high-flexible display section due to one to one correspondences between on-chip DDRAM bits and LCD panel pixels. And it performs DDRAM read / write operation with no externally operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. 2. FEATURES Driver output circuits -. 65 common outputs / 132 segment outputs On-chip display data RAM (DDRAM) -. Capacity: 65 x 132=8,580 bits Multi-chip operation -. Master and slave mode available Applicable duty-ratios Duty ratio Applicable LCD bias Maximum display area 1/65 1/7 or 1/9 65 x 132 1/49 1/6 or 1/8 49 x 132 1/33 1/5 or 1/6 33 x 132 Microprocessor (MPU) interface -. 8-bit parallel bi-directional interface with 6800-series or 8080-series -. Serial interface (write operation only) Various Function set -. Display ON/OFF, set initial display line, set page address, set column address, read status, write / read display data, select segment driver output, reverse display ON/OFF, entire display ON/OFF, select LCD bias, set/reset modify-read, select common driver output, control display power circuit, select internal regulator resistor ratio for V0 voltage regulation, electronic volume, set static indicator state. -. H/W and S/W reset available -. Static drive circuit equipped internally for indicators with 4 flashing modes Built-in analog circuits -. On-chip Oscillator circuit for display clock(external clock can also be used) -. High performance voltage converter (with booster ratios of x2, x3, x4 and x5, where the step-up reference voltage can be used externally) o o -. High accuracy voltage regulator(Temperature coefficient: -0.05% / C, -0.2% / C mask option) -. Electronic contrast control function (64 steps) -. Vref = 2.0V 3% (V0 voltage adjustment voltage) -. High performance voltage follower (V1 to V4 voltage divider resistors and OP-Amp for increasing drive capacity) TOMATO LSI Inc. 5 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Operating voltage range -. Supply voltage (VDD): 2.4V to 5.5V -. LCD driving voltage (VLCD = V0 -VSS): 4.0V to 15.0V Low power consumption -. Operating power: 50A (Typ) (VDD = 3V, x4 boosting, V0=11V, internal power supply ON, display OFF and normal mode is selected) -. Standby power: 10A Max. (during power save[standby] mode) Operating Temperatures -. Wide range of operating temperatures : -40 to 85 CMOS Process Package type -. Gold bumped chip and TCP available TOMATO LSI Inc. 6 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 VDD V0 V1 V2 V3 V4 VSS 33 COMMON DRIVER CIRCUITS COM63 COMS COM32 132 SEGMENT DRIVER CIRCUITS DISPLAY DATA CONTROL CIRCUIT HPM SEG129 SEG130 SEG131 SEG0 SEG1 SEG2 COMS COM0 COM31 3. BLOCK DIAGRAM 33 COMMON DRIVER CIRCUITS COMMON OUTPUT CONTROL CIRCUIT MS VOLTAGE FOLLOWER CL V0 VR INTRS I/O I/O BUFFER BUFFER VOLTAGE REGULATOR LINE LINE ADDRESS ADDRESS CIRCUIT CIRCUIT DISPLAY DISPLAYDATA DATARAM RAM 65 65xx132 132==8,580 8,580BITS BITS PAGE PAGE ADDRESS ADDRESS CIRCUIT CIRCUIT DISPLAY TIMING GENERATOR CIRCUIT COLUMN COLUMNADDRESS ADDRESS CIRCUIT CIRCUIT M FRS DISP DSEL0 DSEL1 VOUT C1C1+ C2C2+ C3C3+ /DC5 STATUS REGISTER INSTRUCTION REGISTER BUS HOLDER INSTRUCTION DECODER VOLTAGE CONVERTER Figure 3-1. block diagram TOMATO LSI Inc. 7 DB0 DB1 DB2 DB3 DB4 DB5 (SCLK)DB6 C68 (SID)DB7 /RESET PS RW_/WR RS E_/RD CS2 /CS1 MPU INTERFACE CIRCUIT(PARALLEL & SERIAL) OSCILLATOR CLS HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 4. PAD CONFIGURATION 292 145 293 144 (0,0) SL09SL0111 Y HT0313A TOP VIEW X 320 117 1 116 Figure 4-1. Chip configuration Table 4-1. Pad dimensions ITEM Pad No. Chip size - Pad pitch Bumped pad size (Bottom) Bumped pad height 9540 2310 2~93, 95~115 70 118~143, 146~291, 294~319 60 1~2, 93~95, 115~116, 117~118 , 143~144, 145~146, 291~292, 293~294, 319~320 80 2~93, 95~115 50 102 118~143, 294~319 102 40 146~291 40 102 1, 94, 116, 145, 292 55 102 117, 144, 293, 320 102 55 Unit m 18 3 (Typ.) 108m 30m 30m 30m 42m 108m (-3960, 415) (3960, -305) Figure 4-3. ILB align key 42m 108m 60m 8 42m 108m 42m 30m 30m 30m 30m (3920, 425) Figure 4-2. COG align key TOMATO LSI Inc. Y All pad 30m 30m 30m (-3920, -305) Size X HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 4-1. PAD CENTER COORDINATES Table 4-2. Pad center coordinates PAD No. PAD name X Y [Unit: um] PAD No. PAD name X Y 1 DUMMY -4045 -991 51 VOUT -535 -991 2 FRS -3965 -991 52 VOUT -465 -991 3 M -3895 -991 53 VOUT -395 -991 4 CL -3825 -991 54 C3+ -325 -991 5 DISP -3755 -991 55 C3+ -255 -991 6 VSS -3685 -991 56 C3+ -185 -991 7 /CS1 -3615 -991 57 C3-115 -991 8 CS2 -3545 -991 58 C3-45 -991 9 VDD -3475 -991 59 C325 -991 10 /RESET -3405 -991 60 C1+ 95 -991 11 RS -3335 -991 61 C1+ 165 -991 12 VSS -3265 -991 62 C1+ 235 -991 13 RW_/WR -3195 -991 63 C1305 -991 14 E_/RD -3125 -991 64 C1375 -991 15 VDD -3055 -991 65 C1445 -991 16 DB0 -2985 -991 66 C2+ 515 -991 17 DB1 -2915 -991 67 C2+ 585 -991 18 DB2 -2845 -991 68 C2+ 655 -991 19 DB3 -2775 -991 69 C2725 -991 20 DB4 -2705 -991 70 C2795 -991 21 DB5 -2635 -991 71 C2865 -991 22 DB6 -2565 -991 72 VSS 935 -991 23 DB7 -2495 -991 73 VSS 1005 -991 24 VSS -2425 -991 74 VR 1075 -991 25 NC0 -2355 -991 75 VR 1145 -991 26 NC1 -2285 -991 76 V0 1215 -991 27 VDD -2215 -991 77 V0 1285 -991 28 DSEL0 -2145 -991 78 V1 1355 -991 29 DSEL1 -2075 -991 79 V1 1425 -991 30 VSS -2005 -991 80 V2 1495 -991 31 VDD -1935 -991 81 V2 1565 -991 32 MS -1865 -991 82 V3 1635 -991 33 CLS -1795 -991 83 V3 1705 -991 34 VSS -1725 -991 84 V4 1775 -991 35 C68 -1655 -991 85 V4 1845 -991 36 VDD -1585 -991 86 VSS 1915 -991 37 PS -1515 -991 87 VSS 1985 -991 38 VSS -1445 -991 88 /DC5 2055 -991 39 VSS -1375 -991 89 VDD 2125 -991 40 VSS -1305 -991 90 HPM 2195 -991 41 VSS -1235 -991 91 VSS 2265 -991 42 VSS -1165 -991 92 INTRS 2335 -991 43 VSS -1095 -991 93 VDD 2405 -991 44 VDD -1025 -991 94 DUMMY 2485 -991 45 VDD -955 -991 95 TEST0 2565 -991 46 VDD -885 -991 96 TEST1 2635 -991 47 VDD -815 -991 97 TEST2 2705 -991 48 VDD -745 -991 98 TEST3 2775 -991 49 VDD -675 -991 99 TEST4 2845 -991 50 VOUT -605 -991 100 TEST5 2915 -991 * 1. NC0, NC1: No Connection 2. Main VSS pad (PAD No. 38,39,40,41,42 and 43) have to be connected TOMATO LSI Inc. 9 PAD No. PAD name X Y 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 TEST6 TEST7 TEST8 TEST9 TEST10 TEST11 TEST12 TEST13 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 DUMMY DUMMY COMS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 DUMMY DUMMY COM25 COM26 COM27 COM28 COM29 2985 3055 3125 3195 3265 3335 3405 3475 3545 3615 3685 3755 3825 3895 3965 4045 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4430 4350 4290 4230 4170 4110 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -860 -780 -720 -660 -600 -540 -480 -420 -360 -300 -240 -180 -120 -60 0 60 120 180 240 300 360 420 480 540 600 660 720 800 991 991 991 991 991 991 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Table 4-2. Pad center coordinates (continued) Ver 0.0 [Unit: um] PAD No. Pad name X Y PAD No. Pad name X Y PAD No. PAD name X Y 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 COM30 COM31 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 4050 3990 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 COMS COM63 COM62 COM61 COM60 COM59 COM58 DUMMY DUMMY COM57 COM56 COM55 COM54 COM53 COM52 COM51 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 -3990 -4050 -4110 -4170 -4230 -4290 -4350 -4430 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 800 720 660 600 540 480 420 360 TOMATO LSI Inc. 10 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Table 4-2. Pad center coordinates (continued) PAD No. Pad name X Y 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 DUMMY -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 300 240 180 120 60 0 -60 -120 -180 -240 -300 -360 -420 -480 -540 -600 -660 -720 -780 -860 TOMATO LSI Inc. 11 PAD No. Pad name Ver 0.0 [Unit: um] X Y PAD No. PAD name X Y HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 5. PIN DESCRIPTION Table 5-1. Pin description Power supply Name I/O VDD Description Shared with the MPU power supply terminal VCC. Power supply VSS This is a 0V terminal connected to the system GND. Main VSS pad (PAD No. 38,39,40,41,42 and 43) have to be connected The voltage is determined by the LCD pixel impedance-converted for application by an operational amplifier. Voltage have the following relationship: V0 >V1>V2>V3>V4>VSS(GND) When the on-chip power circuit is active, these voltages are generated according to the state of LCD bias, as shown in the table below. V0 V1 V2 V3 V4 LCD Bias V1 V2 V3 V4 1/9 bias (8/9) x V0 (7/9) x V0 (2/9) x V0 (1/9) x V0 1/8 bias (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0 1/7 bias (6/7) x V0 (5/7) x V0 (2/7) x V0 (1/7) x V0 1/6 bias (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0 1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0 I/O LCD driver power supply Name I/O Description C1+ Capacitor1+ connect for the internal voltage converter C1- Capacitor1- connect for the internal voltage converter C2+ Capacitor2+ connect for the internal voltage converter O C2- Capacitor2- connect for the internal voltage converter C3+ Capacitor3+ connect for the internal voltage converter C3- Capacitor3- connect for the internal voltage converter VOUT I/O /DC5 I 5 times boosting circuit enable input pin. When this pin is low in 4 times boosting circuit the 5 times boosted voltage appears at VOUT. VR I V0 voltage adjustment pin. It is valid only when using external resistors.(INTRS="L") TOMATO LSI Inc. Voltage converter input / output pin 12 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Table 5-1. Pin description (continued) System control Name I/O Description Master/slave mode select input. Master makes some signals for display, and slave receives them. This for display synchronization. MS ="H": Master mode MS ="L": Slave mode MS I MS CLS OSC Circuit Power Supply CL M FRS DISP H Enable Enable Output Output Output Output L Disable Enable Input Output Output Output - Disable Disable Input Input Output Input H L Built-in oscillator circuit enables / disable select pin. CLS = "H": Enable CLS = "L": Disable (external display clock input to CL pin) CLS I CL I/O Display clock input / output pin. When HT0313A is used in master/slave mode(multi-chip), the CL pin must be connected to each other. M I/O LCD AC signal input / output pin. When HT0313A is used in master/slave mode(multi-chip), the M pin must be connected to each other. MS = "H": Output MS = "L": Input FRS O Static driver segment output. This pin is used together with the M pin. DISP I/O INTRS I HPM I LCD display blanking control input/output. When HT0313A is used in master/slave mode (multi-chip), the DISP pin must be connected to each other. MS = "H": Output MS = "L": Input Internal resistor selects pin. This pin selects the resistor for adjusting V0 voltage level and is available only in master mode. INTRS = "H": using built-in resistors. INTRS = "L": not using built-in resistors. V0 voltage is controlled by VR pin with external resistive divider. Power control pins of the power supply circuit for the LCD driver. HPM = "H": High power mode. HPM = "L": Normal mode This pin is available only in the master mode. The LCD driver duty ratio depends on the following table. DSEL1 DSEL0 TOMATO LSI Inc. DSEL1 DSEL0 Duty ratio L L 1/33 L H 1/49 H H/L 1/65 I 13 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Table 5-1. Pin description (continued) MPU interface Name I/O /RESET I Description Hardware reset input pin. When /RESET is "L", initialization is executed. Parallel/Serial select input pin. PS PS Operating mode Chip select Data/ Instruction H Parallel /CS1, CS2 RS DB7 to DB0 L Serial /CS1, CS2 RS DB7 (SID) I Read/ Write Serial E_/RD, RW_/WR - Write only DB6 (SCLK) Data I/O When PS= "L", DB5 to DB0 are high impedance. E_/RD and RW_/WR are fixed to either "H" or "L". With serial data input, RAM display data reading is not supported. This pin is the MPU interface switch terminal. C68 = "H": 6800 series MPU interface C68 = "L": 8080 series MPU interface C68 I /CS1 CS2 I Chip select input pin. Data input/output is enables only when /CS1 is low and CS2 is high. When chip select is non-active, DB7 to DB0 will be high impedance. RS I Register select input pin. RS = "H": The data on DB7 to DB0 is used the display data. RS = "L": The data on DB7 to DB0 is used the control data. RW_/WR I E_/RD I When interfacing to a 6800-series MPU, read/write is enabled at; RW_/WR = "H": read RW_/WR = "L": write When interfacing to an 8080-series MPU, RW_/WR is enabled at low. The signals on the data bus are latched at the rising edge of the RW_/WR signal. When interfacing to a 6800-series MPU: Active High. This pin is used as an enable clock input pin of the 6800-series MPU. When interfacing to a 8080-series MPU: Active Low. This pin is connected to the RD signal of the 8080-series MPU. While this signal is Low, HT0313A data bus output is enabled. DB7 to DB0 I/O 8-bit bi-directional data bus. It is connected to the standard 8-bit microprocessor data bus. In case of serial interface,(PS = "L") DB7: Serial input data(SID) DB6: Serial input clock(SCLK) DB5 to DB0 : High impedance When chip select is not active, DB7 to DB0 will be high impedance. NC1 NC0 I/O These are set to Open. TEST20 to TEST0 I/O These are pins for IC chip testing. These are set to Open. TOMATO LSI Inc. 14 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Table 5-1. Pin description (continued) LCD driver output Name I/O Description LCD driver output for segment. The display data and the M signal control the output voltage of segment driver. Segment output voltage Display data SEG0 to SEG131 O M Normal Display Reverse Display H H V0 V2 H L VSS V3 L H V2 V0 L L V3 VSS Power save mode VSS LCD driver output for common. The internal scanning data and M signal control the output voltage of common driver. COM0 to COM63 O Scan data M Common output voltage H H VSS H L V0 L H V1 L L V4 Power save mode COMS O Common signal output for the icons. The output signals of two pins are the same. When this signal is not used, should be left open. In multi-chip(master/slave) mode, all COMS pin on both master and slave units are the same signal. Note: -. DUMMY, TEST0 ~ TEST20, NC0, NC1: The pins should be opened(floated). TOMATO LSI Inc. VSS 15 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6. FUNCTIONAL DESCRIPTION 6-1. MICROPROCESSOR INTERFACE a. Chip select input There are /CS1 and CS2 pins for chip selection. The HT0313A can interface with an MPU only when /CS1 is "L" and CS2 is "H". When these pins are set to any other combination, RS, E_/RD, and RW_/WR inputs are disabled and DB7 to DB0 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. b. Interface HT0313A has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 6-1. Table 6-1. Parallel / Serial interface mode PS Type /CS1 CS2 H Parallel /CS1 CS2 L Serial /CS1 CS2 C68 Interface mode H 6800-series MPU mode L 8080-series MPU mode X* Serial MPU mode X : Don't care c. Parallel interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as shown in table 6-2. The type of data transfer is determined by signals at RS, E_/RD, and RW_/WR as shown in table 6-3. Table 6-2. Microprocessor selection for parallel interface C68 /CS1 CS2 RS E_/RD RW_/WR DB7 to DB0 MPU H /CS1 CS2 RS E RW DB7 to DB0 6800-series L /CS1 CS2 RS /RD /WR DB7 to DB0 8080-series Table 6-3. Parallel data transfer Common 6800-series RS E_/RD (E) RW_/WR H 8080-series Description (RW) E_/RD (/RD) RW_/WR (/WR) H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register(instruction) TOMATO LSI Inc. 16 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 d. Serial interface (PS = "L") When the HT0313A is active and serial interface has been selected, the serial data (DB7) and the serial clock (DB6) inputs are enabled. And HT0313A is not active, the internal 8-bit shift register and the 3-bit counter are reset. The serial data can be read on the rising edge of the serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. The serial data input is display data when RS is high and control data when RS is low. Reading is not possible while serial interface mode is activated. /CS1 CS2 SID (DB7) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 SCLK (DB6) RS Figure 6-1. Serial interface timing e. Busy flag The busy flag indicates whether the HT0313A is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the MPU needs not to check this flag before each instruction, which improves the MPU performance. TOMATO LSI Inc. 17 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 f. Data accessing The HT0313A uses bus holder and internal data bus for data read and data write with the MPU. When writing data from the MPU to on-chip RAM, the data is automatically transferred from the bus holder to the on-chip RAM as shown in figure 6-2. When the MPU reads data from on-chip RAM, the first data read cycle stores the data in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 6-3. This means the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. Therefore, a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Internal signals MPU signals RS /WR DB7 to DB0 N D(N) D(N+1) D(N+2) D(N+3) D(N+4) N D(N) D(N+1) D(N+2) D(N+3) D(N+4) /WR Bus Holder Column Address N N+1 N+2 N+3 N+4 Figure 6-2. Write timing MPU signals RS /WR /RD DB7 to DB0 N Dummy D(N) D(N+1) D(N+2) D(N+3) Internal signals /WR /RD Bus Holder N Column Address D(N) N N+1 D(N+1) N+2 Figure 6-3. Read timing TOMATO LSI Inc. 18 D(N+2) D(N+3) N+3 N+4 D(N+4) N+5 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6-2. DISPLAY DATA RAM (DDRAM) a. DDRAM The DDRAM stores pixel data for the LCD. It has 65-row (8 page x 8 bit + 1) by 132-column addressable array. Each pixel can be selected by specifying the page and the column address. The 65 rows are divided into 8 pages of 8 lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the MPU correspond to the LCD common direction as shown in Figure 6-4. The MPU can read from and write to DDRAM through the I/O buffer, which is independent operation from signal reading for the LCD driver. This independent operation makes it possible that the MPU writes the data into the DDRAM at the same time as data is being displayed without causing the LCD flicker. DB0 0 1 1 ...... 0 COM0 ...... DB1 1 0 0 ...... 1 COM1 ...... DB2 1 1 1 ...... 0 COM2 ...... DB3 0 0 1 ...... 1 COM3 ...... DB4 1 1 0 ...... 0 COM4 ...... Display data RAM LCD display Figure 6-4. RAM-to-LCD data transfer b. Page address circuit This circuit is for providing a page address to DDRAM shown in figure 6-6. The 4-bit page address register changed by only the "Set page" instruction. Page address 8 (DB3, DB2, DB1, DB0 = 1, 0, 0, 0) is a special RAM area for the icons and display data DB0 is only valid. c. Column address circuit Column address circuit has a 8-bit preset counter that provides column address to the DDRAM as shown in figure 6-6. When the "Set column address MSB / LSB" instruction is issued, 8-bit [Y7:Y0] is updated. And this address is increased by +1 each display data Read/Write instruction. This allows that the MPU display data can be accessed continuously. The increment of the column address stops with 83H. And the counter is not increased and locked if the address is specified over 84H. It is unlocked if a column address is set again by "Set column address MSB / LSB" instruction. The column address counter is independent of the page address register. The ADC select instruction makes it possible to convert the relationship between the column address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing the ADC select instruction. Refer to the figure 6-5. TOMATO LSI Inc. 19 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 SEG OUTPUT SEG0 SEG1 SEG2 SEG4 ......... SEG128 SEG129 SEG130 SEG131 Column address[Y7:Y0] 00H 01H 02H 04H ......... 80H 81H 82H 83H Display data 1 0 1 1 0 1 0 1 LCD panel display (ADC = 0) LCD panel display (ADC = 1) Figure 6-5. The relationship between the column address and the segment outputs d. Line address circuit This circuit assigns DDRAM a line address corresponding to the first line (COM0) of the display. Using the display start line address set command, what is normally the top line of the display can be specified. By setting the line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of DDRAM as shown in figure 6-6. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by +1 and the line address is generated for transferring the 132-bit RAM data to the display data latch circuit. However, the display data of icons is not scrolled because the MPU can not access the line address of icons. e. Segment control circuit This circuit controls the display data by the Display ON / OFF, reverse display ON / OFF and entire display ON /OFF instructions without changing the data in the DDRAM. TOMATO LSI Inc. 20 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 Column address ADC = 0 ADC = 1 LCD output Page 4 Page 5 Page 6 Page 7 Page 8 00 01 02 03 04 05 06 .............. 7B 7C 7D 7E 7F 80 81 83 83 82 81 80 7F 7E 7D ............. 08 07 06 05 03 02 01 00 .............. Figure 6-6. Display data RAM map TOMATO LSI Inc. 21 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS 1/49 DUTY 1 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH START 0 Page 3 COM output 1/33 DUTY 1 SEG131 1 SEG130 0 SEG129 0 SEG128 0 SEG127 1 SEG126 0 SEG125 0 Page 1 SEG124 1 SEG6 0 SEG5 0 SEG4 0 Page 0 SEG3 0 SEG2 0 SEG1 0 SEG0 0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 Line address 1/65 DUTY Page address data DB3 DB2 DB1 DB0 Ver 0.0 When the initial display line address is 1CH HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6-3. LCD DISPLAY CIRCUITS a. Oscillator HT0313A implement complete on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in the voltage converter and display timing generation circuit. The oscillator circuit is enabled when MS="H" and CLS="H". When the external clock is used, set CLS="L" and imply clock signal to CL pin. b. Display timing generator circuit This circuit generates timing signals to be used for displaying LCD. The display clock (CL) is generated by oscillation clock and CL generates the clock for the line counter and the signal for the display data latch. The line address of DDRAM is generated in synchronization with CL. The 132-bit display data is latched in the display data latch circuit synchronized with CL. Reading to the display data liquid crystal driver circuit is completely independent of access to the DDRAM by the MPU. The display timing generator circuit generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. Driving 2-frame AC driver waveform and internal timing signal are shown in figure 6-7. When HT0313A is used multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 6-4 shows the M, CL, and DISP status. Table 6-4. Master and slave timing signal status Operation mode Clock MS CLS M CL DISP Internal H H Output Output Output External H L Output Input Output Internal L H Input Input Input External L L Input Input Input Master mode Slave mode 64 65 1 2 3 4 5 6 7 8 9 10 ............... 57 58 59 60 61 62 63 64 65 1 2 3 4 CL M V0 V1 V2 V3 V4 VSS COM0 V0 V1 V2 V3 V4 VSS COM1 V0 V1 V2 V3 V4 VSS SEGn Figure 6-7. 2-frame AC driving waveform (Duty ratio = 1/65) TOMATO LSI Inc. 22 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 c. Common output control circuit This circuit controls the relationship between the number of common output and specified duty ratio. SHL select instruction specifies the scanning direction of the common output pins. Table 6-5. The relationship between duty ratio and common output Common output pins Duty SHL COM[0:15] COM[16:23] COM[24:39] COM[40:47] COM[48:63] L COM[0:15] Open COM[16:31] H COM[31:16] Open COM[15:0] 1/33 COMS COMS L COM[0:23] Open COM[24:47] H COM[47:24] Open COM[23:0] 1/49 COMS L COM[0:63] 1/65 COMS H COM[63:0] 6-4. LCD DRIVER CIRCUIT This driver circuit is configured by 66-channel common drivers (including 2 COMS channels) and 132channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal. VDD M VSS COM0 COM1 COM0 COM2 COM3 COM4 COM1 COM5 COM6 COM7 COM2 COM8 COM9 SEG0 COM10 COM11 COM12 SEG1 COM13 COM14 SEG2 SEG4 SEG3 SEG2 SEG1 SEG0 COM15 Figure 6-8. Segment and common timing TOMATO LSI Inc. 23 V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6-5. POWER SUPPLY CIRCUITS The power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For details, refers to "Instruction description". Table 6-6 shows the referenced combinations in using power supply circuits. Table 6-6. Recommended power supply combinations VC,VR,VF Voltage converter Voltage regulator Voltage follower VOUT V0 V1 to V4 All Internal power supply 1, 1, 1 ON ON ON Open Open Open Voltage regulator and voltage follower 0, 1, 1 OFF ON ON External input Open Open Voltage follower 0 , 0, 1 OFF OFF ON Open External input Open All external power supply 0, 0, 0 OFF OFF OFF Open External input External input Mode Settings TOMATO LSI Inc. 24 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 a. Voltage converter circuits These circuits boost up the electric potential between VDD and VSS to 2, 3, 4 or 5 times toward positive side and boosted voltage is outputted from VOUT pin. (C1 = 1.0 to 4.7F) VDD VDD C1 VDD C1 VDD VOUT VOUT C3+ C3+ C3- C3- C2+ C2+ C1 C2C2- C1 C1+ VOUT = 3 x VDD C1+ HT0313A C1- VOUT = 2 x VDD HT0313A C1 C1- VDD VDD VDD VSS /DC5 VSS GND VDD VSS /DC5 GND Figure 6-9. Two times boosting circuit Figure 6-10. Three times boosting circuit VDD VDD C1 C1 VDD VDD VOUT VOUT C3+ C3+ C1 C1 C3- C3- VOUT = 5 x VDD C2+ C2+ C1 C1 C2- C2- VOUT = 4 x VDD C1+ C1+ HT0313A VSS C1 HT0313A C1- C1 C1- VDD VDD VDD VSS /DC5 VSS GND GND Figure 6-11. Four times boosting circuit TOMATO LSI Inc. VSS 25 /DC5 VSS GND Figure 6-12. Five times boosting circuit HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 b. Voltage regulator circuits The function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, V0, by the adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits as shown in figure 6-13, it is necessary to be applied internally or externally. For the equation 1, we determine V0 with Ra, Rb and VEV. Ra and Rb are connected internally or externally via INTRS pin. The voltage of electronic volume, VEV, is determined by equation 2, where the reference voltage parameter is the value selected by instruction, "Set reference voltage register", within the range 0 to 63. Refer to table 6-7. VREF voltage at TOPR =25C is 2.0V 3%. Rb V0 = ( 1 + ) x VEV [V] ------ (Equation 1) Ra ( 63- ) ) x VREF [V] ------ (Equation 2) VEV = (1 300 Table 6-7. Electronic contrast control register (Reference Voltage Parameter : , 64step) Reference Voltage V0 Contrast SV5 SV4 SV3 SV2 SV1 SV0 Parameter ( ) Low Minimum 0 0 0 0 0 0 0 : : : : 0 0 0 0 0 1 1 : : : : : : : : : : : : : : : : : : : : : : 1 0 0 0 0 0 32 (default) : : : : : : : : : : : : : : : : : : : : 1 1 1 1 1 0 62 : : : : 1 1 1 1 1 1 63 High Maximum TOMATO LSI Inc. 26 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 VOUT + V0 - VEV Rb VR Ra VSS GND Figure 6-13. Internal voltage regulator circuit TOMATO LSI Inc. 27 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 b-1. In case of using internal resistors, Ra and Rb (INTRS = "H") When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator resistor select" and "Set reference voltage". Table 6-8. Internal Rb / Ra ratio depending on 3-bit Data (R2, R1, R0) 3-bit data settings (R2 R1 R0: gain) 1+(Rb/Ra) 000 001 010 011 100 101 110 111 1.90 2.19 2.55 3.02 3.61 4.35 5.29 6.48 The following figure shows V0 voltage measured by adjusting internal regulator resistor ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 C. 14 gain 111 12 gain 110 gain 101 10 gain 100 gain 011 gain 010 8 gain 001 V0[V] gain 000 6 4 2 0 0 5 10 15 20 25 30 35 40 45 50 Electronic volum e level Figure 6-14. Electronic volume level TOMATO LSI Inc. 28 55 60 63 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 b-2. In case of using external resistors, Ra and Rb. (INTRS = "L") When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. Example: For the following requirements 1. LCD driver voltage, V0 = 10V 2. 6-bit reference voltage register = ( 1, 0, 0, 0, 0, 0 : = 32 ) 3. Maximum current flowing Ra, Rb = 1[A] From equation 1 Rb 10 = ( 1 ++ Ra ) x VEV [V] ------ (Equation 3) From equation 2 (63-32) ) x 2.0 = 1.79 [V] ------ (Equation 4) VEV = ( 1 - 300 From equation 3 10 ( Ra + Rb ) = 1[A] ------ (Equation 5) From equation 3,4 and 5 Ra = 1.79[M] Rb = 8.21[M] The following table shows the range of V0 depending on the above requirements. Table 6-9. V0 depending on electronic volume level Electric Volume Level V0 TOMATO LSI Inc. 0 ------ 32 ------- 63 8.83 ------ 10.00 ------- 11.17 29 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 c. Voltage follower circuits VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4) and those output impedance are converted by the voltage follower for increasing drive capability. The following table shows the relationship between V1 to V4 level and each duty ratio. Table 6-10. The relationship between V1 to V4 level and duty ratio Duty Ratio DSEL1 DSEL0 1/33 L L 1/49 1/65 L LCD Bias V1 V2 V3 V4 1/5 (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0 1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0 1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0 1/8 (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0 1/7 (6/7) x V0 (5/7) x V0 (2/7) x V0 (1/7) x V0 1/9 (8/9) x V0 (7/9) x V0 (2/9) x V0 (1/9) x V0 H H H/L d. High power mode The power supply circuit equipped in the HT0313A for LCD drive has very low power consumption (in normal mode : HPM = "L"). If use for LCD panels with large loads, this low-power supply may cause display quality to degrade. When this occurs, setting the HPM pin to "H"(high power mode) can improve the quality of the display. Moreover, if the quality of display is inadequate even after High Power mode has been set, then it is necessary to add a liquid crystal drive power supply externally (VOUT or V0 or V1, V2, V3, V4). TOMATO LSI Inc. 30 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6-6. REFERECE CIRCUIT EXAMPLS When using internal regulator resistors. When not using internal regulator resistors. VDD VDD VDD C1 MS VDD VOUT Ra C3+ VR C3C2 C2 C2+ C1 V1 C2 V3 C2 C1- V4 VSS GND VDD C2+ C1 V1 C2- V2 C1+ C1 C3V0 C2 C2 HT0313A C1 Rb C2- V2 C2 C3+ VR C1 C2 V0 C1 MS VOUT C2 V3 C2 HT0313A VSS GND GND C1 C1- V4 /DC5 INTRS C1+ VDD /DC5 INTRS GND GND Figure 6-15. When using all LCD power circuits (4-time, V/C: ON, V/R: ON, V/F: ON) When using internal regulator resistors. When not using internal regulator resistors. VDD VDD VDD VDD MS VOUT C3+ VR V0 C2 C2 GND C2- V2 C2 V3 C2 HT0313A VSS GND GND C2 C2 C1+ C1- V4 C3+ VR C2 C2+ V1 Ra Rb C3C2 MS VOUT External Power Supply C2 VDD C2 /DC5 INTRS C3V0 C2+ V1 C2- V2 V3 HT0313A C1+ C1- V4 VSS GND External Power Supply VDD /DC5 INTRS GND Figure 6-16. When using some LCD power circuits (V/C: OFF, V/R: ON, V/F: ON) TOMATO LSI Inc. 31 GND HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 VDD VDD External Power Supply MS VOUT C3+ VR C3C2 V0 C2 C2+ V1 C2 C2- V2 C2 V3 C2 HT0313A C1+ VDD C1- V4 VSS /DC5 INTRS GND GND Figure 6-17. When using some LCD power circuits (V/C: OFF, V/R: OFF, V/F: ON) VDD VDD MS VOUT C3+ VR Value of external capacitance C3- V0 V1 External Power Supply Item C1 C2 C2+ C2- V2 HT0313A V3 VSS GND Unit F C1+ C1- V4 Value 1.0 ~ 4.7 0.47 ~ 1.0 VDD /DC5 INTRS GND Figure 6-18. When not using any LCD power supply circuits (V/C: OFF, V/R: OFF, V/F: OFF) TOMATO LSI Inc. 32 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6-7. RESET CIRCUIT Setting /RESET to "L" or reset instruction can initialize internal function. When /RESET becomes "L", following procedure is occurred. Display ON / OFF: OFF (DON = 0). Entire display ON / OFF: OFF (normal = 0). ADC select: OFF (normal = 0) Reverse display ON / OFF: OFF (normal = 0). Power control register (VC, VR, VF) = (0, 0, 0) LCD power supply bias ratio: bias bit 0 (Refer to LCD bias select of instruction table and duty ratio by DSEL1, DSEL0 pin setting) Liquid crystal bias Duty ratio DSEL1 DSEL0 Bias = 0 Bias = 1 1/33 0 0 1/5 1/6 1/49 0 1 1/6 1/8 1/65 1 1/0 1/7 1/9 On-chip oscillator OFF (while /RESET is "L") Set modify read: OFF. SHL select: OFF (normal = 0). Static indicator mode: OFF. Static indicator register: (S1, S0) = (0, 0) Display start line: 0 (first) Column address: 0. Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) When RESET instruction is issued, following procedure is occurred. Set modify read: OFF Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) SHL select: OFF (normal = 0) Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) While /RESET is "L", or Reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB4. After DB4 becomes "L", any instruction can be accepted. /RESET must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by /RESET is essential before used. TOMATO LSI Inc. 33 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7. PROGRAM INSTRUCTION DESCRIPTION Table 7-1. Instruction Table X DB7 RS RW Read display data 1 1 Read data Read data from DDRAM Write display data 1 0 Write data Write data into DDRAM Read status 0 1 Busy DB6 ADC DB5 ON / OFF DB4 /RESET DB3 : Don't care Instruction 0 DB2 0 DB1 0 DB0 Description 0 Read the internal status Display ON / OFF 0 0 1 0 1 0 1 1 1 DON Turn ON / OFF LCD panel When DON = 0: display OFF When DON=1 : display ON Initial display line 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 Specify DDRAM line for COM0 Set reference voltage mode 0 0 1 0 0 0 0 0 0 1 Set reference voltage mode Set reference voltage register 0 0 X X SV5 SV4 SV3 SV2 SV1 SV0 Set reference voltage register Set page address 0 0 1 0 1 1 P3 P2 P1 P0 Set page address Set column address MSB 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set column address MSB Set column address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Set column address LSB Select SEG output direction. When ADC = 0 : normal direction ADC select 0 0 1 0 1 0 0 0 0 ADC (SEG0 SEG131) When ADC = 1 ; reverse direction (SEG131 SEG0) Reverse display ON / OFF 0 0 1 0 1 0 0 1 1 REV Select normal / reverse display When REV = 0 : normal display When REV = 1 : reverse display Entire display ON / OFF 0 0 1 0 1 0 0 1 0 EON Select normal / entire display ON When EON = 0 : normal display When EON = 1 : entire display ON LCD bias select 0 0 1 0 1 0 0 0 1 BIAS Select LCD bias Set modify-read 0 0 1 1 1 0 0 0 0 0 Set modify-read mode Reset modify-read 0 0 1 1 1 0 1 1 1 0 Reset modify-read mode Reset 0 0 1 1 1 0 0 0 1 0 Initialize the internal function Select COM output direction When SHL = 0 : normal direction SHL select 0 0 1 1 0 0 SHL X X X (COM0 COM63) When SHL = 1 : reverse direction (COM63 COM0) Power control 0 0 0 0 1 0 1 VC VF Control power circuit operation R1 R0 Select internal resistance ratio of the regulator resistor 1 0 SM Set static indicator mode X S1 S0 Set static indicator register Regulator resistor select 0 0 0 0 1 0 0 R2 Set static indicator mode 0 0 1 0 1 0 1 Set static indicator register 0 0 X X X X X VR Power save - - - - - - - - - - Compound instruction of display OFF and entire display ON Test instruction 0 0 1 1 1 1 X X X X Don't use this instruction. TOMATO LSI Inc. 34 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-1. Read display data The 8-bit data from DDRAM specified by the column address and the page address can be read by this instruction. As the column address is increased by 1 automatically after each this instruction, the MPU can continuously read the data from the addressed page. A dummy read is required after loading an address into the column address register. Display data cannot be read through the serial interface. RS RW 1 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read data 7-2. Write display data 8-bit data of display data from the MPU can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. RS RW 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write data Set page address Set page address Set column address Set column address Dummy data read Data write Column = Column + 1 Data read Column = Column + 1 YES Column = Column + 1 Data write continue? Data read continue? YES NO NO Optional status Figure 7-1. Sequence for writing display data TOMATO LSI Inc. 35 Optional status Figure 7-2. Sequence for reading display data HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-3. Read status Indicates the internal status of the HT0313A. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY ADL ON/OFF /RESET 0 0 0 0 Flag Description BUSY The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy. ADC Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG131 ->SEG0), 1: normal direction (SEG0 ->SEG131) -> -> ON / OFF Indicates display ON / OFF status. 0: display ON, 1: display OFF /RESET Indicate the /RESET. 7-4. Display ON / OFF Turns the display ON or OFF RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 1 DON DON = 1: display ON DON = 0: display OFF 7-5. Initial Display Line Sets the line address of DDRAM to determine the initial display line. The RAM display data is displayed at the top row (COM0 when SHL = L, COM63 when SHL = H) of LCD panel. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 ST5 ST4 ST3 ST2 ST1 ST0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 TOMATO LSI Inc. 36 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-6. Reference voltage select Consists of 2-byte instruction the first instruction sets reference voltage mode, the second one updates the contents of reference voltage register. After second instruction, reference voltage mode is released. The first instruction: Set reference voltage select mode RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 0 0 0 0 1 The second instruction: Set reference voltages select mode RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 X X SV5 SV4 SV3 SV2 SV1 SV0 SV5 SV4 SV3 SV2 SV1 SV0 Reference voltage parameter ( ) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 0 0 0 0 0 32 (default) : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 Setting reference voltage start First instruction for mode setting Second instruction for register setting Setting reference voltage end Figure 7-3. Sequence for setting the reference voltage TOMATO LSI Inc. 37 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-7. Set page address Sets the page address of DDRAM from the MPU into the page address register. Any RAM data bit can be accessed when its page address and column address are specified. Along with the column address, the page address defines the address of the DDRAM to write or read display data. Changing the page address doesn't effect to the display status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 P3 P2 P1 P0 P3 P2 P1 P0 Page 0 0 0 0 0 0 0 0 0 1 : : : : : 0 1 1 1 7 1 0 0 0 8 7-8. Set column address Sets the column address of DDRAM from the MPU into the column address register. Along with the column address, the column address defines the address of the DDRAM to write or read display data. When the MPU reads or writes display data to or from DDRAM, column addresses are automatically increased. Set column address MSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set column address LSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131 TOMATO LSI Inc. 38 : HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-9. ADC select Changes the relationship between DDRAM column address and segment driver. The direction of segment driver output pin can be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 0 ADC ADC = 0: normal direction (SEG0 SEG131) ADC = 1: reverse direction (SEG131 SEG0) 7-10. Reverse display ON / OFF Reverses the display status on LCD panel without rewriting the contents of the DDRAM. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 1 REV REV RAM bit data = "1" RAM bit data = "0" 0(Normal) Liquid crystal pixel is illuminated Liquid crystal pixel is not illuminated 1(Reversed) Liquid crystal pixel is not illuminated Liquid crystal pixel is illuminated 7-11. Entire display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the DDRAM. At this time, the contents of the DDRAM are held. This instruction has priority over the reverse display ON / OFF instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 0 EON EON = 0: normal display EON = 1: entire display ON 7-12. Select LCD bias Selects LCD bias ratio of the voltage required for driving the LCD. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 1 Bias Liquid crystal bias Duty ratio DSEL1 DSEL0 Bias = 0 Bias = 1 1/33 0 0 1/5 1/6 1/49 0 1 1/6 1/8 1/65 1 1/0 1/7 1/9 TOMATO LSI Inc. 39 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-13. Set modify-read This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of the MPU when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset modify-read instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 0 0 7-14. Reset modify-read This instruction cancels the modify-read mode, and makes the column address return to its initial value just before the set modify-read instruction is started. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 1 1 1 0 Set page address Set colum n address(N) Set m odify-read Dummy read Data read Data write NO Change com plete ? YES Reset m odify-read Return colum n address(N) TOMATO LSI Inc. 40 Data process HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Figure 7-4. Sequence for cursor display 7-15. Reset This instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affects the contents of DDRAM. This instruction can not initialize the LCD power supply which is initialized by the /RESET pin. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 0 7-16. SHL select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 SHL X X X SHL = 0: normal direction (COM0 COM63) SHL = 1: reverse direction (COM63 COM0) X : Don't care 7-17. Power control Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 VC VR VF VC VR VF Voltage converter circuit is OFF Voltage converter circuit is ON 0 1 Voltage regulator circuit is OFF Voltage regulator circuit is ON 0 1 Voltage follower circuit is OFF Voltage Follower circuit is ON 0 1 TOMATO LSI Inc. Internal power supply circuits status 41 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-18. Regulator resistor select Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the table 6-8. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 R2 R1 R0 R2 R1 R0 0 0 0 1.90 0 0 1 2.19 0 1 0 2.55 0 1 1 3.02 1 0 0 3.61 1 0 1 4.35 1 1 0 5.29 1 1 1 6.48 Value of ( 1+ Rb/Ra ) 7-19. Set static indicator state Consists of two bytes instruction. The first byte instruction (set static indicator mode) enables the second byte instruction (set static indicator register) to be valid. The first byte sets the static indicator ON / OFF. When it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this static indicator state is released after setting the data of indicator register. The first instruction: Set static indicator mode (ON / OFF) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 0 SM SM = 0: static indicator OFF SM = 1: static indicator ON The second instruction: Set static indicator register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 X X X X X X S1 S0 S1 S0 Static indicator output status 0 0 OFF 0 1 ON ( 1 second blinking) 1 0 ON ( 0.5 second blinking) TOMATO LSI Inc. 42 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD 1 1 Ver 0.0 ON ( always ON) 7-20. Power save (Compound instruction). If the entire display ON / OFF instruction is issued during the display OFF state, HT0313A enters the power save status to reduce the power consumption to the static power consumption value. According to the status of static indicator mode, power save is entered to one of two modes (sleep and standby mode). When static indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power save mode is released by the display ON and entire display OFF instruction. Static indicator OFF Static indicator ON Power save(Compound instruction) [Display OFF] [Entire display ON] Sleep Sleepmode mode Standby Standby mode mode [Oscillator [Oscillator circuit: circuit: OFF] OFF] [LCD [LCDpower power supply supply circuit:OFF] circuit:OFF] [All [All COM/SEG COM/SEG:: VSS] VSS] [Consumption [Consumption current: current: <2A> <2A> [Oscillator [Oscillator circuit: circuit: ON] ON] [LCD [LCD power power supply supply circuit:OFF] circuit:OFF] [All [All COM/SEG COM/SEG:: VSS] VSS] [Consumption [Consumption current: current: <10A> <10A> Power save OFF(Compound instruction) [Entire display OFF] [Static indicator ON] [Display ON] Power save OFF(Compound instruction) [Entire display OFF] [Display ON] Release Releasesleep sleep mode mode Release Releasestandby standby mode mode Figure 7-5. Power save routine TOMATO LSI Inc. 43 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD 7-21. Referential instruction setup flow (1) U ser system setup by external pins SStart tart of of initialization initialization P ow er O N (V D D -VS S)keeping the /R ES E T Pin = "L" W aiting for stabilizing the pow er /R E SE T P in = "H " U ser application setup by internal instructions [A D C select] [S H L select] [LC D bias select] U ser LC D pow er setup by internal instructions [V oltage converter O N ] W aiting for >1m s U ser LC D pow er setup by internal instructions [V oltage regulator O N ] W aiting for >1m s U ser LC D pow er setup by internal instructions [V oltage follow er O N ] U ser LC D pow er setup by internal instructions [R egulator resistor select] [R eference voltage register set] W aiting for stabilizing the LC D pow er levels EEnd nd of of in initialization itialization TOMATO LSI Inc. 44 Ver 0.0 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Figure 7-6. Initializing with the built-in power supply circuits Referential instruction setup flow (2) User system setup by external pins Start Start of of initialization initialization Power On(VDD-VSS)keeping the /RESET Pin = "L" Waiting for stabilizing the power /RESET Pin = "H" Set power save User application setup by internal instructions [ADC select] [SHL select] [LCD bias select] User LCD power setup by internal instructions [Regulator resistor select] [Reference voltage register set] Release power save Waiting for stabilizing the LCD power levels End End of of initialization initialization TOMATO LSI Inc. 45 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Figure 7-7. Initializing without the built -in power supply circuits Referential Instruction Setup Flow (3) End End of of initialization initialization DDRAM address by instruction [initial display line] [Set page address] [Set column address] Write display data by instruction [Display data write] Turn display ON/OFF by instruction [Display ON/OFF] End End of of data data display display Figure 7-8. Data display TOMATO LSI Inc. 46 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Referential instruction setup flow (4) Optional Optional status status Turn display ON/OFF by instruction [Display OFF] User LCD power setup by internal instructions [Voltage regulator OFF] Waiting for >50ms User LCD power setup by internal instructions [Voltage follower OFF] Waiting for >1ms User LCD power setup by internal instructions [Voltage converter OFF] Waiting for >1ms Power Power OFF(VDD OFF(VDD -- VSS) VSS) Figure 7-9. Power off. TOMATO LSI Inc. 47 Ver 0.0 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 8. SPECIFICATIONS 8-1. Absolute maximum ratings Table 8-1. Absolute maximum ratings Parameter Symbol Rating Unit VDD -0.3 to +7.0 VLCD -0.3 to +17.0 Input voltage range VIN -0.3 to VDD +0.3 Operating temperature range TOPR -40 to +85 Supply voltage range V o Storage temperature range TSTR C -55 to +125 Notes: 1. VDD and VLCD are based on VSS = 0V. 2. Voltages V0 >V1>V2>V3>V4>VSS(GND) must always be satisfied.(VLCD = V0 - VSS) 3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result. 8-2. DC Characteristics o Table 8-2. DC characteristics ( VSS = 0V, VDD = 2.4V to 5.5V, Ta = -40 to +85 C) Item Symbol Operating voltage(1) Typ Max VDD 2.4 - 5.5 VDD *1 Operating voltage(2) V0 4.0 - 15.0 V0 *2 High VIH 0.8VDD - VDD Low VIL VSS - 0.2VDD High VOH IOH=-0.5mA 0.8VDD - VDD Low VOL IOL=0.5mA VSS - 0.2VDD -1.0 - +1.0 -3.0 - +3.0 - 2.0 3.0 17 22 27 4.25 5.50 6.75 20 25 30 3.33 4.17 5.00 Output voltage V IIL Output leakage current IOZ LCD driver ON resistance RON Oscillator frequency(2) TOMATO LSI Inc. *3 *4 Input leakage current Oscillator frequency(1) Unit Pin Used Min Input voltage Condition VIN=VDD or VSS VIN=VDD or VSS A *6 o Internal fOSC External fCL Internal fOSC External fCL 48 Ta = 25 C V0 = 8V o Ta = 25 C Duty ratio = 1/65 o Ta = 25 C Duty ratio = 1/49 *5 k COMn SEGn *7 CL*8 kHz CL*8 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 o Table 8-2. DC Characteristics (Continued) ( VSS = 0V, VDD = 2.4V to 5.5V, Ta = -40 to +85 C) Item Symbol Condition Min Typ Max x2 2.4 - 5.5 x3 2.4 5.0 x4 2.4 3.75 x5 2.4 3.0 Unit Pin Used V VDD % VOUT Voltage converter/regulator/follower Voltage converter input voltage VDD Voltage converter output voltage VOUT x2/x3/x4/x5 voltage conversion (no-load) 95 99 - Voltage regulator operating voltage VOUT - 4.0 - 15.0 Voltage follower operating voltage V0 - 4.0 - 15.0 Reference voltage VREF Ta = 25 C o -0.2%/ C 1.94 2.0 2.06 VOUT V V0*9 o *10 o Table 8-2. DC Characteristics (Continued) ( VSS = 0V, VDD = 2.4V to 5.5V, Ta = -40 to +85 C) Dynamic current consumption (1): Built-in circuit OFF (At operating mode) Dynamic current consumption (1) IDD1 VDD = 3.0V, V0 - VSS= 11.0V, 1/65 duty ratio, display pattern OFF - - 20 A *11 Dynamic Current Consumption (2): Built-in circuit ON (At operating mode) Dynamic current consumption (2) IDD2 VDD = 3.0V, Quad boosting, V0 - VSS= 11.0V, 1/65 duty ratio, display pattern OFF, normal power mode VDD = 3.0V, Quad boosting, V0 - VSS= 11.0V, 1/65 duty ratio, display pattern check, normal power mode - 50 - A *12 - 70 - A *12 - - 2.0 A 10.0 A Current consumption during power save mode Sleep mode current IDDS1 During sleep Standby mode current IDDS2 During standby TOMATO LSI Inc. 49 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Table 8-3. The relationship between oscillation frequency and frame frequency Item fCL fM On-chip oscillator circuit is used fOSC / 4 fOSC / ( 8 x 65) External clock is used External Input(fCL) fCL / ( 2 x 65) On-chip oscillator circuit is used fOSC / 6 fOSC / ( 12 x 49) External clock is used External Input(fCL) fCL / ( 2 x 49) On-chip oscillator circuit is used fOSC / 8 fOSC / ( 16 x 33) External clock is used External Input(fCL) fCL / ( 2 x 33) Duty ratio 1/65 1/49 1/33 *(fOSC: oscillation frequency, fCL: display clock frequency, fM: LCD AC signal frequency) <* Remark solves> *1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU *2. In case of external power supply is applied. *3. /CS1, CS2, RS, DB0 to DB7, E_/RD, RW_/RW, /RESET, MS, C68, PS, INTRS, HPM, /DC5, CLS, CL, M, DISP pins. *4. DB0 to DB7, M, FRS, DISP, CL pin. *5. /CS1, CS2, RS, DB7 to DB0, E_/RD, RW_/WR, /RESET, MS, C68, PS, INTRS, HPM, /DC5, CLS, CL, M, DISP pin. *6. Applies when then DB7 to DB0, M, DISP, and CL, pins are in high impedance. *7. Resistance value when 0.1[mA] is applied during the ON status of the output pin SEGn or COMn. RON = V / 0.1[k] (V :Voltage change when 0.1[mA] is applied in the on status) *8. See table 8-3 for the relationship between oscillation frequency and frame frequency. *9. The Voltage regulator circuit adjusts V0 within the voltage follower operating voltage range. *10. On-chip reference voltage source of the voltage regulator circuit to adjust V0. *11, 12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built -in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors (Ra and Rb) is not included. It does not include the current of the LCD penal capacity, wiring capacity, etc. TOMATO LSI Inc. 50 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 8-3. AC CHARACTERISTICS a. Read / write characteristics (8080-series MPU) RS t A S 80 t A H 80 /C S 1 (C S 2= 1) t C Y 80 t P W 80(R ), t P W 80(W ) /R D , /W R 0.9 V D D 0.1 V D D t D S 80 t D H 80 DB7 ~ DB0 (W rite) t A C C 80 t O D 80 DB7 ~ DB0 (R ead) Figure 8-4. Read / write timing chart (8080-series MPU) o Item Signal Address setup time Address hold time RS System cycle time RS Pulse width(/WR) Pulse width(/RD) Data setup time Data hold time Read access time Output disable time Symbol tAS80 tAH80 (VDD = 2.4 to 3.6V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark 13 17 - - ns tCY80 400 - - ns RW-/WR tPW80 ( W ) 55 - - ns E-/RD tPW80 ( R ) 125 - - ns DB7 to DB0 tDS80 tDH80 tACC80 tOD80 35 13 - - ns 10 - 125 90 ns CL = 100pF o Item Signal Address setup time Address hold time RS System cycle time RS Pulse width(/WR) Pulse width(/RD) Data setup time Data hold time TOMATO LSI Inc. Symbol tAS80 tAH80 (VDD = 3.6 to 5.5V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark 10 10 - - ns tCY80 150 - - ns RW-/WR tPW80 ( W ) 25 - - ns E-/RD tPW80 ( R ) 65 - - ns tDS80 tDH80 18 10 - - ns DB7 to DB0 51 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD tACC80 tOD80 Read access time Output disable time 10 Ver 0.0 65 45 - ns CL = 100pF b. Read / write characteristics (6800-series MPU) RS tAS68 tAH68 /CS1 (CS2=1) tCY68 tPW68(R), tPW680(W) E 0.9VDD 0.1VDD tDS68 tDH68 DB7 ~ DB0 (Write) tACC68 tOD68 DB7 ~ DB0 (Read) Figure 8-5. Read / write timing chart (6800-series MPU) o (VDD = 2.4 to 3.6V, Ta = -40 to +85 C) Min. Typ. Max. Unit Item Signal Symbol Address setup time Address hold time RS tAS68 tAH68 13 17 - - ns System cycle time RS tAH68 400 - - ns E-/RD tPW68 ( R ) tPW68 ( W ) 125 55 - - ns DB7 to DB0 tDS68 tDH68 TACC68 tOD68 35 13 10 - - ns - 125 90 ns Enable Read pulse Write width Data setup time Data hold time Access time Output disable time Remark CL = 100pF o (VDD = 3.6 to 5.5V, Ta = -40 to +85 C) Min. Typ. Max. Unit Item Signal Symbol Address setup time Address hold time RS tAS68 tAH68 10 10 - - ns System cycle time RS tAH68 150 - - ns E-/RD tPW68 ( R ) tPW68 ( W ) 25 65 - - ns DB7 to DB0 tDS68 tDH68 18 10 - - ns Enable Read pulse Write width Data setup time Data hold time TOMATO LSI Inc. 52 Remark HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD TACC68 tOD68 Access time Output disable time 10 Ver 0.0 65 45 - ns CL = 100pF c. Serial interface characteristics tCSS tCHS /CS1 (CS2=1) tASS tAHS RS t CYS DB6 (SCLK) 0.9VDD 0.1VDD tWLS tWHS tDSS tDHS DB7 (SID) Figure 8-6. Serial interface characteristics o Item Signal Serial clock cycle SCLK high pulse width SCLK low pulse width DB6 (SCLK) Address setup time Address hold time Data setup time Data hold time /CS1 set up time /CS1 hold time RS DB7 (SID) /CS1 Symbol tCYC tWHS tWLS tASS tAHS tDSS tDHS tCSS tCHS (VDD = 2.4 to 3.6V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark 450 180 135 90 360 90 90 55 180 - - ns - - ns - - ns - - ns o Item Signal Serial clock cycle SCLK high pulse width SCLK low pulse width DB6 (SCLK) Address setup time Address hold time Data setup time Data hold time TOMATO LSI Inc. RS DB7 (SID) 53 Symbol tCYC tWHS tWLS tASS tAHS tDSS tDHS (VDD = 3.6 to 5.5V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark 225 90 70 45 180 45 45 - - ns - - ns - - ns HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD /CS1 set up time /CS1 hold time tCSS tCHS /CS1 25 90 - Ver 0.0 - ns d. Reset input timing tRW /RESET Figure 8-7. Reset input timing o Item Signal Symbol Reset low pulse width /RESET tRW (VDD = 2.4 to 3.6V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark 900 - - ns o Item Signal Symbol Reset low pulse width /RESET tRW (VDD = 3.6 to 5.5V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark 450 - - ns e. Display control output timing e. Display control output timing tDM CL M Figure 8-8. Display control output timing o Item Signal Symbol M delay time M tDM (VDD = 2.4 to 3.6V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark - 13 70 ns o (VDD = 3.6 to 5.5V, Ta = -40 to +85 C) TOMATO LSI Inc. 54 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Item Signal Symbol Min. Typ. Max. Unit M delay time M tDM - 10 35 ns Remark 9. REFERENCE APPLICATION 9-1. Microprocessor interface HT0313A Microprocessor /CS1 CS2 RS SID SCLK /RESET Open VDD or VSS VSS /CS1 CS2 RS DB7(SID) DB6(SCLK) /RESET DB5 to DB0 C68 PS Figure 9-1. Serial Interface(PS = "L", C68 = " H or L", E_/RD = "H or L", RW_/WR = "H or L") HT0313A 6800-series Microprocessor /CS1 CS2 RS E RW DB7 to DB0 /RESET VDD VDD /CS1 CS2 RS E_/RD RW_/WR DB7 to DB0 /RESET C68 PS Figure 9-2. 6800-series MPU Interface(PS = "H", C68 = " H") HT0313A 8080-series Microprocessor TOMATO LSI Inc. 55 /CS1 CS2 RS /RD /WR DB7 to DB0 /RESET VSS VDD /CS1 CS2 RS E_/RD RW_/WR DB7 to DB0 /RESET C68 PS HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Figure 9-3. 8080-series MPU Interface(PS = "H", C68 = " L") 9-2. CONNECTIONS BETWEEN HT0313A AND LCD PANEL a. Single chip configuration (1/65 duty configurations) [ !"#$ @ 64 x 132 PIXELS [ 64 x 132 PIXELS SEG0 .....................SEG131 COM31 HT0313A COM0 COMS COMS COM63 COM32 COM32 (Bottom View) COM31 HT0313A (Top View) COM32 COM0 COMS Figure 9-5. SHL = 0, ADC = 1 COM32 COMS COM0 HT0313A HT0313A (Top View) COM63 COM31 COMS SEG0 ......................SEG131 (Bottom View) COM63 COMS COM31 SEG131 ......................SEG0 [ !"#$ @ 64 x 132 PIXELS Figure 9-6. SHL = 1, ADC = 0 TOMATO LSI Inc. SEG131 ....................SEG0 COMS COM63 Figure 9-4. SHL = 0, ADC = 0 COMS COM0 !"#$ @ 56 [ !"#$ @ 64 x 132 PIXELS Figure 9-7. SHL = 1, ADC = 1 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 b. Single chip configuration (1/49 Duty configurations) [ !"#$ @ 48 x 132 PIXELS [ 48 x 132 PIXELS SEG0 .....................SEG131 COM23 HT0313A COM0 COMS COMS COM63 COM40 COM40 (Bottom View) COM40 !"#$ @ Figure 9-10. SHL = 1, ADC = 0 57 COM0 COMS Figure 9-9. SHL = 0, ADC = 1 COM40 HT0313A 48 x 132 PIXELS TOMATO LSI Inc. COM23 HT0313A (Top View) (Top View) COM63 COM23 COMS SEG0 ......................SEG131 [ SEG131 ....................SEG0 COMS COM63 Figure 9-8. SHL = 0, ADC = 0 COMS COM0 !"#$ @ HT0313A COMS COM0 COM63 (Bottom View) COMS COM23 SEG131 ......................SEG0 [ !"#$ @ 48 x 132 PIXELS Figure 9-11. SHL = 1, ADC = 1 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 c. Single chip configuration (1/33 Duty Configurations) [ !"#$ @ 32 x 132 PIXELS [ 32 x 132 PIXELS SEG0 .....................SEG131 COM15 HT0313A COM0 COMS COMS COM63 COM48 COM48 (Bottom View) COM15 HT0313A (Top View) COM48 COM0 COMS Figure 9-13. SHL = 0, ADC = 1 COM48 COMS COM0 HT0313A HT0313A (Top View) COM63 COM15 COMS SEG0 ......................SEG131 (Bottom View) COM63 COMS COM15 SEG131 ......................SEG0 [ !"#$ @ 32 x 132 PIXELS Figure 9-14. SHL = 1, ADC = 0 TOMATO LSI Inc. SEG131 ....................SEG0 COMS COM63 Figure 9-12. SHL = 0, ADC = 0 COMS COM0 !"#$ @ 58 [ !"#$ @ 32 x 132 PIXELS Figure 9-15. SHL = 1, ADC = 1 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 d. Multiple chip configuration - 65COM (64COM + 1COMS) x 264SEG (132SEG x 2) [ ! " # $ @ 6 4 x 2 6 4 P IX E L S ! " # % & S E G 0 ... ... ... ... ... S E G 131 C O M 31 COM0 COMS ' S E G 0 ... ... ... ... ... S E G 131 H T0313A COMS C O M 63 (B o tto m V ie w ) (M a s te r ) C O M 32 C O M 31 COM0 COMS H T0313A COMS C O M 63 (B o tto m V ie w ) (S la v e ) C O M 32 Figure 9-16. SHL = 0, ADC = 0 Connect the following pins of two chips each other - Display clock pins: CL, M - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4 COM32 COMS COM0 HT0313A COM32 (Bottom View) (Master) COM63 COMS SEG131 [ COM63 COMS SEG131 COM31 ( ( # $ ... ... ... @ 64 x 264 PIXELS ! " # ( ( ' Figure 9-17. SHL = 1, ADC = 1 Connect the following pins of two chips each other - Display clock pins: CL, M TOMATO LSI Inc. 59 COMS COM0 (Bottom View) (Slave) SEG0 ... ... ... HT0313A COM31 SEG0 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4 - 130COM (128COM + 2COMS) x 132SEG C O M 32 COMS COM0 H T0313A ( B o tt o m V ie w ) (M a s te r) C O M 63 COMS C O M 31 S E G 1 3 1 ... . ... ... .. . ... ... ... S E G 0 [ ! " # $ @ 1 2 8 x 1 3 2 P IX E L S ! " # % & ' S E G 0 ... .... ... ... ... ... S E G 1 3 1 C O M 31 H T0313A COM0 COMS ( B o tt o m V ie w ) ( S la v e ) COMS C O M 63 C O M 32 Figure 9-18. 130COM (128COM + 2COMS) x 132SEG Connect the following pins of two chips each other - Display clock pins: CL, M - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4 Common / Segment output direction select - Master chip: SHL = 1, ADC = 1 - Slave chip: SHL = 0, ADC = 0 TOMATO LSI Inc. 60 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 9-3. TCP Pin lay out (sample) M FRS COM32 COM33 COM34 : : : COM45 COM46 COM47 : : : HT0313A (Top view) CL DISP /CS1 CS2 VDD /RESET RS RW _/ER E_/RD DB0 DB1 DB2 DB3 DB4 DB5 DB6(SCLK) DB7( SID) DSEL0 DSEL1 MS CLS C68 PS VSS VDD VOUT C3+ C3C1+ C1C2+ C2VR V0 V1 V2 V3 V4 /DC5 HPM INTRS COM61 COM62 COM63 COMS SEG131 SEG130 SEG129 SEG128 : : SEG65 SEG64 SEG63 SEG62 : : SEG3 SEG2 SEG1 SEG0 COM31 COM30 COM29 : : COM16 COM15 COM14 : : COM2 COM1 COM0 COMS TOMATO LSI Inc. 61 HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Figure 9-19. TCP pin layout 9-4. Application circuit for serial a. Package type: TCP b. Device mode : Master mode, Internal OSC, normal mode, 4-times boost-up, internal resistor /CS1 MPU MPU /RESET RS MPU DB6(SCLK) DB7( SID) MPU TCP out side [20 PINS] TOMATO LSI Inc. TCP in side 62 (Top view) VSS VDD VOUT C3+ C3C1+ C1C2+ C2V0 V1 V2 V3 V4 VSS VSS VDD HT0313A MPU FRS M CL DISP VSS /CS1 CS2 VDD /RESET RS VSS RW_/WR E_/RD VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6, (SCLK) DB7, (SID) VSS NC0 NC1 VDD DSEL0 DSEL1 VSS VDD MS CLS VSS C68 VDD PS VSS[6] VDD[6] VOUT[4] C3+[3] C3-[3] C1+[3] C1-[3] C2+[3] C2-[3] VSS[2] VR[2] V0[2] V1[2] V2[2] V3[2] V4[2] VSS[2] /DC5 VDD HPM VSS INTRS VDD HT0313A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Figure 9-20. HT0313A Application circuit for serial TOMATO LSI Inc. 63 Ver 0.0