Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design LM3489, LM3489-Q1 SNVS443C - MAY 2006 - REVISED DECEMBER 2016 LM3489x Hysteretic PFET Buck Controller With Enable Pin 1 Features 3 Description * * The LM3489 device is a high-efficiency PFET switching regulator controller that can be used to quickly and easily develop a small, cost-effective, switching buck regulator for a wide range of applications. The hysteretic control architecture provides for simple design without any control loop stability concerns using a wide variety of external components. The PFET architecture also allows for low component count as well as ultra-low dropout, 100% duty cycle operation. Another benefit is high efficiency operation at light loads without an increase in output ripple. A dedicated enable pin provides a shutdown mode drawing only 7 A. Leaving the enable pin unconnected defaults to on. 1 * * * * * * * * * * * * * Qualified for Automotive Parts AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 1: -40C to 125C Ambient Operating Temperature Range - Device HBM ESD Classification Level 2 - Device CDM ESD Classification Level C5 Easy-to-Use Control Methodology No Control Loop Compensation Required Wide 4.5-V to 35-V Input Range 1.239 V to VIN Adjustable Output Range High Efficiency: 93% 1.3% (2% Over Temperature) Internal Reference 100% Duty Cycle Operation Maximum Operation Frequency > 1 MHz Current Limit Protection Dedicated Enable Pin (on if Unconnected) Shutdown Mode Draws Only 7-A Supply Current 8-Pin VSSOP Package Current limit protection can be implemented by measuring the voltage across the PFET's RDS(ON), thus eliminating the need for a sense resistor. A sense resistor may be used to improve current limit accuracy if desired. The cycle-by-cycle current limit can be adjusted with a single resistor, ensuring safe operation over a range of output currents. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) 2 Applications LM3489 LM3489-Q1 * * * * * * * * * * (1) For all available packages, see the orderable addendum at the end of the data sheet. Set-Top Boxes DSL or Cable Modems PC/IA Auto PCs TFT Monitors Battery-Powered Portable Applications Distributed Power Systems Always-On Power High-Power LED Drivers Automotive VSSOP (8) 3.00 mm x 3.00 mm Typical Application Circuit L C ADJ R ADJ VIN V OUT Q1 RIS 7 D1 1 PGATE + 5 CIN1 8 3 CIN2 ISENSE ADJ VIN EN LM3489 FB GND PGND Cff R1 + C OUT 4 2 R2 6 Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM3489, LM3489-Q1 SNVS443C - MAY 2006 - REVISED DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings: LM3489 .............................................. ESD Ratings: LM3489-Q1 ........................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................... 9 7.4 Device Functional Mode ......................................... 14 8 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Application .................................................. 15 9 Power Supply Recommendations...................... 19 10 Layout................................................................... 19 10.1 Layout Guidelines ................................................. 19 10.2 Layout Examples................................................... 19 11 Device and Documentation Support ................. 20 11.1 11.2 11.3 11.4 11.5 11.6 Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 20 12 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (February 2013) to Revision C Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 * Added AEC-Q100 Qualification bullets to Features ............................................................................................................... 1 * Deleted Lead temperature (Vapor phase and Infrared maximums) ....................................................................................... 4 * Added Thermal Information table ........................................................................................................................................... 5 Changes from Revision A (February 2013) to Revision B * 2 Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1 Submit Documentation Feedback Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 LM3489, LM3489-Q1 www.ti.com SNVS443C - MAY 2006 - REVISED DECEMBER 2016 5 Pin Configuration and Functions DGK Package 8-Pin VSSOP Top View ISENSE 1 8 VIN GND 2 7 PGATE EN 3 6 PGND FB 4 5 ADJ Not to scale Pin Functions PIN NO. NAME I/O DESCRIPTION The current sense input pin. This pin must be connected to the PFET drain terminal directly or through a series resistor up to 600 for 28 V > VIN > 35 V. 1 ISENSE I 2 GND -- 3 EN I Enable pin. Connect EN pin to ground to shutdown the part or float to enable operation (Internally pulled high). This pin can also be used to perform UVLO function. 4 FB I The feedback input. Connect the FB to a resistor voltage divider between the output and GND for an adjustable output voltage. 5 ADJ I Current limit threshold adjustment. Connected to an internal 5.5-A current source. A resistor is connected between this pin and VIN. The voltage across this resistor is compared with the ISENSE pin voltage to determine if an overcurrent condition has occurred. 6 PGND -- Power ground 7 PGATE O Gate drive output for the external PFET. PGATE swings between VIN and VIN 5-V. 8 VIN I Power supply input pin Signal ground Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 Submit Documentation Feedback 3 LM3489, LM3489-Q1 SNVS443C - MAY 2006 - REVISED DECEMBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings See (1) . MIN MAX UNIT VIN voltage -0.3 36 V PGATE voltage -0.3 36 V FB voltage -0.3 5 V -1 36 ISENSE voltage ADJ voltage EN voltage V -1 (<100 ns) -0.3 (2) 36 -0.3 Power dissipation, TA = 25C (3) V 6 V 417 mW Junction temperature, TJ -40 150 C Storage temperature, Tstg -65 150 C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This pin is internally pulled high and clamped at 8 V (typical). The absolute maximum and operating maximum rating specifies the input level allowed for an external voltage source applied to this pin without triggering the internal clamp with margin. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance, RJA and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD= (TJ - TA) / RJA. Exceeding the maximum allowable power dissipation will lead to excessive die temperature. 6.2 ESD Ratings: LM3489 VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings: LM3489-Q1 VALUE V(ESD) (1) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) 2000 Charged device model (CDM), per AEC Q100-011 750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIN Supply voltage MIN MAX 4.5 35 V 5.5 V EN voltage (1) TJ (1) (2) 4 Operating junction temperature (2) UNIT LM3489 -40 125 C LM3489-Q1 -40 150 C This pin is internally pulled high and clamped at 8 V (typical). The absolute maximum and operating maximum rating specifies the input level allowed for an external voltage source applied to this pin without triggering the internal clamp with margin. High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125C. Submit Documentation Feedback Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 LM3489, LM3489-Q1 www.ti.com SNVS443C - MAY 2006 - REVISED DECEMBER 2016 6.5 Thermal Information LM3489 THERMAL METRIC (1) DGK (VSSOP) UNIT 8 PINS RJA Junction-to-ambient thermal resistance 163.7 C/W RJC(top) Junction-to-case (top) thermal resistance 56.6 C/W RJB Junction-to-board thermal resistance 83.3 C/W JT Junction-to-top characterization parameter 5.4 C/W JB Junction-to-board characterization parameter 82 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.6 Electrical Characteristics Typical values correspond to TJ = 25C. Minimum and maximum limits apply over TJ = -40C to 125C for the LM3489 and LM3489-Q1. VIN = 12 V, VISNS = VIN - 1 V, and VADJ = VIN - 1.1 V (unless otherwise noted). PARAMETER TEST CONDITIONS ISHDN Shutdown input supply current EN = 0 V VEN Enable threshold voltage Enable rising VEN_HYST Enable threshold hysteresis IQ Quiescent current at ground pin VFB Feedback voltage (1) VHYST Comparator hysteresis VCL_OFFSET Current limit comparator offset VFB = 1 V ICL_ADJ Current limit ADJ current source TCL Current limit one-shot offtime RPGATE Driver resistance IPGATE Driver output current IFB MIN 1.15 TYP MAX 7 15 1.5 1.85 130 FB = 1.5 V (not switching) UNIT A V mV 280 400 1.239 1.264 10 20 mV -20 0 20 mV VFB = 1.5 V 3 5.5 7 A VADJ = 11.5 V, VISNS = 11 V, VFB = 1 V 6 9 14 s 1.214 Source, ISOURCE = 100 mA 5.5 Sink, ISINK = 100 mA 8.5 Source, VIN = 7 V, PGATE = 3.5 V A V 0.44 A Sink, VIN = 7 V, PGATE = 3.5 V 0.1 FB pin bias current (2) VFB = 1 V 300 TONMIN_NOR Minimum ON time in normal operation VISNS = VADJ + 0.1 V, Cload on OUT = 1000 pF (3) 100 ns TONMIN_CL Minimum ON time in current limit VISNS = VADJ - 0.1 V, VFB = 1 V, Cload on OUT = 1000 pF (3) 200 ns %VFB/VIN Feedback voltage line regulation 4.5 V VIN 35 V 0.01% V (1) (2) (3) 750 nA The VFB is the trip voltage at the FB pin when PGATE switches from high to low. Bias current flows out from the FB pin. A 1000-pF capacitor is connected between VIN and PGATE. Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 Submit Documentation Feedback 5 LM3489, LM3489-Q1 SNVS443C - MAY 2006 - REVISED DECEMBER 2016 www.ti.com 6.7 Typical Characteristics At TA = 25C and applicable to both LM3489 and LM3489-Q1 at VIN = 12 V with configuration in Detailed Description (unless otherwise noted). 500 15 VFB = 1.5 V, VEN = 5.5 V VFB = 1.5 V, VEN = 5.5 V 400 12 -40 C -40 C 300 9 IIN (PA) IIN (PA) 25 C 125 C 25 C 200 6 100 3 125 C 0 0 0 10 20 30 40 0 10 20 VIN (V) 30 40 VIN (V) Figure 1. Quiescent Current vs Input Voltage Figure 2. Shutdown Current vs Input Voltage 1.264 16 IOUT = 200 mA IOUT = 0 TJ = 25 C 1.254 14 18 V 1.244 VFB (V) VHYST (mV) 35 V 12 V 1.234 10 4.5 V 6 1.224 2 1.214 -40 -20 0 20 40 60 80 100 120 140 0 10 20 40 VIN (V) JUNCTION TEMPERATURE (C) Figure 3. Feedback Voltage vs Temperature Figure 4. Feedback Voltage Hysteresis vs Input Voltage 18 6.5 VFB = 1.5 V IOUT = 0 VIN = 12 V 14 6 ICL_ADJ (mA) VHYST (mV) 30 10 4.5 V 5.5 35 V 18 V 6 5 2 4.5 -40 6 -20 0 20 40 60 80 100 120 140 -20 -40 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE (C) JUNCTION TEMPERATURE (C) Figure 5. Feedback Voltage Hysteresis vs Temperature Figure 6. Current Limit ADJ Current vs Temperature Submit Documentation Feedback Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 LM3489, LM3489-Q1 www.ti.com SNVS443C - MAY 2006 - REVISED DECEMBER 2016 Typical Characteristics (continued) At TA = 25C and applicable to both LM3489 and LM3489-Q1 at VIN = 12 V with configuration in Detailed Description (unless otherwise noted). 6 10 5.5 9.5 125 C 5 VIN -VPGATE (V) TCL (ms) VIN = 12 V VIN = 4.5 V 9 VIN = 35 V VIN = 24 V 25 C 4.5 -40 C 4 8.5 3.5 8 3 -40 -10 20 50 80 110 140 0 10 20 JUNCTION TEMPERATURE, TJ (C) 30 40 VIN (V) Figure 7. Current Limit One Shot OFF Time vs Temperature Figure 8. VIN - VPGATE vs VIN 160 300 140 VIN = 4.5 V 250 VIN = 24 V TONMIN_CL (ns) TONMIN_NOR (ns) 120 VIN = 12 V 100 VIN = 24 V 200 VIN = 4.5 V 80 VIN = 12 V 150 60 40 -40 -10 20 50 80 110 100 -40 140 -10 20 50 110 140 JUNCTION TEMPERATURE, TJ (oC) JUNCTION TEMPERATURE, TJ (C) Figure 9. Minimum ON Time vs Temperature (Normal Operation) Figure 10. Minimum ON Time vs Temperature (Current Limit) 600 10 VOUT = 3.3 V IOUT = 500 mA Cff = 100 pF 500 OPERATING FREQUENCY (kHz) 8 OPERATING ON TIME (ms) 80 6 VIN = 6 V 4 VIN = 24 V 2 VIN = 12 V L = 10 mH 400 L = 15 mH 300 200 L = 22 mH 100 0 0 0 0.2 0.4 0.6 0.8 1 0 10 20 30 40 VIN (V) LOAD CURRENT (A) Figure 11. Operating ON Time vs Load Current Figure 12. Operating Frequency vs Input Voltage Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 Submit Documentation Feedback 7 LM3489, LM3489-Q1 SNVS443C - MAY 2006 - REVISED DECEMBER 2016 www.ti.com Typical Characteristics (continued) At TA = 25C and applicable to both LM3489 and LM3489-Q1 at VIN = 12 V with configuration in Detailed Description (unless otherwise noted). 100 3.0 VIN = 12 V 90 2.0 VIN = 24 V VIN = 24 V 1.0 DVOUT (%) EFFICIENCY (%) 80 70 60 0.0 VIN = 12 V -1.0 L = 22 mH R1 = 60.7 k R2 = 20 k 50 L = 22 mH R1 = 60.7 k R2 = 20 k -2.0 40 -3.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 OUTPUT CURRENT (A) 0.4 0.6 0.8 1.0 1.2 OUTPUT CURRENT (A) VOUT = 5 V, L = 22 H Figure 13. Efficiency vs Load Current VOUT = 5 V, L = 22 H Figure 14. VOUT Regulation vs Load Current VOUT RIPPLE (50 mVac/Div) VOUT RIPPLE (20 mVac/Div) Switch Node Voltage, VD1 (10V/Div) Switch Node Voltage, VD1 (10V/Div) IL (1A/Div) IL (500 mA/Div) TIME (4 ms/DIV) TIME (2 ms/DIV) VIN = 12 V, VOUT = 3.3 V, IOUT = 500 mA Figure 15. Continuous Mode Operation VIN = 12 V, VOUT =3.3 V, IOUT = 50 mA Figure 16. Discontinuous Mode Operation VOUT = 3.3 V, 500 mA loaded Figure 17. Enable Transient VOUT = 3.3 V, 500 mA loaded Figure 18. Shutdown Transient 8 Submit Documentation Feedback Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 LM3489, LM3489-Q1 www.ti.com SNVS443C - MAY 2006 - REVISED DECEMBER 2016 7 Detailed Description 7.1 Overview The LM3489 is a buck (step-down) DC-DC controller that uses a hysteretic control scheme. The control comparator is designed with approximately 10 mV of hysteresis. In response to the voltage at the FB pin, the gate drive (PGATE pin) turns the external PFET on or off. When the inductor current is too high, the current limit protection circuit engages and turns the PFET off for approximately 9 s. Hysteretic control does not require an internal oscillator. Switching frequency depends on the external components and operating conditions. The operating frequency reduces at light loads resulting in excellent efficiency compared to other architectures. The output voltage can be programmed by two external resistors. The output can be set in a wide range from 1.239 V (typical) to VIN. 7.2 Functional Block Diagram Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Hysteretic Control Circuit When the FB input to the control comparator falls below the reference voltage (1.239 V), the output of the comparator switches to a low state. This results in the driver output, PGATE, pulling the gate of the PFET low and turning on the PFET. With the PFET on, the input supply charges COUT and supplies current to the load through the series path through the PFET and the inductor. Current through the Inductor ramps up linearly and the output voltage increases. As the FB voltage reaches the upper threshold, which is the internal reference voltage plus 10 mV, the output of the comparator changes from low to high, and the PGATE responds by turning the PFET off. As the PFET turns off, the inductor voltage reverses, the catch diode turns on, and the current through the inductor ramps down. Then, as the output voltage reaches the internal reference voltage again, the next cycle starts. Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 Submit Documentation Feedback 9 LM3489, LM3489-Q1 SNVS443C - MAY 2006 - REVISED DECEMBER 2016 www.ti.com Feature Description (continued) The LM3489 operates in discontinuous conduction mode at light-load current or continuous conduction mode at heavy-load current. In discontinuous conduction mode, current through the inductor starts at zero and ramps up to the peak then ramps down to zero. The next cycle starts when the FB voltage reaches the reference voltage. Until then, the inductor current remains zero and the output capacitor supplies the load. The operating frequency is lower and switching losses reduced. In continuous conduction mode, current always flows through the inductor and never ramps down to zero. The output voltage (VOUT) can be programmed by 2 external resistors. It can be calculated with Equation 1. VOUT = 1.239 x (R1 + R2) / R2 (1) Figure 19. Hysteretic Window The minimum output voltage ripple (VOUT_PP) can be calculated in the same way with Equation 2. VOUT_PP = VHYST (R1 + R2) / R2 (2) For example, with VOUT set to 3.3 V, VOUT_PP is 26.6 mV in Equation 3. VOUT_PP = 0.01 x (33k + 20k) / 20k = 0.0266 V (3) Operating frequency (F) is determined by knowing the input voltage, output voltage, inductor, VHYST, ESR (Equivalent Series Resistance) of output capacitor, and the delay. It can be approximately calculated using Equation 4. VIN VOUT u ESR VOUT F u VIN VHYST u D u L VIN u delayu ESR where * : (R1 + R2) / R2 (4) 7.3.1.1 Delay It includes the LM3489 propagation delay time and the PFET delay time. The propagation delay is 90 ns typically (see Figure 20). 10 Submit Documentation Feedback Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 LM3489, LM3489-Q1 www.ti.com SNVS443C - MAY 2006 - REVISED DECEMBER 2016 Feature Description (continued) 140 L=22 H PROPOGATION DELAY (ns) 120 L=10 H 100 80 L=4.7 H 60 40 20 0 0 5 10 15 20 25 30 35 INPUT VOLTAGE - OUTPUT VOLTAGE (V) Figure 20. Propagation Delay The operating frequency and output ripple voltage can also be significantly influenced by the speed up capacitor (Cff). Cff is connected in parallel with the high side feedback resistor, R1. The location of this capacitor is similar to where a phase lead capacitor would be located in a PWM control scheme. However it's effect on hysteretic operation is much different. Cff effectively shorts out R1 at the switching frequency and applies the full output ripple to the FB pin without dividing by the R2/R1 ratio. The end result is a reduction in output ripple and an increase in operating frequency. When adding Cff, calculate the formula above with = 1. The value of Cff depend on the desired operating frequency and the value of R2. A good starting point is 470-pF ceramic at 100kHz decreasing linearly with increased operating frequency. Also note that as the output voltage is programmed below 2.5 V, the effect of Cff will decrease significantly. 7.3.2 Current Limit Operation The LM3489 has a cycle-by-cycle current limit. Current limit is sensed across the VDS of the PFET or across an additional sense resistor. When current limit is activated, the LM3489 turns off the external PFET for a period of 9 s (typical). The current limit is adjusted by an external resistor, RADJ. The current limit circuit is composed of the ISENSE comparator and the one-shot pulse generator. The positive input of the ISENSE comparator is the ADJ pin. An internal 5.5-A current sink creates a voltage across the external RADJ resistor. This voltage is compared to the voltage across the PFET or sense resistor. The ADJ voltage can be calculated with Equation 5. VADJ = VIN - (RADJ x 3 A) where * 3 A is the minimum ICL-ADJ value (5) The negative input of the ISENSE comparator is the ISENSE pin that must be connected to the drain of the external PFET. The inductor current is determined by sensing the VDS. It can be calculated with Equation 6. VISENSE = VIN - (RDSON x IIND_PEAK) = VIN - VDS Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 (6) Submit Documentation Feedback 11 LM3489, LM3489-Q1 SNVS443C - MAY 2006 - REVISED DECEMBER 2016 www.ti.com Feature Description (continued) Figure 21. Current Sensing by VDS The current limit is activated when the voltage at the ADJ pin exceeds the voltage at the ISENSE pin. The ISENSE comparator triggers the 9-s one-shot pulse generator forcing the driver to turn the PFET off. The driver turns the PFET back on after 9 s. If the current has not reduced below the set threshold, the cycle will repeat continuously. A filter capacitor, CADJ, must be placed as shown in Figure 21. CADJ filters unwanted noise so that the ISENSE comparator will not be accidentally triggered. A value of 100 pF to 1 nF is recommended in most applications. Higher values can be used to create a soft-start function (see Start Up). The current limit comparator has approximately 100 ns of blanking time. This ensures that the PFET is fully on when the current is sensed. However, under extreme conditions such as cold temperature, some PFETs may not fully turn on within the blanking time. In this case, the current limit threshold must be increased. If the current limit function is used, the on time must be greater than 100 ns. Under low duty cycle operation, the maximum operating frequency is limited by this minimum on-time. During current limit operation, the output voltage drops significantly as does operating frequency. As the load current is reduced, the output returns to the programmed voltage. However, there is a current limit foldback phenomenon inherent in this current limit architecture (see Figure 22). Figure 22. Current Limit Foldback Phenomenon 12 Submit Documentation Feedback Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 LM3489, LM3489-Q1 www.ti.com SNVS443C - MAY 2006 - REVISED DECEMBER 2016 Feature Description (continued) At high input voltages (> 28 V) increased undershoot at the switch node can cause an increase in the current limit threshold. To avoid this problem, a low Vf Schottky catch diode must be used (see Catch Diode Selection (D1)). Additionally, a resistor can be placed between the ISENSE pin and the switch node. Any value in the range of 220 to 600 is recommended. 7.3.3 Start Up The current limit circuit is active during start-up. During start-up, the PFET stays on until either the current limit or the feedback comparator is tripped If the current limit comparator is tripped first, then take the the foldback characteristic into account. Start-up into full load may require a higher current limit set point or the load must be applied after start-up. One problem with selecting a higher current limit is inrush current during start-up. Increasing the capacitance (CADJ) in parallel with RADJ results in a soft-start characteristic. CADJ and RADJ create an RC time constant forcing current limit to activate at a lower current. The output voltage will ramp more slowly when using this technique. There is example start-up plot for CADJ equal to 1 nF in Typical Characteristics. Lower values for CADJ will have little to no effect on soft-start. 7.3.4 External Sense Resistor The VDS of a PFET tends to vary significantly over temperature. This will result an equivalent variation in current limit. To improve current limit accuracy, an external sense resistor can be connected from VIN to the source of the PFET, as shown in Figure 23. The current sense resistor, RCS must have value comparable with RDSON of the PFET used, typically in the range of 50 m to 200 m. Equation 6 in Current Limit Operation can be used by replacing the RDSON with RCS. Figure 23. Current Sensing by External Resistor 7.3.5 PGATE When switching, the PGATE pin swings from VIN (off) to some voltage below VIN (on). How far the PGATE will swing depends on several factors including the capacitance, on-time, and input voltage. PGATE voltage swing will increase with decreasing gate capacitance. Although PGATE voltage will typically be around VIN-5V, with very small gate capacitances, this value can increase to a typical maximum of VIN-8.3 V. Additionally, PGATE swing voltage will increase as on-time increases. During long on-times, such as when operating at 100% duty cycle, the PGATE voltage will eventually fall to its maximum voltage of VIN-8.3 V (typical) regardless of the PFET gate capacitance. The PGATE voltage will not fall below 0.4 V (typical). Therefore, when the input voltage falls below approximately 9 V, the PGATE swing voltage range is reduced. At an input voltage of 7 V, for instance, PGATE will swing from 7 V to a minimum of 0.4 V. Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 Submit Documentation Feedback 13 LM3489, LM3489-Q1 SNVS443C - MAY 2006 - REVISED DECEMBER 2016 www.ti.com Feature Description (continued) 7.3.6 Adjustable UVLO The undervoltage lockout (UVLO) function can be implemented as shown in Figure 24. By incorporating the feature of the internal enable threshold, the lockout level can be programmed through an external potential divider formed with R3 and R4. The input voltage information is detected and compared with the enable threshold and the device operation is inhibited when VIN drops below the preset UVLO level. The UVLO and hysteresis voltage can be calculated with Equation 7 and Equation 8. R4 * VIN(UVLO) = VEN 1 (c) R3 (7) VIN(UVLO_HYST) R4 * VEN_HYST u 1 (c) R3 where * * VEN is the enable rising threshold voltage VEN_HYST is the enable threshold hysteresis (8) VIN 1 ISENSE FB 4 5 ADJ R4 8 VIN VEN R3 PGATE 7 3 EN LM3489 GND 2 PGND 6 Copyright (c) 2016, Texas Instruments Incorporated Figure 24. Adjustable UVLO 7.4 Device Functional Mode 7.4.1 Device Enable and Shutdown The LM3489 can be remotely shutdown by forcing the enable pin to ground. With EN pin grounded, the internal blocks other than the enable logic are deactivated and the shutdown current of the device is lowered to only 7 A (typical). Releasing the EN pin allows for normal operation to resume. The EN pin is internally pulled high with the voltage clamped at 8 V typical. For normal operation, this pin must be left open. In case an external voltage source is applied to this pin for enable control, the applied voltage must not exceed the maximum operating voltage level specified in this datasheet (that is 5.5 V). 14 Submit Documentation Feedback Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 LM3489, LM3489-Q1 www.ti.com SNVS443C - MAY 2006 - REVISED DECEMBER 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information Hysteretic control is a simple control scheme. However the operating frequency and other performance characteristics highly depend on external conditions and components. If either the inductance, output capacitance, ESR, VIN, or Cff is changed, there is a change in the operating frequency and output ripple. The best approach is to determine what operating frequency is desirable in the application and then begin with the selection of the inductor and COUT ESR. 8.2 Typical Application VIN 7 V 35V C ADJ R ADJ 1 nF 24k L 22 PH Q 1 FDC5614P V OUT 3.3V/0.5A MBRS140 RIS 270 7 CIN1 22 PF 50V ISENSE PGATE + 5 8 3 CIN2 0.1 PF 50V ADJ VIN LM3489 EN SD* FB GND 1 D1 R1 33k Cff 4 2 PGND + C OUT 100 PF 6.3V 100 pF R2 20k 6 *Short to shutdown the device Copyright (c) 2016, Texas Instruments Incorporated Figure 25. Typical Application Schematic for VOUT = 3.3 V, 500 mA 8.2.1 Design Requirements The important parameters for the inductor are the inductance and the current rating. The LM3489 operates over a wide frequency range and can use a wide range of inductance values. A rule of thumb is to use the equations used for Simple Switchers(R). The equations for inductor ripple (i) as a function of output current (IOUT) depend on Iout: For Iout < 2 A, i Iout x Iout-0.366726. For Iout > 2 A, i Iout x 0.3. 8.2.2 Detailed Design Procedure 8.2.2.1 Inductor Selection (L) The inductance can be calculated with Equation 9 and Equation 10 based upon the desired operating frequency. VIN VDS VOUT D u L (9) 'i f Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 Submit Documentation Feedback 15 LM3489, LM3489-Q1 SNVS443C - MAY 2006 - REVISED DECEMBER 2016 www.ti.com Typical Application (continued) Ipk IOUT (c) 'i * u 1.1 2 where * * * D is the duty cycle VD is the diode forward voltage VDS is the voltage drop across the PFET (10) The inductor must be rated with Equation 11. 'i * u 1.1 Ipk IOUT 2 (c) (11) The inductance value and the resulting ripple is one of the key parameters controlling operating frequency. The second is the inductor ESR that contribute to the steady-state power loss due to current flowing through the inductor. 8.2.2.2 Output Capacitor Selection (COUT) The ESR of the output capacitor times the inductor ripple current is equal to the output ripple of the regulator. However, the VHYST sets the first-order value of this ripple. As ESR is increased with a given inductance, operating frequency increases as well. If ESR is reduced then the operating frequency reduces. The use of ceramic capacitors has become a common desire of many power supply designers. However, ceramic capacitors have a very low ESR resulting in a 90 phase shift of the output voltage ripple. This results in low operating frequency and increased output ripple. To fix this problem a low-value resistor must be added in series with the ceramic output capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance provides highly accurate control over the output voltage ripple. Other types capacitor, such as Sanyo POS CAP and OS-CON, Panasonic SP CAP, and Nichicon NA series, are also recommended and may be used without additional series resistance. For all practical purposes, any type of output capacitor may be used with proper circuit verification. 8.2.2.3 Input Capacitor Selection (CIN) A bypass capacitor is required between the input source and ground. It must be located near the source pin of the external PFET. The input capacitor prevents large voltage transients at the input and provides the instantaneous current when the PFET turns on. The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the manufacturer's recommended voltage derating. For high-input voltage applications, low-ESR electrolytic, Nichicon UD series or the Panasonic FK series are available. The RMS current in the input capacitor can be calculated with Equation 12. IRSM_CIN IOUT u VOUT (VIN VOUT ) VIN (12) The input capacitor power dissipation can be calculated with Equation 13. PD(CIN) = IRMS_CIN2 x ESRCIN (13) The input capacitor must be able to handle the RMS current and the dissipation. Several input capacitors may be connected in parallel to handle large RMS currents. In some cases it may be much cheaper to use multiple electrolytic capacitors than a single low-ESR, high-performance capacitor such as OS-CON or Tantalum. The capacitance value must be selected such that the ripple voltage created by the switch current pulses is less than 10% of the total DC voltage across the capacitor. For high VIN conditions (> 28 V), the fast switching, high swing of the internal gate drive introduces unwanted disturbance to the VIN rail and the current limit function can be affected. To eliminate this potential problem, a high-quality ceramic capacitor of 0.1 F is recommended to filter out the internal disturbance at the VIN pin. This capacitor must be placed right next to the VIN pin for best performance. 16 Submit Documentation Feedback Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 LM3489, LM3489-Q1 www.ti.com SNVS443C - MAY 2006 - REVISED DECEMBER 2016 Typical Application (continued) 8.2.2.4 Programming the Current Limit (RADJ) The current limit is determined with Equation 14 by connecting a resistor (RADJ) between input voltage and the ADJ pin, pin 5. R R ADJ IIND_PEAK u DSON ICL_ADJ where * * * RDSON is Drain-Source ON resistance of the external PFET ICL_ADJ is 3 A minimum IIND_PEAK = ILOAD + IRIPPLE / 2 (14) Using the minimum value for ICL_ADJ (3 A) ensures that the current limit threshold is set higher than the peak inductor current. The RADJ value must be selected to ensure that the voltage at the ADJ pin does not fall below 3.5 V. With this in mind, RADJ_MAX = (VIN - 3.5) / 7 A. If a larger RADJ value is needed to set the desired current limit, either use a PFET with a lower RDSON or use a current sense resistor as shown in Figure 23. The current limit function can be disabled by connecting the ADJ pin to ground and ISENSE to VIN. 8.2.2.5 Catch Diode Selection (D1) The important parameters for the catch diode are the peak current, the peak reverse voltage, and the average power dissipation. The average current through the diode can be calculated with Equation 15. ID_AVE = IOUT x (1 - D) (15) The off-state voltage across the catch diode is approximately equal to the input voltage. The peak reverse voltage rating must be greater than input voltage. In nearly all cases a Schottky diode is recommended. In lowoutput voltage applications, a low forward voltage provides improved efficiency. For high-temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance. 8.2.2.6 P-Channel MOSFET Selection (Q1) The important parameters for the PFET are the maximum Drain-Source voltage (VDS), the ON resistance (RDSON), Current rating, and the input capacitance. The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The VDS must be selected to provide some margin beyond the input voltage. PFET drain current, Id, must be rated higher than the peak inductor current, IIND-PEAK. Depending on operating conditions, the PGATE voltage may fall as low as VIN - 8.3 V. Therefore, a PFET must be selected with a VGS maximum rating greater than the maximum PGATE swing voltage. As input voltage decreases below 9 V, PGATE swing voltage may also decrease. At 5-V input the PGATE will swing from VIN to VIN - 4.6 V. To ensure that the PFET turns on quickly and completely, a low threshold PFET must be used when the input voltage is less than 7 V. Total power loss in the FET can be approximated using Equation 16. PDswitch = RDSON x IOUT2x D + F x IOUT x VIN x (ton + toff) / 2 where * * ton is the FET turn on time toff is the FET turn off time (16) A value of 10 ns to 20 ns is typical for ton and toff. A PFET must be selected with a turnon rise time of less than 100 ns. Slower rise times will degrade efficiency, can cause false current limiting, and in extreme cases may cause abnormal spiking at the PGATE pin. Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 Submit Documentation Feedback 17 LM3489, LM3489-Q1 SNVS443C - MAY 2006 - REVISED DECEMBER 2016 www.ti.com Typical Application (continued) The RDSON is used in determining the current limit resistor value, RADJ. Note that the RDSON has a positive temperature coefficient. At 100C, the RDSON may be as much as 150% higher than the 25C value. This increase in RDSON must be considered when determining RADJ in wide temperature range applications. If the current limit is set based upon 25C ratings, then false current limiting can occur at high temperature. Keeping the gate capacitance below 2000 pF is recommended to keep switching losses and transition times low. This will also help keep the PFET drive current low, which will improve efficiency and lower the power dissipation within the controller. As gate capacitance increases, operating frequency must be reduced and as gate capacitance decreases operating frequency can be increased. 8.2.2.7 Interfacing With the Enable Pin The enable pin is internally pulled high with clamping at 8 V typical. For normal operation this pin must be left open. To disable the device, the enable pin must be connected to ground externally. If an external voltage source is applied to this pin for enable control, the applied voltage must not exceed the maximum operating voltage level specified in this datasheet, that is 5.5 V. For most applications, an open-drain or open-collector transistor can be used to short this pin to ground to shutdown the device . 8.2.3 Application Curves 100 3.0 VIN = 4.5 V 90 2.0 VIN = 12 V 1.0 VIN = 24 V 'VOUT (%) EFFICIENCY (%) 80 70 60 VIN = 24 V 0.0 VIN = 4.5 V -1.0 VIN = 12 V 50 -2.0 40 -3.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 OUTPUT CURRENT (A) 0.4 0.6 0.8 1.0 1.2 OUTPUT CURRENT (A) VOUT = 3.3 V, L = 22 H Figure 26. Efficiency vs Load Current VOUT = 3.3 V, L = 22 H Figure 27. VOUT Regulation vs Load Current No load, CADJ = 1 nF VOUT = 3.3 V, 50 mA to 500 mA load Figure 29. Load Transient Figure 28. Power Up 18 Submit Documentation Feedback Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 LM3489, LM3489-Q1 www.ti.com SNVS443C - MAY 2006 - REVISED DECEMBER 2016 9 Power Supply Recommendations This device is designed to operate over a recommended input voltage supply range of 4.5 V to 35 V. The input supply must be well regulated. If the input supply is located far from the LM3485 EVM and needs a long power supply cable to connect, an additional bulk capacitor may be required. An electrolytic capacitor with a value of 47 F can be used typically. As mentioned in Current Limit Operation, at higher input voltages (> 28 V) an increased negative SW transient spike at the switch node can lead to an increase in the current limit threshold due to the formation of the parasitic NPN connection between the ISENSE pin, the internal substrate and the ADJ pin . To avoid this issue, a Schottky catch diode with lower forward voltage drop must be used. In addition to that, a resistor must be placed between the ISENSE pin and the external switch node. A resistor value in the range of 220 to 600 is recommended. 10 Layout 10.1 Layout Guidelines The PCB layout is very important in all switching regulator designs. Poor layout can cause switching noise into the feedback signal and generate EMI problems. For minimal inductance, the wires indicated by heavy lines in schematic diagram must be as wide and short as possible. Keep the ground pin of the input capacitor as close as possible to the anode of the catch diode. This path carries a large AC current. The switching node, the node with the diode cathode, inductor and FET drain must be kept short. This node is one of the main sources for radiated EMI since it sees a large AC voltage at the switching frequency. It is always a good practice to use a ground plane in the design, particularly for high-current applications. The two ground pins, PGND and GND, must be connected by as short a trace as possible. They can be connected underneath the device. These pins are resistively connected internally by approximately 50 . The ground pins must be tied to the ground plane, or to a large ground trace in close proximity to both the FB divider and COUT grounds. The gate pin of the external PFET must be placed close to the PGATE pin. However, if a very small FET is used, a resistor may be required between PGATE pin and the gate of the PFET to reduce high-frequency ringing. Because this resistor will slow down the PFET's rise time, the current limit blanking time must be taken into consideration (see Current Limit Operation). The feedback voltage signal line can be sensitive to noise. Avoid inductive coupling with the inductor or the switching node. The FB trace must be kept away from those areas. Also, the orientation of the inductor can contribute un-wanted noise coupling to the FB path. If noise problems are observed it may be worth trying a different orientation of the inductor and select the best for final component placement. 10.2 Layout Examples SPACE Figure 30. LM3489 EVM PCB Top Layer Layout Figure 31. LM3489 EVM PCB Bottom Layer Layout Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 Submit Documentation Feedback 19 LM3489, LM3489-Q1 SNVS443C - MAY 2006 - REVISED DECEMBER 2016 www.ti.com 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LM3489 Click here Click here Click here Click here Click here LM3489-Q1 Click here Click here Click here Click here Click here 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. Simple Switchers is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright (c) 2006-2016, Texas Instruments Incorporated Product Folder Links: LM3489 LM3489-Q1 PACKAGE OPTION ADDENDUM www.ti.com 22-Feb-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) TBD Call TI Call TI Op Temp (C) Device Marking (4/5) LM3489MM NRND VSSOP DGK 8 1000 -40 to 125 SKSB LM3489MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM & no Sb/Br) -40 to 125 SKSB LM3489MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM & no Sb/Br) -40 to 125 SKSB LM3489QMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 STEB LM3489QMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 STEB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 22-Feb-2016 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF LM3489, LM3489-Q1 : * Catalog: LM3489 * Automotive: LM3489-Q1 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM3489MM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3489MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3489MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3489QMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3489QMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3489MM VSSOP DGK 8 1000 210.0 185.0 35.0 LM3489MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM3489MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LM3489QMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM3489QMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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