74AHC273D - NXP - Datasheet.Directory

1. General description

The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard

No. 7-A.

The 74AHC273; 74AHCT273 has eight edge-triggered, D-type ﬂip-ﬂops with individual D

inputs and Q outputs.

The common clock (CP) and master reset (MR) inputs, load and reset (clear) all ﬂip-ﬂops

simultaneously.

The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is

transferred to the corresponding output (Qn) of the ﬂip-ﬂop.

All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR

input.

The device is useful for applications where only the true output is required and the clock

and master reset are common to all storage elements.

2. Features

nBalanced propagation delays

nAll inputs have Schmitt-trigger actions

nInputs accept voltages higher than VCC

nIdeal buffer for MOS microcontroller or memory

nCommon clock and master reset

nRelated product versions:

u 74AHC377; 74AHCT377 for clock enable version

u74AHC373; 74AHCT373 for transparent latch version

u74AHC374; 74AHCT374 for 3-state version

nInput levels:

uFor 74AHC273: CMOS level

uFor 74AHCT273: TTL level

nESD protection:

uHBM EIA/JESD22-A114E exceeds 2000 V

uMM EIA/JESD22-A115-A exceeds 200 V

uCDM EIA/JESD22-C101C exceeds 1000 V

nMultiple package options

nSpeciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

Rev. 03 — 13 May 2008 Product data sheet

Product data sheet Rev. 03 — 13 May 2008 2 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

3. Ordering information

4. Functional diagram

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AHC273

74AHC273D −40 °C to +125 °C SO20 plastic small outline package; 20 leads;

body width 7.5 mm SOT163-1

74AHC273PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;

body width 4.4 mm SOT360-1

74AHC273BQ −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 20 terminals; body

2.5 × 4.5 × 0.85 mm

SOT764-1

74AHCT273

74AHCT273D −40 °C to +125 °C SO20 plastic small outline package; 20 leads;

body width 7.5 mm SOT163-1

74AHCT273PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;

body width 4.4 mm SOT360-1

74AHCT273BQ −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 20 terminals; body

2.5 × 4.5 × 0.85 mm

SOT764-1

Fig 1. Logic symbol Fig 2. IEC logic symbol

mna763

D7 MR

CP Q0

mna764

11 C1

1D 2

Product data sheet Rev. 03 — 13 May 2008 3 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

Fig 3. Logic diagram

001aae056

FF8

FF7

FF6

FF5

FF4

FF3

FF2

CPCPCPCP

FF1

Fig 4. Functional diagram

001aae055

FF1

FF8

Product data sheet Rev. 03 — 13 May 2008 4 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

5. Pinning information

5.1 Pinning

5.2 Pin description

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as a

supply pin or input.

Fig 5. Pin conﬁguration SO20 and TSSOP20 Fig 6. Pin conﬁguration DHVQFN20

74AHC273

74AHCT273

MR VCC

Q0 Q7

D0 D7

D1 D6

Q1 Q6

Q2 Q5

D2 D5

D3 D4

Q3 Q4

GND CP

001aai066

001aai067

74AHC273

74AHCT273

Transparent top view

D2 D5

Q2 Q5

Q1 Q6

D1 D6

D0 D7

Q0 Q7

GND

VCC

912

8 13

7 14

6 15

5 16

4 17

3 18

2 19

terminal 1

index area

GND(1)

Table 2. Pin description

Symbol Pin Description

MR 1 master reset input (active LOW)

Q0 2 ﬂip-ﬂop output

D0 3 data input

D1 4 data input

Q1 5 ﬂip-ﬂop output

Q2 6 ﬂip-ﬂop output

D2 7 data input

D3 8 data input

Q3 9 ﬂip-ﬂop output

GND 10 ground (0 V)

CP 11 clock input (LOW-to-HIGH edge-triggered)

Q4 12 ﬂip-ﬂop output

D4 13 data input

D5 14 data input

Q5 15 ﬂip-ﬂop output

Q6 16 ﬂip-ﬂop output

Product data sheet Rev. 03 — 13 May 2008 5 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

6. Functional description

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;

↑= LOW-to-HIGH;

X = don’t care.

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.

For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.

For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.

D6 17 data input

D7 18 data input

Q7 19 ﬂip-ﬂop output

VCC 20 supply voltage

Table 2. Pin description

…continued

Symbol Pin Description

Table 3. Function table[1]

Operating mode Control Input Output

MR CP Dn Qn

Reset (clear) L X X L

Load ‘1’ H ↑hH

Load ‘0’ H ↑lL

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +7.0 V

VIinput voltage −0.5 +7.0 V

IIK input clamping current VI < −0.5 V [1] −20 - mA

IOK output clamping current VO < −0.5 V or VO>V

CC + 0.5 V [1] −20 +20 mA

IOoutput current VO = −0.5 V to (VCC + 0.5 V) −25 +25 mA

ICC supply current - +75 mA

IGND ground current −75 - mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation Tamb = −40 °C to +125 °C[2] - 500 mW

Product data sheet Rev. 03 — 13 May 2008 6 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

8. Recommended operating conditions

9. Static characteristics

Table 5. Operating conditions

Symbol Parameter Conditions Min Typ Max Unit

74AHC273

VCC supply voltage 2.0 5.0 5.5 V

VIinput voltage 0 - 5.5 V

VOoutput voltage 0 - VCC V

Tamb ambient temperature −40 +25 +125 °C

∆t/∆V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V

VCC = 4.5 V to 5.5 V - - 20 ns/V

74AHCT273

VCC supply voltage 4.5 5.0 5.5 V

VIinput voltage 0 - 5.5 V

VOoutput voltage 0 - VCC V

Tamb ambient temperature −40 +25 +125 °C

∆t/∆V input transition rise and fall rate VCC = 4.5 V to 5.5 V - - 20 ns/V

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

74AHC273

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V

VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V

VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V

VIL LOW-level

input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V

VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V

VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V

VOH HIGH-level

output voltage VI= VIH or VIL

IO=−50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO=−50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V

IO=−50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO=−4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V

IO=−8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V

VOL LOW-level

output voltage VI= VIH or VIL

IO= 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO= 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V

IO= 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V

IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V

Product data sheet Rev. 03 — 13 May 2008 7 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

IIinput leakage

current VI= 5.5 V or GND;

VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 µA

ICC supply current VI=V

CC or GND; IO = 0 A;

VCC = 5.5 V - - 4.0 - 40 - 80 µA

CIinput

capacitance - 3 10 - 10 - 10 pF

COoutput

capacitance -4- - - - -pF

74AHCT273

VIH HIGH-level

input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V

VIL LOW-level

input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V

VOH HIGH-level

output voltage VI= VIH or VIL; VCC = 4.5 V

IO=−50 µA 4.4 - - 4.4 - 4.4 - V

IO=−8.0 mA 3.94 - - 3.80 - 3.70 - V

VOL LOW-level

output voltage VI= VIH or VIL; VCC = 4.5 V

IO= 50 µA - 0 0.1 - 0.1 - 0.1 V

IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V

IIinput leakage

current VI= 5.5 V or GND;

VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 µA

ICC supply current VI=V

CC or GND; IO = 0 A;

VCC = 5.5 V - - 4.0 - 40 - 80 µA

∆ICC additional

supply current per input pin;

VI=V

CC −2.1 V; other pins

at VCC or GND; IO=0A;

VCC = 4.5 V to 5.5 V

- - 1.35 - 1.5 - 1.5 mA

CIinput

capacitance - 3 10 - 10 - 10 pF

COoutput

capacitance -4- - - - -pF

Table 6. Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

Product data sheet Rev. 03 — 13 May 2008 8 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max Min Max

74AHC273

tpd propagation

delay CP to Qn; see Figure 7 [2]

VCC = 3.0 V to 3.6 V

CL= 15 pF - 6.0 13.6 1.0 16.0 1.0 17.0 ns

CL= 50 pF - 8.6 17.1 1.0 19.5 1.0 21.5 ns

VCC = 4.5 V to 5.5 V

CL= 15 pF - 4.2 9 1.0 10.5 1.0 11.5 ns

CL= 50 pF - 6.0 11.0 1.0 12.5 1.0 14.0 ns

MR to Qn; see Figure 8 [3]

VCC = 3.0 V to 3.6 V

CL= 15 pF - 5.1 13.6 1.0 16.0 1.0 17.0 ns

CL= 50 pF - 7.3 17.1 1.0 19.5 1.0 21.5 ns

VCC = 4.5 V to 5.5 V

CL= 15 pF - 3.7 8.5 1.0 10.0 1.0 11.0 ns

CL= 50 pF - 5.3 10.5 1.0 12.0 1.0 13.5 ns

fmax maximum

frequency see Figure 7

VCC = 3.0 V to 3.6 V

CL= 15 pF 75 120 - 65 - 65 - MHz

CL= 50 pF 50 75 - 45 - 45 - MHz

VCC = 4.5 V to 5.5 V

CL= 15 pF 120 165 - 100 - 100 - MHz

CL= 50 pF 80 110 - 70 - 70 - MHz

tWpulse width CP HIGH or LOW;

see Figure 7

VCC = 3.0 V to 3.6 V 5.0 - - 6.5 - 6.5 - ns

VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns

MR LOW; see Figure 8

VCC = 3.0 V to 3.6 V 5.0 - - 6.0 - 6.0 - ns

VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns

tsu set-up time Dn to CP; see Figure 9

VCC = 3.0 V to 3.6 V 3.0 - - 3.0 - 3.0 - ns

VCC = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.0 - ns

thhold time Dn to CP; see Figure 9

VCC = 3.0 V to 3.6 V 1.0 - - 1.0 - 1.0 - ns

VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - 1.0 - ns

Product data sheet Rev. 03 — 13 May 2008 9 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).

[2] tpd is the same as tPLH and tPHL.

[3] tpd is the same as tPHL only.

[4] CPD is used to determine the dynamic power dissipation (PD in µW).

PD=C

PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

Σ(CL×VCC2×fo) = sum of the outputs.

trec recovery

time MR to CP; see Figure 8

VCC = 3.0 V to 3.6 V 2.5 - - 2.5 - 2.5 - ns

VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - ns

CPD power

dissipation

capacitance

fi= 1 MHz; VI= GND to VCC [4] -14- - - - - pF

74AHCT273; VCC = 4.5 V to 5.5 V

tpd propagation

delay CP to Qn; see Figure 7 [2]

CL= 15 pF - 4.0 7.5 1.0 8.8 1.0 9.5 ns

CL= 50 pF - 5.8 9.2 1.0 10.5 1.0 11.5 ns

MR to Qn; see Figure 8 [3]

CL= 15 pF - 3.9 10.0 1.0 11.6 1.0 12.5 ns

CL= 50 pF - 5.6 11.0 1.0 12.6 1.0 14.0 ns

fmax maximum

frequency see Figure 7

CL= 15 pF 75 120 - 65 - 65 - MHz

CL= 50 pF 50 75 - 45 - 45 - MHz

tWpulse width CP HIGH or LOW;

see Figure 7 5.0 - - 6.5 - 6.5 - ns

MR LOW; see Figure 8 5.0 - - 6.0 - 6.0 - ns

tsu set-up time Dn to CP; see Figure 9 3.0 - - 3.0 - 3.0 - ns

thhold time Dn to CP; see Figure 9 1.0 - - 1.0 - 1.0 - ns

trec recovery

time MR to CP; see Figure 8 2.5 - - 2.5 - 2.5 - ns

CPD power

dissipation

capacitance

fi= 1 MHz; VI= GND to VCC [4] -18- - - - - pF

Table 7. Dynamic characteristics

…continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max Min Max

Product data sheet Rev. 03 — 13 May 2008 10 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

11. Waveforms

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 7. Clock pulse width, maximum frequency and input to output propagation delays

001aac426

CP input

Qn output

tPHL tPLH

VOH

GND

VOL

1/fmax

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 8. Master reset pulse width, recovery time and propagation delay

mna464

MR input

CP input

Qn output

tPHL

tWtrec

GND

VOL

GND

VOH

Product data sheet Rev. 03 — 13 May 2008 11 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 9. Data set-up and hold times

mna202

GND

thth

tsu

VOH

VOL

Qn output

CP input

Dn input

Table 8. Measurement points

Type Input Output

VMVM

74AHC273 0.5 ×VCC 0.5 ×VCC

74AHCT273 1.5 V 0.5 ×VCC

Product data sheet Rev. 03 — 13 May 2008 12 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

Test data is given in Table 9.

Deﬁnitions test circuit:

RT = termination resistance should be equal to output impedance Zo of the pulse generator.

CL = load capacitance including jig and probe capacitance.

Fig 10. Load circuitry for measuring switching times

001aah768

negative

pulse

GND

positive

pulse

GND

10 %

90 %

10 % VMVM

VCC

DUT

VIVO

Table 9. Test data

Type Input Load Test

VItr, tfCL

74AHC273 VCC ≤3.0 ns 15 pF, 50 pF tPLH, tPHL

74AHCT273 3.0 V ≤3.0 ns 15 pF, 50 pF tPLH, tPHL

Product data sheet Rev. 03 — 13 May 2008 13 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

12. Package outline

Fig 11. Package outline SOT163-1 (SO20)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 13.0

12.6 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT163-1

detail X

0.25

075E04 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.51

0.49 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

vMA

(A )

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

99-12-27

03-02-19

Product data sheet Rev. 03 — 13 May 2008 14 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

Fig 12. Package outline SOT360-1 (TSSOP20)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 6.6

6.4 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.5

0.2 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT360-1 MO-153 99-12-27

03-02-19

0.25

110

20 11

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

max.

1.1

Product data sheet Rev. 03 — 13 May 2008 15 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

Fig 13. Package outline SOT764-1 (DHVQFN20)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.6

4.4

3.15

2.85

2.6

2.4 1.15

0.85

3.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT764-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT764-1

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

19 12

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

02-10-17

03-01-27

Product data sheet Rev. 03 — 13 May 2008 16 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

CDM Charged Device Model

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

LSTTL Low-power Schottky Transistor-Transistor Logic

MM Machine Model

MOS Metal-Oxide Semiconductor

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74AHC_AHCT273_3 20080513 Product data sheet - 74AHC_AHCT273_2

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Table 6: the conditions for input leakage current have been changed.

74AHC_AHCT273_2 20030721 Product speciﬁcation - 74AHC_AHCT273_1

74AHC_AHCT273_1 19990901 Product speciﬁcation - -

Product data sheet Rev. 03 — 13 May 2008 17 of 18

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 May 2008

Document identifier: 74AHC_AHCT273_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Recommended operating conditions. . . . . . . . 6

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

15.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16 Contact information. . . . . . . . . . . . . . . . . . . . . 17

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18