FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0
April 2009
FOD073L
LVTTL/LVCMOS Compatible Low Input Current
High Gain Split Darlington Optocoupler
Features
■
Low power consumption
■
Low input current: 0.5mA
■
Dual channel 8-pin SOIC package
■
High CTR: 400% minimum
■
High CMR: 10kV/µs
■
Guaranteed performance over temperature
0°C to 70°C
■
U.L. recognized (File # E90700)
■
LVTTL/LVCMOS Compatible output
Applications
■
Digital logic ground isolation – LVTTL/LVCMOS
■
Telephone ring detector
■
EIA-RS-232C line receiver
■
High common mode noise line receiver
■
µP bus isolation
■
Current loop receiver
Description
The FOD073L optocoupler consists of an AlGaAs LED
optically coupled to a high gain split darlington photo-
detector. This device is specified to operate at a 3.3V
supply voltage.
An integrated emitter – base resistor provides superior
stability over temperature.
The combination of a very low input current of 0.5mA
and a high current transfer ratio of 2000% (typical)
makes this device particularly useful for input interface to
MOS, CMOS, LSTTL and EIA RS232C, while output
compatibility is ensured to LVCMOS as well as high
fan-out LVTTL requirements.
An internal noise shield provides exceptional common
mode rejection of 10kV/µs.
Schematic Package Outline
1
2
3
4 5
6
7
8
+
_
VF1
VCC
V01
V02
GND
VF2
_
+
Truth Table
LED VO
ON LOW
OFF HIGH
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0 2
FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler
Absolute Maximum Ratings
(No derating required up to 85°C)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Value Units
T
STG
Storage Temperature -40 to +125 °C
T
OPR
Operating Temperature -40 to +85 °C
T
SOL
Lead Solder Temperature
(Wave solder only. See reflow profile for surface mount devices)
260 for 10 sec °C
EMITTER
I
F
(avg) DC/Average Forward Input Current Each Channel 20 mA
I
F
(pk) Peak Forward Input Current
(50% duty cycle, 1ms P.W.)
Each Channel 40 mA
I
F
(trans) Peak Transient Input Current (
≤
1µs P. W., 300 pps) Each Channel 1.0 A
V
R
Reverse Input Voltage Each Channel 5 V
P
D
Input Power Dissipation Each Channel 35 mW
DETECTOR
I
O
(avg) Average Output Current Each Channel 60 mA
V
EB
Emitter-Base Reverse Voltage (FOD070L, FOD270L) Each Channel 0.5 V
V
CC
,
V
O
Supply Voltage, Output Voltage Each Channel -0.5 to 7 V
P
D
Output power dissipation Each Channel 100 mW
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0 3
FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler
Electrical Characteristics
(T
A
= 0 to 70°C unless otherwise specified)
Individual Component Characteristics
Transfer Characteristics
Switching Characteristics
(V
CC
= 3.3 V)
*All typicals at T
A
= 25°C
Symbol Parameter Test Conditions Min. Typ.* Max. Unit
EMITTER
V
F
Input Forward Voltage T
A
=25°C 1.35 1.7 V
I
F
= 1.6mA (Each Channel) 1.75
BV
R
Input Reverse
Breakdown Voltage
T
A
=25°C, I
R
= 10µA
(Each Channel)
5.0 V
DETECTOR
I
OH
Logic High Output Current I
F
= 0 mA, V
O
= V
CC
= 3.3V
(Each Channel)
0.05 25 µA
I
CCL
Logic Low Supply Current I
F1
= I
F2
= 1.6mA,
V
O1
= V
O2
= Open, V
CC
= 3.3V
0.8 3 mA
I
CCH
Logic High Supply Current I
F1
= I
F2
= 0mA,
V
O1
= V
O2
= Open, V
CC
= 3.3V
0.01 2 µA
Symbol Parameter Test Conditions Min. Typ.* Max. Unit
CTR COUPLED
Current Transfer Ratio
(Note 1)
I
F
= 0.5mA, V
O
= 0.4V, V
CC
= 3.3V 400 7000 %
V
OL
Logic Low Output Voltage I
F
= 1.6mA, I
O
= 8mA, V
CC
= 3.3V 0.07 0.3 V
I
F
= 5mA, I
O
= 15mA, V
CC
= 3.3V 0.07 0.4
Symbol Parameter Test Conditions Min. Typ.* Max. Unit
T
PHL
Propagation Delay
Time to Logic LOW
R
L
= 4.7k
Ω
, I
F
= 0.5mA
(Fig. 9)
530µs
T
PLH
Propagation Delay
Time to Logic HIGH
R
L
= 4.7k
Ω
, I
F
= 0.5mA
(Fig. 9)
25 90 µs
|CM
H
| Common Mode Transient
Immunity at Logic HIGH
I
F
= 0 mA, |V
CM
| = 10 V
P-P
, T
A
= 25°C,
R
L
= 2.2k
Ω
(Note 2) (Fig. 10)
1,000 10,000 V/µs
|CM
L
| Common Mode Transient
Immunity at Logic LOW
I
F
= 1.6mA, |V
CM
| = 10 V
P-P
, R
L
= 2.2k
Ω
,
T
A
= 25°C (Note 2) (Fig. 10)
1,000 10,000 V/µs
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0 4
FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler
Electrical Characteristics
(Continued) (T
A
= 0 to 70°C unless otherwise specified)
Isolation Characteristics
*All typicals at T
A
= 25°C
Notes:
1. Current Transfer Ratio is defined as a ratio of output collector current, I
O
, to the forward LED input current, I
F
, times
100%.
2. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV
CM
/dt on the leading
edge of the common mode pulse signal, V
CM
, to assure that the output will remain in a logic high state
(i.e., V
O
> 2.0V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dV
CM
/dt
on the trailing edge of the common mode pulse signal, V
CM
, to assure that the output will remain in a logic low state
(i.e., V
O
<0.8 V).
3. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are
shorted together.
4. CI-O is measured by shorting pins 1 and 2 or pins 3 and 4 together and pins 5 through 8 shorted together.
5. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
Symbol Characteristics Test Conditions Min. Typ.* Max. Unit
I
I-O
Input-Output Insulation
Leakage Current
Relative humidity = 45%, T
A
= 25°C,
t = 5 s, V
I-O
= 3000 VDC (Note 3)
1.0 µA
V
ISO
Withstand Insulation Test
Voltage
R
H
≤ 50%, TA = 25°C, II-O ≤ 2µA,
t = 1 min. (Note 3)
2500 VRMS
RI-O Resistance (Input to Output) VI-O = 500 VDC (Note 3) 1012 Ω
CI-O Capacitance (Input to Output) f = 1 MHz (Notes 3, 4) 0.7 pF
II-I Input-Input Insulation
Leakage Current
RH ≤ 45%, VI-I = 500 VDC (Note 5) 0.005 µA
RI-I Input-Input Resistance VI-I = 500 VDC (Note 5) 1011 Ω
CI-I Input-Input Capacitance f = 1 MHz (Note 5) 0.03 pF
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0 5
FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler
Typical Performance Curves
Fig. 1 Input Forward Current vs Forward Voltage
VF - FORWARD VOLTAGE (V)
1.11.00.9 1.2 1.3 1.4 1.5 1.6 1.7
IF - FORWARD CURRENT (mA)
0.001
0.01
0.1
1
10
100
CTR - CURRENT TRANSFER RATIO (%)
VO - OUTPUT VOLTAGE (V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0
20
40
60
80
100
120
140
Fig. 3 DC Transfer Characterstics
I
O
- OUTPUT CURRENT (mA)
TA = 85°C
TA = 70°C
TA = 25°C
TA = -40°C
TA = 0°C
4mA
3.5mA
2.5mA
0.5mA
3mA
2mA
1mA
TA = 25°C
VCC = 3.3V
IF = 5mA
IF = 4.5mA
1.5mA
Fig. 2 Current Transfer Ratio vs. Input Forward Current
IF - FORWARD CURRENT (mA)
1100.1
CTR - CURRENT TRANSFER RATIO (%)
0
500
1000
1500
2000
2500
3000
3500
VO = 0.4V
VCC = 3.3V
TA = 25°C
TA = 85°C
TA = 70°C
TA = 25°C
TA = 0°C
TA = -40°C
Fig. 4 Supply Current vs Input Forward Current
IF - Input Forward Current (mA)
0.1 1 10
I
CC
- (Per Channel) - Supply Current (mA)
0.01
0.1
1
10
Fig. 6 Propagation Delay vs. Ambient Temperature
Fig. 5 Output Current vs Input Forward Current
TA - Ambient Temperature (°C)
-40 -20 0 20 40 60 80 100
t
P
- Propagation Delay (µs)
IF - Forward Current (mA)
0.1 1 10
I
O
- Output Current (mA)
0.1
10
1
100
TA = 25°C
VCC = 3.3V
tPLH
tPHL
0
40
30
20
10
50
60
70
VO = 0.4V
VCC = 3.3V
TA = 25°C
TA = -40°C
TA = 70°C, 85°C
TA = 0°C
TA = 25°C
VCC = 3.3V
IF = 0.5mA
RL = 4.7kΩ
1/f = 100µs
Duty Cycle = 10%
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0 6
FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler
Typical Performance Curves (Continued)
Fig. 7 Propagation Delay To Logic Low vs Pulse Period
T - Pulse Period (ms)
0.01 0.1 1 10
tPLH
tPHL
t
PHL
- Propagation Delay to Logic Low (µs)
1
10
100
Fig. 8 Propagation Delay vs. Input Forward Current
IF - Input Forward Current (mA)
012345678910
t
PHL
- Propagation Delay to Logic Low (µs)
t
PLH
- Propagation Delay to Logic High (µs)
0
4
2
6
8
12
10
16
24
22
20
18
26
28
TA = 25°C
VCC = 3.3V
I = 0.5mA
RL = 4.7kΩ
Duty Cycle = 50µs
TA = 25°C
VCC = 3.3V
RL = 4.7kΩ
1/f = 100µs
Duty Cycle = 10%
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0 7
FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler
Fig. 10 Common Mode Immunity Test Circuit
Fig. 9 Switching Time Test Circuit
PLH
OL
V
VO3.3 V
50%
F
I
50%
T
PHL
T
4 5
Noise
1
2
3
Shield 8
7
6
O
V
VCC
V01
V02
GND
VF1
-
+
F2V
FI+
FI
MONITOR
LR0.1 µF
Pulse
Generator
tr = 5ns
Z = 50
OV
+3.3 V
*Includes Probe and Fixture Capacitance
Rm
-
C = 15 pF*L
Switch at A : I = 0 mA
F
Switch at B : I = 1.6 mA
F
tr
VO
O
V
OL
V
3.3 V
0 V 10% 10%
90%
CM
V 10 V
GND
+
-
F2V
VF1
-
+3.3 V
CCV
L
V02
V
R
01 VO
VCM
A
B
Pulse Gen
F
I
+-
+
f
t
FF
V
90%
1
3
4
2
Shield
Noise
8
6
5
7
0.1 µF
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0 8
FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler
Package Dimensions
8-pin SOIC Surface Mount
Recommended Pad Layout
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
Lead Coplanarity: 0.004 (0.10) MAX
0.202 (5.13)
0.182 (4.63)
0.021 (0.53)
0.011 (0.28)
0.050 (1.27) Typ.
0.164 (4.16)
1
8
0.144 (3.66)
0.244 (6.19)
0.224 (5.69)
0.143 (3.63)
0.123 (3.13)
0.008 (0.20)
0.003 (0.08)
0.010 (0.25)
0.006 (0.16)
SEATING PLANE
0.024 (0.61)
0.050 (1.27)
Dimensions in inches (mm).
0.155 (3.94)
0.275 (6.99)
0.060 (1.52)
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0 9
FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler
Ordering Information
Marking Information
Option
Order Entry
Identifier Description
No Suffix FOD073L Shipped in tubes (50 units per tube)
R2 FOD073LR2 Tape and reel (2,500 units per reel)
12
5
34
Definitions
1Fairchild logo
2Device number
3 One digit year code, e.g., ‘3’
4Two digit work week ranging from ‘01’ to ‘53’
5 Assembly package code
73L
SYYX
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0 10
FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler
Carrier Tape Specifications
4.0 ± 0.10
Ø1.5 MIN
User Direction of Feed
2.0 ± 0.05
1.75 ± 0.10
5.5 ± 0.05
12.0 ± 0.3
8.0 ± 0.10
0.30 MAX
8.3 ± 0.10
3.50 ± 0.20
Dimensions in mm
0.1 MAX 6.40 ± 0.20
5.20 ± 0.20
Ø1.5 ± 0.1
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0 11
FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler
Reflow Profile
Profile Freature Pb-Free Assembly Profile
Temperature Min. (Tsmin) 150°C
Temperature Max. (Tsmax) 200°C
Time (tS) from (Tsmin to Tsmax) 60–120 seconds
Ramp-up Rate (tL to tP) 3°C/second max.
Liquidous Temperature (TL) 217°C
Time (tL) Maintained Above (TL) 60–150 seconds
Peak Body Package Temperature 260°C +0°C / –5°C
Time (tP) within 5°C of 260°C 30 seconds
Ramp-down Rate (TP to TL) 6°C/second max.
Time 25°C to Peak Temperature 8 minutes max.
Time (seconds)
Temperature (°C)
Time 25°C to Peak
260
240
220
200
180
160
140
120
100
80
60
40
20
0
TL
ts
tL
tP
TP
Tsmax
Tsmin
120
Preheat Area
Max. Ramp-up Rate = 3°C/S
Max. Ramp-down Rate = 6°C/S
240 360
©2004 Fairchild Semiconductor Corporation www.fairchildsemi.com
FOD073L Rev. 1.0 12
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intended to be an exhaustive list of all such trademarks.
Auto-SPM™
Build it Now™
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CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EfficentMax™
EZSWITCH™*
™*
®
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FACT®
FAST®
FastvCore™
FETBench™
FlashWriter®*
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F-PFS™
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Green FPS™e-Series™
Gmax™
GTO™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MillerDrive™
MotionMax™
Motion-SPM™
OPTOLOGIC®
OPTOPLANAR®
®
PDP SPM™
Power-SPM™
PowerTrench®
PowerXS™
Programmable Active Droop™
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QS™
Quiet Series™
RapidConfigure™
™
Saving our world, 1mW/W/kW at a time™
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SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SupreMOS™
SyncFET™
Sync-Lock™
®*
ThePower Franchise®
TinyBoost™
TinyBuck™
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TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
TriFault Detect™
TRUECURRENT™*
µSerDes™
UHC®
Ultra FRFET™
UniFET™
VCX™
VisualMax™
XS™
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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any manner without notice.
Preliminary Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
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The datasheet is for reference information only.
Rev. I40
First Production
FOD073L — LVTTL/LVCMOS Compatible Low Input Current High Gain Split Darlington Optocoupler